drivers/net/ethernet/intel/i40evf/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2015 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36
  37 /* Device IDs */
  38 #define I40E_DEV_ID_SFP_XL710           0x1572
  39 #define I40E_DEV_ID_QEMU                0x1574
  40 #define I40E_DEV_ID_KX_A                0x157F
  41 #define I40E_DEV_ID_KX_B                0x1580
  42 #define I40E_DEV_ID_KX_C                0x1581
  43 #define I40E_DEV_ID_QSFP_A              0x1583
  44 #define I40E_DEV_ID_QSFP_B              0x1584
  45 #define I40E_DEV_ID_QSFP_C              0x1585
  46 #define I40E_DEV_ID_10G_BASE_T          0x1586
  47 #define I40E_DEV_ID_20G_KR2             0x1587
  48 #define I40E_DEV_ID_20G_KR2_A           0x1588
  49 #define I40E_DEV_ID_VF                  0x154C
  50 #define I40E_DEV_ID_VF_HV               0x1571
  51 #define I40E_DEV_ID_SFP_X722            0x37D0
  52 #define I40E_DEV_ID_1G_BASE_T_X722      0x37D1
  53 #define I40E_DEV_ID_10G_BASE_T_X722     0x37D2
  54 #define I40E_DEV_ID_X722_VF             0x37CD
  55 #define I40E_DEV_ID_X722_VF_HV          0x37D9
  56
  57 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  58                                          (d) == I40E_DEV_ID_QSFP_B  || \
  59                                          (d) == I40E_DEV_ID_QSFP_C)
  60
  61 /* I40E_MASK is a macro used on 32 bit registers */
  62 #define I40E_MASK(mask, shift) (mask << shift)
  63
  64 #define I40E_MAX_VSI_QP                 16
  65 #define I40E_MAX_VF_VSI                 3
  66 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  67 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  68
  69 /* Max default timeout in ms, */
  70 #define I40E_MAX_NVM_TIMEOUT            18000
  71
  72 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  73 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  74
  75 /* forward declaration */
  76 struct i40e_hw;
  77 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  78
  79 /* Data type manipulation macros. */
  80
  81 #define I40E_DESC_UNUSED(R)     \
  82         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  83         (R)->next_to_clean - (R)->next_to_use - 1)
  84
  85 /* bitfields for Tx queue mapping in QTX_CTL */
  86 #define I40E_QTX_CTL_VF_QUEUE   0x0
  87 #define I40E_QTX_CTL_VM_QUEUE   0x1
  88 #define I40E_QTX_CTL_PF_QUEUE   0x2
  89
  90 /* debug masks - set these bits in hw->debug_mask to control output */
  91 enum i40e_debug_mask {
  92         I40E_DEBUG_INIT                 = 0x00000001,
  93         I40E_DEBUG_RELEASE              = 0x00000002,
  94
  95         I40E_DEBUG_LINK                 = 0x00000010,
  96         I40E_DEBUG_PHY                  = 0x00000020,
  97         I40E_DEBUG_HMC                  = 0x00000040,
  98         I40E_DEBUG_NVM                  = 0x00000080,
  99         I40E_DEBUG_LAN                  = 0x00000100,
 100         I40E_DEBUG_FLOW                 = 0x00000200,
 101         I40E_DEBUG_DCB                  = 0x00000400,
 102         I40E_DEBUG_DIAG                 = 0x00000800,
 103         I40E_DEBUG_FD                   = 0x00001000,
 104
 105         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 106         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 107         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 108         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 109         I40E_DEBUG_AQ                   = 0x0F000000,
 110
 111         I40E_DEBUG_USER                 = 0xF0000000,
 112
 113         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 114 };
 115
 116 /* These are structs for managing the hardware information and the operations.
 117  * The structures of function pointers are filled out at init time when we
 118  * know for sure exactly which hardware we're working with.  This gives us the
 119  * flexibility of using the same main driver code but adapting to slightly
 120  * different hardware needs as new parts are developed.  For this architecture,
 121  * the Firmware and AdminQ are intended to insulate the driver from most of the
 122  * future changes, but these structures will also do part of the job.
 123  */
 124 enum i40e_mac_type {
 125         I40E_MAC_UNKNOWN = 0,
 126         I40E_MAC_X710,
 127         I40E_MAC_XL710,
 128         I40E_MAC_VF,
 129         I40E_MAC_X722,
 130         I40E_MAC_X722_VF,
 131         I40E_MAC_GENERIC,
 132 };
 133
 134 enum i40e_media_type {
 135         I40E_MEDIA_TYPE_UNKNOWN = 0,
 136         I40E_MEDIA_TYPE_FIBER,
 137         I40E_MEDIA_TYPE_BASET,
 138         I40E_MEDIA_TYPE_BACKPLANE,
 139         I40E_MEDIA_TYPE_CX4,
 140         I40E_MEDIA_TYPE_DA,
 141         I40E_MEDIA_TYPE_VIRTUAL
 142 };
 143
 144 enum i40e_fc_mode {
 145         I40E_FC_NONE = 0,
 146         I40E_FC_RX_PAUSE,
 147         I40E_FC_TX_PAUSE,
 148         I40E_FC_FULL,
 149         I40E_FC_PFC,
 150         I40E_FC_DEFAULT
 151 };
 152
 153 enum i40e_set_fc_aq_failures {
 154         I40E_SET_FC_AQ_FAIL_NONE = 0,
 155         I40E_SET_FC_AQ_FAIL_GET = 1,
 156         I40E_SET_FC_AQ_FAIL_SET = 2,
 157         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 158         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 159 };
 160
 161 enum i40e_vsi_type {
 162         I40E_VSI_MAIN = 0,
 163         I40E_VSI_VMDQ1,
 164         I40E_VSI_VMDQ2,
 165         I40E_VSI_CTRL,
 166         I40E_VSI_FCOE,
 167         I40E_VSI_MIRROR,
 168         I40E_VSI_SRIOV,
 169         I40E_VSI_FDIR,
 170         I40E_VSI_TYPE_UNKNOWN
 171 };
 172
 173 enum i40e_queue_type {
 174         I40E_QUEUE_TYPE_RX = 0,
 175         I40E_QUEUE_TYPE_TX,
 176         I40E_QUEUE_TYPE_PE_CEQ,
 177         I40E_QUEUE_TYPE_UNKNOWN
 178 };
 179
 180 struct i40e_link_status {
 181         enum i40e_aq_phy_type phy_type;
 182         enum i40e_aq_link_speed link_speed;
 183         u8 link_info;
 184         u8 an_info;
 185         u8 ext_info;
 186         u8 loopback;
 187         /* is Link Status Event notification to SW enabled */
 188         bool lse_enable;
 189         u16 max_frame_size;
 190         bool crc_enable;
 191         u8 pacing;
 192         u8 requested_speeds;
 193 };
 194
 195 struct i40e_phy_info {
 196         struct i40e_link_status link_info;
 197         struct i40e_link_status link_info_old;
 198         u32 autoneg_advertised;
 199         u32 phy_id;
 200         u32 module_type;
 201         bool get_link_info;
 202         enum i40e_media_type media_type;
 203 };
 204
 205 #define I40E_HW_CAP_MAX_GPIO                    30
 206 /* Capabilities of a PF or a VF or the whole device */
 207 struct i40e_hw_capabilities {
 208         u32  switch_mode;
 209 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 210 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 211 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 212
 213         u32  management_mode;
 214         u32  npar_enable;
 215         u32  os2bmc;
 216         u32  valid_functions;
 217         bool sr_iov_1_1;
 218         bool vmdq;
 219         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 220         bool evb_802_1_qbh; /* Bridge Port Extension */
 221         bool dcb;
 222         bool fcoe;
 223         bool iscsi; /* Indicates iSCSI enabled */
 224         bool flex10_enable;
 225         bool flex10_capable;
 226         u32  flex10_mode;
 227 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 228 #define I40E_FLEX10_MODE_DCC            0x1
 229 #define I40E_FLEX10_MODE_DCI            0x2
 230
 231         u32 flex10_status;
 232 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 233 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 234
 235         bool mgmt_cem;
 236         bool ieee_1588;
 237         bool iwarp;
 238         bool fd;
 239         u32 fd_filters_guaranteed;
 240         u32 fd_filters_best_effort;
 241         bool rss;
 242         u32 rss_table_size;
 243         u32 rss_table_entry_width;
 244         bool led[I40E_HW_CAP_MAX_GPIO];
 245         bool sdp[I40E_HW_CAP_MAX_GPIO];
 246         u32 nvm_image_type;
 247         u32 num_flow_director_filters;
 248         u32 num_vfs;
 249         u32 vf_base_id;
 250         u32 num_vsis;
 251         u32 num_rx_qp;
 252         u32 num_tx_qp;
 253         u32 base_queue;
 254         u32 num_msix_vectors;
 255         u32 num_msix_vectors_vf;
 256         u32 led_pin_num;
 257         u32 sdp_pin_num;
 258         u32 mdio_port_num;
 259         u32 mdio_port_mode;
 260         u8 rx_buf_chain_len;
 261         u32 enabled_tcmap;
 262         u32 maxtc;
 263         u64 wr_csr_prot;
 264 };
 265
 266 struct i40e_mac_info {
 267         enum i40e_mac_type type;
 268         u8 addr[ETH_ALEN];
 269         u8 perm_addr[ETH_ALEN];
 270         u8 san_addr[ETH_ALEN];
 271         u16 max_fcoeq;
 272 };
 273
 274 enum i40e_aq_resources_ids {
 275         I40E_NVM_RESOURCE_ID = 1
 276 };
 277
 278 enum i40e_aq_resource_access_type {
 279         I40E_RESOURCE_READ = 1,
 280         I40E_RESOURCE_WRITE
 281 };
 282
 283 struct i40e_nvm_info {
 284         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 285         u32 timeout;              /* [ms] */
 286         u16 sr_size;              /* Shadow RAM size in words */
 287         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 288         u16 version;              /* NVM package version */
 289         u32 eetrack;              /* NVM data version */
 290 };
 291
 292 /* definitions used in NVM update support */
 293
 294 enum i40e_nvmupd_cmd {
 295         I40E_NVMUPD_INVALID,
 296         I40E_NVMUPD_READ_CON,
 297         I40E_NVMUPD_READ_SNT,
 298         I40E_NVMUPD_READ_LCB,
 299         I40E_NVMUPD_READ_SA,
 300         I40E_NVMUPD_WRITE_ERA,
 301         I40E_NVMUPD_WRITE_CON,
 302         I40E_NVMUPD_WRITE_SNT,
 303         I40E_NVMUPD_WRITE_LCB,
 304         I40E_NVMUPD_WRITE_SA,
 305         I40E_NVMUPD_CSUM_CON,
 306         I40E_NVMUPD_CSUM_SA,
 307         I40E_NVMUPD_CSUM_LCB,
 308         I40E_NVMUPD_STATUS,
 309         I40E_NVMUPD_EXEC_AQ,
 310         I40E_NVMUPD_GET_AQ_RESULT,
 311 };
 312
 313 enum i40e_nvmupd_state {
 314         I40E_NVMUPD_STATE_INIT,
 315         I40E_NVMUPD_STATE_READING,
 316         I40E_NVMUPD_STATE_WRITING,
 317         I40E_NVMUPD_STATE_INIT_WAIT,
 318         I40E_NVMUPD_STATE_WRITE_WAIT,
 319 };
 320
 321 /* nvm_access definition and its masks/shifts need to be accessible to
 322  * application, core driver, and shared code.  Where is the right file?
 323  */
 324 #define I40E_NVM_READ   0xB
 325 #define I40E_NVM_WRITE  0xC
 326
 327 #define I40E_NVM_MOD_PNT_MASK 0xFF
 328
 329 #define I40E_NVM_TRANS_SHIFT    8
 330 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 331 #define I40E_NVM_CON            0x0
 332 #define I40E_NVM_SNT            0x1
 333 #define I40E_NVM_LCB            0x2
 334 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 335 #define I40E_NVM_ERA            0x4
 336 #define I40E_NVM_CSUM           0x8
 337 #define I40E_NVM_EXEC           0xf
 338
 339 #define I40E_NVM_ADAPT_SHIFT    16
 340 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 341
 342 #define I40E_NVMUPD_MAX_DATA    4096
 343 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 344
 345 struct i40e_nvm_access {
 346         u32 command;
 347         u32 config;
 348         u32 offset;     /* in bytes */
 349         u32 data_size;  /* in bytes */
 350         u8 data[1];
 351 };
 352
 353 /* PCI bus types */
 354 enum i40e_bus_type {
 355         i40e_bus_type_unknown = 0,
 356         i40e_bus_type_pci,
 357         i40e_bus_type_pcix,
 358         i40e_bus_type_pci_express,
 359         i40e_bus_type_reserved
 360 };
 361
 362 /* PCI bus speeds */
 363 enum i40e_bus_speed {
 364         i40e_bus_speed_unknown  = 0,
 365         i40e_bus_speed_33       = 33,
 366         i40e_bus_speed_66       = 66,
 367         i40e_bus_speed_100      = 100,
 368         i40e_bus_speed_120      = 120,
 369         i40e_bus_speed_133      = 133,
 370         i40e_bus_speed_2500     = 2500,
 371         i40e_bus_speed_5000     = 5000,
 372         i40e_bus_speed_8000     = 8000,
 373         i40e_bus_speed_reserved
 374 };
 375
 376 /* PCI bus widths */
 377 enum i40e_bus_width {
 378         i40e_bus_width_unknown  = 0,
 379         i40e_bus_width_pcie_x1  = 1,
 380         i40e_bus_width_pcie_x2  = 2,
 381         i40e_bus_width_pcie_x4  = 4,
 382         i40e_bus_width_pcie_x8  = 8,
 383         i40e_bus_width_32       = 32,
 384         i40e_bus_width_64       = 64,
 385         i40e_bus_width_reserved
 386 };
 387
 388 /* Bus parameters */
 389 struct i40e_bus_info {
 390         enum i40e_bus_speed speed;
 391         enum i40e_bus_width width;
 392         enum i40e_bus_type type;
 393
 394         u16 func;
 395         u16 device;
 396         u16 lan_id;
 397 };
 398
 399 /* Flow control (FC) parameters */
 400 struct i40e_fc_info {
 401         enum i40e_fc_mode current_mode; /* FC mode in effect */
 402         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 403 };
 404
 405 #define I40E_MAX_TRAFFIC_CLASS          8
 406 #define I40E_MAX_USER_PRIORITY          8
 407 #define I40E_DCBX_MAX_APPS              32
 408 #define I40E_LLDPDU_SIZE                1500
 409
 410 /* IEEE 802.1Qaz ETS Configuration data */
 411 struct i40e_ieee_ets_config {
 412         u8 willing;
 413         u8 cbs;
 414         u8 maxtcs;
 415         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 416         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 417         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 418 };
 419
 420 /* IEEE 802.1Qaz ETS Recommendation data */
 421 struct i40e_ieee_ets_recommend {
 422         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 423         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 424         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 425 };
 426
 427 /* IEEE 802.1Qaz PFC Configuration data */
 428 struct i40e_ieee_pfc_config {
 429         u8 willing;
 430         u8 mbc;
 431         u8 pfccap;
 432         u8 pfcenable;
 433 };
 434
 435 /* IEEE 802.1Qaz Application Priority data */
 436 struct i40e_ieee_app_priority_table {
 437         u8  priority;
 438         u8  selector;
 439         u16 protocolid;
 440 };
 441
 442 struct i40e_dcbx_config {
 443         u32 numapps;
 444         u32 tlv_status; /* CEE mode TLV status */
 445         struct i40e_ieee_ets_config etscfg;
 446         struct i40e_ieee_ets_recommend etsrec;
 447         struct i40e_ieee_pfc_config pfc;
 448         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 449 };
 450
 451 /* Port hardware description */
 452 struct i40e_hw {
 453         u8 __iomem *hw_addr;
 454         void *back;
 455
 456         /* subsystem structs */
 457         struct i40e_phy_info phy;
 458         struct i40e_mac_info mac;
 459         struct i40e_bus_info bus;
 460         struct i40e_nvm_info nvm;
 461         struct i40e_fc_info fc;
 462
 463         /* pci info */
 464         u16 device_id;
 465         u16 vendor_id;
 466         u16 subsystem_device_id;
 467         u16 subsystem_vendor_id;
 468         u8 revision_id;
 469         u8 port;
 470         bool adapter_stopped;
 471
 472         /* capabilities for entire device and PCI func */
 473         struct i40e_hw_capabilities dev_caps;
 474         struct i40e_hw_capabilities func_caps;
 475
 476         /* Flow Director shared filter space */
 477         u16 fdir_shared_filter_count;
 478
 479         /* device profile info */
 480         u8  pf_id;
 481         u16 main_vsi_seid;
 482
 483         /* for multi-function MACs */
 484         u16 partition_id;
 485         u16 num_partitions;
 486         u16 num_ports;
 487
 488         /* Closest numa node to the device */
 489         u16 numa_node;
 490
 491         /* Admin Queue info */
 492         struct i40e_adminq_info aq;
 493
 494         /* state of nvm update process */
 495         enum i40e_nvmupd_state nvmupd_state;
 496         struct i40e_aq_desc nvm_wb_desc;
 497         struct i40e_virt_mem nvm_buff;
 498
 499         /* HMC info */
 500         struct i40e_hmc_info hmc; /* HMC info struct */
 501
 502         /* LLDP/DCBX Status */
 503         u16 dcbx_status;
 504
 505         /* DCBX info */
 506         struct i40e_dcbx_config local_dcbx_config;
 507         struct i40e_dcbx_config remote_dcbx_config;
 508
 509         /* debug mask */
 510         u32 debug_mask;
 511         char err_str[16];
 512 };
 513
 514 static inline bool i40e_is_vf(struct i40e_hw *hw)
 515 {
 516         return (hw->mac.type == I40E_MAC_VF ||
 517                 hw->mac.type == I40E_MAC_X722_VF);
 518 }
 519
 520 struct i40e_driver_version {
 521         u8 major_version;
 522         u8 minor_version;
 523         u8 build_version;
 524         u8 subbuild_version;
 525         u8 driver_string[32];
 526 };
 527
 528 /* RX Descriptors */
 529 union i40e_16byte_rx_desc {
 530         struct {
 531                 __le64 pkt_addr; /* Packet buffer address */
 532                 __le64 hdr_addr; /* Header buffer address */
 533         } read;
 534         struct {
 535                 struct {
 536                         struct {
 537                                 union {
 538                                         __le16 mirroring_status;
 539                                         __le16 fcoe_ctx_id;
 540                                 } mirr_fcoe;
 541                                 __le16 l2tag1;
 542                         } lo_dword;
 543                         union {
 544                                 __le32 rss; /* RSS Hash */
 545                                 __le32 fd_id; /* Flow director filter id */
 546                                 __le32 fcoe_param; /* FCoE DDP Context id */
 547                         } hi_dword;
 548                 } qword0;
 549                 struct {
 550                         /* ext status/error/pktype/length */
 551                         __le64 status_error_len;
 552                 } qword1;
 553         } wb;  /* writeback */
 554 };
 555
 556 union i40e_32byte_rx_desc {
 557         struct {
 558                 __le64  pkt_addr; /* Packet buffer address */
 559                 __le64  hdr_addr; /* Header buffer address */
 560                         /* bit 0 of hdr_buffer_addr is DD bit */
 561                 __le64  rsvd1;
 562                 __le64  rsvd2;
 563         } read;
 564         struct {
 565                 struct {
 566                         struct {
 567                                 union {
 568                                         __le16 mirroring_status;
 569                                         __le16 fcoe_ctx_id;
 570                                 } mirr_fcoe;
 571                                 __le16 l2tag1;
 572                         } lo_dword;
 573                         union {
 574                                 __le32 rss; /* RSS Hash */
 575                                 __le32 fcoe_param; /* FCoE DDP Context id */
 576                                 /* Flow director filter id in case of
 577                                  * Programming status desc WB
 578                                  */
 579                                 __le32 fd_id;
 580                         } hi_dword;
 581                 } qword0;
 582                 struct {
 583                         /* status/error/pktype/length */
 584                         __le64 status_error_len;
 585                 } qword1;
 586                 struct {
 587                         __le16 ext_status; /* extended status */
 588                         __le16 rsvd;
 589                         __le16 l2tag2_1;
 590                         __le16 l2tag2_2;
 591                 } qword2;
 592                 struct {
 593                         union {
 594                                 __le32 flex_bytes_lo;
 595                                 __le32 pe_status;
 596                         } lo_dword;
 597                         union {
 598                                 __le32 flex_bytes_hi;
 599                                 __le32 fd_id;
 600                         } hi_dword;
 601                 } qword3;
 602         } wb;  /* writeback */
 603 };
 604
 605 enum i40e_rx_desc_status_bits {
 606         /* Note: These are predefined bit offsets */
 607         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 608         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 609         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 610         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 611         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 612         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 613         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 614         /* Note: Bit 8 is reserved in X710 and XL710 */
 615         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 616         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 617         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 618         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 619         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 620         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 621         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 622         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 623          * UDP header
 624          */
 625         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 626         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 627 };
 628
 629 #define I40E_RXD_QW1_STATUS_SHIFT       0
 630 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 631                                          << I40E_RXD_QW1_STATUS_SHIFT)
 632
 633 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 634 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 635                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 636
 637 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 638 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 639                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 640
 641 enum i40e_rx_desc_fltstat_values {
 642         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 643         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 644         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 645         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 646 };
 647
 648 #define I40E_RXD_QW1_ERROR_SHIFT        19
 649 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 650
 651 enum i40e_rx_desc_error_bits {
 652         /* Note: These are predefined bit offsets */
 653         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 654         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 655         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 656         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 657         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 658         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 659         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 660         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 661         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 662 };
 663
 664 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 665         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 666         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 667         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 668         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 669         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 670 };
 671
 672 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 673 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 674
 675 /* Packet type non-ip values */
 676 enum i40e_rx_l2_ptype {
 677         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 678         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 679         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 680         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 681         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 682         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 683         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 684         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 685         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 686         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 687         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 688         I40E_RX_PTYPE_L2_ARP                            = 11,
 689         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 690         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 691         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 692         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 693         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 694         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 695         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 696         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 697         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 698         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 699         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 700         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 701         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 702         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 703 };
 704
 705 struct i40e_rx_ptype_decoded {
 706         u32 ptype:8;
 707         u32 known:1;
 708         u32 outer_ip:1;
 709         u32 outer_ip_ver:1;
 710         u32 outer_frag:1;
 711         u32 tunnel_type:3;
 712         u32 tunnel_end_prot:2;
 713         u32 tunnel_end_frag:1;
 714         u32 inner_prot:4;
 715         u32 payload_layer:3;
 716 };
 717
 718 enum i40e_rx_ptype_outer_ip {
 719         I40E_RX_PTYPE_OUTER_L2  = 0,
 720         I40E_RX_PTYPE_OUTER_IP  = 1
 721 };
 722
 723 enum i40e_rx_ptype_outer_ip_ver {
 724         I40E_RX_PTYPE_OUTER_NONE        = 0,
 725         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 726         I40E_RX_PTYPE_OUTER_IPV6        = 1
 727 };
 728
 729 enum i40e_rx_ptype_outer_fragmented {
 730         I40E_RX_PTYPE_NOT_FRAG  = 0,
 731         I40E_RX_PTYPE_FRAG      = 1
 732 };
 733
 734 enum i40e_rx_ptype_tunnel_type {
 735         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 736         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 737         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 738         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 739         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 740 };
 741
 742 enum i40e_rx_ptype_tunnel_end_prot {
 743         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 744         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 745         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 746 };
 747
 748 enum i40e_rx_ptype_inner_prot {
 749         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 750         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 751         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 752         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 753         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 754         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 755 };
 756
 757 enum i40e_rx_ptype_payload_layer {
 758         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 759         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 760         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 761         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 762 };
 763
 764 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 765 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 766                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 767
 768 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 769 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 770                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 771
 772 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 773 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 774
 775 enum i40e_rx_desc_ext_status_bits {
 776         /* Note: These are predefined bit offsets */
 777         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 778         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 779         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 780         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 781         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 782         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 783         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 784 };
 785
 786 enum i40e_rx_desc_pe_status_bits {
 787         /* Note: These are predefined bit offsets */
 788         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 789         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 790         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 791         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 792         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 793         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 794         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 795         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 796         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 797 };
 798
 799 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 800 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 801
 802 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 803 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 804                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 805
 806 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 807 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 808                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 809
 810 enum i40e_rx_prog_status_desc_status_bits {
 811         /* Note: These are predefined bit offsets */
 812         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 813         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 814 };
 815
 816 enum i40e_rx_prog_status_desc_prog_id_masks {
 817         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 818         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 819         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 820 };
 821
 822 enum i40e_rx_prog_status_desc_error_bits {
 823         /* Note: These are predefined bit offsets */
 824         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 825         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 826         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 827         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 828 };
 829
 830 /* TX Descriptor */
 831 struct i40e_tx_desc {
 832         __le64 buffer_addr; /* Address of descriptor's data buf */
 833         __le64 cmd_type_offset_bsz;
 834 };
 835
 836 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 837 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 838
 839 enum i40e_tx_desc_dtype_value {
 840         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 841         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 842         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 843         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 844         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 845         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 846         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 847         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 848         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 849         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 850 };
 851
 852 #define I40E_TXD_QW1_CMD_SHIFT  4
 853 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 854
 855 enum i40e_tx_desc_cmd_bits {
 856         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 857         I40E_TX_DESC_CMD_RS                     = 0x0002,
 858         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 859         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 860         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 861         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 862         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 863         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 864         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 865         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 866         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 867         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 868         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 869         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 870         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 871         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 872         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 873         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 874 };
 875
 876 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 877 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 878                                          I40E_TXD_QW1_OFFSET_SHIFT)
 879
 880 enum i40e_tx_desc_length_fields {
 881         /* Note: These are predefined bit offsets */
 882         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 883         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 884         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 885 };
 886
 887 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 888 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 889                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 890
 891 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 892 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 893
 894 /* Context descriptors */
 895 struct i40e_tx_context_desc {
 896         __le32 tunneling_params;
 897         __le16 l2tag2;
 898         __le16 rsvd;
 899         __le64 type_cmd_tso_mss;
 900 };
 901
 902 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 903 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 904
 905 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 906 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 907
 908 enum i40e_tx_ctx_desc_cmd_bits {
 909         I40E_TX_CTX_DESC_TSO            = 0x01,
 910         I40E_TX_CTX_DESC_TSYN           = 0x02,
 911         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 912         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 913         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 914         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 915         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 916         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 917         I40E_TX_CTX_DESC_SWPE           = 0x40
 918 };
 919
 920 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 921 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 922                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 923
 924 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 925 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 926                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 927
 928 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 929 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 930
 931 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 932 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 933                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 934
 935 enum i40e_tx_ctx_desc_eipt_offload {
 936         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 937         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 938         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 939         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 940 };
 941
 942 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 943 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 944                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 945
 946 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 947 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 948
 949 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
 950 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 951
 952 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 953 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
 954                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 955
 956 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 957
 958 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 959 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 960                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 961
 962 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 963 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 964                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 965
 966 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
 967 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
 968 struct i40e_filter_program_desc {
 969         __le32 qindex_flex_ptype_vsi;
 970         __le32 rsvd;
 971         __le32 dtype_cmd_cntindex;
 972         __le32 fd_id;
 973 };
 974 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 975 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 976                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 977 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 978 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 979                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 980 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 981 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 982                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 983
 984 /* Packet Classifier Types for filters */
 985 enum i40e_filter_pctype {
 986         /* Note: Values 0-28 are reserved for future use.
 987          * Value 29, 30, 32 are not supported on XL710 and X710.
 988          */
 989         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
 990         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
 991         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 992         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
 993         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 994         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 995         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 996         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 997         /* Note: Values 37-38 are reserved for future use.
 998          * Value 39, 40, 42 are not supported on XL710 and X710.
 999          */
1000         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1001         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1002         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1003         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1004         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1005         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1006         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1007         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1008         /* Note: Value 47 is reserved for future use */
1009         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1010         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1011         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1012         /* Note: Values 51-62 are reserved for future use */
1013         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1014 };
1015
1016 enum i40e_filter_program_desc_dest {
1017         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1018         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1019         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1020 };
1021
1022 enum i40e_filter_program_desc_fd_status {
1023         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1024         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1025         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1026         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1027 };
1028
1029 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1030 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1031                                        BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1032
1033 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1034 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1035                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1036
1037 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1038 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1039
1040 enum i40e_filter_program_desc_pcmd {
1041         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1042         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1043 };
1044
1045 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1046 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1047
1048 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1049 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1050
1051 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1052                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1053 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1054                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1055
1056 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1057 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1058                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1059
1060 enum i40e_filter_type {
1061         I40E_FLOW_DIRECTOR_FLTR = 0,
1062         I40E_PE_QUAD_HASH_FLTR = 1,
1063         I40E_ETHERTYPE_FLTR,
1064         I40E_FCOE_CTX_FLTR,
1065         I40E_MAC_VLAN_FLTR,
1066         I40E_HASH_FLTR
1067 };
1068
1069 struct i40e_vsi_context {
1070         u16 seid;
1071         u16 uplink_seid;
1072         u16 vsi_number;
1073         u16 vsis_allocated;
1074         u16 vsis_unallocated;
1075         u16 flags;
1076         u8 pf_num;
1077         u8 vf_num;
1078         u8 connection_type;
1079         struct i40e_aqc_vsi_properties_data info;
1080 };
1081
1082 struct i40e_veb_context {
1083         u16 seid;
1084         u16 uplink_seid;
1085         u16 veb_number;
1086         u16 vebs_allocated;
1087         u16 vebs_unallocated;
1088         u16 flags;
1089         struct i40e_aqc_get_veb_parameters_completion info;
1090 };
1091
1092 /* Statistics collected by each port, VSI, VEB, and S-channel */
1093 struct i40e_eth_stats {
1094         u64 rx_bytes;                   /* gorc */
1095         u64 rx_unicast;                 /* uprc */
1096         u64 rx_multicast;               /* mprc */
1097         u64 rx_broadcast;               /* bprc */
1098         u64 rx_discards;                /* rdpc */
1099         u64 rx_unknown_protocol;        /* rupp */
1100         u64 tx_bytes;                   /* gotc */
1101         u64 tx_unicast;                 /* uptc */
1102         u64 tx_multicast;               /* mptc */
1103         u64 tx_broadcast;               /* bptc */
1104         u64 tx_discards;                /* tdpc */
1105         u64 tx_errors;                  /* tepc */
1106 };
1107
1108 /* Statistics collected per VEB per TC */
1109 struct i40e_veb_tc_stats {
1110         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1111         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1112         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1113         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1114 };
1115
1116 /* Statistics collected by the MAC */
1117 struct i40e_hw_port_stats {
1118         /* eth stats collected by the port */
1119         struct i40e_eth_stats eth;
1120
1121         /* additional port specific stats */
1122         u64 tx_dropped_link_down;       /* tdold */
1123         u64 crc_errors;                 /* crcerrs */
1124         u64 illegal_bytes;              /* illerrc */
1125         u64 error_bytes;                /* errbc */
1126         u64 mac_local_faults;           /* mlfc */
1127         u64 mac_remote_faults;          /* mrfc */
1128         u64 rx_length_errors;           /* rlec */
1129         u64 link_xon_rx;                /* lxonrxc */
1130         u64 link_xoff_rx;               /* lxoffrxc */
1131         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1132         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1133         u64 link_xon_tx;                /* lxontxc */
1134         u64 link_xoff_tx;               /* lxofftxc */
1135         u64 priority_xon_tx[8];         /* pxontxc[8] */
1136         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1137         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1138         u64 rx_size_64;                 /* prc64 */
1139         u64 rx_size_127;                /* prc127 */
1140         u64 rx_size_255;                /* prc255 */
1141         u64 rx_size_511;                /* prc511 */
1142         u64 rx_size_1023;               /* prc1023 */
1143         u64 rx_size_1522;               /* prc1522 */
1144         u64 rx_size_big;                /* prc9522 */
1145         u64 rx_undersize;               /* ruc */
1146         u64 rx_fragments;               /* rfc */
1147         u64 rx_oversize;                /* roc */
1148         u64 rx_jabber;                  /* rjc */
1149         u64 tx_size_64;                 /* ptc64 */
1150         u64 tx_size_127;                /* ptc127 */
1151         u64 tx_size_255;                /* ptc255 */
1152         u64 tx_size_511;                /* ptc511 */
1153         u64 tx_size_1023;               /* ptc1023 */
1154         u64 tx_size_1522;               /* ptc1522 */
1155         u64 tx_size_big;                /* ptc9522 */
1156         u64 mac_short_packet_dropped;   /* mspdc */
1157         u64 checksum_error;             /* xec */
1158         /* flow director stats */
1159         u64 fd_atr_match;
1160         u64 fd_sb_match;
1161         u64 fd_atr_tunnel_match;
1162         u32 fd_atr_status;
1163         u32 fd_sb_status;
1164         /* EEE LPI */
1165         u32 tx_lpi_status;
1166         u32 rx_lpi_status;
1167         u64 tx_lpi_count;               /* etlpic */
1168         u64 rx_lpi_count;               /* erlpic */
1169 };
1170
1171 /* Checksum and Shadow RAM pointers */
1172 #define I40E_SR_NVM_CONTROL_WORD                0x00
1173 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1174 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1175 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1176 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1177 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1178 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1179 #define I40E_SR_VPD_PTR                         0x2F
1180 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1181 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1182
1183 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1184 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1185 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1186 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1187 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1188
1189 /* Shadow RAM related */
1190 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1191 #define I40E_SR_WORDS_IN_1KB            512
1192 /* Checksum should be calculated such that after adding all the words,
1193  * including the checksum word itself, the sum should be 0xBABA.
1194  */
1195 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1196
1197 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1198
1199 enum i40e_switch_element_types {
1200         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1201         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1202         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1203         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1204         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1205         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1206         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1207         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1208         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1209 };
1210
1211 /* Supported EtherType filters */
1212 enum i40e_ether_type_index {
1213         I40E_ETHER_TYPE_1588            = 0,
1214         I40E_ETHER_TYPE_FIP             = 1,
1215         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1216         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1217         I40E_ETHER_TYPE_LLDP            = 4,
1218         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1219         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1220         I40E_ETHER_TYPE_QCN_CNM         = 7,
1221         I40E_ETHER_TYPE_8021X           = 8,
1222         I40E_ETHER_TYPE_ARP             = 9,
1223         I40E_ETHER_TYPE_RSV1            = 10,
1224         I40E_ETHER_TYPE_RSV2            = 11,
1225 };
1226
1227 /* Filter context base size is 1K */
1228 #define I40E_HASH_FILTER_BASE_SIZE      1024
1229 /* Supported Hash filter values */
1230 enum i40e_hash_filter_size {
1231         I40E_HASH_FILTER_SIZE_1K        = 0,
1232         I40E_HASH_FILTER_SIZE_2K        = 1,
1233         I40E_HASH_FILTER_SIZE_4K        = 2,
1234         I40E_HASH_FILTER_SIZE_8K        = 3,
1235         I40E_HASH_FILTER_SIZE_16K       = 4,
1236         I40E_HASH_FILTER_SIZE_32K       = 5,
1237         I40E_HASH_FILTER_SIZE_64K       = 6,
1238         I40E_HASH_FILTER_SIZE_128K      = 7,
1239         I40E_HASH_FILTER_SIZE_256K      = 8,
1240         I40E_HASH_FILTER_SIZE_512K      = 9,
1241         I40E_HASH_FILTER_SIZE_1M        = 10,
1242 };
1243
1244 /* DMA context base size is 0.5K */
1245 #define I40E_DMA_CNTX_BASE_SIZE         512
1246 /* Supported DMA context values */
1247 enum i40e_dma_cntx_size {
1248         I40E_DMA_CNTX_SIZE_512          = 0,
1249         I40E_DMA_CNTX_SIZE_1K           = 1,
1250         I40E_DMA_CNTX_SIZE_2K           = 2,
1251         I40E_DMA_CNTX_SIZE_4K           = 3,
1252         I40E_DMA_CNTX_SIZE_8K           = 4,
1253         I40E_DMA_CNTX_SIZE_16K          = 5,
1254         I40E_DMA_CNTX_SIZE_32K          = 6,
1255         I40E_DMA_CNTX_SIZE_64K          = 7,
1256         I40E_DMA_CNTX_SIZE_128K         = 8,
1257         I40E_DMA_CNTX_SIZE_256K         = 9,
1258 };
1259
1260 /* Supported Hash look up table (LUT) sizes */
1261 enum i40e_hash_lut_size {
1262         I40E_HASH_LUT_SIZE_128          = 0,
1263         I40E_HASH_LUT_SIZE_512          = 1,
1264 };
1265
1266 /* Structure to hold a per PF filter control settings */
1267 struct i40e_filter_control_settings {
1268         /* number of PE Quad Hash filter buckets */
1269         enum i40e_hash_filter_size pe_filt_num;
1270         /* number of PE Quad Hash contexts */
1271         enum i40e_dma_cntx_size pe_cntx_num;
1272         /* number of FCoE filter buckets */
1273         enum i40e_hash_filter_size fcoe_filt_num;
1274         /* number of FCoE DDP contexts */
1275         enum i40e_dma_cntx_size fcoe_cntx_num;
1276         /* size of the Hash LUT */
1277         enum i40e_hash_lut_size hash_lut_size;
1278         /* enable FDIR filters for PF and its VFs */
1279         bool enable_fdir;
1280         /* enable Ethertype filters for PF and its VFs */
1281         bool enable_ethtype;
1282         /* enable MAC/VLAN filters for PF and its VFs */
1283         bool enable_macvlan;
1284 };
1285
1286 /* Structure to hold device level control filter counts */
1287 struct i40e_control_filter_stats {
1288         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1289         u16 etype_used;       /* Used perfect EtherType filters */
1290         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1291         u16 etype_free;       /* Un-used perfect EtherType filters */
1292 };
1293
1294 enum i40e_reset_type {
1295         I40E_RESET_POR          = 0,
1296         I40E_RESET_CORER        = 1,
1297         I40E_RESET_GLOBR        = 2,
1298         I40E_RESET_EMPR         = 3,
1299 };
1300
1301 /* RSS Hash Table Size */
1302 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1303 #endif /* _I40E_TYPE_H_ */