drivers/net/ethernet/intel/i40evf/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2015 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36
  37 /* Device IDs */
  38 #define I40E_DEV_ID_SFP_XL710           0x1572
  39 #define I40E_DEV_ID_QEMU                0x1574
  40 #define I40E_DEV_ID_KX_A                0x157F
  41 #define I40E_DEV_ID_KX_B                0x1580
  42 #define I40E_DEV_ID_KX_C                0x1581
  43 #define I40E_DEV_ID_QSFP_A              0x1583
  44 #define I40E_DEV_ID_QSFP_B              0x1584
  45 #define I40E_DEV_ID_QSFP_C              0x1585
  46 #define I40E_DEV_ID_10G_BASE_T          0x1586
  47 #define I40E_DEV_ID_20G_KR2             0x1587
  48 #define I40E_DEV_ID_VF                  0x154C
  49 #define I40E_DEV_ID_VF_HV               0x1571
  50 #define I40E_DEV_ID_SFP_X722            0x37D0
  51 #define I40E_DEV_ID_1G_BASE_T_X722      0x37D1
  52 #define I40E_DEV_ID_10G_BASE_T_X722     0x37D2
  53 #define I40E_DEV_ID_X722_VF             0x37CD
  54 #define I40E_DEV_ID_X722_VF_HV          0x37D9
  55
  56 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  57                                          (d) == I40E_DEV_ID_QSFP_B  || \
  58                                          (d) == I40E_DEV_ID_QSFP_C)
  59
  60 /* I40E_MASK is a macro used on 32 bit registers */
  61 #define I40E_MASK(mask, shift) (mask << shift)
  62
  63 #define I40E_MAX_VSI_QP                 16
  64 #define I40E_MAX_VF_VSI                 3
  65 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  66 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  67
  68 /* Max default timeout in ms, */
  69 #define I40E_MAX_NVM_TIMEOUT            18000
  70
  71 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  72 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  73
  74 /* forward declaration */
  75 struct i40e_hw;
  76 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  77
  78 /* Data type manipulation macros. */
  79
  80 #define I40E_DESC_UNUSED(R)     \
  81         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  82         (R)->next_to_clean - (R)->next_to_use - 1)
  83
  84 /* bitfields for Tx queue mapping in QTX_CTL */
  85 #define I40E_QTX_CTL_VF_QUEUE   0x0
  86 #define I40E_QTX_CTL_VM_QUEUE   0x1
  87 #define I40E_QTX_CTL_PF_QUEUE   0x2
  88
  89 /* debug masks - set these bits in hw->debug_mask to control output */
  90 enum i40e_debug_mask {
  91         I40E_DEBUG_INIT                 = 0x00000001,
  92         I40E_DEBUG_RELEASE              = 0x00000002,
  93
  94         I40E_DEBUG_LINK                 = 0x00000010,
  95         I40E_DEBUG_PHY                  = 0x00000020,
  96         I40E_DEBUG_HMC                  = 0x00000040,
  97         I40E_DEBUG_NVM                  = 0x00000080,
  98         I40E_DEBUG_LAN                  = 0x00000100,
  99         I40E_DEBUG_FLOW                 = 0x00000200,
 100         I40E_DEBUG_DCB                  = 0x00000400,
 101         I40E_DEBUG_DIAG                 = 0x00000800,
 102         I40E_DEBUG_FD                   = 0x00001000,
 103
 104         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 105         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 106         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 107         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 108         I40E_DEBUG_AQ                   = 0x0F000000,
 109
 110         I40E_DEBUG_USER                 = 0xF0000000,
 111
 112         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 113 };
 114
 115 /* These are structs for managing the hardware information and the operations.
 116  * The structures of function pointers are filled out at init time when we
 117  * know for sure exactly which hardware we're working with.  This gives us the
 118  * flexibility of using the same main driver code but adapting to slightly
 119  * different hardware needs as new parts are developed.  For this architecture,
 120  * the Firmware and AdminQ are intended to insulate the driver from most of the
 121  * future changes, but these structures will also do part of the job.
 122  */
 123 enum i40e_mac_type {
 124         I40E_MAC_UNKNOWN = 0,
 125         I40E_MAC_X710,
 126         I40E_MAC_XL710,
 127         I40E_MAC_VF,
 128         I40E_MAC_X722,
 129         I40E_MAC_X722_VF,
 130         I40E_MAC_GENERIC,
 131 };
 132
 133 enum i40e_media_type {
 134         I40E_MEDIA_TYPE_UNKNOWN = 0,
 135         I40E_MEDIA_TYPE_FIBER,
 136         I40E_MEDIA_TYPE_BASET,
 137         I40E_MEDIA_TYPE_BACKPLANE,
 138         I40E_MEDIA_TYPE_CX4,
 139         I40E_MEDIA_TYPE_DA,
 140         I40E_MEDIA_TYPE_VIRTUAL
 141 };
 142
 143 enum i40e_fc_mode {
 144         I40E_FC_NONE = 0,
 145         I40E_FC_RX_PAUSE,
 146         I40E_FC_TX_PAUSE,
 147         I40E_FC_FULL,
 148         I40E_FC_PFC,
 149         I40E_FC_DEFAULT
 150 };
 151
 152 enum i40e_set_fc_aq_failures {
 153         I40E_SET_FC_AQ_FAIL_NONE = 0,
 154         I40E_SET_FC_AQ_FAIL_GET = 1,
 155         I40E_SET_FC_AQ_FAIL_SET = 2,
 156         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 157         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 158 };
 159
 160 enum i40e_vsi_type {
 161         I40E_VSI_MAIN = 0,
 162         I40E_VSI_VMDQ1,
 163         I40E_VSI_VMDQ2,
 164         I40E_VSI_CTRL,
 165         I40E_VSI_FCOE,
 166         I40E_VSI_MIRROR,
 167         I40E_VSI_SRIOV,
 168         I40E_VSI_FDIR,
 169         I40E_VSI_TYPE_UNKNOWN
 170 };
 171
 172 enum i40e_queue_type {
 173         I40E_QUEUE_TYPE_RX = 0,
 174         I40E_QUEUE_TYPE_TX,
 175         I40E_QUEUE_TYPE_PE_CEQ,
 176         I40E_QUEUE_TYPE_UNKNOWN
 177 };
 178
 179 struct i40e_link_status {
 180         enum i40e_aq_phy_type phy_type;
 181         enum i40e_aq_link_speed link_speed;
 182         u8 link_info;
 183         u8 an_info;
 184         u8 ext_info;
 185         u8 loopback;
 186         /* is Link Status Event notification to SW enabled */
 187         bool lse_enable;
 188         u16 max_frame_size;
 189         bool crc_enable;
 190         u8 pacing;
 191         u8 requested_speeds;
 192 };
 193
 194 struct i40e_phy_info {
 195         struct i40e_link_status link_info;
 196         struct i40e_link_status link_info_old;
 197         u32 autoneg_advertised;
 198         u32 phy_id;
 199         u32 module_type;
 200         bool get_link_info;
 201         enum i40e_media_type media_type;
 202 };
 203
 204 #define I40E_HW_CAP_MAX_GPIO                    30
 205 /* Capabilities of a PF or a VF or the whole device */
 206 struct i40e_hw_capabilities {
 207         u32  switch_mode;
 208 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 209 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 210 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 211
 212         u32  management_mode;
 213         u32  npar_enable;
 214         u32  os2bmc;
 215         u32  valid_functions;
 216         bool sr_iov_1_1;
 217         bool vmdq;
 218         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 219         bool evb_802_1_qbh; /* Bridge Port Extension */
 220         bool dcb;
 221         bool fcoe;
 222         bool iscsi; /* Indicates iSCSI enabled */
 223         bool flex10_enable;
 224         bool flex10_capable;
 225         u32  flex10_mode;
 226 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 227 #define I40E_FLEX10_MODE_DCC            0x1
 228 #define I40E_FLEX10_MODE_DCI            0x2
 229
 230         u32 flex10_status;
 231 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 232 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 233
 234         bool mgmt_cem;
 235         bool ieee_1588;
 236         bool iwarp;
 237         bool fd;
 238         u32 fd_filters_guaranteed;
 239         u32 fd_filters_best_effort;
 240         bool rss;
 241         u32 rss_table_size;
 242         u32 rss_table_entry_width;
 243         bool led[I40E_HW_CAP_MAX_GPIO];
 244         bool sdp[I40E_HW_CAP_MAX_GPIO];
 245         u32 nvm_image_type;
 246         u32 num_flow_director_filters;
 247         u32 num_vfs;
 248         u32 vf_base_id;
 249         u32 num_vsis;
 250         u32 num_rx_qp;
 251         u32 num_tx_qp;
 252         u32 base_queue;
 253         u32 num_msix_vectors;
 254         u32 num_msix_vectors_vf;
 255         u32 led_pin_num;
 256         u32 sdp_pin_num;
 257         u32 mdio_port_num;
 258         u32 mdio_port_mode;
 259         u8 rx_buf_chain_len;
 260         u32 enabled_tcmap;
 261         u32 maxtc;
 262         u64 wr_csr_prot;
 263 };
 264
 265 struct i40e_mac_info {
 266         enum i40e_mac_type type;
 267         u8 addr[ETH_ALEN];
 268         u8 perm_addr[ETH_ALEN];
 269         u8 san_addr[ETH_ALEN];
 270         u16 max_fcoeq;
 271 };
 272
 273 enum i40e_aq_resources_ids {
 274         I40E_NVM_RESOURCE_ID = 1
 275 };
 276
 277 enum i40e_aq_resource_access_type {
 278         I40E_RESOURCE_READ = 1,
 279         I40E_RESOURCE_WRITE
 280 };
 281
 282 struct i40e_nvm_info {
 283         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 284         u32 timeout;              /* [ms] */
 285         u16 sr_size;              /* Shadow RAM size in words */
 286         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 287         u16 version;              /* NVM package version */
 288         u32 eetrack;              /* NVM data version */
 289 };
 290
 291 /* definitions used in NVM update support */
 292
 293 enum i40e_nvmupd_cmd {
 294         I40E_NVMUPD_INVALID,
 295         I40E_NVMUPD_READ_CON,
 296         I40E_NVMUPD_READ_SNT,
 297         I40E_NVMUPD_READ_LCB,
 298         I40E_NVMUPD_READ_SA,
 299         I40E_NVMUPD_WRITE_ERA,
 300         I40E_NVMUPD_WRITE_CON,
 301         I40E_NVMUPD_WRITE_SNT,
 302         I40E_NVMUPD_WRITE_LCB,
 303         I40E_NVMUPD_WRITE_SA,
 304         I40E_NVMUPD_CSUM_CON,
 305         I40E_NVMUPD_CSUM_SA,
 306         I40E_NVMUPD_CSUM_LCB,
 307 };
 308
 309 enum i40e_nvmupd_state {
 310         I40E_NVMUPD_STATE_INIT,
 311         I40E_NVMUPD_STATE_READING,
 312         I40E_NVMUPD_STATE_WRITING
 313 };
 314
 315 /* nvm_access definition and its masks/shifts need to be accessible to
 316  * application, core driver, and shared code.  Where is the right file?
 317  */
 318 #define I40E_NVM_READ   0xB
 319 #define I40E_NVM_WRITE  0xC
 320
 321 #define I40E_NVM_MOD_PNT_MASK 0xFF
 322
 323 #define I40E_NVM_TRANS_SHIFT    8
 324 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 325 #define I40E_NVM_CON            0x0
 326 #define I40E_NVM_SNT            0x1
 327 #define I40E_NVM_LCB            0x2
 328 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 329 #define I40E_NVM_ERA            0x4
 330 #define I40E_NVM_CSUM           0x8
 331
 332 #define I40E_NVM_ADAPT_SHIFT    16
 333 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 334
 335 #define I40E_NVMUPD_MAX_DATA    4096
 336 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 337
 338 struct i40e_nvm_access {
 339         u32 command;
 340         u32 config;
 341         u32 offset;     /* in bytes */
 342         u32 data_size;  /* in bytes */
 343         u8 data[1];
 344 };
 345
 346 /* PCI bus types */
 347 enum i40e_bus_type {
 348         i40e_bus_type_unknown = 0,
 349         i40e_bus_type_pci,
 350         i40e_bus_type_pcix,
 351         i40e_bus_type_pci_express,
 352         i40e_bus_type_reserved
 353 };
 354
 355 /* PCI bus speeds */
 356 enum i40e_bus_speed {
 357         i40e_bus_speed_unknown  = 0,
 358         i40e_bus_speed_33       = 33,
 359         i40e_bus_speed_66       = 66,
 360         i40e_bus_speed_100      = 100,
 361         i40e_bus_speed_120      = 120,
 362         i40e_bus_speed_133      = 133,
 363         i40e_bus_speed_2500     = 2500,
 364         i40e_bus_speed_5000     = 5000,
 365         i40e_bus_speed_8000     = 8000,
 366         i40e_bus_speed_reserved
 367 };
 368
 369 /* PCI bus widths */
 370 enum i40e_bus_width {
 371         i40e_bus_width_unknown  = 0,
 372         i40e_bus_width_pcie_x1  = 1,
 373         i40e_bus_width_pcie_x2  = 2,
 374         i40e_bus_width_pcie_x4  = 4,
 375         i40e_bus_width_pcie_x8  = 8,
 376         i40e_bus_width_32       = 32,
 377         i40e_bus_width_64       = 64,
 378         i40e_bus_width_reserved
 379 };
 380
 381 /* Bus parameters */
 382 struct i40e_bus_info {
 383         enum i40e_bus_speed speed;
 384         enum i40e_bus_width width;
 385         enum i40e_bus_type type;
 386
 387         u16 func;
 388         u16 device;
 389         u16 lan_id;
 390 };
 391
 392 /* Flow control (FC) parameters */
 393 struct i40e_fc_info {
 394         enum i40e_fc_mode current_mode; /* FC mode in effect */
 395         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 396 };
 397
 398 #define I40E_MAX_TRAFFIC_CLASS          8
 399 #define I40E_MAX_USER_PRIORITY          8
 400 #define I40E_DCBX_MAX_APPS              32
 401 #define I40E_LLDPDU_SIZE                1500
 402
 403 /* IEEE 802.1Qaz ETS Configuration data */
 404 struct i40e_ieee_ets_config {
 405         u8 willing;
 406         u8 cbs;
 407         u8 maxtcs;
 408         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 409         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 410         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 411 };
 412
 413 /* IEEE 802.1Qaz ETS Recommendation data */
 414 struct i40e_ieee_ets_recommend {
 415         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 416         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 417         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 418 };
 419
 420 /* IEEE 802.1Qaz PFC Configuration data */
 421 struct i40e_ieee_pfc_config {
 422         u8 willing;
 423         u8 mbc;
 424         u8 pfccap;
 425         u8 pfcenable;
 426 };
 427
 428 /* IEEE 802.1Qaz Application Priority data */
 429 struct i40e_ieee_app_priority_table {
 430         u8  priority;
 431         u8  selector;
 432         u16 protocolid;
 433 };
 434
 435 struct i40e_dcbx_config {
 436         u32 numapps;
 437         u32 tlv_status; /* CEE mode TLV status */
 438         struct i40e_ieee_ets_config etscfg;
 439         struct i40e_ieee_ets_recommend etsrec;
 440         struct i40e_ieee_pfc_config pfc;
 441         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 442 };
 443
 444 /* Port hardware description */
 445 struct i40e_hw {
 446         u8 __iomem *hw_addr;
 447         void *back;
 448
 449         /* subsystem structs */
 450         struct i40e_phy_info phy;
 451         struct i40e_mac_info mac;
 452         struct i40e_bus_info bus;
 453         struct i40e_nvm_info nvm;
 454         struct i40e_fc_info fc;
 455
 456         /* pci info */
 457         u16 device_id;
 458         u16 vendor_id;
 459         u16 subsystem_device_id;
 460         u16 subsystem_vendor_id;
 461         u8 revision_id;
 462         u8 port;
 463         bool adapter_stopped;
 464
 465         /* capabilities for entire device and PCI func */
 466         struct i40e_hw_capabilities dev_caps;
 467         struct i40e_hw_capabilities func_caps;
 468
 469         /* Flow Director shared filter space */
 470         u16 fdir_shared_filter_count;
 471
 472         /* device profile info */
 473         u8  pf_id;
 474         u16 main_vsi_seid;
 475
 476         /* for multi-function MACs */
 477         u16 partition_id;
 478         u16 num_partitions;
 479         u16 num_ports;
 480
 481         /* Closest numa node to the device */
 482         u16 numa_node;
 483
 484         /* Admin Queue info */
 485         struct i40e_adminq_info aq;
 486
 487         /* state of nvm update process */
 488         enum i40e_nvmupd_state nvmupd_state;
 489
 490         /* HMC info */
 491         struct i40e_hmc_info hmc; /* HMC info struct */
 492
 493         /* LLDP/DCBX Status */
 494         u16 dcbx_status;
 495
 496         /* DCBX info */
 497         struct i40e_dcbx_config local_dcbx_config;
 498         struct i40e_dcbx_config remote_dcbx_config;
 499
 500         /* debug mask */
 501         u32 debug_mask;
 502         char err_str[16];
 503 };
 504
 505 static inline bool i40e_is_vf(struct i40e_hw *hw)
 506 {
 507         return (hw->mac.type == I40E_MAC_VF ||
 508                 hw->mac.type == I40E_MAC_X722_VF);
 509 }
 510
 511 struct i40e_driver_version {
 512         u8 major_version;
 513         u8 minor_version;
 514         u8 build_version;
 515         u8 subbuild_version;
 516         u8 driver_string[32];
 517 };
 518
 519 /* RX Descriptors */
 520 union i40e_16byte_rx_desc {
 521         struct {
 522                 __le64 pkt_addr; /* Packet buffer address */
 523                 __le64 hdr_addr; /* Header buffer address */
 524         } read;
 525         struct {
 526                 struct {
 527                         struct {
 528                                 union {
 529                                         __le16 mirroring_status;
 530                                         __le16 fcoe_ctx_id;
 531                                 } mirr_fcoe;
 532                                 __le16 l2tag1;
 533                         } lo_dword;
 534                         union {
 535                                 __le32 rss; /* RSS Hash */
 536                                 __le32 fd_id; /* Flow director filter id */
 537                                 __le32 fcoe_param; /* FCoE DDP Context id */
 538                         } hi_dword;
 539                 } qword0;
 540                 struct {
 541                         /* ext status/error/pktype/length */
 542                         __le64 status_error_len;
 543                 } qword1;
 544         } wb;  /* writeback */
 545 };
 546
 547 union i40e_32byte_rx_desc {
 548         struct {
 549                 __le64  pkt_addr; /* Packet buffer address */
 550                 __le64  hdr_addr; /* Header buffer address */
 551                         /* bit 0 of hdr_buffer_addr is DD bit */
 552                 __le64  rsvd1;
 553                 __le64  rsvd2;
 554         } read;
 555         struct {
 556                 struct {
 557                         struct {
 558                                 union {
 559                                         __le16 mirroring_status;
 560                                         __le16 fcoe_ctx_id;
 561                                 } mirr_fcoe;
 562                                 __le16 l2tag1;
 563                         } lo_dword;
 564                         union {
 565                                 __le32 rss; /* RSS Hash */
 566                                 __le32 fcoe_param; /* FCoE DDP Context id */
 567                                 /* Flow director filter id in case of
 568                                  * Programming status desc WB
 569                                  */
 570                                 __le32 fd_id;
 571                         } hi_dword;
 572                 } qword0;
 573                 struct {
 574                         /* status/error/pktype/length */
 575                         __le64 status_error_len;
 576                 } qword1;
 577                 struct {
 578                         __le16 ext_status; /* extended status */
 579                         __le16 rsvd;
 580                         __le16 l2tag2_1;
 581                         __le16 l2tag2_2;
 582                 } qword2;
 583                 struct {
 584                         union {
 585                                 __le32 flex_bytes_lo;
 586                                 __le32 pe_status;
 587                         } lo_dword;
 588                         union {
 589                                 __le32 flex_bytes_hi;
 590                                 __le32 fd_id;
 591                         } hi_dword;
 592                 } qword3;
 593         } wb;  /* writeback */
 594 };
 595
 596 enum i40e_rx_desc_status_bits {
 597         /* Note: These are predefined bit offsets */
 598         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 599         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 600         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 601         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 602         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 603         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 604         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 605         /* Note: Bit 8 is reserved in X710 and XL710 */
 606         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 607         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 608         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 609         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 610         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 611         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 612         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 613         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 614          * UDP header
 615          */
 616         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 617         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 618 };
 619
 620 #define I40E_RXD_QW1_STATUS_SHIFT       0
 621 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 622                                          << I40E_RXD_QW1_STATUS_SHIFT)
 623
 624 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 625 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 626                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 627
 628 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 629 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 630                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 631
 632 enum i40e_rx_desc_fltstat_values {
 633         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 634         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 635         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 636         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 637 };
 638
 639 #define I40E_RXD_QW1_ERROR_SHIFT        19
 640 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 641
 642 enum i40e_rx_desc_error_bits {
 643         /* Note: These are predefined bit offsets */
 644         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 645         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 646         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 647         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 648         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 649         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 650         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 651         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 652         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 653 };
 654
 655 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 656         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 657         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 658         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 659         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 660         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 661 };
 662
 663 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 664 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 665
 666 /* Packet type non-ip values */
 667 enum i40e_rx_l2_ptype {
 668         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 669         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 670         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 671         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 672         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 673         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 674         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 675         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 676         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 677         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 678         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 679         I40E_RX_PTYPE_L2_ARP                            = 11,
 680         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 681         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 682         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 683         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 684         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 685         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 686         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 687         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 688         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 689         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 690         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 691         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 692         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 693         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 694 };
 695
 696 struct i40e_rx_ptype_decoded {
 697         u32 ptype:8;
 698         u32 known:1;
 699         u32 outer_ip:1;
 700         u32 outer_ip_ver:1;
 701         u32 outer_frag:1;
 702         u32 tunnel_type:3;
 703         u32 tunnel_end_prot:2;
 704         u32 tunnel_end_frag:1;
 705         u32 inner_prot:4;
 706         u32 payload_layer:3;
 707 };
 708
 709 enum i40e_rx_ptype_outer_ip {
 710         I40E_RX_PTYPE_OUTER_L2  = 0,
 711         I40E_RX_PTYPE_OUTER_IP  = 1
 712 };
 713
 714 enum i40e_rx_ptype_outer_ip_ver {
 715         I40E_RX_PTYPE_OUTER_NONE        = 0,
 716         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 717         I40E_RX_PTYPE_OUTER_IPV6        = 1
 718 };
 719
 720 enum i40e_rx_ptype_outer_fragmented {
 721         I40E_RX_PTYPE_NOT_FRAG  = 0,
 722         I40E_RX_PTYPE_FRAG      = 1
 723 };
 724
 725 enum i40e_rx_ptype_tunnel_type {
 726         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 727         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 728         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 729         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 730         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 731 };
 732
 733 enum i40e_rx_ptype_tunnel_end_prot {
 734         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 735         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 736         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 737 };
 738
 739 enum i40e_rx_ptype_inner_prot {
 740         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 741         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 742         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 743         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 744         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 745         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 746 };
 747
 748 enum i40e_rx_ptype_payload_layer {
 749         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 750         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 751         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 752         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 753 };
 754
 755 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 756 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 757                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 758
 759 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 760 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 761                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 762
 763 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 764 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 765
 766 enum i40e_rx_desc_ext_status_bits {
 767         /* Note: These are predefined bit offsets */
 768         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 769         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 770         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 771         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 772         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 773         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 774         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 775 };
 776
 777 enum i40e_rx_desc_pe_status_bits {
 778         /* Note: These are predefined bit offsets */
 779         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 780         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 781         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 782         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 783         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 784         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 785         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 786         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 787         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 788 };
 789
 790 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 791 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 792
 793 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 794 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 795                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 796
 797 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 798 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 799                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 800
 801 enum i40e_rx_prog_status_desc_status_bits {
 802         /* Note: These are predefined bit offsets */
 803         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 804         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 805 };
 806
 807 enum i40e_rx_prog_status_desc_prog_id_masks {
 808         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 809         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 810         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 811 };
 812
 813 enum i40e_rx_prog_status_desc_error_bits {
 814         /* Note: These are predefined bit offsets */
 815         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 816         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 817         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 818         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 819 };
 820
 821 /* TX Descriptor */
 822 struct i40e_tx_desc {
 823         __le64 buffer_addr; /* Address of descriptor's data buf */
 824         __le64 cmd_type_offset_bsz;
 825 };
 826
 827 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 828 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 829
 830 enum i40e_tx_desc_dtype_value {
 831         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 832         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 833         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 834         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 835         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 836         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 837         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 838         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 839         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 840         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 841 };
 842
 843 #define I40E_TXD_QW1_CMD_SHIFT  4
 844 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 845
 846 enum i40e_tx_desc_cmd_bits {
 847         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 848         I40E_TX_DESC_CMD_RS                     = 0x0002,
 849         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 850         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 851         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 852         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 853         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 854         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 855         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 856         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 857         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 858         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 859         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 860         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 861         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 862         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 863         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 864         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 865 };
 866
 867 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 868 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 869                                          I40E_TXD_QW1_OFFSET_SHIFT)
 870
 871 enum i40e_tx_desc_length_fields {
 872         /* Note: These are predefined bit offsets */
 873         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 874         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 875         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 876 };
 877
 878 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 879 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 880                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 881
 882 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 883 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 884
 885 /* Context descriptors */
 886 struct i40e_tx_context_desc {
 887         __le32 tunneling_params;
 888         __le16 l2tag2;
 889         __le16 rsvd;
 890         __le64 type_cmd_tso_mss;
 891 };
 892
 893 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 894 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 895
 896 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 897 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 898
 899 enum i40e_tx_ctx_desc_cmd_bits {
 900         I40E_TX_CTX_DESC_TSO            = 0x01,
 901         I40E_TX_CTX_DESC_TSYN           = 0x02,
 902         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 903         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 904         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 905         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 906         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 907         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 908         I40E_TX_CTX_DESC_SWPE           = 0x40
 909 };
 910
 911 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 912 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 913                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 914
 915 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 916 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 917                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 918
 919 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 920 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 921
 922 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 923 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 924                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 925
 926 enum i40e_tx_ctx_desc_eipt_offload {
 927         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 928         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 929         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 930         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 931 };
 932
 933 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 934 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 935                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 936
 937 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 938 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 939
 940 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
 941 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 942
 943 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 944 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
 945                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 946
 947 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 948
 949 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 950 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 951                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 952
 953 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 954 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 955                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 956
 957 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
 958 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
 959 struct i40e_filter_program_desc {
 960         __le32 qindex_flex_ptype_vsi;
 961         __le32 rsvd;
 962         __le32 dtype_cmd_cntindex;
 963         __le32 fd_id;
 964 };
 965 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 966 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 967                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 968 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 969 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 970                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 971 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 972 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 973                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 974
 975 /* Packet Classifier Types for filters */
 976 enum i40e_filter_pctype {
 977         /* Note: Values 0-28 are reserved for future use.
 978          * Value 29, 30, 32 are not supported on XL710 and X710.
 979          */
 980         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
 981         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
 982         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 983         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
 984         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 985         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 986         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 987         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 988         /* Note: Values 37-38 are reserved for future use.
 989          * Value 39, 40, 42 are not supported on XL710 and X710.
 990          */
 991         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
 992         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
 993         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 994         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
 995         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 996         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 997         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 998         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 999         /* Note: Value 47 is reserved for future use */
1000         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1001         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1002         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1003         /* Note: Values 51-62 are reserved for future use */
1004         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1005 };
1006
1007 enum i40e_filter_program_desc_dest {
1008         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1009         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1010         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1011 };
1012
1013 enum i40e_filter_program_desc_fd_status {
1014         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1015         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1016         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1017         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1018 };
1019
1020 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1021 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1022                                        BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1023
1024 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1025 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1026                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1027
1028 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1029 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1030
1031 enum i40e_filter_program_desc_pcmd {
1032         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1033         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1034 };
1035
1036 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1037 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1038
1039 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1040 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1041
1042 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1043                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1044 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1045                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1046
1047 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1048 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1049                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1050
1051 enum i40e_filter_type {
1052         I40E_FLOW_DIRECTOR_FLTR = 0,
1053         I40E_PE_QUAD_HASH_FLTR = 1,
1054         I40E_ETHERTYPE_FLTR,
1055         I40E_FCOE_CTX_FLTR,
1056         I40E_MAC_VLAN_FLTR,
1057         I40E_HASH_FLTR
1058 };
1059
1060 struct i40e_vsi_context {
1061         u16 seid;
1062         u16 uplink_seid;
1063         u16 vsi_number;
1064         u16 vsis_allocated;
1065         u16 vsis_unallocated;
1066         u16 flags;
1067         u8 pf_num;
1068         u8 vf_num;
1069         u8 connection_type;
1070         struct i40e_aqc_vsi_properties_data info;
1071 };
1072
1073 struct i40e_veb_context {
1074         u16 seid;
1075         u16 uplink_seid;
1076         u16 veb_number;
1077         u16 vebs_allocated;
1078         u16 vebs_unallocated;
1079         u16 flags;
1080         struct i40e_aqc_get_veb_parameters_completion info;
1081 };
1082
1083 /* Statistics collected by each port, VSI, VEB, and S-channel */
1084 struct i40e_eth_stats {
1085         u64 rx_bytes;                   /* gorc */
1086         u64 rx_unicast;                 /* uprc */
1087         u64 rx_multicast;               /* mprc */
1088         u64 rx_broadcast;               /* bprc */
1089         u64 rx_discards;                /* rdpc */
1090         u64 rx_unknown_protocol;        /* rupp */
1091         u64 tx_bytes;                   /* gotc */
1092         u64 tx_unicast;                 /* uptc */
1093         u64 tx_multicast;               /* mptc */
1094         u64 tx_broadcast;               /* bptc */
1095         u64 tx_discards;                /* tdpc */
1096         u64 tx_errors;                  /* tepc */
1097 };
1098
1099 /* Statistics collected per VEB per TC */
1100 struct i40e_veb_tc_stats {
1101         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1102         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1103         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1104         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1105 };
1106
1107 /* Statistics collected by the MAC */
1108 struct i40e_hw_port_stats {
1109         /* eth stats collected by the port */
1110         struct i40e_eth_stats eth;
1111
1112         /* additional port specific stats */
1113         u64 tx_dropped_link_down;       /* tdold */
1114         u64 crc_errors;                 /* crcerrs */
1115         u64 illegal_bytes;              /* illerrc */
1116         u64 error_bytes;                /* errbc */
1117         u64 mac_local_faults;           /* mlfc */
1118         u64 mac_remote_faults;          /* mrfc */
1119         u64 rx_length_errors;           /* rlec */
1120         u64 link_xon_rx;                /* lxonrxc */
1121         u64 link_xoff_rx;               /* lxoffrxc */
1122         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1123         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1124         u64 link_xon_tx;                /* lxontxc */
1125         u64 link_xoff_tx;               /* lxofftxc */
1126         u64 priority_xon_tx[8];         /* pxontxc[8] */
1127         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1128         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1129         u64 rx_size_64;                 /* prc64 */
1130         u64 rx_size_127;                /* prc127 */
1131         u64 rx_size_255;                /* prc255 */
1132         u64 rx_size_511;                /* prc511 */
1133         u64 rx_size_1023;               /* prc1023 */
1134         u64 rx_size_1522;               /* prc1522 */
1135         u64 rx_size_big;                /* prc9522 */
1136         u64 rx_undersize;               /* ruc */
1137         u64 rx_fragments;               /* rfc */
1138         u64 rx_oversize;                /* roc */
1139         u64 rx_jabber;                  /* rjc */
1140         u64 tx_size_64;                 /* ptc64 */
1141         u64 tx_size_127;                /* ptc127 */
1142         u64 tx_size_255;                /* ptc255 */
1143         u64 tx_size_511;                /* ptc511 */
1144         u64 tx_size_1023;               /* ptc1023 */
1145         u64 tx_size_1522;               /* ptc1522 */
1146         u64 tx_size_big;                /* ptc9522 */
1147         u64 mac_short_packet_dropped;   /* mspdc */
1148         u64 checksum_error;             /* xec */
1149         /* flow director stats */
1150         u64 fd_atr_match;
1151         u64 fd_sb_match;
1152         u64 fd_atr_tunnel_match;
1153         u32 fd_atr_status;
1154         u32 fd_sb_status;
1155         /* EEE LPI */
1156         u32 tx_lpi_status;
1157         u32 rx_lpi_status;
1158         u64 tx_lpi_count;               /* etlpic */
1159         u64 rx_lpi_count;               /* erlpic */
1160 };
1161
1162 /* Checksum and Shadow RAM pointers */
1163 #define I40E_SR_NVM_CONTROL_WORD                0x00
1164 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1165 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1166 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1167 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1168 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1169 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1170 #define I40E_SR_VPD_PTR                         0x2F
1171 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1172 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1173
1174 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1175 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1176 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1177 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1178 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1179
1180 /* Shadow RAM related */
1181 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1182 #define I40E_SR_WORDS_IN_1KB            512
1183 /* Checksum should be calculated such that after adding all the words,
1184  * including the checksum word itself, the sum should be 0xBABA.
1185  */
1186 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1187
1188 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1189
1190 enum i40e_switch_element_types {
1191         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1192         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1193         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1194         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1195         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1196         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1197         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1198         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1199         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1200 };
1201
1202 /* Supported EtherType filters */
1203 enum i40e_ether_type_index {
1204         I40E_ETHER_TYPE_1588            = 0,
1205         I40E_ETHER_TYPE_FIP             = 1,
1206         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1207         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1208         I40E_ETHER_TYPE_LLDP            = 4,
1209         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1210         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1211         I40E_ETHER_TYPE_QCN_CNM         = 7,
1212         I40E_ETHER_TYPE_8021X           = 8,
1213         I40E_ETHER_TYPE_ARP             = 9,
1214         I40E_ETHER_TYPE_RSV1            = 10,
1215         I40E_ETHER_TYPE_RSV2            = 11,
1216 };
1217
1218 /* Filter context base size is 1K */
1219 #define I40E_HASH_FILTER_BASE_SIZE      1024
1220 /* Supported Hash filter values */
1221 enum i40e_hash_filter_size {
1222         I40E_HASH_FILTER_SIZE_1K        = 0,
1223         I40E_HASH_FILTER_SIZE_2K        = 1,
1224         I40E_HASH_FILTER_SIZE_4K        = 2,
1225         I40E_HASH_FILTER_SIZE_8K        = 3,
1226         I40E_HASH_FILTER_SIZE_16K       = 4,
1227         I40E_HASH_FILTER_SIZE_32K       = 5,
1228         I40E_HASH_FILTER_SIZE_64K       = 6,
1229         I40E_HASH_FILTER_SIZE_128K      = 7,
1230         I40E_HASH_FILTER_SIZE_256K      = 8,
1231         I40E_HASH_FILTER_SIZE_512K      = 9,
1232         I40E_HASH_FILTER_SIZE_1M        = 10,
1233 };
1234
1235 /* DMA context base size is 0.5K */
1236 #define I40E_DMA_CNTX_BASE_SIZE         512
1237 /* Supported DMA context values */
1238 enum i40e_dma_cntx_size {
1239         I40E_DMA_CNTX_SIZE_512          = 0,
1240         I40E_DMA_CNTX_SIZE_1K           = 1,
1241         I40E_DMA_CNTX_SIZE_2K           = 2,
1242         I40E_DMA_CNTX_SIZE_4K           = 3,
1243         I40E_DMA_CNTX_SIZE_8K           = 4,
1244         I40E_DMA_CNTX_SIZE_16K          = 5,
1245         I40E_DMA_CNTX_SIZE_32K          = 6,
1246         I40E_DMA_CNTX_SIZE_64K          = 7,
1247         I40E_DMA_CNTX_SIZE_128K         = 8,
1248         I40E_DMA_CNTX_SIZE_256K         = 9,
1249 };
1250
1251 /* Supported Hash look up table (LUT) sizes */
1252 enum i40e_hash_lut_size {
1253         I40E_HASH_LUT_SIZE_128          = 0,
1254         I40E_HASH_LUT_SIZE_512          = 1,
1255 };
1256
1257 /* Structure to hold a per PF filter control settings */
1258 struct i40e_filter_control_settings {
1259         /* number of PE Quad Hash filter buckets */
1260         enum i40e_hash_filter_size pe_filt_num;
1261         /* number of PE Quad Hash contexts */
1262         enum i40e_dma_cntx_size pe_cntx_num;
1263         /* number of FCoE filter buckets */
1264         enum i40e_hash_filter_size fcoe_filt_num;
1265         /* number of FCoE DDP contexts */
1266         enum i40e_dma_cntx_size fcoe_cntx_num;
1267         /* size of the Hash LUT */
1268         enum i40e_hash_lut_size hash_lut_size;
1269         /* enable FDIR filters for PF and its VFs */
1270         bool enable_fdir;
1271         /* enable Ethertype filters for PF and its VFs */
1272         bool enable_ethtype;
1273         /* enable MAC/VLAN filters for PF and its VFs */
1274         bool enable_macvlan;
1275 };
1276
1277 /* Structure to hold device level control filter counts */
1278 struct i40e_control_filter_stats {
1279         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1280         u16 etype_used;       /* Used perfect EtherType filters */
1281         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1282         u16 etype_free;       /* Un-used perfect EtherType filters */
1283 };
1284
1285 enum i40e_reset_type {
1286         I40E_RESET_POR          = 0,
1287         I40E_RESET_CORER        = 1,
1288         I40E_RESET_GLOBR        = 2,
1289         I40E_RESET_EMPR         = 3,
1290 };
1291
1292 /* RSS Hash Table Size */
1293 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1294 #endif /* _I40E_TYPE_H_ */