drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2015 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  30 {
  31         struct ixgbe_mac_info *mac = &hw->mac;
  32         struct ixgbe_phy_info *phy = &hw->phy;
  33
  34         /* Start with X540 invariants, since so simular */
  35         ixgbe_get_invariants_X540(hw);
  36
  37         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  38                 phy->ops.set_phy_power = NULL;
  39
  40         return 0;
  41 }
  42
  43 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  44  *  @hw: pointer to hardware structure
  45  **/
  46 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  47 {
  48         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  49
  50         if (hw->bus.lan_id) {
  51                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  52                 esdp |= IXGBE_ESDP_SDP1_DIR;
  53         }
  54         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  55         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  56         IXGBE_WRITE_FLUSH(hw);
  57 }
  58
  59 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
  60  *  @hw: pointer to hardware structure
  61  *
  62  *  Returns error code
  63  */
  64 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  65 {
  66         switch (hw->device_id) {
  67         case IXGBE_DEV_ID_X550EM_X_SFP:
  68                 /* set up for CS4227 usage */
  69                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
  70                 ixgbe_setup_mux_ctl(hw);
  71
  72                 return ixgbe_identify_module_generic(hw);
  73         case IXGBE_DEV_ID_X550EM_X_KX4:
  74                 hw->phy.type = ixgbe_phy_x550em_kx4;
  75                 break;
  76         case IXGBE_DEV_ID_X550EM_X_KR:
  77                 hw->phy.type = ixgbe_phy_x550em_kr;
  78                 break;
  79         case IXGBE_DEV_ID_X550EM_X_1G_T:
  80         case IXGBE_DEV_ID_X550EM_X_10G_T:
  81                 return ixgbe_identify_phy_generic(hw);
  82         default:
  83                 break;
  84         }
  85         return 0;
  86 }
  87
  88 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
  89                                      u32 device_type, u16 *phy_data)
  90 {
  91         return IXGBE_NOT_IMPLEMENTED;
  92 }
  93
  94 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
  95                                       u32 device_type, u16 phy_data)
  96 {
  97         return IXGBE_NOT_IMPLEMENTED;
  98 }
  99
 100 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 101  *  @hw: pointer to hardware structure
 102  *
 103  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 104  *  ixgbe_hw struct in order to set up EEPROM access.
 105  **/
 106 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 107 {
 108         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 109         u32 eec;
 110         u16 eeprom_size;
 111
 112         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 113                 eeprom->semaphore_delay = 10;
 114                 eeprom->type = ixgbe_flash;
 115
 116                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 117                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 118                                     IXGBE_EEC_SIZE_SHIFT);
 119                 eeprom->word_size = 1 << (eeprom_size +
 120                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 121
 122                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 123                        eeprom->type, eeprom->word_size);
 124         }
 125
 126         return 0;
 127 }
 128
 129 /**
 130  * ixgbe_iosf_wait - Wait for IOSF command completion
 131  * @hw: pointer to hardware structure
 132  * @ctrl: pointer to location to receive final IOSF control value
 133  *
 134  * Return: failing status on timeout
 135  *
 136  * Note: ctrl can be NULL if the IOSF control register value is not needed
 137  */
 138 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 139 {
 140         u32 i, command;
 141
 142         /* Check every 10 usec to see if the address cycle completed.
 143          * The SB IOSF BUSY bit will clear when the operation is
 144          * complete.
 145          */
 146         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 147                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 148                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 149                         break;
 150                 usleep_range(10, 20);
 151         }
 152         if (ctrl)
 153                 *ctrl = command;
 154         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 155                 hw_dbg(hw, "IOSF wait timed out\n");
 156                 return IXGBE_ERR_PHY;
 157         }
 158
 159         return 0;
 160 }
 161
 162 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 163  *  IOSF device
 164  *  @hw: pointer to hardware structure
 165  *  @reg_addr: 32 bit PHY register to write
 166  *  @device_type: 3 bit device type
 167  *  @phy_data: Pointer to read data from the register
 168  **/
 169 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 170                                        u32 device_type, u32 *data)
 171 {
 172         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 173         u32 command, error;
 174         s32 ret;
 175
 176         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 177         if (ret)
 178                 return ret;
 179
 180         ret = ixgbe_iosf_wait(hw, NULL);
 181         if (ret)
 182                 goto out;
 183
 184         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 185                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 186
 187         /* Write IOSF control register */
 188         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 189
 190         ret = ixgbe_iosf_wait(hw, &command);
 191
 192         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 193                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 194                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 195                 hw_dbg(hw, "Failed to read, error %x\n", error);
 196                 return IXGBE_ERR_PHY;
 197         }
 198
 199         if (!ret)
 200                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 201
 202 out:
 203         hw->mac.ops.release_swfw_sync(hw, gssr);
 204         return ret;
 205 }
 206
 207 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 208  *  command assuming that the semaphore is already obtained.
 209  *  @hw: pointer to hardware structure
 210  *  @offset: offset of  word in the EEPROM to read
 211  *  @data: word read from the EEPROM
 212  *
 213  *  Reads a 16 bit word from the EEPROM using the hostif.
 214  **/
 215 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 216                                           u16 *data)
 217 {
 218         s32 status;
 219         struct ixgbe_hic_read_shadow_ram buffer;
 220
 221         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 222         buffer.hdr.req.buf_lenh = 0;
 223         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 224         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 225
 226         /* convert offset from words to bytes */
 227         buffer.address = cpu_to_be32(offset * 2);
 228         /* one word */
 229         buffer.length = cpu_to_be16(sizeof(u16));
 230
 231         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 232                                               sizeof(buffer),
 233                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 234         if (status)
 235                 return status;
 236
 237         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 238                                           FW_NVM_DATA_OFFSET);
 239
 240         return 0;
 241 }
 242
 243 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 244  *  @hw: pointer to hardware structure
 245  *  @offset: offset of  word in the EEPROM to read
 246  *  @words: number of words
 247  *  @data: word(s) read from the EEPROM
 248  *
 249  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 250  **/
 251 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 252                                             u16 offset, u16 words, u16 *data)
 253 {
 254         struct ixgbe_hic_read_shadow_ram buffer;
 255         u32 current_word = 0;
 256         u16 words_to_read;
 257         s32 status;
 258         u32 i;
 259
 260         /* Take semaphore for the entire operation. */
 261         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 262         if (status) {
 263                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 264                 return status;
 265         }
 266
 267         while (words) {
 268                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 269                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 270                 else
 271                         words_to_read = words;
 272
 273                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 274                 buffer.hdr.req.buf_lenh = 0;
 275                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 276                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 277
 278                 /* convert offset from words to bytes */
 279                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 280                 buffer.length = cpu_to_be16(words_to_read * 2);
 281
 282                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 283                                                       sizeof(buffer),
 284                                                       IXGBE_HI_COMMAND_TIMEOUT,
 285                                                       false);
 286                 if (status) {
 287                         hw_dbg(hw, "Host interface command failed\n");
 288                         goto out;
 289                 }
 290
 291                 for (i = 0; i < words_to_read; i++) {
 292                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 293                                   2 * i;
 294                         u32 value = IXGBE_READ_REG(hw, reg);
 295
 296                         data[current_word] = (u16)(value & 0xffff);
 297                         current_word++;
 298                         i++;
 299                         if (i < words_to_read) {
 300                                 value >>= 16;
 301                                 data[current_word] = (u16)(value & 0xffff);
 302                                 current_word++;
 303                         }
 304                 }
 305                 words -= words_to_read;
 306         }
 307
 308 out:
 309         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 310         return status;
 311 }
 312
 313 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 314  *  @hw: pointer to hardware structure
 315  *  @ptr: pointer offset in eeprom
 316  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 317  *  @csum: address of checksum to update
 318  *
 319  *  Returns error status for any failure
 320  **/
 321 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 322                                    u16 size, u16 *csum, u16 *buffer,
 323                                    u32 buffer_size)
 324 {
 325         u16 buf[256];
 326         s32 status;
 327         u16 length, bufsz, i, start;
 328         u16 *local_buffer;
 329
 330         bufsz = sizeof(buf) / sizeof(buf[0]);
 331
 332         /* Read a chunk at the pointer location */
 333         if (!buffer) {
 334                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 335                 if (status) {
 336                         hw_dbg(hw, "Failed to read EEPROM image\n");
 337                         return status;
 338                 }
 339                 local_buffer = buf;
 340         } else {
 341                 if (buffer_size < ptr)
 342                         return  IXGBE_ERR_PARAM;
 343                 local_buffer = &buffer[ptr];
 344         }
 345
 346         if (size) {
 347                 start = 0;
 348                 length = size;
 349         } else {
 350                 start = 1;
 351                 length = local_buffer[0];
 352
 353                 /* Skip pointer section if length is invalid. */
 354                 if (length == 0xFFFF || length == 0 ||
 355                     (ptr + length) >= hw->eeprom.word_size)
 356                         return 0;
 357         }
 358
 359         if (buffer && ((u32)start + (u32)length > buffer_size))
 360                 return IXGBE_ERR_PARAM;
 361
 362         for (i = start; length; i++, length--) {
 363                 if (i == bufsz && !buffer) {
 364                         ptr += bufsz;
 365                         i = 0;
 366                         if (length < bufsz)
 367                                 bufsz = length;
 368
 369                         /* Read a chunk at the pointer location */
 370                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 371                                                                   bufsz, buf);
 372                         if (status) {
 373                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 374                                 return status;
 375                         }
 376                 }
 377                 *csum += local_buffer[i];
 378         }
 379         return 0;
 380 }
 381
 382 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 383  *  @hw: pointer to hardware structure
 384  *  @buffer: pointer to buffer containing calculated checksum
 385  *  @buffer_size: size of buffer
 386  *
 387  *  Returns a negative error code on error, or the 16-bit checksum
 388  **/
 389 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 390                                     u32 buffer_size)
 391 {
 392         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 393         u16 *local_buffer;
 394         s32 status;
 395         u16 checksum = 0;
 396         u16 pointer, i, size;
 397
 398         hw->eeprom.ops.init_params(hw);
 399
 400         if (!buffer) {
 401                 /* Read pointer area */
 402                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 403                                                 IXGBE_EEPROM_LAST_WORD + 1,
 404                                                 eeprom_ptrs);
 405                 if (status) {
 406                         hw_dbg(hw, "Failed to read EEPROM image\n");
 407                         return status;
 408                 }
 409                 local_buffer = eeprom_ptrs;
 410         } else {
 411                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 412                         return IXGBE_ERR_PARAM;
 413                 local_buffer = buffer;
 414         }
 415
 416         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 417          * checksum word itself
 418          */
 419         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 420                 if (i != IXGBE_EEPROM_CHECKSUM)
 421                         checksum += local_buffer[i];
 422
 423         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 424          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 425          */
 426         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 427                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 428                         continue;
 429
 430                 pointer = local_buffer[i];
 431
 432                 /* Skip pointer section if the pointer is invalid. */
 433                 if (pointer == 0xFFFF || pointer == 0 ||
 434                     pointer >= hw->eeprom.word_size)
 435                         continue;
 436
 437                 switch (i) {
 438                 case IXGBE_PCIE_GENERAL_PTR:
 439                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 440                         break;
 441                 case IXGBE_PCIE_CONFIG0_PTR:
 442                 case IXGBE_PCIE_CONFIG1_PTR:
 443                         size = IXGBE_PCIE_CONFIG_SIZE;
 444                         break;
 445                 default:
 446                         size = 0;
 447                         break;
 448                 }
 449
 450                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 451                                                  buffer, buffer_size);
 452                 if (status)
 453                         return status;
 454         }
 455
 456         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 457
 458         return (s32)checksum;
 459 }
 460
 461 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 462  *  @hw: pointer to hardware structure
 463  *
 464  *  Returns a negative error code on error, or the 16-bit checksum
 465  **/
 466 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 467 {
 468         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 469 }
 470
 471 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 472  *  @hw: pointer to hardware structure
 473  *  @offset: offset of  word in the EEPROM to read
 474  *  @data: word read from the EEPROM
 475  *
 476  *   Reads a 16 bit word from the EEPROM using the hostif.
 477  **/
 478 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 479 {
 480         s32 status = 0;
 481
 482         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 483                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 484                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 485         } else {
 486                 status = IXGBE_ERR_SWFW_SYNC;
 487         }
 488
 489         return status;
 490 }
 491
 492 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 493  *  @hw: pointer to hardware structure
 494  *  @checksum_val: calculated checksum
 495  *
 496  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 497  *  caller does not need checksum_val, the value can be NULL.
 498  **/
 499 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 500                                                u16 *checksum_val)
 501 {
 502         s32 status;
 503         u16 checksum;
 504         u16 read_checksum = 0;
 505
 506         /* Read the first word from the EEPROM. If this times out or fails, do
 507          * not continue or we could be in for a very long wait while every
 508          * EEPROM read fails
 509          */
 510         status = hw->eeprom.ops.read(hw, 0, &checksum);
 511         if (status) {
 512                 hw_dbg(hw, "EEPROM read failed\n");
 513                 return status;
 514         }
 515
 516         status = hw->eeprom.ops.calc_checksum(hw);
 517         if (status < 0)
 518                 return status;
 519
 520         checksum = (u16)(status & 0xffff);
 521
 522         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 523                                            &read_checksum);
 524         if (status)
 525                 return status;
 526
 527         /* Verify read checksum from EEPROM is the same as
 528          * calculated checksum
 529          */
 530         if (read_checksum != checksum) {
 531                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 532                 hw_dbg(hw, "Invalid EEPROM checksum");
 533         }
 534
 535         /* If the user cares, return the calculated checksum */
 536         if (checksum_val)
 537                 *checksum_val = checksum;
 538
 539         return status;
 540 }
 541
 542 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 543  *  @hw: pointer to hardware structure
 544  *  @offset: offset of  word in the EEPROM to write
 545  *  @data: word write to the EEPROM
 546  *
 547  *  Write a 16 bit word to the EEPROM using the hostif.
 548  **/
 549 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 550                                            u16 data)
 551 {
 552         s32 status;
 553         struct ixgbe_hic_write_shadow_ram buffer;
 554
 555         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 556         buffer.hdr.req.buf_lenh = 0;
 557         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 558         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 559
 560         /* one word */
 561         buffer.length = cpu_to_be16(sizeof(u16));
 562         buffer.data = data;
 563         buffer.address = cpu_to_be32(offset * 2);
 564
 565         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 566                                               sizeof(buffer),
 567                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 568         return status;
 569 }
 570
 571 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 572  *  @hw: pointer to hardware structure
 573  *  @offset: offset of  word in the EEPROM to write
 574  *  @data: word write to the EEPROM
 575  *
 576  *  Write a 16 bit word to the EEPROM using the hostif.
 577  **/
 578 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 579 {
 580         s32 status = 0;
 581
 582         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 583                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 584                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 585         } else {
 586                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 587                 status = IXGBE_ERR_SWFW_SYNC;
 588         }
 589
 590         return status;
 591 }
 592
 593 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 594  *  @hw: pointer to hardware structure
 595  *
 596  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 597  **/
 598 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 599 {
 600         s32 status = 0;
 601         union ixgbe_hic_hdr2 buffer;
 602
 603         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 604         buffer.req.buf_lenh = 0;
 605         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 606         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 607
 608         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 609                                               sizeof(buffer),
 610                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 611         return status;
 612 }
 613
 614 /**
 615  * ixgbe_get_bus_info_X550em - Set PCI bus info
 616  * @hw: pointer to hardware structure
 617  *
 618  * Sets bus link width and speed to unknown because X550em is
 619  * not a PCI device.
 620  **/
 621 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 622 {
 623         hw->bus.type  = ixgbe_bus_type_internal;
 624         hw->bus.width = ixgbe_bus_width_unknown;
 625         hw->bus.speed = ixgbe_bus_speed_unknown;
 626
 627         hw->mac.ops.set_lan_id(hw);
 628
 629         return 0;
 630 }
 631
 632 /** ixgbe_disable_rx_x550 - Disable RX unit
 633  *
 634  *  Enables the Rx DMA unit for x550
 635  **/
 636 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 637 {
 638         u32 rxctrl, pfdtxgswc;
 639         s32 status;
 640         struct ixgbe_hic_disable_rxen fw_cmd;
 641
 642         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 643         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 644                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 645                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 646                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 647                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 648                         hw->mac.set_lben = true;
 649                 } else {
 650                         hw->mac.set_lben = false;
 651                 }
 652
 653                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 654                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 655                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 656                 fw_cmd.port_number = (u8)hw->bus.lan_id;
 657
 658                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
 659                                         sizeof(struct ixgbe_hic_disable_rxen),
 660                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 661
 662                 /* If we fail - disable RX using register write */
 663                 if (status) {
 664                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 665                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 666                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
 667                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
 668                         }
 669                 }
 670         }
 671 }
 672
 673 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
 674  *  @hw: pointer to hardware structure
 675  *
 676  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
 677  *  checksum and updates the EEPROM and instructs the hardware to update
 678  *  the flash.
 679  **/
 680 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
 681 {
 682         s32 status;
 683         u16 checksum = 0;
 684
 685         /* Read the first word from the EEPROM. If this times out or fails, do
 686          * not continue or we could be in for a very long wait while every
 687          * EEPROM read fails
 688          */
 689         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
 690         if (status) {
 691                 hw_dbg(hw, "EEPROM read failed\n");
 692                 return status;
 693         }
 694
 695         status = ixgbe_calc_eeprom_checksum_X550(hw);
 696         if (status < 0)
 697                 return status;
 698
 699         checksum = (u16)(status & 0xffff);
 700
 701         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 702                                             checksum);
 703         if (status)
 704                 return status;
 705
 706         status = ixgbe_update_flash_X550(hw);
 707
 708         return status;
 709 }
 710
 711 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
 712  *  @hw: pointer to hardware structure
 713  *  @offset: offset of  word in the EEPROM to write
 714  *  @words: number of words
 715  *  @data: word(s) write to the EEPROM
 716  *
 717  *
 718  *  Write a 16 bit word(s) to the EEPROM using the hostif.
 719  **/
 720 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 721                                              u16 offset, u16 words,
 722                                              u16 *data)
 723 {
 724         s32 status = 0;
 725         u32 i = 0;
 726
 727         /* Take semaphore for the entire operation. */
 728         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 729         if (status) {
 730                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
 731                 return status;
 732         }
 733
 734         for (i = 0; i < words; i++) {
 735                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
 736                                                          data[i]);
 737                 if (status) {
 738                         hw_dbg(hw, "Eeprom buffered write failed\n");
 739                         break;
 740                 }
 741         }
 742
 743         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 744
 745         return status;
 746 }
 747
 748 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
 749  *  IOSF device
 750  *
 751  *  @hw: pointer to hardware structure
 752  *  @reg_addr: 32 bit PHY register to write
 753  *  @device_type: 3 bit device type
 754  *  @data: Data to write to the register
 755  **/
 756 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 757                                         u32 device_type, u32 data)
 758 {
 759         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 760         u32 command, error;
 761         s32 ret;
 762
 763         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 764         if (ret)
 765                 return ret;
 766
 767         ret = ixgbe_iosf_wait(hw, NULL);
 768         if (ret)
 769                 goto out;
 770
 771         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 772                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 773
 774         /* Write IOSF control register */
 775         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 776
 777         /* Write IOSF data register */
 778         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 779
 780         ret = ixgbe_iosf_wait(hw, &command);
 781
 782         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 783                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 784                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 785                 hw_dbg(hw, "Failed to write, error %x\n", error);
 786                 return IXGBE_ERR_PHY;
 787         }
 788
 789 out:
 790         hw->mac.ops.release_swfw_sync(hw, gssr);
 791         return ret;
 792 }
 793
 794 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
 795  *  @hw: pointer to hardware structure
 796  *  @speed: the link speed to force
 797  *
 798  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
 799  *  internal and external PHY at a specific speed, without autonegotiation.
 800  **/
 801 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
 802 {
 803         s32 status;
 804         u32 reg_val;
 805
 806         /* Disable AN and force speed to 10G Serial. */
 807         status = ixgbe_read_iosf_sb_reg_x550(hw,
 808                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 809                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 810         if (status)
 811                 return status;
 812
 813         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
 814         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
 815
 816         /* Select forced link speed for internal PHY. */
 817         switch (*speed) {
 818         case IXGBE_LINK_SPEED_10GB_FULL:
 819                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
 820                 break;
 821         case IXGBE_LINK_SPEED_1GB_FULL:
 822                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
 823                 break;
 824         default:
 825                 /* Other link speeds are not supported by internal KR PHY. */
 826                 return IXGBE_ERR_LINK_SETUP;
 827         }
 828
 829         status = ixgbe_write_iosf_sb_reg_x550(hw,
 830                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 831                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 832         if (status)
 833                 return status;
 834
 835         /* Disable training protocol FSM. */
 836         status = ixgbe_read_iosf_sb_reg_x550(hw,
 837                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
 838                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 839         if (status)
 840                 return status;
 841
 842         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
 843         status = ixgbe_write_iosf_sb_reg_x550(hw,
 844                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
 845                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 846         if (status)
 847                 return status;
 848
 849         /* Disable Flex from training TXFFE. */
 850         status = ixgbe_read_iosf_sb_reg_x550(hw,
 851                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
 852                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 853         if (status)
 854                 return status;
 855
 856         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
 857         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
 858         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
 859         status = ixgbe_write_iosf_sb_reg_x550(hw,
 860                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
 861                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 862         if (status)
 863                 return status;
 864
 865         status = ixgbe_read_iosf_sb_reg_x550(hw,
 866                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
 867                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 868         if (status)
 869                 return status;
 870
 871         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
 872         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
 873         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
 874         status = ixgbe_write_iosf_sb_reg_x550(hw,
 875                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
 876                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 877         if (status)
 878                 return status;
 879
 880         /* Enable override for coefficients. */
 881         status = ixgbe_read_iosf_sb_reg_x550(hw,
 882                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
 883                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 884         if (status)
 885                 return status;
 886
 887         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
 888         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
 889         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
 890         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
 891         status = ixgbe_write_iosf_sb_reg_x550(hw,
 892                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
 893                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 894         if (status)
 895                 return status;
 896
 897         /* Toggle port SW reset by AN reset. */
 898         status = ixgbe_read_iosf_sb_reg_x550(hw,
 899                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 900                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 901         if (status)
 902                 return status;
 903
 904         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
 905         status = ixgbe_write_iosf_sb_reg_x550(hw,
 906                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 907                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 908
 909         return status;
 910 }
 911
 912 /**
 913  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
 914  *  @hw: pointer to hardware structure
 915  *
 916  *  Configures the extern PHY and the integrated KR PHY for SFP support.
 917  */
 918 static s32
 919 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
 920                                 ixgbe_link_speed speed,
 921                                 __always_unused bool autoneg_wait_to_complete)
 922 {
 923         return ixgbe_setup_ixfi_x550em(hw, &speed);
 924 }
 925
 926 /**
 927  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
 928  * @hw: pointer to hardware structure
 929  * @speed: new link speed
 930  * @autoneg_wait_to_complete: true when waiting for completion is needed
 931  *
 932  * Setup internal/external PHY link speed based on link speed, then set
 933  * external PHY auto advertised link speed.
 934  *
 935  * Returns error status for any failure
 936  **/
 937 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
 938                                          ixgbe_link_speed speed,
 939                                          bool autoneg_wait)
 940 {
 941         s32 status;
 942         ixgbe_link_speed force_speed;
 943
 944         /* Setup internal/external PHY link speed to iXFI (10G), unless
 945          * only 1G is auto advertised then setup KX link.
 946          */
 947         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 948                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
 949         else
 950                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
 951
 952         /* If internal link mode is XFI, then setup XFI internal link. */
 953         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
 954                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
 955
 956                 if (status)
 957                         return status;
 958         }
 959
 960         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
 961 }
 962
 963 /** ixgbe_check_link_t_X550em - Determine link and speed status
 964   * @hw: pointer to hardware structure
 965   * @speed: pointer to link speed
 966   * @link_up: true when link is up
 967   * @link_up_wait_to_complete: bool used to wait for link up or not
 968   *
 969   * Check that both the MAC and X557 external PHY have link.
 970   **/
 971 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
 972                                      ixgbe_link_speed *speed,
 973                                      bool *link_up,
 974                                      bool link_up_wait_to_complete)
 975 {
 976         u32 status;
 977         u16 autoneg_status;
 978
 979         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
 980                 return IXGBE_ERR_CONFIG;
 981
 982         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
 983                                               link_up_wait_to_complete);
 984
 985         /* If check link fails or MAC link is not up, then return */
 986         if (status || !(*link_up))
 987                 return status;
 988
 989          /* MAC link is up, so check external PHY link.
 990           * Read this twice back to back to indicate current status.
 991           */
 992         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 993                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 994                                       &autoneg_status);
 995         if (status)
 996                 return status;
 997
 998         /* If external PHY link is not up, then indicate link not up */
 999         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1000                 *link_up = false;
1001
1002         return 0;
1003 }
1004
1005 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1006  *  @hw: pointer to hardware structure
1007  **/
1008 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1009 {
1010         struct ixgbe_mac_info *mac = &hw->mac;
1011
1012         switch (mac->ops.get_media_type(hw)) {
1013         case ixgbe_media_type_fiber:
1014                 /* CS4227 does not support autoneg, so disable the laser control
1015                  * functions for SFP+ fiber
1016                  */
1017                 mac->ops.disable_tx_laser = NULL;
1018                 mac->ops.enable_tx_laser = NULL;
1019                 mac->ops.flap_tx_laser = NULL;
1020                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1021                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1022                 mac->ops.set_rate_select_speed =
1023                                         ixgbe_set_soft_rate_select_speed;
1024                 break;
1025         case ixgbe_media_type_copper:
1026                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1027                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1028                 break;
1029         default:
1030                 break;
1031         }
1032 }
1033
1034 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1035  * @hw: pointer to hardware structure
1036  */
1037 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1038 {
1039         bool setup_linear;
1040         u16 reg_slice, edc_mode;
1041         s32 ret_val;
1042
1043         switch (hw->phy.sfp_type) {
1044         case ixgbe_sfp_type_unknown:
1045                 return 0;
1046         case ixgbe_sfp_type_not_present:
1047                 return IXGBE_ERR_SFP_NOT_PRESENT;
1048         case ixgbe_sfp_type_da_cu_core0:
1049         case ixgbe_sfp_type_da_cu_core1:
1050                 setup_linear = true;
1051                 break;
1052         case ixgbe_sfp_type_srlr_core0:
1053         case ixgbe_sfp_type_srlr_core1:
1054         case ixgbe_sfp_type_da_act_lmt_core0:
1055         case ixgbe_sfp_type_da_act_lmt_core1:
1056         case ixgbe_sfp_type_1g_sx_core0:
1057         case ixgbe_sfp_type_1g_sx_core1:
1058                 setup_linear = false;
1059                 break;
1060         default:
1061                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1062         }
1063
1064         ixgbe_init_mac_link_ops_X550em(hw);
1065         hw->phy.ops.reset = NULL;
1066
1067         /* The CS4227 slice address is the base address + the port-pair reg
1068          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1069          */
1070         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1071
1072         if (setup_linear)
1073                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1074         else
1075                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1076
1077         /* Configure CS4227 for connection type. */
1078         ret_val = hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1079                                                  edc_mode);
1080
1081         if (ret_val)
1082                 ret_val = hw->phy.ops.write_i2c_combined(hw, 0x80, reg_slice,
1083                                                          edc_mode);
1084
1085         return ret_val;
1086 }
1087
1088 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1089  * @hw: pointer to hardware structure
1090  * @speed: pointer to link speed
1091  * @autoneg: true when autoneg or autotry is enabled
1092  **/
1093 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1094                                               ixgbe_link_speed *speed,
1095                                               bool *autoneg)
1096 {
1097         /* SFP */
1098         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1099                 /* CS4227 SFP must not enable auto-negotiation */
1100                 *autoneg = false;
1101
1102                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1103                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
1104                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1105                         return 0;
1106                 }
1107
1108                 /* Link capabilities are based on SFP */
1109                 if (hw->phy.multispeed_fiber)
1110                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1111                                  IXGBE_LINK_SPEED_1GB_FULL;
1112                 else
1113                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1114         } else {
1115                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1116                          IXGBE_LINK_SPEED_1GB_FULL;
1117                 *autoneg = true;
1118         }
1119         return 0;
1120 }
1121
1122 /**
1123  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1124  * @hw: pointer to hardware structure
1125  * @lsc: pointer to boolean flag which indicates whether external Base T
1126  *       PHY interrupt is lsc
1127  *
1128  * Determime if external Base T PHY interrupt cause is high temperature
1129  * failure alarm or link status change.
1130  *
1131  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1132  * failure alarm, else return PHY access status.
1133  **/
1134 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1135 {
1136         u32 status;
1137         u16 reg;
1138
1139         *lsc = false;
1140
1141         /* Vendor alarm triggered */
1142         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1143                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1144                                       &reg);
1145
1146         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1147                 return status;
1148
1149         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1150         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1151                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1152                                       &reg);
1153
1154         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1155                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1156                 return status;
1157
1158         /* High temperature failure alarm triggered */
1159         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1160                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1161                                       &reg);
1162
1163         if (status)
1164                 return status;
1165
1166         /* If high temperature failure, then return over temp error and exit */
1167         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1168                 /* power down the PHY in case the PHY FW didn't already */
1169                 ixgbe_set_copper_phy_power(hw, false);
1170                 return IXGBE_ERR_OVERTEMP;
1171         }
1172
1173         /* Vendor alarm 2 triggered */
1174         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1175                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1176
1177         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1178                 return status;
1179
1180         /* link connect/disconnect event occurred */
1181         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1182                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1183
1184         if (status)
1185                 return status;
1186
1187         /* Indicate LSC */
1188         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1189                 *lsc = true;
1190
1191         return 0;
1192 }
1193
1194 /**
1195  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1196  * @hw: pointer to hardware structure
1197  *
1198  * Enable link status change and temperature failure alarm for the external
1199  * Base T PHY
1200  *
1201  * Returns PHY access status
1202  **/
1203 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1204 {
1205         u32 status;
1206         u16 reg;
1207         bool lsc;
1208
1209         /* Clear interrupt flags */
1210         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1211
1212         /* Enable link status change alarm */
1213         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1214                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1215         if (status)
1216                 return status;
1217
1218         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1219
1220         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1221                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1222         if (status)
1223                 return status;
1224
1225         /* Enables high temperature failure alarm */
1226         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1227                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1228                                       &reg);
1229         if (status)
1230                 return status;
1231
1232         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1233
1234         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1235                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1236                                        reg);
1237         if (status)
1238                 return status;
1239
1240         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1241         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1242                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1243                                       &reg);
1244         if (status)
1245                 return status;
1246
1247         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1248                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1249
1250         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1251                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1252                                        reg);
1253         if (status)
1254                 return status;
1255
1256         /* Enable chip-wide vendor alarm */
1257         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1258                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1259                                       &reg);
1260         if (status)
1261                 return status;
1262
1263         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1264
1265         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1266                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1267                                        reg);
1268
1269         return status;
1270 }
1271
1272 /**
1273  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1274  * @hw: pointer to hardware structure
1275  *
1276  * Handle external Base T PHY interrupt. If high temperature
1277  * failure alarm then return error, else if link status change
1278  * then setup internal/external PHY link
1279  *
1280  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1281  * failure alarm, else return PHY access status.
1282  **/
1283 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1284 {
1285         struct ixgbe_phy_info *phy = &hw->phy;
1286         bool lsc;
1287         u32 status;
1288
1289         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1290         if (status)
1291                 return status;
1292
1293         if (lsc)
1294                 return phy->ops.setup_internal_link(hw);
1295
1296         return 0;
1297 }
1298
1299 /**
1300  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1301  * @hw: pointer to hardware structure
1302  * @speed: link speed
1303  *
1304  * Configures the integrated KR PHY.
1305  **/
1306 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1307                                        ixgbe_link_speed speed)
1308 {
1309         s32 status;
1310         u32 reg_val;
1311
1312         status = ixgbe_read_iosf_sb_reg_x550(hw,
1313                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1314                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1315         if (status)
1316                 return status;
1317
1318         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1319         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1320                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1321         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1322                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1323
1324         /* Advertise 10G support. */
1325         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1326                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1327
1328         /* Advertise 1G support. */
1329         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1330                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1331
1332         /* Restart auto-negotiation. */
1333         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1334         status = ixgbe_write_iosf_sb_reg_x550(hw,
1335                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1336                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1337
1338         return status;
1339 }
1340
1341 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1342  *  @hw: pointer to hardware structure
1343  *
1344  *   Configures the integrated KX4 PHY.
1345  **/
1346 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1347 {
1348         s32 status;
1349         u32 reg_val;
1350
1351         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1352                                              IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1353                                              hw->bus.lan_id, &reg_val);
1354         if (status)
1355                 return status;
1356
1357         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1358                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1359
1360         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1361
1362         /* Advertise 10G support. */
1363         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1364                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1365
1366         /* Advertise 1G support. */
1367         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1368                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1369
1370         /* Restart auto-negotiation. */
1371         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1372         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1373                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1374                                               hw->bus.lan_id, reg_val);
1375
1376         return status;
1377 }
1378
1379 /**  ixgbe_setup_kr_x550em - Configure the KR PHY.
1380  *   @hw: pointer to hardware structure
1381  *
1382  *   Configures the integrated KR PHY.
1383  **/
1384 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1385 {
1386         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1387 }
1388
1389 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1390  *  @hw: address of hardware structure
1391  *  @link_up: address of boolean to indicate link status
1392  *
1393  *  Returns error code if unable to get link status.
1394  **/
1395 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1396 {
1397         u32 ret;
1398         u16 autoneg_status;
1399
1400         *link_up = false;
1401
1402         /* read this twice back to back to indicate current status */
1403         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1404                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1405                                    &autoneg_status);
1406         if (ret)
1407                 return ret;
1408
1409         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1410                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1411                                    &autoneg_status);
1412         if (ret)
1413                 return ret;
1414
1415         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1416
1417         return 0;
1418 }
1419
1420 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1421  *  @hw: point to hardware structure
1422  *
1423  *  Configures the link between the integrated KR PHY and the external X557 PHY
1424  *  The driver will call this function when it gets a link status change
1425  *  interrupt from the X557 PHY. This function configures the link speed
1426  *  between the PHYs to match the link speed of the BASE-T link.
1427  *
1428  * A return of a non-zero value indicates an error, and the base driver should
1429  * not report link up.
1430  **/
1431 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1432 {
1433         ixgbe_link_speed force_speed;
1434         bool link_up;
1435         u32 status;
1436         u16 speed;
1437
1438         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1439                 return IXGBE_ERR_CONFIG;
1440
1441         /* If link is not up, then there is no setup necessary so return  */
1442         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1443         if (status)
1444                 return status;
1445
1446         if (!link_up)
1447                 return 0;
1448
1449         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1450                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1451                                       &speed);
1452         if (status)
1453                 return status;
1454
1455         /* If link is not still up, then no setup is necessary so return */
1456         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1457         if (status)
1458                 return status;
1459
1460         if (!link_up)
1461                 return 0;
1462
1463         /* clear everything but the speed and duplex bits */
1464         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1465
1466         switch (speed) {
1467         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1468                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1469                 break;
1470         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1471                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1472                 break;
1473         default:
1474                 /* Internal PHY does not support anything else */
1475                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1476         }
1477
1478         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1479 }
1480
1481 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
1482  *  @hw: pointer to hardware structure
1483  **/
1484 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
1485 {
1486         s32 status;
1487
1488         status = ixgbe_reset_phy_generic(hw);
1489
1490         if (status)
1491                 return status;
1492
1493         /* Configure Link Status Alarm and Temperature Threshold interrupts */
1494         return ixgbe_enable_lasi_ext_t_x550em(hw);
1495 }
1496
1497 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
1498  *  @hw: pointer to hardware structure
1499  *  @lcd_speed: pointer to lowest common link speed
1500  *
1501  *  Determine lowest common link speed with link partner.
1502  **/
1503 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
1504                                   ixgbe_link_speed *lcd_speed)
1505 {
1506         u16 an_lp_status;
1507         s32 status;
1508         u16 word = hw->eeprom.ctrl_word_3;
1509
1510         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
1511
1512         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
1513                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1514                                       &an_lp_status);
1515         if (status)
1516                 return status;
1517
1518         /* If link partner advertised 1G, return 1G */
1519         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
1520                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
1521                 return status;
1522         }
1523
1524         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
1525         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
1526             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
1527                 return status;
1528
1529         /* Link partner not capable of lower speeds, return 10G */
1530         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
1531         return status;
1532 }
1533
1534 /** ixgbe_enter_lplu_x550em - Transition to low power states
1535  *  @hw: pointer to hardware structure
1536  *
1537  *  Configures Low Power Link Up on transition to low power states
1538  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
1539  *  the X557 PHY immediately prior to entering LPLU.
1540  **/
1541 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
1542 {
1543         u16 an_10g_cntl_reg, autoneg_reg, speed;
1544         s32 status;
1545         ixgbe_link_speed lcd_speed;
1546         u32 save_autoneg;
1547         bool link_up;
1548
1549         /* SW LPLU not required on later HW revisions. */
1550         if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
1551                 return 0;
1552
1553         /* If blocked by MNG FW, then don't restart AN */
1554         if (ixgbe_check_reset_blocked(hw))
1555                 return 0;
1556
1557         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1558         if (status)
1559                 return status;
1560
1561         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
1562                                      &hw->eeprom.ctrl_word_3);
1563         if (status)
1564                 return status;
1565
1566         /* If link is down, LPLU disabled in NVM, WoL disabled, or
1567          * manageability disabled, then force link down by entering
1568          * low power mode.
1569          */
1570         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
1571             !(hw->wol_enabled || ixgbe_mng_present(hw)))
1572                 return ixgbe_set_copper_phy_power(hw, false);
1573
1574         /* Determine LCD */
1575         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
1576         if (status)
1577                 return status;
1578
1579         /* If no valid LCD link speed, then force link down and exit. */
1580         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
1581                 return ixgbe_set_copper_phy_power(hw, false);
1582
1583         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1584                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1585                                       &speed);
1586         if (status)
1587                 return status;
1588
1589         /* If no link now, speed is invalid so take link down */
1590         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1591         if (status)
1592                 return ixgbe_set_copper_phy_power(hw, false);
1593
1594         /* clear everything but the speed bits */
1595         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
1596
1597         /* If current speed is already LCD, then exit. */
1598         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
1599              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
1600             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
1601              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
1602                 return status;
1603
1604         /* Clear AN completed indication */
1605         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
1606                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1607                                       &autoneg_reg);
1608         if (status)
1609                 return status;
1610
1611         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1612                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1613                                       &an_10g_cntl_reg);
1614         if (status)
1615                 return status;
1616
1617         status = hw->phy.ops.read_reg(hw,
1618                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1619                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1620                                       &autoneg_reg);
1621         if (status)
1622                 return status;
1623
1624         save_autoneg = hw->phy.autoneg_advertised;
1625
1626         /* Setup link at least common link speed */
1627         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
1628
1629         /* restore autoneg from before setting lplu speed */
1630         hw->phy.autoneg_advertised = save_autoneg;
1631
1632         return status;
1633 }
1634
1635 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1636  *  @hw: pointer to hardware structure
1637  *
1638  *  Initialize any function pointers that were not able to be
1639  *  set during init_shared_code because the PHY/SFP type was
1640  *  not known.  Perform the SFP init if necessary.
1641  **/
1642 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1643 {
1644         struct ixgbe_phy_info *phy = &hw->phy;
1645         ixgbe_link_speed speed;
1646         s32 ret_val;
1647
1648         hw->mac.ops.set_lan_id(hw);
1649
1650         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1651                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1652                 ixgbe_setup_mux_ctl(hw);
1653
1654                 /* Save NW management interface connected on board. This is used
1655                  * to determine internal PHY mode.
1656                  */
1657                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1658
1659                 /* If internal PHY mode is KR, then initialize KR link */
1660                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1661                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1662                                 IXGBE_LINK_SPEED_1GB_FULL;
1663                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1664                 }
1665         }
1666
1667         /* Identify the PHY or SFP module */
1668         ret_val = phy->ops.identify(hw);
1669
1670         /* Setup function pointers based on detected hardware */
1671         ixgbe_init_mac_link_ops_X550em(hw);
1672         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1673                 phy->ops.reset = NULL;
1674
1675         /* Set functions pointers based on phy type */
1676         switch (hw->phy.type) {
1677         case ixgbe_phy_x550em_kx4:
1678                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1679                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1680                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1681                 break;
1682         case ixgbe_phy_x550em_kr:
1683                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1684                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1685                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1686                 break;
1687         case ixgbe_phy_x550em_ext_t:
1688                 /* Save NW management interface connected on board. This is used
1689                  * to determine internal PHY mode
1690                  */
1691                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1692
1693                 /* If internal link mode is XFI, then setup iXFI internal link,
1694                  * else setup KR now.
1695                  */
1696                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1697                         phy->ops.setup_internal_link =
1698                                         ixgbe_setup_internal_phy_t_x550em;
1699                 } else {
1700                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1701                                 IXGBE_LINK_SPEED_1GB_FULL;
1702                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1703                 }
1704
1705                 /* setup SW LPLU only for first revision */
1706                 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1707                                                         IXGBE_FUSES0_GROUP(0))))
1708                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1709
1710                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1711                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1712                 break;
1713         default:
1714                 break;
1715         }
1716
1717         return ret_val;
1718 }
1719
1720 /** ixgbe_get_media_type_X550em - Get media type
1721  *  @hw: pointer to hardware structure
1722  *
1723  *  Returns the media type (fiber, copper, backplane)
1724  *
1725  */
1726 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1727 {
1728         enum ixgbe_media_type media_type;
1729
1730         /* Detect if there is a copper PHY attached. */
1731         switch (hw->device_id) {
1732         case IXGBE_DEV_ID_X550EM_X_KR:
1733         case IXGBE_DEV_ID_X550EM_X_KX4:
1734                 media_type = ixgbe_media_type_backplane;
1735                 break;
1736         case IXGBE_DEV_ID_X550EM_X_SFP:
1737                 media_type = ixgbe_media_type_fiber;
1738                 break;
1739         case IXGBE_DEV_ID_X550EM_X_1G_T:
1740         case IXGBE_DEV_ID_X550EM_X_10G_T:
1741                  media_type = ixgbe_media_type_copper;
1742                 break;
1743         default:
1744                 media_type = ixgbe_media_type_unknown;
1745                 break;
1746         }
1747         return media_type;
1748 }
1749
1750 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1751  ** @hw: pointer to hardware structure
1752  **/
1753 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1754 {
1755         s32 status;
1756         u16 reg;
1757
1758         status = hw->phy.ops.read_reg(hw,
1759                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1760                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1761                                       &reg);
1762         if (status)
1763                 return status;
1764
1765         /* If PHY FW reset completed bit is set then this is the first
1766          * SW instance after a power on so the PHY FW must be un-stalled.
1767          */
1768         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1769                 status = hw->phy.ops.read_reg(hw,
1770                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1771                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1772                                         &reg);
1773                 if (status)
1774                         return status;
1775
1776                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1777
1778                 status = hw->phy.ops.write_reg(hw,
1779                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1780                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1781                                         reg);
1782                 if (status)
1783                         return status;
1784         }
1785
1786         return status;
1787 }
1788
1789 /**  ixgbe_reset_hw_X550em - Perform hardware reset
1790  **  @hw: pointer to hardware structure
1791  **
1792  **  Resets the hardware by resetting the transmit and receive units, masks
1793  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1794  **  reset.
1795  **/
1796 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1797 {
1798         ixgbe_link_speed link_speed;
1799         s32 status;
1800         u32 ctrl = 0;
1801         u32 i;
1802         u32 hlreg0;
1803         bool link_up = false;
1804
1805         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1806         status = hw->mac.ops.stop_adapter(hw);
1807         if (status)
1808                 return status;
1809
1810         /* flush pending Tx transactions */
1811         ixgbe_clear_tx_pending(hw);
1812
1813         /* PHY ops must be identified and initialized prior to reset */
1814
1815         /* Identify PHY and related function pointers */
1816         status = hw->phy.ops.init(hw);
1817
1818         /* start the external PHY */
1819         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1820                 status = ixgbe_init_ext_t_x550em(hw);
1821                 if (status)
1822                         return status;
1823         }
1824
1825         /* Setup SFP module if there is one present. */
1826         if (hw->phy.sfp_setup_needed) {
1827                 status = hw->mac.ops.setup_sfp(hw);
1828                 hw->phy.sfp_setup_needed = false;
1829         }
1830
1831         /* Reset PHY */
1832         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1833                 hw->phy.ops.reset(hw);
1834
1835 mac_reset_top:
1836         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1837          * If link reset is used when link is up, it might reset the PHY when
1838          * mng is using it.  If link is down or the flag to force full link
1839          * reset is set, then perform link reset.
1840          */
1841         ctrl = IXGBE_CTRL_LNK_RST;
1842
1843         if (!hw->force_full_reset) {
1844                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1845                 if (link_up)
1846                         ctrl = IXGBE_CTRL_RST;
1847         }
1848
1849         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1850         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1851         IXGBE_WRITE_FLUSH(hw);
1852
1853         /* Poll for reset bit to self-clear meaning reset is complete */
1854         for (i = 0; i < 10; i++) {
1855                 udelay(1);
1856                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1857                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1858                         break;
1859         }
1860
1861         if (ctrl & IXGBE_CTRL_RST_MASK) {
1862                 status = IXGBE_ERR_RESET_FAILED;
1863                 hw_dbg(hw, "Reset polling failed to complete.\n");
1864         }
1865
1866         msleep(50);
1867
1868         /* Double resets are required for recovery from certain error
1869          * clear the multicast table.  Also reset num_rar_entries to 128,
1870          * since we modify this value when programming the SAN MAC address.
1871          */
1872         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1873                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1874                 goto mac_reset_top;
1875         }
1876
1877         /* Store the permanent mac address */
1878         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1879
1880         /* Store MAC address from RAR0, clear receive address registers, and
1881          * clear the multicast table.  Also reset num_rar_entries to 128,
1882          * since we modify this value when programming the SAN MAC address.
1883          */
1884         hw->mac.num_rar_entries = 128;
1885         hw->mac.ops.init_rx_addrs(hw);
1886
1887         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1888                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1889                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1890                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1891         }
1892
1893         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1894                 ixgbe_setup_mux_ctl(hw);
1895
1896         return status;
1897 }
1898
1899 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
1900  *      anti-spoofing
1901  *  @hw:  pointer to hardware structure
1902  *  @enable: enable or disable switch for Ethertype anti-spoofing
1903  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1904  **/
1905 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1906                                                    bool enable, int vf)
1907 {
1908         int vf_target_reg = vf >> 3;
1909         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1910         u32 pfvfspoof;
1911
1912         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1913         if (enable)
1914                 pfvfspoof |= (1 << vf_target_shift);
1915         else
1916                 pfvfspoof &= ~(1 << vf_target_shift);
1917
1918         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1919 }
1920
1921 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
1922  *  @hw: pointer to hardware structure
1923  *  @enable: enable or disable source address pruning
1924  *  @pool: Rx pool to set source address pruning for
1925  **/
1926 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
1927                                                   bool enable,
1928                                                   unsigned int pool)
1929 {
1930         u64 pfflp;
1931
1932         /* max rx pool is 63 */
1933         if (pool > 63)
1934                 return;
1935
1936         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1937         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1938
1939         if (enable)
1940                 pfflp |= (1ULL << pool);
1941         else
1942                 pfflp &= ~(1ULL << pool);
1943
1944         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1945         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1946 }
1947
1948 #define X550_COMMON_MAC \
1949         .init_hw                        = &ixgbe_init_hw_generic, \
1950         .start_hw                       = &ixgbe_start_hw_X540, \
1951         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
1952         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
1953         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
1954         .get_device_caps                = &ixgbe_get_device_caps_generic, \
1955         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
1956         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
1957         .read_analog_reg8               = NULL, \
1958         .write_analog_reg8              = NULL, \
1959         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
1960         .check_link                     = &ixgbe_check_mac_link_generic, \
1961         .led_on                         = &ixgbe_led_on_generic, \
1962         .led_off                        = &ixgbe_led_off_generic, \
1963         .blink_led_start                = &ixgbe_blink_led_start_X540, \
1964         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
1965         .set_rar                        = &ixgbe_set_rar_generic, \
1966         .clear_rar                      = &ixgbe_clear_rar_generic, \
1967         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
1968         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
1969         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
1970         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
1971         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
1972         .enable_mc                      = &ixgbe_enable_mc_generic, \
1973         .disable_mc                     = &ixgbe_disable_mc_generic, \
1974         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
1975         .set_vfta                       = &ixgbe_set_vfta_generic, \
1976         .fc_enable                      = &ixgbe_fc_enable_generic, \
1977         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
1978         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
1979         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
1980         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
1981         .set_source_address_pruning     = \
1982                                 &ixgbe_set_source_address_pruning_X550, \
1983         .set_ethertype_anti_spoofing    = \
1984                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
1985         .acquire_swfw_sync              = &ixgbe_acquire_swfw_sync_X540, \
1986         .release_swfw_sync              = &ixgbe_release_swfw_sync_X540, \
1987         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
1988         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
1989         .get_thermal_sensor_data        = NULL, \
1990         .init_thermal_sensor_thresh     = NULL, \
1991         .prot_autoc_read                = &prot_autoc_read_generic, \
1992         .prot_autoc_write               = &prot_autoc_write_generic, \
1993         .enable_rx                      = &ixgbe_enable_rx_generic, \
1994         .disable_rx                     = &ixgbe_disable_rx_x550, \
1995
1996 static struct ixgbe_mac_operations mac_ops_X550 = {
1997         X550_COMMON_MAC
1998         .reset_hw               = &ixgbe_reset_hw_X540,
1999         .get_media_type         = &ixgbe_get_media_type_X540,
2000         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2001         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2002         .setup_link             = &ixgbe_setup_mac_link_X540,
2003         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2004         .get_bus_info           = &ixgbe_get_bus_info_generic,
2005         .setup_sfp              = NULL,
2006 };
2007
2008 static struct ixgbe_mac_operations mac_ops_X550EM_x = {
2009         X550_COMMON_MAC
2010         .reset_hw               = &ixgbe_reset_hw_X550em,
2011         .get_media_type         = &ixgbe_get_media_type_X550em,
2012         .get_san_mac_addr       = NULL,
2013         .get_wwn_prefix         = NULL,
2014         .setup_link             = NULL, /* defined later */
2015         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2016         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2017         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2018
2019 };
2020
2021 #define X550_COMMON_EEP \
2022         .read                   = &ixgbe_read_ee_hostif_X550, \
2023         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2024         .write                  = &ixgbe_write_ee_hostif_X550, \
2025         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
2026         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
2027         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
2028         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
2029
2030 static struct ixgbe_eeprom_operations eeprom_ops_X550 = {
2031         X550_COMMON_EEP
2032         .init_params            = &ixgbe_init_eeprom_params_X550,
2033 };
2034
2035 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
2036         X550_COMMON_EEP
2037         .init_params            = &ixgbe_init_eeprom_params_X540,
2038 };
2039
2040 #define X550_COMMON_PHY \
2041         .identify_sfp           = &ixgbe_identify_module_generic, \
2042         .reset                  = NULL, \
2043         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
2044         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
2045         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
2046         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
2047         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
2048         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
2049         .read_reg               = &ixgbe_read_phy_reg_generic, \
2050         .write_reg              = &ixgbe_write_phy_reg_generic, \
2051         .setup_link             = &ixgbe_setup_phy_link_generic, \
2052         .set_phy_power          = NULL, \
2053         .check_overtemp         = &ixgbe_tn_check_overtemp, \
2054         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
2055
2056 static struct ixgbe_phy_operations phy_ops_X550 = {
2057         X550_COMMON_PHY
2058         .init                   = NULL,
2059         .identify               = &ixgbe_identify_phy_generic,
2060 };
2061
2062 static struct ixgbe_phy_operations phy_ops_X550EM_x = {
2063         X550_COMMON_PHY
2064         .init                   = &ixgbe_init_phy_ops_X550em,
2065         .identify               = &ixgbe_identify_phy_x550em,
2066         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
2067         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
2068         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
2069         .write_i2c_combined_unlocked =
2070                                      &ixgbe_write_i2c_combined_generic_unlocked,
2071 };
2072
2073 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
2074         IXGBE_MVALS_INIT(X550)
2075 };
2076
2077 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
2078         IXGBE_MVALS_INIT(X550EM_x)
2079 };
2080
2081 struct ixgbe_info ixgbe_X550_info = {
2082         .mac                    = ixgbe_mac_X550,
2083         .get_invariants         = &ixgbe_get_invariants_X540,
2084         .mac_ops                = &mac_ops_X550,
2085         .eeprom_ops             = &eeprom_ops_X550,
2086         .phy_ops                = &phy_ops_X550,
2087         .mbx_ops                = &mbx_ops_generic,
2088         .mvals                  = ixgbe_mvals_X550,
2089 };
2090
2091 struct ixgbe_info ixgbe_X550EM_x_info = {
2092         .mac                    = ixgbe_mac_X550EM_x,
2093         .get_invariants         = &ixgbe_get_invariants_X550_x,
2094         .mac_ops                = &mac_ops_X550EM_x,
2095         .eeprom_ops             = &eeprom_ops_X550EM_x,
2096         .phy_ops                = &phy_ops_X550EM_x,
2097         .mbx_ops                = &mbx_ops_generic,
2098         .mvals                  = ixgbe_mvals_X550EM_x,
2099 };