drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2015 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  30 {
  31         struct ixgbe_mac_info *mac = &hw->mac;
  32         struct ixgbe_phy_info *phy = &hw->phy;
  33
  34         /* Start with X540 invariants, since so simular */
  35         ixgbe_get_invariants_X540(hw);
  36
  37         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  38                 phy->ops.set_phy_power = NULL;
  39
  40         return 0;
  41 }
  42
  43 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  44  *  @hw: pointer to hardware structure
  45  **/
  46 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  47 {
  48         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  49
  50         if (hw->bus.lan_id) {
  51                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  52                 esdp |= IXGBE_ESDP_SDP1_DIR;
  53         }
  54         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  55         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  56         IXGBE_WRITE_FLUSH(hw);
  57 }
  58
  59 /**
  60  * ixgbe_read_cs4227 - Read CS4227 register
  61  * @hw: pointer to hardware structure
  62  * @reg: register number to write
  63  * @value: pointer to receive value read
  64  *
  65  * Returns status code
  66  */
  67 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  68 {
  69         return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  70                                                       value);
  71 }
  72
  73 /**
  74  * ixgbe_write_cs4227 - Write CS4227 register
  75  * @hw: pointer to hardware structure
  76  * @reg: register number to write
  77  * @value: value to write to register
  78  *
  79  * Returns status code
  80  */
  81 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  82 {
  83         return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  84                                                        value);
  85 }
  86
  87 /**
  88  * ixgbe_check_cs4227_reg - Perform diag on a CS4227 register
  89  * @hw: pointer to hardware structure
  90  * @reg: the register to check
  91  *
  92  * Performs a diagnostic on a register in the CS4227 chip. Returns an error
  93  * if it is not operating correctly.
  94  * This function assumes that the caller has acquired the proper semaphore.
  95  */
  96 static s32 ixgbe_check_cs4227_reg(struct ixgbe_hw *hw, u16 reg)
  97 {
  98         s32 status;
  99         u32 retry;
 100         u16 reg_val;
 101
 102         reg_val = (IXGBE_CS4227_EDC_MODE_DIAG << 1) | 1;
 103         status = ixgbe_write_cs4227(hw, reg, reg_val);
 104         if (status)
 105                 return status;
 106         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 107                 msleep(IXGBE_CS4227_CHECK_DELAY);
 108                 reg_val = 0xFFFF;
 109                 ixgbe_read_cs4227(hw, reg, &reg_val);
 110                 if (!reg_val)
 111                         break;
 112         }
 113         if (reg_val) {
 114                 hw_err(hw, "CS4227 reg 0x%04X failed diagnostic\n", reg);
 115                 return status;
 116         }
 117
 118         return 0;
 119 }
 120
 121 /**
 122  * ixgbe_get_cs4227_status - Return CS4227 status
 123  * @hw: pointer to hardware structure
 124  *
 125  * Performs a diagnostic on the CS4227 chip. Returns an error if it is
 126  * not operating correctly.
 127  * This function assumes that the caller has acquired the proper semaphore.
 128  */
 129 static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 130 {
 131         s32 status;
 132         u16 value = 0;
 133
 134         /* Exit if the diagnostic has already been performed. */
 135         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 136         if (status)
 137                 return status;
 138         if (value == IXGBE_CS4227_RESET_COMPLETE)
 139                 return 0;
 140
 141         /* Check port 0. */
 142         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB);
 143         if (status)
 144                 return status;
 145
 146         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB);
 147         if (status)
 148                 return status;
 149
 150         /* Check port 1. */
 151         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB +
 152                                         (1 << 12));
 153         if (status)
 154                 return status;
 155
 156         return ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB +
 157                                       (1 << 12));
 158 }
 159
 160 /**
 161  * ixgbe_read_pe - Read register from port expander
 162  * @hw: pointer to hardware structure
 163  * @reg: register number to read
 164  * @value: pointer to receive read value
 165  *
 166  * Returns status code
 167  */
 168 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 169 {
 170         s32 status;
 171
 172         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 173         if (status)
 174                 hw_err(hw, "port expander access failed with %d\n", status);
 175         return status;
 176 }
 177
 178 /**
 179  * ixgbe_write_pe - Write register to port expander
 180  * @hw: pointer to hardware structure
 181  * @reg: register number to write
 182  * @value: value to write
 183  *
 184  * Returns status code
 185  */
 186 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 187 {
 188         s32 status;
 189
 190         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 191                                                        value);
 192         if (status)
 193                 hw_err(hw, "port expander access failed with %d\n", status);
 194         return status;
 195 }
 196
 197 /**
 198  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 199  * @hw: pointer to hardware structure
 200  *
 201  * Returns error code
 202  */
 203 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 204 {
 205         s32 status;
 206         u32 retry;
 207         u16 value;
 208         u8 reg;
 209
 210         /* Trigger hard reset. */
 211         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 212         if (status)
 213                 return status;
 214         reg |= IXGBE_PE_BIT1;
 215         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 216         if (status)
 217                 return status;
 218
 219         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 220         if (status)
 221                 return status;
 222         reg &= ~IXGBE_PE_BIT1;
 223         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 224         if (status)
 225                 return status;
 226
 227         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 228         if (status)
 229                 return status;
 230         reg &= ~IXGBE_PE_BIT1;
 231         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 232         if (status)
 233                 return status;
 234
 235         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 236
 237         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 238         if (status)
 239                 return status;
 240         reg |= IXGBE_PE_BIT1;
 241         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 242         if (status)
 243                 return status;
 244
 245         /* Wait for the reset to complete. */
 246         msleep(IXGBE_CS4227_RESET_DELAY);
 247         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 248                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 249                                            &value);
 250                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 251                         break;
 252                 msleep(IXGBE_CS4227_CHECK_DELAY);
 253         }
 254         if (retry == IXGBE_CS4227_RETRIES) {
 255                 hw_err(hw, "CS4227 reset did not complete\n");
 256                 return IXGBE_ERR_PHY;
 257         }
 258
 259         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 260         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 261                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 262                 return IXGBE_ERR_PHY;
 263         }
 264
 265         return 0;
 266 }
 267
 268 /**
 269  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 270  * @hw: pointer to hardware structure
 271  */
 272 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 273 {
 274         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 275         s32 status;
 276         u16 value;
 277         u8 retry;
 278
 279         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 280                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 281                 if (status) {
 282                         hw_err(hw, "semaphore failed with %d\n", status);
 283                         msleep(IXGBE_CS4227_CHECK_DELAY);
 284                         continue;
 285                 }
 286
 287                 /* Get status of reset flow. */
 288                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 289                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 290                         goto out;
 291
 292                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 293                         break;
 294
 295                 /* Reset is pending. Wait and check again. */
 296                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297                 msleep(IXGBE_CS4227_CHECK_DELAY);
 298         }
 299
 300         /* Reset the CS4227. */
 301         status = ixgbe_reset_cs4227(hw);
 302         if (status) {
 303                 hw_err(hw, "CS4227 reset failed: %d", status);
 304                 goto out;
 305         }
 306
 307         /* Reset takes so long, temporarily release semaphore in case the
 308          * other driver instance is waiting for the reset indication.
 309          */
 310         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 311                            IXGBE_CS4227_RESET_PENDING);
 312         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 313         usleep_range(10000, 12000);
 314         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 315         if (status) {
 316                 hw_err(hw, "semaphore failed with %d", status);
 317                 return;
 318         }
 319
 320         /* Is the CS4227 working correctly? */
 321         status = ixgbe_get_cs4227_status(hw);
 322         if (status) {
 323                 hw_err(hw, "CS4227 status failed: %d", status);
 324                 goto out;
 325         }
 326
 327         /* Record completion for next time. */
 328         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 329                                     IXGBE_CS4227_RESET_COMPLETE);
 330
 331 out:
 332         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 333         msleep(hw->eeprom.semaphore_delay);
 334 }
 335
 336 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 337  *  @hw: pointer to hardware structure
 338  *
 339  *  Returns error code
 340  */
 341 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 342 {
 343         switch (hw->device_id) {
 344         case IXGBE_DEV_ID_X550EM_X_SFP:
 345                 /* set up for CS4227 usage */
 346                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 347                 ixgbe_setup_mux_ctl(hw);
 348                 ixgbe_check_cs4227(hw);
 349                 return ixgbe_identify_module_generic(hw);
 350         case IXGBE_DEV_ID_X550EM_X_KX4:
 351                 hw->phy.type = ixgbe_phy_x550em_kx4;
 352                 break;
 353         case IXGBE_DEV_ID_X550EM_X_KR:
 354                 hw->phy.type = ixgbe_phy_x550em_kr;
 355                 break;
 356         case IXGBE_DEV_ID_X550EM_X_1G_T:
 357         case IXGBE_DEV_ID_X550EM_X_10G_T:
 358                 return ixgbe_identify_phy_generic(hw);
 359         default:
 360                 break;
 361         }
 362         return 0;
 363 }
 364
 365 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 366                                      u32 device_type, u16 *phy_data)
 367 {
 368         return IXGBE_NOT_IMPLEMENTED;
 369 }
 370
 371 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 372                                       u32 device_type, u16 phy_data)
 373 {
 374         return IXGBE_NOT_IMPLEMENTED;
 375 }
 376
 377 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 378  *  @hw: pointer to hardware structure
 379  *
 380  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 381  *  ixgbe_hw struct in order to set up EEPROM access.
 382  **/
 383 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 384 {
 385         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 386         u32 eec;
 387         u16 eeprom_size;
 388
 389         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 390                 eeprom->semaphore_delay = 10;
 391                 eeprom->type = ixgbe_flash;
 392
 393                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 394                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 395                                     IXGBE_EEC_SIZE_SHIFT);
 396                 eeprom->word_size = 1 << (eeprom_size +
 397                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 398
 399                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 400                        eeprom->type, eeprom->word_size);
 401         }
 402
 403         return 0;
 404 }
 405
 406 /**
 407  * ixgbe_iosf_wait - Wait for IOSF command completion
 408  * @hw: pointer to hardware structure
 409  * @ctrl: pointer to location to receive final IOSF control value
 410  *
 411  * Return: failing status on timeout
 412  *
 413  * Note: ctrl can be NULL if the IOSF control register value is not needed
 414  */
 415 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 416 {
 417         u32 i, command;
 418
 419         /* Check every 10 usec to see if the address cycle completed.
 420          * The SB IOSF BUSY bit will clear when the operation is
 421          * complete.
 422          */
 423         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 424                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 425                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 426                         break;
 427                 usleep_range(10, 20);
 428         }
 429         if (ctrl)
 430                 *ctrl = command;
 431         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 432                 hw_dbg(hw, "IOSF wait timed out\n");
 433                 return IXGBE_ERR_PHY;
 434         }
 435
 436         return 0;
 437 }
 438
 439 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 440  *  IOSF device
 441  *  @hw: pointer to hardware structure
 442  *  @reg_addr: 32 bit PHY register to write
 443  *  @device_type: 3 bit device type
 444  *  @phy_data: Pointer to read data from the register
 445  **/
 446 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 447                                        u32 device_type, u32 *data)
 448 {
 449         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 450         u32 command, error;
 451         s32 ret;
 452
 453         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 454         if (ret)
 455                 return ret;
 456
 457         ret = ixgbe_iosf_wait(hw, NULL);
 458         if (ret)
 459                 goto out;
 460
 461         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 462                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 463
 464         /* Write IOSF control register */
 465         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 466
 467         ret = ixgbe_iosf_wait(hw, &command);
 468
 469         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 470                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 471                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 472                 hw_dbg(hw, "Failed to read, error %x\n", error);
 473                 return IXGBE_ERR_PHY;
 474         }
 475
 476         if (!ret)
 477                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 478
 479 out:
 480         hw->mac.ops.release_swfw_sync(hw, gssr);
 481         return ret;
 482 }
 483
 484 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 485  *  command assuming that the semaphore is already obtained.
 486  *  @hw: pointer to hardware structure
 487  *  @offset: offset of  word in the EEPROM to read
 488  *  @data: word read from the EEPROM
 489  *
 490  *  Reads a 16 bit word from the EEPROM using the hostif.
 491  **/
 492 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 493                                           u16 *data)
 494 {
 495         s32 status;
 496         struct ixgbe_hic_read_shadow_ram buffer;
 497
 498         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 499         buffer.hdr.req.buf_lenh = 0;
 500         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 501         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 502
 503         /* convert offset from words to bytes */
 504         buffer.address = cpu_to_be32(offset * 2);
 505         /* one word */
 506         buffer.length = cpu_to_be16(sizeof(u16));
 507
 508         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 509                                               sizeof(buffer),
 510                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 511         if (status)
 512                 return status;
 513
 514         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 515                                           FW_NVM_DATA_OFFSET);
 516
 517         return 0;
 518 }
 519
 520 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 521  *  @hw: pointer to hardware structure
 522  *  @offset: offset of  word in the EEPROM to read
 523  *  @words: number of words
 524  *  @data: word(s) read from the EEPROM
 525  *
 526  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 527  **/
 528 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 529                                             u16 offset, u16 words, u16 *data)
 530 {
 531         struct ixgbe_hic_read_shadow_ram buffer;
 532         u32 current_word = 0;
 533         u16 words_to_read;
 534         s32 status;
 535         u32 i;
 536
 537         /* Take semaphore for the entire operation. */
 538         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 539         if (status) {
 540                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 541                 return status;
 542         }
 543
 544         while (words) {
 545                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 546                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 547                 else
 548                         words_to_read = words;
 549
 550                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 551                 buffer.hdr.req.buf_lenh = 0;
 552                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 553                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 554
 555                 /* convert offset from words to bytes */
 556                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 557                 buffer.length = cpu_to_be16(words_to_read * 2);
 558
 559                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 560                                                       sizeof(buffer),
 561                                                       IXGBE_HI_COMMAND_TIMEOUT,
 562                                                       false);
 563                 if (status) {
 564                         hw_dbg(hw, "Host interface command failed\n");
 565                         goto out;
 566                 }
 567
 568                 for (i = 0; i < words_to_read; i++) {
 569                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 570                                   2 * i;
 571                         u32 value = IXGBE_READ_REG(hw, reg);
 572
 573                         data[current_word] = (u16)(value & 0xffff);
 574                         current_word++;
 575                         i++;
 576                         if (i < words_to_read) {
 577                                 value >>= 16;
 578                                 data[current_word] = (u16)(value & 0xffff);
 579                                 current_word++;
 580                         }
 581                 }
 582                 words -= words_to_read;
 583         }
 584
 585 out:
 586         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 587         return status;
 588 }
 589
 590 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 591  *  @hw: pointer to hardware structure
 592  *  @ptr: pointer offset in eeprom
 593  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 594  *  @csum: address of checksum to update
 595  *
 596  *  Returns error status for any failure
 597  **/
 598 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 599                                    u16 size, u16 *csum, u16 *buffer,
 600                                    u32 buffer_size)
 601 {
 602         u16 buf[256];
 603         s32 status;
 604         u16 length, bufsz, i, start;
 605         u16 *local_buffer;
 606
 607         bufsz = sizeof(buf) / sizeof(buf[0]);
 608
 609         /* Read a chunk at the pointer location */
 610         if (!buffer) {
 611                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 612                 if (status) {
 613                         hw_dbg(hw, "Failed to read EEPROM image\n");
 614                         return status;
 615                 }
 616                 local_buffer = buf;
 617         } else {
 618                 if (buffer_size < ptr)
 619                         return  IXGBE_ERR_PARAM;
 620                 local_buffer = &buffer[ptr];
 621         }
 622
 623         if (size) {
 624                 start = 0;
 625                 length = size;
 626         } else {
 627                 start = 1;
 628                 length = local_buffer[0];
 629
 630                 /* Skip pointer section if length is invalid. */
 631                 if (length == 0xFFFF || length == 0 ||
 632                     (ptr + length) >= hw->eeprom.word_size)
 633                         return 0;
 634         }
 635
 636         if (buffer && ((u32)start + (u32)length > buffer_size))
 637                 return IXGBE_ERR_PARAM;
 638
 639         for (i = start; length; i++, length--) {
 640                 if (i == bufsz && !buffer) {
 641                         ptr += bufsz;
 642                         i = 0;
 643                         if (length < bufsz)
 644                                 bufsz = length;
 645
 646                         /* Read a chunk at the pointer location */
 647                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 648                                                                   bufsz, buf);
 649                         if (status) {
 650                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 651                                 return status;
 652                         }
 653                 }
 654                 *csum += local_buffer[i];
 655         }
 656         return 0;
 657 }
 658
 659 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 660  *  @hw: pointer to hardware structure
 661  *  @buffer: pointer to buffer containing calculated checksum
 662  *  @buffer_size: size of buffer
 663  *
 664  *  Returns a negative error code on error, or the 16-bit checksum
 665  **/
 666 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 667                                     u32 buffer_size)
 668 {
 669         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 670         u16 *local_buffer;
 671         s32 status;
 672         u16 checksum = 0;
 673         u16 pointer, i, size;
 674
 675         hw->eeprom.ops.init_params(hw);
 676
 677         if (!buffer) {
 678                 /* Read pointer area */
 679                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 680                                                 IXGBE_EEPROM_LAST_WORD + 1,
 681                                                 eeprom_ptrs);
 682                 if (status) {
 683                         hw_dbg(hw, "Failed to read EEPROM image\n");
 684                         return status;
 685                 }
 686                 local_buffer = eeprom_ptrs;
 687         } else {
 688                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 689                         return IXGBE_ERR_PARAM;
 690                 local_buffer = buffer;
 691         }
 692
 693         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 694          * checksum word itself
 695          */
 696         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 697                 if (i != IXGBE_EEPROM_CHECKSUM)
 698                         checksum += local_buffer[i];
 699
 700         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 701          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 702          */
 703         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 704                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 705                         continue;
 706
 707                 pointer = local_buffer[i];
 708
 709                 /* Skip pointer section if the pointer is invalid. */
 710                 if (pointer == 0xFFFF || pointer == 0 ||
 711                     pointer >= hw->eeprom.word_size)
 712                         continue;
 713
 714                 switch (i) {
 715                 case IXGBE_PCIE_GENERAL_PTR:
 716                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 717                         break;
 718                 case IXGBE_PCIE_CONFIG0_PTR:
 719                 case IXGBE_PCIE_CONFIG1_PTR:
 720                         size = IXGBE_PCIE_CONFIG_SIZE;
 721                         break;
 722                 default:
 723                         size = 0;
 724                         break;
 725                 }
 726
 727                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 728                                                  buffer, buffer_size);
 729                 if (status)
 730                         return status;
 731         }
 732
 733         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 734
 735         return (s32)checksum;
 736 }
 737
 738 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 739  *  @hw: pointer to hardware structure
 740  *
 741  *  Returns a negative error code on error, or the 16-bit checksum
 742  **/
 743 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 744 {
 745         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 746 }
 747
 748 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 749  *  @hw: pointer to hardware structure
 750  *  @offset: offset of  word in the EEPROM to read
 751  *  @data: word read from the EEPROM
 752  *
 753  *   Reads a 16 bit word from the EEPROM using the hostif.
 754  **/
 755 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 756 {
 757         s32 status = 0;
 758
 759         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 760                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 761                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 762         } else {
 763                 status = IXGBE_ERR_SWFW_SYNC;
 764         }
 765
 766         return status;
 767 }
 768
 769 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 770  *  @hw: pointer to hardware structure
 771  *  @checksum_val: calculated checksum
 772  *
 773  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 774  *  caller does not need checksum_val, the value can be NULL.
 775  **/
 776 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 777                                                u16 *checksum_val)
 778 {
 779         s32 status;
 780         u16 checksum;
 781         u16 read_checksum = 0;
 782
 783         /* Read the first word from the EEPROM. If this times out or fails, do
 784          * not continue or we could be in for a very long wait while every
 785          * EEPROM read fails
 786          */
 787         status = hw->eeprom.ops.read(hw, 0, &checksum);
 788         if (status) {
 789                 hw_dbg(hw, "EEPROM read failed\n");
 790                 return status;
 791         }
 792
 793         status = hw->eeprom.ops.calc_checksum(hw);
 794         if (status < 0)
 795                 return status;
 796
 797         checksum = (u16)(status & 0xffff);
 798
 799         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 800                                            &read_checksum);
 801         if (status)
 802                 return status;
 803
 804         /* Verify read checksum from EEPROM is the same as
 805          * calculated checksum
 806          */
 807         if (read_checksum != checksum) {
 808                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 809                 hw_dbg(hw, "Invalid EEPROM checksum");
 810         }
 811
 812         /* If the user cares, return the calculated checksum */
 813         if (checksum_val)
 814                 *checksum_val = checksum;
 815
 816         return status;
 817 }
 818
 819 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 820  *  @hw: pointer to hardware structure
 821  *  @offset: offset of  word in the EEPROM to write
 822  *  @data: word write to the EEPROM
 823  *
 824  *  Write a 16 bit word to the EEPROM using the hostif.
 825  **/
 826 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 827                                            u16 data)
 828 {
 829         s32 status;
 830         struct ixgbe_hic_write_shadow_ram buffer;
 831
 832         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 833         buffer.hdr.req.buf_lenh = 0;
 834         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 835         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 836
 837         /* one word */
 838         buffer.length = cpu_to_be16(sizeof(u16));
 839         buffer.data = data;
 840         buffer.address = cpu_to_be32(offset * 2);
 841
 842         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 843                                               sizeof(buffer),
 844                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 845         return status;
 846 }
 847
 848 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 849  *  @hw: pointer to hardware structure
 850  *  @offset: offset of  word in the EEPROM to write
 851  *  @data: word write to the EEPROM
 852  *
 853  *  Write a 16 bit word to the EEPROM using the hostif.
 854  **/
 855 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 856 {
 857         s32 status = 0;
 858
 859         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 860                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 861                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 862         } else {
 863                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 864                 status = IXGBE_ERR_SWFW_SYNC;
 865         }
 866
 867         return status;
 868 }
 869
 870 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 871  *  @hw: pointer to hardware structure
 872  *
 873  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 874  **/
 875 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 876 {
 877         s32 status = 0;
 878         union ixgbe_hic_hdr2 buffer;
 879
 880         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 881         buffer.req.buf_lenh = 0;
 882         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 883         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 884
 885         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 886                                               sizeof(buffer),
 887                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 888         return status;
 889 }
 890
 891 /**
 892  * ixgbe_get_bus_info_X550em - Set PCI bus info
 893  * @hw: pointer to hardware structure
 894  *
 895  * Sets bus link width and speed to unknown because X550em is
 896  * not a PCI device.
 897  **/
 898 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 899 {
 900         hw->bus.type  = ixgbe_bus_type_internal;
 901         hw->bus.width = ixgbe_bus_width_unknown;
 902         hw->bus.speed = ixgbe_bus_speed_unknown;
 903
 904         hw->mac.ops.set_lan_id(hw);
 905
 906         return 0;
 907 }
 908
 909 /** ixgbe_disable_rx_x550 - Disable RX unit
 910  *
 911  *  Enables the Rx DMA unit for x550
 912  **/
 913 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 914 {
 915         u32 rxctrl, pfdtxgswc;
 916         s32 status;
 917         struct ixgbe_hic_disable_rxen fw_cmd;
 918
 919         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 920         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 921                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 922                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 923                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 924                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 925                         hw->mac.set_lben = true;
 926                 } else {
 927                         hw->mac.set_lben = false;
 928                 }
 929
 930                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 931                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 932                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 933                 fw_cmd.port_number = (u8)hw->bus.lan_id;
 934
 935                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
 936                                         sizeof(struct ixgbe_hic_disable_rxen),
 937                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 938
 939                 /* If we fail - disable RX using register write */
 940                 if (status) {
 941                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 942                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 943                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
 944                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
 945                         }
 946                 }
 947         }
 948 }
 949
 950 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
 951  *  @hw: pointer to hardware structure
 952  *
 953  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
 954  *  checksum and updates the EEPROM and instructs the hardware to update
 955  *  the flash.
 956  **/
 957 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
 958 {
 959         s32 status;
 960         u16 checksum = 0;
 961
 962         /* Read the first word from the EEPROM. If this times out or fails, do
 963          * not continue or we could be in for a very long wait while every
 964          * EEPROM read fails
 965          */
 966         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
 967         if (status) {
 968                 hw_dbg(hw, "EEPROM read failed\n");
 969                 return status;
 970         }
 971
 972         status = ixgbe_calc_eeprom_checksum_X550(hw);
 973         if (status < 0)
 974                 return status;
 975
 976         checksum = (u16)(status & 0xffff);
 977
 978         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 979                                             checksum);
 980         if (status)
 981                 return status;
 982
 983         status = ixgbe_update_flash_X550(hw);
 984
 985         return status;
 986 }
 987
 988 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
 989  *  @hw: pointer to hardware structure
 990  *  @offset: offset of  word in the EEPROM to write
 991  *  @words: number of words
 992  *  @data: word(s) write to the EEPROM
 993  *
 994  *
 995  *  Write a 16 bit word(s) to the EEPROM using the hostif.
 996  **/
 997 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 998                                              u16 offset, u16 words,
 999                                              u16 *data)
1000 {
1001         s32 status = 0;
1002         u32 i = 0;
1003
1004         /* Take semaphore for the entire operation. */
1005         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1006         if (status) {
1007                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1008                 return status;
1009         }
1010
1011         for (i = 0; i < words; i++) {
1012                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1013                                                          data[i]);
1014                 if (status) {
1015                         hw_dbg(hw, "Eeprom buffered write failed\n");
1016                         break;
1017                 }
1018         }
1019
1020         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1021
1022         return status;
1023 }
1024
1025 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1026  *  IOSF device
1027  *
1028  *  @hw: pointer to hardware structure
1029  *  @reg_addr: 32 bit PHY register to write
1030  *  @device_type: 3 bit device type
1031  *  @data: Data to write to the register
1032  **/
1033 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1034                                         u32 device_type, u32 data)
1035 {
1036         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1037         u32 command, error;
1038         s32 ret;
1039
1040         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1041         if (ret)
1042                 return ret;
1043
1044         ret = ixgbe_iosf_wait(hw, NULL);
1045         if (ret)
1046                 goto out;
1047
1048         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1049                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1050
1051         /* Write IOSF control register */
1052         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1053
1054         /* Write IOSF data register */
1055         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1056
1057         ret = ixgbe_iosf_wait(hw, &command);
1058
1059         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1060                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1061                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1062                 hw_dbg(hw, "Failed to write, error %x\n", error);
1063                 return IXGBE_ERR_PHY;
1064         }
1065
1066 out:
1067         hw->mac.ops.release_swfw_sync(hw, gssr);
1068         return ret;
1069 }
1070
1071 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1072  *  @hw: pointer to hardware structure
1073  *  @speed: the link speed to force
1074  *
1075  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1076  *  internal and external PHY at a specific speed, without autonegotiation.
1077  **/
1078 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1079 {
1080         s32 status;
1081         u32 reg_val;
1082
1083         /* Disable AN and force speed to 10G Serial. */
1084         status = ixgbe_read_iosf_sb_reg_x550(hw,
1085                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1086                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1087         if (status)
1088                 return status;
1089
1090         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1091         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1092
1093         /* Select forced link speed for internal PHY. */
1094         switch (*speed) {
1095         case IXGBE_LINK_SPEED_10GB_FULL:
1096                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1097                 break;
1098         case IXGBE_LINK_SPEED_1GB_FULL:
1099                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1100                 break;
1101         default:
1102                 /* Other link speeds are not supported by internal KR PHY. */
1103                 return IXGBE_ERR_LINK_SETUP;
1104         }
1105
1106         status = ixgbe_write_iosf_sb_reg_x550(hw,
1107                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1108                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1109         if (status)
1110                 return status;
1111
1112         /* Disable training protocol FSM. */
1113         status = ixgbe_read_iosf_sb_reg_x550(hw,
1114                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1115                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1116         if (status)
1117                 return status;
1118
1119         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1120         status = ixgbe_write_iosf_sb_reg_x550(hw,
1121                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1122                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1123         if (status)
1124                 return status;
1125
1126         /* Disable Flex from training TXFFE. */
1127         status = ixgbe_read_iosf_sb_reg_x550(hw,
1128                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1129                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1130         if (status)
1131                 return status;
1132
1133         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1134         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1135         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1136         status = ixgbe_write_iosf_sb_reg_x550(hw,
1137                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1138                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1139         if (status)
1140                 return status;
1141
1142         status = ixgbe_read_iosf_sb_reg_x550(hw,
1143                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1144                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1145         if (status)
1146                 return status;
1147
1148         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1149         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1150         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1151         status = ixgbe_write_iosf_sb_reg_x550(hw,
1152                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1153                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1154         if (status)
1155                 return status;
1156
1157         /* Enable override for coefficients. */
1158         status = ixgbe_read_iosf_sb_reg_x550(hw,
1159                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1160                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1161         if (status)
1162                 return status;
1163
1164         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1165         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1166         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1167         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1168         status = ixgbe_write_iosf_sb_reg_x550(hw,
1169                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1170                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1171         if (status)
1172                 return status;
1173
1174         /* Toggle port SW reset by AN reset. */
1175         status = ixgbe_read_iosf_sb_reg_x550(hw,
1176                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1177                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1178         if (status)
1179                 return status;
1180
1181         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1182         status = ixgbe_write_iosf_sb_reg_x550(hw,
1183                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1184                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1185
1186         return status;
1187 }
1188
1189 /**
1190  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1191  *  @hw: pointer to hardware structure
1192  *  @linear: true if SFP module is linear
1193  */
1194 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1195 {
1196         switch (hw->phy.sfp_type) {
1197         case ixgbe_sfp_type_not_present:
1198                 return IXGBE_ERR_SFP_NOT_PRESENT;
1199         case ixgbe_sfp_type_da_cu_core0:
1200         case ixgbe_sfp_type_da_cu_core1:
1201                 *linear = true;
1202                 break;
1203         case ixgbe_sfp_type_srlr_core0:
1204         case ixgbe_sfp_type_srlr_core1:
1205         case ixgbe_sfp_type_da_act_lmt_core0:
1206         case ixgbe_sfp_type_da_act_lmt_core1:
1207         case ixgbe_sfp_type_1g_sx_core0:
1208         case ixgbe_sfp_type_1g_sx_core1:
1209         case ixgbe_sfp_type_1g_lx_core0:
1210         case ixgbe_sfp_type_1g_lx_core1:
1211                 *linear = false;
1212                 break;
1213         case ixgbe_sfp_type_unknown:
1214         case ixgbe_sfp_type_1g_cu_core0:
1215         case ixgbe_sfp_type_1g_cu_core1:
1216         default:
1217                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1218         }
1219
1220         return 0;
1221 }
1222
1223 /**
1224  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1225  *  @hw: pointer to hardware structure
1226  *
1227  *  Configures the extern PHY and the integrated KR PHY for SFP support.
1228  */
1229 static s32
1230 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1231                                 ixgbe_link_speed speed,
1232                                 __always_unused bool autoneg_wait_to_complete)
1233 {
1234         s32 status;
1235         u16 slice, value;
1236         bool setup_linear = false;
1237
1238         /* Check if SFP module is supported and linear */
1239         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1240
1241         /* If no SFP module present, then return success. Return success since
1242          * there is no reason to configure CS4227 and SFP not present error is
1243          * not accepted in the setup MAC link flow.
1244          */
1245         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1246                 return 0;
1247
1248         if (status)
1249                 return status;
1250
1251         /* Configure CS4227 LINE side to 10G SR. */
1252         slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1253         value = IXGBE_CS4227_SPEED_10G;
1254         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1255                                                   value);
1256
1257         /* Configure CS4227 for HOST connection rate then type. */
1258         slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1259         value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1260                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1261         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1262                                                   value);
1263
1264         slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1265         if (setup_linear)
1266                 value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1267         else
1268                 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1269         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1270                                                   value);
1271
1272         /* If internal link mode is XFI, then setup XFI internal link. */
1273         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1274                 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1275
1276         return status;
1277 }
1278
1279 /**
1280  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1281  * @hw: pointer to hardware structure
1282  * @speed: new link speed
1283  * @autoneg_wait_to_complete: true when waiting for completion is needed
1284  *
1285  * Setup internal/external PHY link speed based on link speed, then set
1286  * external PHY auto advertised link speed.
1287  *
1288  * Returns error status for any failure
1289  **/
1290 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1291                                          ixgbe_link_speed speed,
1292                                          bool autoneg_wait)
1293 {
1294         s32 status;
1295         ixgbe_link_speed force_speed;
1296
1297         /* Setup internal/external PHY link speed to iXFI (10G), unless
1298          * only 1G is auto advertised then setup KX link.
1299          */
1300         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1301                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1302         else
1303                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1304
1305         /* If internal link mode is XFI, then setup XFI internal link. */
1306         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1307                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1308
1309                 if (status)
1310                         return status;
1311         }
1312
1313         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1314 }
1315
1316 /** ixgbe_check_link_t_X550em - Determine link and speed status
1317   * @hw: pointer to hardware structure
1318   * @speed: pointer to link speed
1319   * @link_up: true when link is up
1320   * @link_up_wait_to_complete: bool used to wait for link up or not
1321   *
1322   * Check that both the MAC and X557 external PHY have link.
1323   **/
1324 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1325                                      ixgbe_link_speed *speed,
1326                                      bool *link_up,
1327                                      bool link_up_wait_to_complete)
1328 {
1329         u32 status;
1330         u16 autoneg_status;
1331
1332         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1333                 return IXGBE_ERR_CONFIG;
1334
1335         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1336                                               link_up_wait_to_complete);
1337
1338         /* If check link fails or MAC link is not up, then return */
1339         if (status || !(*link_up))
1340                 return status;
1341
1342          /* MAC link is up, so check external PHY link.
1343           * Read this twice back to back to indicate current status.
1344           */
1345         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1346                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1347                                       &autoneg_status);
1348         if (status)
1349                 return status;
1350
1351         /* If external PHY link is not up, then indicate link not up */
1352         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1353                 *link_up = false;
1354
1355         return 0;
1356 }
1357
1358 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1359  *  @hw: pointer to hardware structure
1360  **/
1361 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1362 {
1363         struct ixgbe_mac_info *mac = &hw->mac;
1364
1365         switch (mac->ops.get_media_type(hw)) {
1366         case ixgbe_media_type_fiber:
1367                 /* CS4227 does not support autoneg, so disable the laser control
1368                  * functions for SFP+ fiber
1369                  */
1370                 mac->ops.disable_tx_laser = NULL;
1371                 mac->ops.enable_tx_laser = NULL;
1372                 mac->ops.flap_tx_laser = NULL;
1373                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1374                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1375                 mac->ops.set_rate_select_speed =
1376                                         ixgbe_set_soft_rate_select_speed;
1377                 break;
1378         case ixgbe_media_type_copper:
1379                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1380                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1381                 break;
1382         default:
1383                 break;
1384         }
1385 }
1386
1387 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1388  * @hw: pointer to hardware structure
1389  */
1390 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1391 {
1392         s32 status;
1393         bool linear;
1394
1395         /* Check if SFP module is supported */
1396         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1397         if (status)
1398                 return status;
1399
1400         ixgbe_init_mac_link_ops_X550em(hw);
1401         hw->phy.ops.reset = NULL;
1402
1403         return 0;
1404 }
1405
1406 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1407  * @hw: pointer to hardware structure
1408  * @speed: pointer to link speed
1409  * @autoneg: true when autoneg or autotry is enabled
1410  **/
1411 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1412                                               ixgbe_link_speed *speed,
1413                                               bool *autoneg)
1414 {
1415         /* SFP */
1416         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1417                 /* CS4227 SFP must not enable auto-negotiation */
1418                 *autoneg = false;
1419
1420                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1421                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
1422                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1423                         return 0;
1424                 }
1425
1426                 /* Link capabilities are based on SFP */
1427                 if (hw->phy.multispeed_fiber)
1428                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1429                                  IXGBE_LINK_SPEED_1GB_FULL;
1430                 else
1431                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1432         } else {
1433                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1434                          IXGBE_LINK_SPEED_1GB_FULL;
1435                 *autoneg = true;
1436         }
1437         return 0;
1438 }
1439
1440 /**
1441  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1442  * @hw: pointer to hardware structure
1443  * @lsc: pointer to boolean flag which indicates whether external Base T
1444  *       PHY interrupt is lsc
1445  *
1446  * Determime if external Base T PHY interrupt cause is high temperature
1447  * failure alarm or link status change.
1448  *
1449  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1450  * failure alarm, else return PHY access status.
1451  **/
1452 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1453 {
1454         u32 status;
1455         u16 reg;
1456
1457         *lsc = false;
1458
1459         /* Vendor alarm triggered */
1460         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1461                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1462                                       &reg);
1463
1464         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1465                 return status;
1466
1467         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1468         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1469                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1470                                       &reg);
1471
1472         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1473                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1474                 return status;
1475
1476         /* High temperature failure alarm triggered */
1477         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1478                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1479                                       &reg);
1480
1481         if (status)
1482                 return status;
1483
1484         /* If high temperature failure, then return over temp error and exit */
1485         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1486                 /* power down the PHY in case the PHY FW didn't already */
1487                 ixgbe_set_copper_phy_power(hw, false);
1488                 return IXGBE_ERR_OVERTEMP;
1489         }
1490
1491         /* Vendor alarm 2 triggered */
1492         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1493                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1494
1495         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1496                 return status;
1497
1498         /* link connect/disconnect event occurred */
1499         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1500                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1501
1502         if (status)
1503                 return status;
1504
1505         /* Indicate LSC */
1506         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1507                 *lsc = true;
1508
1509         return 0;
1510 }
1511
1512 /**
1513  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1514  * @hw: pointer to hardware structure
1515  *
1516  * Enable link status change and temperature failure alarm for the external
1517  * Base T PHY
1518  *
1519  * Returns PHY access status
1520  **/
1521 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1522 {
1523         u32 status;
1524         u16 reg;
1525         bool lsc;
1526
1527         /* Clear interrupt flags */
1528         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1529
1530         /* Enable link status change alarm */
1531         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1532                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1533         if (status)
1534                 return status;
1535
1536         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1537
1538         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1539                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1540         if (status)
1541                 return status;
1542
1543         /* Enables high temperature failure alarm */
1544         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1545                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1546                                       &reg);
1547         if (status)
1548                 return status;
1549
1550         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1551
1552         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1553                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1554                                        reg);
1555         if (status)
1556                 return status;
1557
1558         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1559         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1560                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1561                                       &reg);
1562         if (status)
1563                 return status;
1564
1565         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1566                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1567
1568         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1569                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1570                                        reg);
1571         if (status)
1572                 return status;
1573
1574         /* Enable chip-wide vendor alarm */
1575         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1576                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1577                                       &reg);
1578         if (status)
1579                 return status;
1580
1581         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1582
1583         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1584                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1585                                        reg);
1586
1587         return status;
1588 }
1589
1590 /**
1591  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1592  * @hw: pointer to hardware structure
1593  *
1594  * Handle external Base T PHY interrupt. If high temperature
1595  * failure alarm then return error, else if link status change
1596  * then setup internal/external PHY link
1597  *
1598  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1599  * failure alarm, else return PHY access status.
1600  **/
1601 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1602 {
1603         struct ixgbe_phy_info *phy = &hw->phy;
1604         bool lsc;
1605         u32 status;
1606
1607         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1608         if (status)
1609                 return status;
1610
1611         if (lsc)
1612                 return phy->ops.setup_internal_link(hw);
1613
1614         return 0;
1615 }
1616
1617 /**
1618  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1619  * @hw: pointer to hardware structure
1620  * @speed: link speed
1621  *
1622  * Configures the integrated KR PHY.
1623  **/
1624 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1625                                        ixgbe_link_speed speed)
1626 {
1627         s32 status;
1628         u32 reg_val;
1629
1630         status = ixgbe_read_iosf_sb_reg_x550(hw,
1631                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1632                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1633         if (status)
1634                 return status;
1635
1636         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1637         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1638                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1639         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1640                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1641
1642         /* Advertise 10G support. */
1643         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1644                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1645
1646         /* Advertise 1G support. */
1647         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1648                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1649
1650         /* Restart auto-negotiation. */
1651         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1652         status = ixgbe_write_iosf_sb_reg_x550(hw,
1653                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1654                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1655
1656         return status;
1657 }
1658
1659 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1660  *  @hw: pointer to hardware structure
1661  *
1662  *   Configures the integrated KX4 PHY.
1663  **/
1664 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1665 {
1666         s32 status;
1667         u32 reg_val;
1668
1669         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1670                                              IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1671                                              hw->bus.lan_id, &reg_val);
1672         if (status)
1673                 return status;
1674
1675         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1676                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1677
1678         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1679
1680         /* Advertise 10G support. */
1681         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1682                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1683
1684         /* Advertise 1G support. */
1685         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1686                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1687
1688         /* Restart auto-negotiation. */
1689         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1690         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1691                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1692                                               hw->bus.lan_id, reg_val);
1693
1694         return status;
1695 }
1696
1697 /**  ixgbe_setup_kr_x550em - Configure the KR PHY.
1698  *   @hw: pointer to hardware structure
1699  *
1700  *   Configures the integrated KR PHY.
1701  **/
1702 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1703 {
1704         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1705 }
1706
1707 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1708  *  @hw: address of hardware structure
1709  *  @link_up: address of boolean to indicate link status
1710  *
1711  *  Returns error code if unable to get link status.
1712  **/
1713 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1714 {
1715         u32 ret;
1716         u16 autoneg_status;
1717
1718         *link_up = false;
1719
1720         /* read this twice back to back to indicate current status */
1721         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1722                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1723                                    &autoneg_status);
1724         if (ret)
1725                 return ret;
1726
1727         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1728                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1729                                    &autoneg_status);
1730         if (ret)
1731                 return ret;
1732
1733         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1734
1735         return 0;
1736 }
1737
1738 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1739  *  @hw: point to hardware structure
1740  *
1741  *  Configures the link between the integrated KR PHY and the external X557 PHY
1742  *  The driver will call this function when it gets a link status change
1743  *  interrupt from the X557 PHY. This function configures the link speed
1744  *  between the PHYs to match the link speed of the BASE-T link.
1745  *
1746  * A return of a non-zero value indicates an error, and the base driver should
1747  * not report link up.
1748  **/
1749 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1750 {
1751         ixgbe_link_speed force_speed;
1752         bool link_up;
1753         u32 status;
1754         u16 speed;
1755
1756         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1757                 return IXGBE_ERR_CONFIG;
1758
1759         /* If link is not up, then there is no setup necessary so return  */
1760         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1761         if (status)
1762                 return status;
1763
1764         if (!link_up)
1765                 return 0;
1766
1767         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1768                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1769                                       &speed);
1770         if (status)
1771                 return status;
1772
1773         /* If link is not still up, then no setup is necessary so return */
1774         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1775         if (status)
1776                 return status;
1777
1778         if (!link_up)
1779                 return 0;
1780
1781         /* clear everything but the speed and duplex bits */
1782         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1783
1784         switch (speed) {
1785         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1786                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1787                 break;
1788         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1789                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1790                 break;
1791         default:
1792                 /* Internal PHY does not support anything else */
1793                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1794         }
1795
1796         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1797 }
1798
1799 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
1800  *  @hw: pointer to hardware structure
1801  **/
1802 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
1803 {
1804         s32 status;
1805
1806         status = ixgbe_reset_phy_generic(hw);
1807
1808         if (status)
1809                 return status;
1810
1811         /* Configure Link Status Alarm and Temperature Threshold interrupts */
1812         return ixgbe_enable_lasi_ext_t_x550em(hw);
1813 }
1814
1815 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
1816  *  @hw: pointer to hardware structure
1817  *  @lcd_speed: pointer to lowest common link speed
1818  *
1819  *  Determine lowest common link speed with link partner.
1820  **/
1821 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
1822                                   ixgbe_link_speed *lcd_speed)
1823 {
1824         u16 an_lp_status;
1825         s32 status;
1826         u16 word = hw->eeprom.ctrl_word_3;
1827
1828         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
1829
1830         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
1831                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1832                                       &an_lp_status);
1833         if (status)
1834                 return status;
1835
1836         /* If link partner advertised 1G, return 1G */
1837         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
1838                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
1839                 return status;
1840         }
1841
1842         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
1843         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
1844             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
1845                 return status;
1846
1847         /* Link partner not capable of lower speeds, return 10G */
1848         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
1849         return status;
1850 }
1851
1852 /** ixgbe_enter_lplu_x550em - Transition to low power states
1853  *  @hw: pointer to hardware structure
1854  *
1855  *  Configures Low Power Link Up on transition to low power states
1856  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
1857  *  the X557 PHY immediately prior to entering LPLU.
1858  **/
1859 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
1860 {
1861         u16 an_10g_cntl_reg, autoneg_reg, speed;
1862         s32 status;
1863         ixgbe_link_speed lcd_speed;
1864         u32 save_autoneg;
1865         bool link_up;
1866
1867         /* SW LPLU not required on later HW revisions. */
1868         if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
1869                 return 0;
1870
1871         /* If blocked by MNG FW, then don't restart AN */
1872         if (ixgbe_check_reset_blocked(hw))
1873                 return 0;
1874
1875         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1876         if (status)
1877                 return status;
1878
1879         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
1880                                      &hw->eeprom.ctrl_word_3);
1881         if (status)
1882                 return status;
1883
1884         /* If link is down, LPLU disabled in NVM, WoL disabled, or
1885          * manageability disabled, then force link down by entering
1886          * low power mode.
1887          */
1888         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
1889             !(hw->wol_enabled || ixgbe_mng_present(hw)))
1890                 return ixgbe_set_copper_phy_power(hw, false);
1891
1892         /* Determine LCD */
1893         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
1894         if (status)
1895                 return status;
1896
1897         /* If no valid LCD link speed, then force link down and exit. */
1898         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
1899                 return ixgbe_set_copper_phy_power(hw, false);
1900
1901         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1902                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1903                                       &speed);
1904         if (status)
1905                 return status;
1906
1907         /* If no link now, speed is invalid so take link down */
1908         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1909         if (status)
1910                 return ixgbe_set_copper_phy_power(hw, false);
1911
1912         /* clear everything but the speed bits */
1913         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
1914
1915         /* If current speed is already LCD, then exit. */
1916         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
1917              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
1918             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
1919              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
1920                 return status;
1921
1922         /* Clear AN completed indication */
1923         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
1924                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1925                                       &autoneg_reg);
1926         if (status)
1927                 return status;
1928
1929         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1930                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1931                                       &an_10g_cntl_reg);
1932         if (status)
1933                 return status;
1934
1935         status = hw->phy.ops.read_reg(hw,
1936                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1937                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1938                                       &autoneg_reg);
1939         if (status)
1940                 return status;
1941
1942         save_autoneg = hw->phy.autoneg_advertised;
1943
1944         /* Setup link at least common link speed */
1945         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
1946
1947         /* restore autoneg from before setting lplu speed */
1948         hw->phy.autoneg_advertised = save_autoneg;
1949
1950         return status;
1951 }
1952
1953 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1954  *  @hw: pointer to hardware structure
1955  *
1956  *  Initialize any function pointers that were not able to be
1957  *  set during init_shared_code because the PHY/SFP type was
1958  *  not known.  Perform the SFP init if necessary.
1959  **/
1960 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1961 {
1962         struct ixgbe_phy_info *phy = &hw->phy;
1963         ixgbe_link_speed speed;
1964         s32 ret_val;
1965
1966         hw->mac.ops.set_lan_id(hw);
1967
1968         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1969                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1970                 ixgbe_setup_mux_ctl(hw);
1971
1972                 /* Save NW management interface connected on board. This is used
1973                  * to determine internal PHY mode.
1974                  */
1975                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1976
1977                 /* If internal PHY mode is KR, then initialize KR link */
1978                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1979                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1980                                 IXGBE_LINK_SPEED_1GB_FULL;
1981                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1982                 }
1983         }
1984
1985         /* Identify the PHY or SFP module */
1986         ret_val = phy->ops.identify(hw);
1987
1988         /* Setup function pointers based on detected hardware */
1989         ixgbe_init_mac_link_ops_X550em(hw);
1990         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1991                 phy->ops.reset = NULL;
1992
1993         /* Set functions pointers based on phy type */
1994         switch (hw->phy.type) {
1995         case ixgbe_phy_x550em_kx4:
1996                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1997                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1998                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1999                 break;
2000         case ixgbe_phy_x550em_kr:
2001                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2002                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2003                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2004                 break;
2005         case ixgbe_phy_x550em_ext_t:
2006                 /* Save NW management interface connected on board. This is used
2007                  * to determine internal PHY mode
2008                  */
2009                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2010
2011                 /* If internal link mode is XFI, then setup iXFI internal link,
2012                  * else setup KR now.
2013                  */
2014                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2015                         phy->ops.setup_internal_link =
2016                                         ixgbe_setup_internal_phy_t_x550em;
2017                 } else {
2018                         speed = IXGBE_LINK_SPEED_10GB_FULL |
2019                                 IXGBE_LINK_SPEED_1GB_FULL;
2020                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
2021                 }
2022
2023                 /* setup SW LPLU only for first revision */
2024                 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
2025                                                         IXGBE_FUSES0_GROUP(0))))
2026                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2027
2028                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2029                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2030                 break;
2031         default:
2032                 break;
2033         }
2034
2035         return ret_val;
2036 }
2037
2038 /** ixgbe_get_media_type_X550em - Get media type
2039  *  @hw: pointer to hardware structure
2040  *
2041  *  Returns the media type (fiber, copper, backplane)
2042  *
2043  */
2044 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2045 {
2046         enum ixgbe_media_type media_type;
2047
2048         /* Detect if there is a copper PHY attached. */
2049         switch (hw->device_id) {
2050         case IXGBE_DEV_ID_X550EM_X_KR:
2051         case IXGBE_DEV_ID_X550EM_X_KX4:
2052                 media_type = ixgbe_media_type_backplane;
2053                 break;
2054         case IXGBE_DEV_ID_X550EM_X_SFP:
2055                 media_type = ixgbe_media_type_fiber;
2056                 break;
2057         case IXGBE_DEV_ID_X550EM_X_1G_T:
2058         case IXGBE_DEV_ID_X550EM_X_10G_T:
2059                  media_type = ixgbe_media_type_copper;
2060                 break;
2061         default:
2062                 media_type = ixgbe_media_type_unknown;
2063                 break;
2064         }
2065         return media_type;
2066 }
2067
2068 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2069  ** @hw: pointer to hardware structure
2070  **/
2071 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2072 {
2073         s32 status;
2074         u16 reg;
2075
2076         status = hw->phy.ops.read_reg(hw,
2077                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2078                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2079                                       &reg);
2080         if (status)
2081                 return status;
2082
2083         /* If PHY FW reset completed bit is set then this is the first
2084          * SW instance after a power on so the PHY FW must be un-stalled.
2085          */
2086         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2087                 status = hw->phy.ops.read_reg(hw,
2088                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2089                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2090                                         &reg);
2091                 if (status)
2092                         return status;
2093
2094                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2095
2096                 status = hw->phy.ops.write_reg(hw,
2097                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2098                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2099                                         reg);
2100                 if (status)
2101                         return status;
2102         }
2103
2104         return status;
2105 }
2106
2107 /**  ixgbe_reset_hw_X550em - Perform hardware reset
2108  **  @hw: pointer to hardware structure
2109  **
2110  **  Resets the hardware by resetting the transmit and receive units, masks
2111  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2112  **  reset.
2113  **/
2114 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2115 {
2116         ixgbe_link_speed link_speed;
2117         s32 status;
2118         u32 ctrl = 0;
2119         u32 i;
2120         u32 hlreg0;
2121         bool link_up = false;
2122
2123         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2124         status = hw->mac.ops.stop_adapter(hw);
2125         if (status)
2126                 return status;
2127
2128         /* flush pending Tx transactions */
2129         ixgbe_clear_tx_pending(hw);
2130
2131         /* PHY ops must be identified and initialized prior to reset */
2132
2133         /* Identify PHY and related function pointers */
2134         status = hw->phy.ops.init(hw);
2135
2136         /* start the external PHY */
2137         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2138                 status = ixgbe_init_ext_t_x550em(hw);
2139                 if (status)
2140                         return status;
2141         }
2142
2143         /* Setup SFP module if there is one present. */
2144         if (hw->phy.sfp_setup_needed) {
2145                 status = hw->mac.ops.setup_sfp(hw);
2146                 hw->phy.sfp_setup_needed = false;
2147         }
2148
2149         /* Reset PHY */
2150         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2151                 hw->phy.ops.reset(hw);
2152
2153 mac_reset_top:
2154         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2155          * If link reset is used when link is up, it might reset the PHY when
2156          * mng is using it.  If link is down or the flag to force full link
2157          * reset is set, then perform link reset.
2158          */
2159         ctrl = IXGBE_CTRL_LNK_RST;
2160
2161         if (!hw->force_full_reset) {
2162                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2163                 if (link_up)
2164                         ctrl = IXGBE_CTRL_RST;
2165         }
2166
2167         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2168         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2169         IXGBE_WRITE_FLUSH(hw);
2170
2171         /* Poll for reset bit to self-clear meaning reset is complete */
2172         for (i = 0; i < 10; i++) {
2173                 udelay(1);
2174                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2175                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2176                         break;
2177         }
2178
2179         if (ctrl & IXGBE_CTRL_RST_MASK) {
2180                 status = IXGBE_ERR_RESET_FAILED;
2181                 hw_dbg(hw, "Reset polling failed to complete.\n");
2182         }
2183
2184         msleep(50);
2185
2186         /* Double resets are required for recovery from certain error
2187          * clear the multicast table.  Also reset num_rar_entries to 128,
2188          * since we modify this value when programming the SAN MAC address.
2189          */
2190         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2191                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2192                 goto mac_reset_top;
2193         }
2194
2195         /* Store the permanent mac address */
2196         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2197
2198         /* Store MAC address from RAR0, clear receive address registers, and
2199          * clear the multicast table.  Also reset num_rar_entries to 128,
2200          * since we modify this value when programming the SAN MAC address.
2201          */
2202         hw->mac.num_rar_entries = 128;
2203         hw->mac.ops.init_rx_addrs(hw);
2204
2205         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
2206                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2207                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2208                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2209         }
2210
2211         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2212                 ixgbe_setup_mux_ctl(hw);
2213
2214         return status;
2215 }
2216
2217 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2218  *      anti-spoofing
2219  *  @hw:  pointer to hardware structure
2220  *  @enable: enable or disable switch for Ethertype anti-spoofing
2221  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2222  **/
2223 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2224                                                    bool enable, int vf)
2225 {
2226         int vf_target_reg = vf >> 3;
2227         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2228         u32 pfvfspoof;
2229
2230         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2231         if (enable)
2232                 pfvfspoof |= (1 << vf_target_shift);
2233         else
2234                 pfvfspoof &= ~(1 << vf_target_shift);
2235
2236         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2237 }
2238
2239 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2240  *  @hw: pointer to hardware structure
2241  *  @enable: enable or disable source address pruning
2242  *  @pool: Rx pool to set source address pruning for
2243  **/
2244 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2245                                                   bool enable,
2246                                                   unsigned int pool)
2247 {
2248         u64 pfflp;
2249
2250         /* max rx pool is 63 */
2251         if (pool > 63)
2252                 return;
2253
2254         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2255         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2256
2257         if (enable)
2258                 pfflp |= (1ULL << pool);
2259         else
2260                 pfflp &= ~(1ULL << pool);
2261
2262         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
2263         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
2264 }
2265
2266 /**
2267  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2268  * @hw: pointer to hardware structure
2269  * @state: set mux if 1, clear if 0
2270  */
2271 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2272 {
2273         u32 esdp;
2274
2275         if (!hw->bus.lan_id)
2276                 return;
2277         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2278         if (state)
2279                 esdp |= IXGBE_ESDP_SDP1;
2280         else
2281                 esdp &= ~IXGBE_ESDP_SDP1;
2282         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2283         IXGBE_WRITE_FLUSH(hw);
2284 }
2285
2286 /**
2287  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2288  * @hw: pointer to hardware structure
2289  * @mask: Mask to specify which semaphore to acquire
2290  *
2291  * Acquires the SWFW semaphore and sets the I2C MUX
2292  */
2293 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2294 {
2295         s32 status;
2296
2297         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2298         if (status)
2299                 return status;
2300
2301         if (mask & IXGBE_GSSR_I2C_MASK)
2302                 ixgbe_set_mux(hw, 1);
2303
2304         return 0;
2305 }
2306
2307 /**
2308  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2309  * @hw: pointer to hardware structure
2310  * @mask: Mask to specify which semaphore to release
2311  *
2312  * Releases the SWFW semaphore and sets the I2C MUX
2313  */
2314 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2315 {
2316         if (mask & IXGBE_GSSR_I2C_MASK)
2317                 ixgbe_set_mux(hw, 0);
2318
2319         ixgbe_release_swfw_sync_X540(hw, mask);
2320 }
2321
2322 #define X550_COMMON_MAC \
2323         .init_hw                        = &ixgbe_init_hw_generic, \
2324         .start_hw                       = &ixgbe_start_hw_X540, \
2325         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
2326         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
2327         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
2328         .get_device_caps                = &ixgbe_get_device_caps_generic, \
2329         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
2330         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
2331         .read_analog_reg8               = NULL, \
2332         .write_analog_reg8              = NULL, \
2333         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
2334         .check_link                     = &ixgbe_check_mac_link_generic, \
2335         .led_on                         = &ixgbe_led_on_generic, \
2336         .led_off                        = &ixgbe_led_off_generic, \
2337         .blink_led_start                = &ixgbe_blink_led_start_X540, \
2338         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
2339         .set_rar                        = &ixgbe_set_rar_generic, \
2340         .clear_rar                      = &ixgbe_clear_rar_generic, \
2341         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
2342         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
2343         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
2344         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
2345         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
2346         .enable_mc                      = &ixgbe_enable_mc_generic, \
2347         .disable_mc                     = &ixgbe_disable_mc_generic, \
2348         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
2349         .set_vfta                       = &ixgbe_set_vfta_generic, \
2350         .fc_enable                      = &ixgbe_fc_enable_generic, \
2351         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
2352         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
2353         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
2354         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
2355         .set_source_address_pruning     = \
2356                                 &ixgbe_set_source_address_pruning_X550, \
2357         .set_ethertype_anti_spoofing    = \
2358                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
2359         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
2360         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
2361         .get_thermal_sensor_data        = NULL, \
2362         .init_thermal_sensor_thresh     = NULL, \
2363         .prot_autoc_read                = &prot_autoc_read_generic, \
2364         .prot_autoc_write               = &prot_autoc_write_generic, \
2365         .enable_rx                      = &ixgbe_enable_rx_generic, \
2366         .disable_rx                     = &ixgbe_disable_rx_x550, \
2367
2368 static struct ixgbe_mac_operations mac_ops_X550 = {
2369         X550_COMMON_MAC
2370         .reset_hw               = &ixgbe_reset_hw_X540,
2371         .get_media_type         = &ixgbe_get_media_type_X540,
2372         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2373         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2374         .setup_link             = &ixgbe_setup_mac_link_X540,
2375         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2376         .get_bus_info           = &ixgbe_get_bus_info_generic,
2377         .setup_sfp              = NULL,
2378         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
2379         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
2380 };
2381
2382 static struct ixgbe_mac_operations mac_ops_X550EM_x = {
2383         X550_COMMON_MAC
2384         .reset_hw               = &ixgbe_reset_hw_X550em,
2385         .get_media_type         = &ixgbe_get_media_type_X550em,
2386         .get_san_mac_addr       = NULL,
2387         .get_wwn_prefix         = NULL,
2388         .setup_link             = NULL, /* defined later */
2389         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2390         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2391         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2392         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
2393         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
2394 };
2395
2396 #define X550_COMMON_EEP \
2397         .read                   = &ixgbe_read_ee_hostif_X550, \
2398         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2399         .write                  = &ixgbe_write_ee_hostif_X550, \
2400         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
2401         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
2402         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
2403         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
2404
2405 static struct ixgbe_eeprom_operations eeprom_ops_X550 = {
2406         X550_COMMON_EEP
2407         .init_params            = &ixgbe_init_eeprom_params_X550,
2408 };
2409
2410 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
2411         X550_COMMON_EEP
2412         .init_params            = &ixgbe_init_eeprom_params_X540,
2413 };
2414
2415 #define X550_COMMON_PHY \
2416         .identify_sfp           = &ixgbe_identify_module_generic, \
2417         .reset                  = NULL, \
2418         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
2419         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
2420         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
2421         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
2422         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
2423         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
2424         .read_reg               = &ixgbe_read_phy_reg_generic, \
2425         .write_reg              = &ixgbe_write_phy_reg_generic, \
2426         .setup_link             = &ixgbe_setup_phy_link_generic, \
2427         .set_phy_power          = NULL, \
2428         .check_overtemp         = &ixgbe_tn_check_overtemp, \
2429         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
2430
2431 static struct ixgbe_phy_operations phy_ops_X550 = {
2432         X550_COMMON_PHY
2433         .init                   = NULL,
2434         .identify               = &ixgbe_identify_phy_generic,
2435 };
2436
2437 static struct ixgbe_phy_operations phy_ops_X550EM_x = {
2438         X550_COMMON_PHY
2439         .init                   = &ixgbe_init_phy_ops_X550em,
2440         .identify               = &ixgbe_identify_phy_x550em,
2441         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
2442         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
2443         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
2444         .write_i2c_combined_unlocked =
2445                                      &ixgbe_write_i2c_combined_generic_unlocked,
2446 };
2447
2448 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
2449         IXGBE_MVALS_INIT(X550)
2450 };
2451
2452 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
2453         IXGBE_MVALS_INIT(X550EM_x)
2454 };
2455
2456 struct ixgbe_info ixgbe_X550_info = {
2457         .mac                    = ixgbe_mac_X550,
2458         .get_invariants         = &ixgbe_get_invariants_X540,
2459         .mac_ops                = &mac_ops_X550,
2460         .eeprom_ops             = &eeprom_ops_X550,
2461         .phy_ops                = &phy_ops_X550,
2462         .mbx_ops                = &mbx_ops_generic,
2463         .mvals                  = ixgbe_mvals_X550,
2464 };
2465
2466 struct ixgbe_info ixgbe_X550EM_x_info = {
2467         .mac                    = ixgbe_mac_X550EM_x,
2468         .get_invariants         = &ixgbe_get_invariants_X550_x,
2469         .mac_ops                = &mac_ops_X550EM_x,
2470         .eeprom_ops             = &eeprom_ops_X550EM_x,
2471         .phy_ops                = &phy_ops_X550EM_x,
2472         .mbx_ops                = &mbx_ops_generic,
2473         .mvals                  = ixgbe_mvals_X550EM_x,
2474 };