2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
40 #include <linux/string.h>
41 #include <linux/bitops.h>
42 #include <linux/if_vlan.h>
47 struct mlxsw_reg_info {
52 #define MLXSW_REG(type) (&mlxsw_reg_##type)
53 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
54 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
56 /* SGCR - Switch General Configuration Register
57 * --------------------------------------------
58 * This register is used for configuration of the switch capabilities.
60 #define MLXSW_REG_SGCR_ID 0x2000
61 #define MLXSW_REG_SGCR_LEN 0x10
63 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
64 .id = MLXSW_REG_SGCR_ID,
65 .len = MLXSW_REG_SGCR_LEN,
69 * Link Local Broadcast (Default=0)
70 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
71 * packets and ignore the IGMP snooping entries.
74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
76 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
78 MLXSW_REG_ZERO(sgcr, payload);
79 mlxsw_reg_sgcr_llb_set(payload, !!llb);
82 /* SPAD - Switch Physical Address Register
83 * ---------------------------------------
84 * The SPAD register configures the switch physical MAC address.
86 #define MLXSW_REG_SPAD_ID 0x2002
87 #define MLXSW_REG_SPAD_LEN 0x10
89 static const struct mlxsw_reg_info mlxsw_reg_spad = {
90 .id = MLXSW_REG_SPAD_ID,
91 .len = MLXSW_REG_SPAD_LEN,
95 * Base MAC address for the switch partitions.
96 * Per switch partition MAC address is equal to:
100 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
102 /* SSPR - Switch System Port Record Register
103 * -----------------------------------------
104 * Configures the system port to local port mapping.
106 #define MLXSW_REG_SSPR_ID 0x2008
107 #define MLXSW_REG_SSPR_LEN 0x8
109 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
110 .id = MLXSW_REG_SSPR_ID,
111 .len = MLXSW_REG_SSPR_LEN,
115 * Master - if set, then the record describes the master system port.
116 * This is needed in case a local port is mapped into several system ports
117 * (for multipathing). That number will be reported as the source system
118 * port when packets are forwarded to the CPU. Only one master port is allowed
121 * Note: Must be set for Spectrum.
124 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
126 /* reg_sspr_local_port
131 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
134 * Virtual port within the physical port.
135 * Should be set to 0 when virtual ports are not enabled on the port.
139 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
141 /* reg_sspr_system_port
142 * Unique identifier within the stacking domain that represents all the ports
143 * that are available in the system (external ports).
145 * Currently, only single-ASIC configurations are supported, so we default to
146 * 1:1 mapping between system ports and local ports.
149 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
151 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
153 MLXSW_REG_ZERO(sspr, payload);
154 mlxsw_reg_sspr_m_set(payload, 1);
155 mlxsw_reg_sspr_local_port_set(payload, local_port);
156 mlxsw_reg_sspr_sub_port_set(payload, 0);
157 mlxsw_reg_sspr_system_port_set(payload, local_port);
160 /* SFDAT - Switch Filtering Database Aging Time
161 * --------------------------------------------
162 * Controls the Switch aging time. Aging time is able to be set per Switch
165 #define MLXSW_REG_SFDAT_ID 0x2009
166 #define MLXSW_REG_SFDAT_LEN 0x8
168 static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
169 .id = MLXSW_REG_SFDAT_ID,
170 .len = MLXSW_REG_SFDAT_LEN,
174 * Switch partition ID.
177 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
179 /* reg_sfdat_age_time
180 * Aging time in seconds
182 * Max - 1,000,000 seconds
183 * Default is 300 seconds.
186 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
188 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
190 MLXSW_REG_ZERO(sfdat, payload);
191 mlxsw_reg_sfdat_swid_set(payload, 0);
192 mlxsw_reg_sfdat_age_time_set(payload, age_time);
195 /* SFD - Switch Filtering Database
196 * -------------------------------
197 * The following register defines the access to the filtering database.
198 * The register supports querying, adding, removing and modifying the database.
199 * The access is optimized for bulk updates in which case more than one
200 * FDB record is present in the same command.
202 #define MLXSW_REG_SFD_ID 0x200A
203 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
204 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
205 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
206 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
207 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
209 static const struct mlxsw_reg_info mlxsw_reg_sfd = {
210 .id = MLXSW_REG_SFD_ID,
211 .len = MLXSW_REG_SFD_LEN,
215 * Switch partition ID for queries. Reserved on Write.
218 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
220 enum mlxsw_reg_sfd_op {
221 /* Dump entire FDB a (process according to record_locator) */
222 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
223 /* Query records by {MAC, VID/FID} value */
224 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
225 /* Query and clear activity. Query records by {MAC, VID/FID} value */
226 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
227 /* Test. Response indicates if each of the records could be
230 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
231 /* Add/modify. Aged-out records cannot be added. This command removes
232 * the learning notification of the {MAC, VID/FID}. Response includes
233 * the entries that were added to the FDB.
235 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
236 /* Remove record by {MAC, VID/FID}. This command also removes
237 * the learning notification and aged-out notifications
238 * of the {MAC, VID/FID}. The response provides current (pre-removal)
239 * entries as non-aged-out.
241 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
242 /* Remove learned notification by {MAC, VID/FID}. The response provides
243 * the removed learning notification.
245 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
252 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
254 /* reg_sfd_record_locator
255 * Used for querying the FDB. Use record_locator=0 to initiate the
256 * query. When a record is returned, a new record_locator is
257 * returned to be used in the subsequent query.
258 * Reserved for database update.
261 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
264 * Request: Number of records to read/add/modify/remove
265 * Response: Number of records read/added/replaced/removed
266 * See above description for more details.
270 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
272 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
275 MLXSW_REG_ZERO(sfd, payload);
276 mlxsw_reg_sfd_op_set(payload, op);
277 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
281 * Switch partition ID.
284 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
285 MLXSW_REG_SFD_REC_LEN, 0x00, false);
287 enum mlxsw_reg_sfd_rec_type {
288 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
295 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
296 MLXSW_REG_SFD_REC_LEN, 0x00, false);
298 enum mlxsw_reg_sfd_rec_policy {
299 /* Replacement disabled, aging disabled. */
300 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
301 /* (mlag remote): Replacement enabled, aging disabled,
302 * learning notification enabled on this port.
304 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
305 /* (ingress device): Replacement enabled, aging enabled. */
306 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
309 /* reg_sfd_rec_policy
313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
314 MLXSW_REG_SFD_REC_LEN, 0x00, false);
317 * Activity. Set for new static entries. Set for static entries if a frame SMAC
318 * lookup hits on the entry.
319 * To clear the a bit, use "query and clear activity" op.
322 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
323 MLXSW_REG_SFD_REC_LEN, 0x00, false);
329 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
330 MLXSW_REG_SFD_REC_LEN, 0x02);
332 enum mlxsw_reg_sfd_rec_action {
334 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
335 /* forward and trap, trap_id is FDB_TRAP */
336 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
337 /* trap and do not forward, trap_id is FDB_TRAP */
338 MLXSW_REG_SFD_REC_ACTION_TRAP = 3,
339 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
342 /* reg_sfd_rec_action
343 * Action to apply on the packet.
344 * Note: Dynamic entries can only be configured with NOP action.
347 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
348 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
350 /* reg_sfd_uc_sub_port
351 * VEPA channel on local port.
352 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
353 * VEPA is not enabled.
356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
357 MLXSW_REG_SFD_REC_LEN, 0x08, false);
359 /* reg_sfd_uc_fid_vid
360 * Filtering ID or VLAN ID
361 * For SwitchX and SwitchX-2:
362 * - Dynamic entries (policy 2,3) use FID
363 * - Static entries (policy 0) use VID
364 * - When independent learning is configured, VID=FID
365 * For Spectrum: use FID for both Dynamic and Static entries.
366 * VID should not be used.
369 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
370 MLXSW_REG_SFD_REC_LEN, 0x08, false);
372 /* reg_sfd_uc_system_port
373 * Unique port identifier for the final destination of the packet.
376 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
377 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
379 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
380 enum mlxsw_reg_sfd_rec_policy policy,
381 const char *mac, u16 vid,
382 enum mlxsw_reg_sfd_rec_action action,
385 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
387 if (rec_index >= num_rec)
388 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
389 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
390 mlxsw_reg_sfd_rec_type_set(payload, rec_index,
391 MLXSW_REG_SFD_REC_TYPE_UNICAST);
392 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
393 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
394 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
395 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, vid);
396 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
397 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
401 mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
402 char *mac, u16 *p_vid,
405 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
406 *p_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
407 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
410 /* SFN - Switch FDB Notification Register
411 * -------------------------------------------
412 * The switch provides notifications on newly learned FDB entries and
413 * aged out entries. The notifications can be polled by software.
415 #define MLXSW_REG_SFN_ID 0x200B
416 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
417 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
418 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
419 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
420 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
422 static const struct mlxsw_reg_info mlxsw_reg_sfn = {
423 .id = MLXSW_REG_SFN_ID,
424 .len = MLXSW_REG_SFN_LEN,
428 * Switch partition ID.
431 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
434 * Request: Number of learned notifications and aged-out notification
436 * Response: Number of notification records returned (must be smaller
437 * than or equal to the value requested)
441 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
443 static inline void mlxsw_reg_sfn_pack(char *payload)
445 MLXSW_REG_ZERO(sfn, payload);
446 mlxsw_reg_sfn_swid_set(payload, 0);
447 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
451 * Switch partition ID.
454 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
455 MLXSW_REG_SFN_REC_LEN, 0x00, false);
457 enum mlxsw_reg_sfn_rec_type {
458 /* MAC addresses learned on a regular port. */
459 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
460 /* Aged-out MAC address on a regular port */
461 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
465 * Notification record type.
468 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
469 MLXSW_REG_SFN_REC_LEN, 0x00, false);
475 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
476 MLXSW_REG_SFN_REC_LEN, 0x02);
478 /* reg_sfd_mac_sub_port
479 * VEPA channel on the local port.
480 * 0 if multichannel VEPA is not enabled.
483 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
484 MLXSW_REG_SFN_REC_LEN, 0x08, false);
487 * Filtering identifier.
490 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
491 MLXSW_REG_SFN_REC_LEN, 0x08, false);
493 /* reg_sfd_mac_system_port
494 * Unique port identifier for the final destination of the packet.
497 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
498 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
500 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
501 char *mac, u16 *p_vid,
504 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
505 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
506 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
509 /* SPMS - Switch Port MSTP/RSTP State Register
510 * -------------------------------------------
511 * Configures the spanning tree state of a physical port.
513 #define MLXSW_REG_SPMS_ID 0x200D
514 #define MLXSW_REG_SPMS_LEN 0x404
516 static const struct mlxsw_reg_info mlxsw_reg_spms = {
517 .id = MLXSW_REG_SPMS_ID,
518 .len = MLXSW_REG_SPMS_LEN,
521 /* reg_spms_local_port
525 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
527 enum mlxsw_reg_spms_state {
528 MLXSW_REG_SPMS_STATE_NO_CHANGE,
529 MLXSW_REG_SPMS_STATE_DISCARDING,
530 MLXSW_REG_SPMS_STATE_LEARNING,
531 MLXSW_REG_SPMS_STATE_FORWARDING,
535 * Spanning tree state of each VLAN ID (VID) of the local port.
536 * 0 - Do not change spanning tree state (used only when writing).
537 * 1 - Discarding. No learning or forwarding to/from this port (default).
538 * 2 - Learning. Port is learning, but not forwarding.
539 * 3 - Forwarding. Port is learning and forwarding.
542 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
544 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
546 MLXSW_REG_ZERO(spms, payload);
547 mlxsw_reg_spms_local_port_set(payload, local_port);
550 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
551 enum mlxsw_reg_spms_state state)
553 mlxsw_reg_spms_state_set(payload, vid, state);
556 /* SPVID - Switch Port VID
557 * -----------------------
558 * The switch port VID configures the default VID for a port.
560 #define MLXSW_REG_SPVID_ID 0x200E
561 #define MLXSW_REG_SPVID_LEN 0x08
563 static const struct mlxsw_reg_info mlxsw_reg_spvid = {
564 .id = MLXSW_REG_SPVID_ID,
565 .len = MLXSW_REG_SPVID_LEN,
568 /* reg_spvid_local_port
572 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
574 /* reg_spvid_sub_port
575 * Virtual port within the physical port.
576 * Should be set to 0 when virtual ports are not enabled on the port.
579 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
585 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
587 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
589 MLXSW_REG_ZERO(spvid, payload);
590 mlxsw_reg_spvid_local_port_set(payload, local_port);
591 mlxsw_reg_spvid_pvid_set(payload, pvid);
594 /* SPVM - Switch Port VLAN Membership
595 * ----------------------------------
596 * The Switch Port VLAN Membership register configures the VLAN membership
597 * of a port in a VLAN denoted by VID. VLAN membership is managed per
598 * virtual port. The register can be used to add and remove VID(s) from a port.
600 #define MLXSW_REG_SPVM_ID 0x200F
601 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
602 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
603 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256
604 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
605 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
607 static const struct mlxsw_reg_info mlxsw_reg_spvm = {
608 .id = MLXSW_REG_SPVM_ID,
609 .len = MLXSW_REG_SPVM_LEN,
613 * Priority tagged. If this bit is set, packets forwarded to the port with
614 * untagged VLAN membership (u bit is set) will be tagged with priority tag
618 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
621 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
622 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
625 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
627 /* reg_spvm_local_port
631 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
634 * Virtual port within the physical port.
635 * Should be set to 0 when virtual ports are not enabled on the port.
638 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
641 * Number of records to update. Each record contains: i, e, u, vid.
644 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
647 * Ingress membership in VLAN ID.
650 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
651 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
652 MLXSW_REG_SPVM_REC_LEN, 0, false);
655 * Egress membership in VLAN ID.
658 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
659 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
660 MLXSW_REG_SPVM_REC_LEN, 0, false);
663 * Untagged - port is an untagged member - egress transmission uses untagged
667 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
668 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
669 MLXSW_REG_SPVM_REC_LEN, 0, false);
672 * Egress membership in VLAN ID.
675 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
676 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
677 MLXSW_REG_SPVM_REC_LEN, 0, false);
679 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
680 u16 vid_begin, u16 vid_end,
681 bool is_member, bool untagged)
683 int size = vid_end - vid_begin + 1;
686 MLXSW_REG_ZERO(spvm, payload);
687 mlxsw_reg_spvm_local_port_set(payload, local_port);
688 mlxsw_reg_spvm_num_rec_set(payload, size);
690 for (i = 0; i < size; i++) {
691 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
692 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
693 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
694 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
698 /* SFGC - Switch Flooding Group Configuration
699 * ------------------------------------------
700 * The following register controls the association of flooding tables and MIDs
701 * to packet types used for flooding.
703 #define MLXSW_REG_SFGC_ID 0x2011
704 #define MLXSW_REG_SFGC_LEN 0x10
706 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
707 .id = MLXSW_REG_SFGC_ID,
708 .len = MLXSW_REG_SFGC_LEN,
711 enum mlxsw_reg_sfgc_type {
712 MLXSW_REG_SFGC_TYPE_BROADCAST,
713 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
714 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
715 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
716 MLXSW_REG_SFGC_TYPE_RESERVED,
717 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
718 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
719 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
720 MLXSW_REG_SFGC_TYPE_MAX,
724 * The traffic type to reach the flooding table.
727 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
729 enum mlxsw_reg_sfgc_bridge_type {
730 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
731 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
734 /* reg_sfgc_bridge_type
737 * Note: SwitchX-2 only supports 802.1Q mode.
739 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
741 enum mlxsw_flood_table_type {
742 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
743 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
744 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
745 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
746 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
749 /* reg_sfgc_table_type
750 * See mlxsw_flood_table_type
753 * Note: FID offset and FID types are not supported in SwitchX-2.
755 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
757 /* reg_sfgc_flood_table
758 * Flooding table index to associate with the specific type on the specific
762 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
765 * The multicast ID for the swid. Not supported for Spectrum
768 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
770 /* reg_sfgc_counter_set_type
771 * Counter Set Type for flow counters.
774 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
776 /* reg_sfgc_counter_index
777 * Counter Index for flow counters.
780 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
783 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
784 enum mlxsw_reg_sfgc_bridge_type bridge_type,
785 enum mlxsw_flood_table_type table_type,
786 unsigned int flood_table)
788 MLXSW_REG_ZERO(sfgc, payload);
789 mlxsw_reg_sfgc_type_set(payload, type);
790 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
791 mlxsw_reg_sfgc_table_type_set(payload, table_type);
792 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
793 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
796 /* SFTR - Switch Flooding Table Register
797 * -------------------------------------
798 * The switch flooding table is used for flooding packet replication. The table
799 * defines a bit mask of ports for packet replication.
801 #define MLXSW_REG_SFTR_ID 0x2012
802 #define MLXSW_REG_SFTR_LEN 0x420
804 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
805 .id = MLXSW_REG_SFTR_ID,
806 .len = MLXSW_REG_SFTR_LEN,
810 * Switch partition ID with which to associate the port.
813 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
815 /* reg_sftr_flood_table
816 * Flooding table index to associate with the specific type on the specific
820 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
823 * Index. Used as an index into the Flooding Table in case the table is
824 * configured to use VID / FID or FID Offset.
827 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
829 /* reg_sftr_table_type
830 * See mlxsw_flood_table_type
833 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
836 * Range of entries to update
839 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
842 * Local port membership (1 bit per port).
845 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
847 /* reg_sftr_cpu_port_mask
848 * CPU port mask (1 bit per port).
851 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
853 static inline void mlxsw_reg_sftr_pack(char *payload,
854 unsigned int flood_table,
856 enum mlxsw_flood_table_type table_type,
857 unsigned int range, u8 port, bool set)
859 MLXSW_REG_ZERO(sftr, payload);
860 mlxsw_reg_sftr_swid_set(payload, 0);
861 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
862 mlxsw_reg_sftr_index_set(payload, index);
863 mlxsw_reg_sftr_table_type_set(payload, table_type);
864 mlxsw_reg_sftr_range_set(payload, range);
865 mlxsw_reg_sftr_port_set(payload, port, set);
866 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
869 /* SPMLR - Switch Port MAC Learning Register
870 * -----------------------------------------
871 * Controls the Switch MAC learning policy per port.
873 #define MLXSW_REG_SPMLR_ID 0x2018
874 #define MLXSW_REG_SPMLR_LEN 0x8
876 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
877 .id = MLXSW_REG_SPMLR_ID,
878 .len = MLXSW_REG_SPMLR_LEN,
881 /* reg_spmlr_local_port
885 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
887 /* reg_spmlr_sub_port
888 * Virtual port within the physical port.
889 * Should be set to 0 when virtual ports are not enabled on the port.
892 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
894 enum mlxsw_reg_spmlr_learn_mode {
895 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
896 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
897 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
900 /* reg_spmlr_learn_mode
901 * Learning mode on the port.
902 * 0 - Learning disabled.
903 * 2 - Learning enabled.
906 * In security mode the switch does not learn MACs on the port, but uses the
907 * SMAC to see if it exists on another ingress port. If so, the packet is
908 * classified as a bad packet and is discarded unless the software registers
909 * to receive port security error packets usign HPKT.
911 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
913 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
914 enum mlxsw_reg_spmlr_learn_mode mode)
916 MLXSW_REG_ZERO(spmlr, payload);
917 mlxsw_reg_spmlr_local_port_set(payload, local_port);
918 mlxsw_reg_spmlr_sub_port_set(payload, 0);
919 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
922 /* SVFA - Switch VID to FID Allocation Register
923 * --------------------------------------------
924 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
927 #define MLXSW_REG_SVFA_ID 0x201C
928 #define MLXSW_REG_SVFA_LEN 0x10
930 static const struct mlxsw_reg_info mlxsw_reg_svfa = {
931 .id = MLXSW_REG_SVFA_ID,
932 .len = MLXSW_REG_SVFA_LEN,
936 * Switch partition ID.
939 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
941 /* reg_svfa_local_port
945 * Note: Reserved for 802.1Q FIDs.
947 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
949 enum mlxsw_reg_svfa_mt {
950 MLXSW_REG_SVFA_MT_VID_TO_FID,
951 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
954 /* reg_svfa_mapping_table
957 * 1 - {Port, VID} to FID
960 * Note: Reserved for SwitchX-2.
962 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
969 * Note: Reserved for SwitchX-2.
971 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
977 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
983 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
985 /* reg_svfa_counter_set_type
986 * Counter set type for flow counters.
989 * Note: Reserved for SwitchX-2.
991 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
993 /* reg_svfa_counter_index
994 * Counter index for flow counters.
997 * Note: Reserved for SwitchX-2.
999 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1001 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1002 enum mlxsw_reg_svfa_mt mt, bool valid,
1005 MLXSW_REG_ZERO(svfa, payload);
1006 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1007 mlxsw_reg_svfa_swid_set(payload, 0);
1008 mlxsw_reg_svfa_local_port_set(payload, local_port);
1009 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1010 mlxsw_reg_svfa_v_set(payload, valid);
1011 mlxsw_reg_svfa_fid_set(payload, fid);
1012 mlxsw_reg_svfa_vid_set(payload, vid);
1015 /* SVPE - Switch Virtual-Port Enabling Register
1016 * --------------------------------------------
1017 * Enables port virtualization.
1019 #define MLXSW_REG_SVPE_ID 0x201E
1020 #define MLXSW_REG_SVPE_LEN 0x4
1022 static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1023 .id = MLXSW_REG_SVPE_ID,
1024 .len = MLXSW_REG_SVPE_LEN,
1027 /* reg_svpe_local_port
1031 * Note: CPU port is not supported (uses VLAN mode only).
1033 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1036 * Virtual port enable.
1037 * 0 - Disable, VLAN mode (VID to FID).
1038 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1041 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1043 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1046 MLXSW_REG_ZERO(svpe, payload);
1047 mlxsw_reg_svpe_local_port_set(payload, local_port);
1048 mlxsw_reg_svpe_vp_en_set(payload, enable);
1051 /* SFMR - Switch FID Management Register
1052 * -------------------------------------
1053 * Creates and configures FIDs.
1055 #define MLXSW_REG_SFMR_ID 0x201F
1056 #define MLXSW_REG_SFMR_LEN 0x18
1058 static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1059 .id = MLXSW_REG_SFMR_ID,
1060 .len = MLXSW_REG_SFMR_LEN,
1063 enum mlxsw_reg_sfmr_op {
1064 MLXSW_REG_SFMR_OP_CREATE_FID,
1065 MLXSW_REG_SFMR_OP_DESTROY_FID,
1070 * 0 - Create or edit FID.
1074 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1080 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1082 /* reg_sfmr_fid_offset
1084 * Used to point into the flooding table selected by SFGC register if
1085 * the table is of type FID-Offset. Otherwise, this field is reserved.
1088 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1091 * Valid Tunnel Flood Pointer.
1092 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1095 * Note: Reserved for 802.1Q FIDs.
1097 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1099 /* reg_sfmr_nve_tunnel_flood_ptr
1100 * Underlay Flooding and BC Pointer.
1101 * Used as a pointer to the first entry of the group based link lists of
1102 * flooding or BC entries (for NVE tunnels).
1105 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1109 * If not set, then vni is reserved.
1112 * Note: Reserved for 802.1Q FIDs.
1114 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1117 * Virtual Network Identifier.
1120 * Note: A given VNI can only be assigned to one FID.
1122 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1124 static inline void mlxsw_reg_sfmr_pack(char *payload,
1125 enum mlxsw_reg_sfmr_op op, u16 fid,
1128 MLXSW_REG_ZERO(sfmr, payload);
1129 mlxsw_reg_sfmr_op_set(payload, op);
1130 mlxsw_reg_sfmr_fid_set(payload, fid);
1131 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1132 mlxsw_reg_sfmr_vtfp_set(payload, false);
1133 mlxsw_reg_sfmr_vv_set(payload, false);
1136 /* SPVMLR - Switch Port VLAN MAC Learning Register
1137 * -----------------------------------------------
1138 * Controls the switch MAC learning policy per {Port, VID}.
1140 #define MLXSW_REG_SPVMLR_ID 0x2020
1141 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1142 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1143 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1144 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1145 MLXSW_REG_SPVMLR_REC_LEN * \
1146 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1148 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1149 .id = MLXSW_REG_SPVMLR_ID,
1150 .len = MLXSW_REG_SPVMLR_LEN,
1153 /* reg_spvmlr_local_port
1154 * Local ingress port.
1157 * Note: CPU port is not supported.
1159 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1161 /* reg_spvmlr_num_rec
1162 * Number of records to update.
1165 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1167 /* reg_spvmlr_rec_learn_enable
1168 * 0 - Disable learning for {Port, VID}.
1169 * 1 - Enable learning for {Port, VID}.
1172 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1173 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1175 /* reg_spvmlr_rec_vid
1176 * VLAN ID to be added/removed from port or for querying.
1179 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1180 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1182 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1183 u16 vid_begin, u16 vid_end,
1186 int num_rec = vid_end - vid_begin + 1;
1189 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1191 MLXSW_REG_ZERO(spvmlr, payload);
1192 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1193 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1195 for (i = 0; i < num_rec; i++) {
1196 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1197 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1201 /* PMLP - Ports Module to Local Port Register
1202 * ------------------------------------------
1203 * Configures the assignment of modules to local ports.
1205 #define MLXSW_REG_PMLP_ID 0x5002
1206 #define MLXSW_REG_PMLP_LEN 0x40
1208 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1209 .id = MLXSW_REG_PMLP_ID,
1210 .len = MLXSW_REG_PMLP_LEN,
1214 * 0 - Tx value is used for both Tx and Rx.
1215 * 1 - Rx value is taken from a separte field.
1218 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
1220 /* reg_pmlp_local_port
1221 * Local port number.
1224 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
1227 * 0 - Unmap local port.
1228 * 1 - Lane 0 is used.
1229 * 2 - Lanes 0 and 1 are used.
1230 * 4 - Lanes 0, 1, 2 and 3 are used.
1233 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
1239 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false);
1242 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
1245 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false);
1248 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
1252 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false);
1254 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
1256 MLXSW_REG_ZERO(pmlp, payload);
1257 mlxsw_reg_pmlp_local_port_set(payload, local_port);
1260 /* PMTU - Port MTU Register
1261 * ------------------------
1262 * Configures and reports the port MTU.
1264 #define MLXSW_REG_PMTU_ID 0x5003
1265 #define MLXSW_REG_PMTU_LEN 0x10
1267 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
1268 .id = MLXSW_REG_PMTU_ID,
1269 .len = MLXSW_REG_PMTU_LEN,
1272 /* reg_pmtu_local_port
1273 * Local port number.
1276 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
1280 * When port type (e.g. Ethernet) is configured, the relevant MTU is
1281 * reported, otherwise the minimum between the max_mtu of the different
1282 * types is reported.
1285 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
1287 /* reg_pmtu_admin_mtu
1288 * MTU value to set port to. Must be smaller or equal to max_mtu.
1289 * Note: If port type is Infiniband, then port must be disabled, when its
1293 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
1295 /* reg_pmtu_oper_mtu
1296 * The actual MTU configured on the port. Packets exceeding this size
1298 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
1299 * oper_mtu might be smaller than admin_mtu.
1302 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
1304 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
1307 MLXSW_REG_ZERO(pmtu, payload);
1308 mlxsw_reg_pmtu_local_port_set(payload, local_port);
1309 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
1310 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
1311 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
1314 /* PTYS - Port Type and Speed Register
1315 * -----------------------------------
1316 * Configures and reports the port speed type.
1318 * Note: When set while the link is up, the changes will not take effect
1319 * until the port transitions from down to up state.
1321 #define MLXSW_REG_PTYS_ID 0x5004
1322 #define MLXSW_REG_PTYS_LEN 0x40
1324 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
1325 .id = MLXSW_REG_PTYS_ID,
1326 .len = MLXSW_REG_PTYS_LEN,
1329 /* reg_ptys_local_port
1330 * Local port number.
1333 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
1335 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
1337 /* reg_ptys_proto_mask
1338 * Protocol mask. Indicates which protocol is used.
1340 * 1 - Fibre Channel.
1344 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
1346 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
1347 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
1348 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
1349 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
1350 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
1351 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
1352 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
1353 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
1354 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
1355 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
1356 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
1357 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
1358 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
1359 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
1360 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
1361 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
1362 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
1363 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
1364 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
1365 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
1366 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
1367 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
1368 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
1369 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
1370 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
1371 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
1372 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
1374 /* reg_ptys_eth_proto_cap
1375 * Ethernet port supported speeds and protocols.
1378 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
1380 /* reg_ptys_eth_proto_admin
1381 * Speed and protocol to set port to.
1384 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
1386 /* reg_ptys_eth_proto_oper
1387 * The current speed and protocol configured for the port.
1390 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
1392 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
1395 MLXSW_REG_ZERO(ptys, payload);
1396 mlxsw_reg_ptys_local_port_set(payload, local_port);
1397 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
1398 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
1401 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
1402 u32 *p_eth_proto_adm,
1403 u32 *p_eth_proto_oper)
1405 if (p_eth_proto_cap)
1406 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
1407 if (p_eth_proto_adm)
1408 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
1409 if (p_eth_proto_oper)
1410 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
1413 /* PPAD - Port Physical Address Register
1414 * -------------------------------------
1415 * The PPAD register configures the per port physical MAC address.
1417 #define MLXSW_REG_PPAD_ID 0x5005
1418 #define MLXSW_REG_PPAD_LEN 0x10
1420 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
1421 .id = MLXSW_REG_PPAD_ID,
1422 .len = MLXSW_REG_PPAD_LEN,
1425 /* reg_ppad_single_base_mac
1426 * 0: base_mac, local port should be 0 and mac[7:0] is
1427 * reserved. HW will set incremental
1428 * 1: single_mac - mac of the local_port
1431 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
1433 /* reg_ppad_local_port
1434 * port number, if single_base_mac = 0 then local_port is reserved
1437 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
1440 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
1441 * If single_base_mac = 1 - the per port MAC address
1444 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
1446 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
1449 MLXSW_REG_ZERO(ppad, payload);
1450 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
1451 mlxsw_reg_ppad_local_port_set(payload, local_port);
1454 /* PAOS - Ports Administrative and Operational Status Register
1455 * -----------------------------------------------------------
1456 * Configures and retrieves per port administrative and operational status.
1458 #define MLXSW_REG_PAOS_ID 0x5006
1459 #define MLXSW_REG_PAOS_LEN 0x10
1461 static const struct mlxsw_reg_info mlxsw_reg_paos = {
1462 .id = MLXSW_REG_PAOS_ID,
1463 .len = MLXSW_REG_PAOS_LEN,
1467 * Switch partition ID with which to associate the port.
1468 * Note: while external ports uses unique local port numbers (and thus swid is
1469 * redundant), router ports use the same local port number where swid is the
1470 * only indication for the relevant port.
1473 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
1475 /* reg_paos_local_port
1476 * Local port number.
1479 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
1481 /* reg_paos_admin_status
1482 * Port administrative state (the desired state of the port):
1485 * 3 - Up once. This means that in case of link failure, the port won't go
1486 * into polling mode, but will wait to be re-enabled by software.
1487 * 4 - Disabled by system. Can only be set by hardware.
1490 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
1492 /* reg_paos_oper_status
1493 * Port operational state (the current state):
1496 * 3 - Down by port failure. This means that the device will not let the
1497 * port up again until explicitly specified by software.
1500 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
1503 * Admin state update enabled.
1506 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
1509 * Event update enable. If this bit is set, event generation will be
1510 * updated based on the e field.
1513 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
1516 * Event generation on operational state change:
1517 * 0 - Do not generate event.
1518 * 1 - Generate Event.
1519 * 2 - Generate Single Event.
1522 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
1524 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
1525 enum mlxsw_port_admin_status status)
1527 MLXSW_REG_ZERO(paos, payload);
1528 mlxsw_reg_paos_swid_set(payload, 0);
1529 mlxsw_reg_paos_local_port_set(payload, local_port);
1530 mlxsw_reg_paos_admin_status_set(payload, status);
1531 mlxsw_reg_paos_oper_status_set(payload, 0);
1532 mlxsw_reg_paos_ase_set(payload, 1);
1533 mlxsw_reg_paos_ee_set(payload, 1);
1534 mlxsw_reg_paos_e_set(payload, 1);
1537 /* PPCNT - Ports Performance Counters Register
1538 * -------------------------------------------
1539 * The PPCNT register retrieves per port performance counters.
1541 #define MLXSW_REG_PPCNT_ID 0x5008
1542 #define MLXSW_REG_PPCNT_LEN 0x100
1544 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
1545 .id = MLXSW_REG_PPCNT_ID,
1546 .len = MLXSW_REG_PPCNT_LEN,
1550 * For HCA: must be always 0.
1551 * Switch partition ID to associate port with.
1552 * Switch partitions are numbered from 0 to 7 inclusively.
1553 * Switch partition 254 indicates stacking ports.
1554 * Switch partition 255 indicates all switch partitions.
1555 * Only valid on Set() operation with local_port=255.
1558 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
1560 /* reg_ppcnt_local_port
1561 * Local port number.
1562 * 255 indicates all ports on the device, and is only allowed
1563 * for Set() operation.
1566 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
1569 * Port number access type:
1570 * 0 - Local port number
1571 * 1 - IB port number
1574 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
1577 * Performance counter group.
1578 * Group 63 indicates all groups. Only valid on Set() operation with
1580 * 0x0: IEEE 802.3 Counters
1581 * 0x1: RFC 2863 Counters
1582 * 0x2: RFC 2819 Counters
1583 * 0x3: RFC 3635 Counters
1584 * 0x5: Ethernet Extended Counters
1585 * 0x8: Link Level Retransmission Counters
1586 * 0x10: Per Priority Counters
1587 * 0x11: Per Traffic Class Counters
1588 * 0x12: Physical Layer Counters
1591 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
1594 * Clear counters. Setting the clr bit will reset the counter value
1595 * for all counters in the counter group. This bit can be set
1596 * for both Set() and Get() operation.
1599 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
1601 /* reg_ppcnt_prio_tc
1602 * Priority for counter set that support per priority, valid values: 0-7.
1603 * Traffic class for counter set that support per traffic class,
1604 * valid values: 0- cap_max_tclass-1 .
1605 * For HCA: cap_max_tclass is always 8.
1606 * Otherwise must be 0.
1609 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
1611 /* reg_ppcnt_a_frames_transmitted_ok
1614 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
1615 0x08 + 0x00, 0, 64);
1617 /* reg_ppcnt_a_frames_received_ok
1620 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
1621 0x08 + 0x08, 0, 64);
1623 /* reg_ppcnt_a_frame_check_sequence_errors
1626 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
1627 0x08 + 0x10, 0, 64);
1629 /* reg_ppcnt_a_alignment_errors
1632 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
1633 0x08 + 0x18, 0, 64);
1635 /* reg_ppcnt_a_octets_transmitted_ok
1638 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
1639 0x08 + 0x20, 0, 64);
1641 /* reg_ppcnt_a_octets_received_ok
1644 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
1645 0x08 + 0x28, 0, 64);
1647 /* reg_ppcnt_a_multicast_frames_xmitted_ok
1650 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
1651 0x08 + 0x30, 0, 64);
1653 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
1656 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
1657 0x08 + 0x38, 0, 64);
1659 /* reg_ppcnt_a_multicast_frames_received_ok
1662 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
1663 0x08 + 0x40, 0, 64);
1665 /* reg_ppcnt_a_broadcast_frames_received_ok
1668 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
1669 0x08 + 0x48, 0, 64);
1671 /* reg_ppcnt_a_in_range_length_errors
1674 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
1675 0x08 + 0x50, 0, 64);
1677 /* reg_ppcnt_a_out_of_range_length_field
1680 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
1681 0x08 + 0x58, 0, 64);
1683 /* reg_ppcnt_a_frame_too_long_errors
1686 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
1687 0x08 + 0x60, 0, 64);
1689 /* reg_ppcnt_a_symbol_error_during_carrier
1692 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
1693 0x08 + 0x68, 0, 64);
1695 /* reg_ppcnt_a_mac_control_frames_transmitted
1698 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
1699 0x08 + 0x70, 0, 64);
1701 /* reg_ppcnt_a_mac_control_frames_received
1704 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
1705 0x08 + 0x78, 0, 64);
1707 /* reg_ppcnt_a_unsupported_opcodes_received
1710 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
1711 0x08 + 0x80, 0, 64);
1713 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
1716 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
1717 0x08 + 0x88, 0, 64);
1719 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
1722 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
1723 0x08 + 0x90, 0, 64);
1725 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
1727 MLXSW_REG_ZERO(ppcnt, payload);
1728 mlxsw_reg_ppcnt_swid_set(payload, 0);
1729 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
1730 mlxsw_reg_ppcnt_pnat_set(payload, 0);
1731 mlxsw_reg_ppcnt_grp_set(payload, 0);
1732 mlxsw_reg_ppcnt_clr_set(payload, 0);
1733 mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
1736 /* PBMC - Port Buffer Management Control Register
1737 * ----------------------------------------------
1738 * The PBMC register configures and retrieves the port packet buffer
1739 * allocation for different Prios, and the Pause threshold management.
1741 #define MLXSW_REG_PBMC_ID 0x500C
1742 #define MLXSW_REG_PBMC_LEN 0x68
1744 static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
1745 .id = MLXSW_REG_PBMC_ID,
1746 .len = MLXSW_REG_PBMC_LEN,
1749 /* reg_pbmc_local_port
1750 * Local port number.
1753 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
1755 /* reg_pbmc_xoff_timer_value
1756 * When device generates a pause frame, it uses this value as the pause
1757 * timer (time for the peer port to pause in quota-512 bit time).
1760 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
1762 /* reg_pbmc_xoff_refresh
1763 * The time before a new pause frame should be sent to refresh the pause RW
1764 * state. Using the same units as xoff_timer_value above (in quota-512 bit
1768 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
1770 /* reg_pbmc_buf_lossy
1771 * The field indicates if the buffer is lossy.
1776 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
1778 /* reg_pbmc_buf_epsb
1779 * Eligible for Port Shared buffer.
1780 * If epsb is set, packets assigned to buffer are allowed to insert the port
1782 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
1785 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
1787 /* reg_pbmc_buf_size
1788 * The part of the packet buffer array is allocated for the specific buffer.
1789 * Units are represented in cells.
1792 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
1794 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
1795 u16 xoff_timer_value, u16 xoff_refresh)
1797 MLXSW_REG_ZERO(pbmc, payload);
1798 mlxsw_reg_pbmc_local_port_set(payload, local_port);
1799 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
1800 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
1803 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
1807 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
1808 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
1809 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
1812 /* PSPA - Port Switch Partition Allocation
1813 * ---------------------------------------
1814 * Controls the association of a port with a switch partition and enables
1815 * configuring ports as stacking ports.
1817 #define MLXSW_REG_PSPA_ID 0x500D
1818 #define MLXSW_REG_PSPA_LEN 0x8
1820 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
1821 .id = MLXSW_REG_PSPA_ID,
1822 .len = MLXSW_REG_PSPA_LEN,
1826 * Switch partition ID.
1829 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
1831 /* reg_pspa_local_port
1832 * Local port number.
1835 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
1837 /* reg_pspa_sub_port
1838 * Virtual port within the local port. Set to 0 when virtual ports are
1839 * disabled on the local port.
1842 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
1844 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
1846 MLXSW_REG_ZERO(pspa, payload);
1847 mlxsw_reg_pspa_swid_set(payload, swid);
1848 mlxsw_reg_pspa_local_port_set(payload, local_port);
1849 mlxsw_reg_pspa_sub_port_set(payload, 0);
1852 /* HTGT - Host Trap Group Table
1853 * ----------------------------
1854 * Configures the properties for forwarding to CPU.
1856 #define MLXSW_REG_HTGT_ID 0x7002
1857 #define MLXSW_REG_HTGT_LEN 0x100
1859 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
1860 .id = MLXSW_REG_HTGT_ID,
1861 .len = MLXSW_REG_HTGT_LEN,
1865 * Switch partition ID.
1868 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
1870 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
1876 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
1878 enum mlxsw_reg_htgt_trap_group {
1879 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1880 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1881 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
1884 /* reg_htgt_trap_group
1885 * Trap group number. User defined number specifying which trap groups
1886 * should be forwarded to the CPU. The mapping between trap IDs and trap
1887 * groups is configured using HPKT register.
1890 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
1893 MLXSW_REG_HTGT_POLICER_DISABLE,
1894 MLXSW_REG_HTGT_POLICER_ENABLE,
1898 * Enable policer ID specified using 'pid' field.
1901 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
1904 * Policer ID for the trap group.
1907 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
1909 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
1911 /* reg_htgt_mirror_action
1912 * Mirror action to use.
1914 * 1 - Trap to CPU and mirror to a mirroring agent.
1915 * 2 - Mirror to a mirroring agent and do not trap to CPU.
1918 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
1920 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
1922 /* reg_htgt_mirroring_agent
1926 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
1928 /* reg_htgt_priority
1929 * Trap group priority.
1930 * In case a packet matches multiple classification rules, the packet will
1931 * only be trapped once, based on the trap ID associated with the group (via
1932 * register HPKT) with the highest priority.
1933 * Supported values are 0-7, with 7 represnting the highest priority.
1936 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
1937 * by the 'trap_group' field.
1939 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
1941 /* reg_htgt_local_path_cpu_tclass
1942 * CPU ingress traffic class for the trap group.
1945 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
1947 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
1948 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
1949 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
1951 /* reg_htgt_local_path_rdq
1952 * Receive descriptor queue (RDQ) to use for the trap group.
1955 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
1957 static inline void mlxsw_reg_htgt_pack(char *payload,
1958 enum mlxsw_reg_htgt_trap_group group)
1962 MLXSW_REG_ZERO(htgt, payload);
1964 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
1965 swid = MLXSW_PORT_SWID_ALL_SWIDS;
1966 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
1968 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
1970 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
1972 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
1974 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
1977 mlxsw_reg_htgt_swid_set(payload, swid);
1978 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
1979 mlxsw_reg_htgt_trap_group_set(payload, group);
1980 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
1981 mlxsw_reg_htgt_pid_set(payload, 0);
1982 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
1983 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
1984 mlxsw_reg_htgt_priority_set(payload, 0);
1985 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
1986 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
1989 /* HPKT - Host Packet Trap
1990 * -----------------------
1991 * Configures trap IDs inside trap groups.
1993 #define MLXSW_REG_HPKT_ID 0x7003
1994 #define MLXSW_REG_HPKT_LEN 0x10
1996 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
1997 .id = MLXSW_REG_HPKT_ID,
1998 .len = MLXSW_REG_HPKT_LEN,
2002 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
2003 MLXSW_REG_HPKT_ACK_REQUIRED,
2007 * Require acknowledgements from the host for events.
2008 * If set, then the device will wait for the event it sent to be acknowledged
2009 * by the host. This option is only relevant for event trap IDs.
2012 * Note: Currently not supported by firmware.
2014 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
2016 enum mlxsw_reg_hpkt_action {
2017 MLXSW_REG_HPKT_ACTION_FORWARD,
2018 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2019 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
2020 MLXSW_REG_HPKT_ACTION_DISCARD,
2021 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
2022 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
2026 * Action to perform on packet when trapped.
2027 * 0 - No action. Forward to CPU based on switching rules.
2028 * 1 - Trap to CPU (CPU receives sole copy).
2029 * 2 - Mirror to CPU (CPU receives a replica of the packet).
2031 * 4 - Soft discard (allow other traps to act on the packet).
2032 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
2035 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
2036 * addressed to the CPU.
2038 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
2040 /* reg_hpkt_trap_group
2041 * Trap group to associate the trap with.
2044 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
2050 * Note: A trap ID can only be associated with a single trap group. The device
2051 * will associate the trap ID with the last trap group configured.
2053 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
2056 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
2057 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
2058 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
2062 * Configure dedicated buffer resources for control packets.
2063 * 0 - Keep factory defaults.
2064 * 1 - Do not use control buffer for this trap ID.
2065 * 2 - Use control buffer for this trap ID.
2068 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
2070 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
2072 enum mlxsw_reg_htgt_trap_group trap_group;
2074 MLXSW_REG_ZERO(hpkt, payload);
2075 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
2076 mlxsw_reg_hpkt_action_set(payload, action);
2078 case MLXSW_TRAP_ID_ETHEMAD:
2079 case MLXSW_TRAP_ID_PUDE:
2080 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
2083 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
2086 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
2087 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
2088 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
2091 /* SBPR - Shared Buffer Pools Register
2092 * -----------------------------------
2093 * The SBPR configures and retrieves the shared buffer pools and configuration.
2095 #define MLXSW_REG_SBPR_ID 0xB001
2096 #define MLXSW_REG_SBPR_LEN 0x14
2098 static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
2099 .id = MLXSW_REG_SBPR_ID,
2100 .len = MLXSW_REG_SBPR_LEN,
2103 enum mlxsw_reg_sbpr_dir {
2104 MLXSW_REG_SBPR_DIR_INGRESS,
2105 MLXSW_REG_SBPR_DIR_EGRESS,
2112 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
2118 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
2121 * Pool size in buffer cells.
2124 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
2126 enum mlxsw_reg_sbpr_mode {
2127 MLXSW_REG_SBPR_MODE_STATIC,
2128 MLXSW_REG_SBPR_MODE_DYNAMIC,
2132 * Pool quota calculation mode.
2135 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
2137 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
2138 enum mlxsw_reg_sbpr_dir dir,
2139 enum mlxsw_reg_sbpr_mode mode, u32 size)
2141 MLXSW_REG_ZERO(sbpr, payload);
2142 mlxsw_reg_sbpr_pool_set(payload, pool);
2143 mlxsw_reg_sbpr_dir_set(payload, dir);
2144 mlxsw_reg_sbpr_mode_set(payload, mode);
2145 mlxsw_reg_sbpr_size_set(payload, size);
2148 /* SBCM - Shared Buffer Class Management Register
2149 * ----------------------------------------------
2150 * The SBCM register configures and retrieves the shared buffer allocation
2151 * and configuration according to Port-PG, including the binding to pool
2152 * and definition of the associated quota.
2154 #define MLXSW_REG_SBCM_ID 0xB002
2155 #define MLXSW_REG_SBCM_LEN 0x28
2157 static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
2158 .id = MLXSW_REG_SBCM_ID,
2159 .len = MLXSW_REG_SBCM_LEN,
2162 /* reg_sbcm_local_port
2163 * Local port number.
2164 * For Ingress: excludes CPU port and Router port
2165 * For Egress: excludes IP Router
2168 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
2171 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
2172 * For PG buffer: range is 0..cap_max_pg_buffers - 1
2173 * For traffic class: range is 0..cap_max_tclass - 1
2174 * Note that when traffic class is in MC aware mode then the traffic
2175 * classes which are MC aware cannot be configured.
2178 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
2180 enum mlxsw_reg_sbcm_dir {
2181 MLXSW_REG_SBCM_DIR_INGRESS,
2182 MLXSW_REG_SBCM_DIR_EGRESS,
2189 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
2191 /* reg_sbcm_min_buff
2192 * Minimum buffer size for the limiter, in cells.
2195 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
2197 /* reg_sbcm_max_buff
2198 * When the pool associated to the port-pg/tclass is configured to
2199 * static, Maximum buffer size for the limiter configured in cells.
2200 * When the pool associated to the port-pg/tclass is configured to
2201 * dynamic, the max_buff holds the "alpha" parameter, supporting
2202 * the following values:
2204 * i: (1/128)*2^(i-1), for i=1..14
2208 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
2211 * Association of the port-priority to a pool.
2214 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
2216 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
2217 enum mlxsw_reg_sbcm_dir dir,
2218 u32 min_buff, u32 max_buff, u8 pool)
2220 MLXSW_REG_ZERO(sbcm, payload);
2221 mlxsw_reg_sbcm_local_port_set(payload, local_port);
2222 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
2223 mlxsw_reg_sbcm_dir_set(payload, dir);
2224 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
2225 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
2226 mlxsw_reg_sbcm_pool_set(payload, pool);
2229 /* SBPM - Shared Buffer Class Management Register
2230 * ----------------------------------------------
2231 * The SBPM register configures and retrieves the shared buffer allocation
2232 * and configuration according to Port-Pool, including the definition
2233 * of the associated quota.
2235 #define MLXSW_REG_SBPM_ID 0xB003
2236 #define MLXSW_REG_SBPM_LEN 0x28
2238 static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
2239 .id = MLXSW_REG_SBPM_ID,
2240 .len = MLXSW_REG_SBPM_LEN,
2243 /* reg_sbpm_local_port
2244 * Local port number.
2245 * For Ingress: excludes CPU port and Router port
2246 * For Egress: excludes IP Router
2249 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
2252 * The pool associated to quota counting on the local_port.
2255 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
2257 enum mlxsw_reg_sbpm_dir {
2258 MLXSW_REG_SBPM_DIR_INGRESS,
2259 MLXSW_REG_SBPM_DIR_EGRESS,
2266 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
2268 /* reg_sbpm_min_buff
2269 * Minimum buffer size for the limiter, in cells.
2272 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
2274 /* reg_sbpm_max_buff
2275 * When the pool associated to the port-pg/tclass is configured to
2276 * static, Maximum buffer size for the limiter configured in cells.
2277 * When the pool associated to the port-pg/tclass is configured to
2278 * dynamic, the max_buff holds the "alpha" parameter, supporting
2279 * the following values:
2281 * i: (1/128)*2^(i-1), for i=1..14
2285 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
2287 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
2288 enum mlxsw_reg_sbpm_dir dir,
2289 u32 min_buff, u32 max_buff)
2291 MLXSW_REG_ZERO(sbpm, payload);
2292 mlxsw_reg_sbpm_local_port_set(payload, local_port);
2293 mlxsw_reg_sbpm_pool_set(payload, pool);
2294 mlxsw_reg_sbpm_dir_set(payload, dir);
2295 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
2296 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
2299 /* SBMM - Shared Buffer Multicast Management Register
2300 * --------------------------------------------------
2301 * The SBMM register configures and retrieves the shared buffer allocation
2302 * and configuration for MC packets according to Switch-Priority, including
2303 * the binding to pool and definition of the associated quota.
2305 #define MLXSW_REG_SBMM_ID 0xB004
2306 #define MLXSW_REG_SBMM_LEN 0x28
2308 static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
2309 .id = MLXSW_REG_SBMM_ID,
2310 .len = MLXSW_REG_SBMM_LEN,
2317 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
2319 /* reg_sbmm_min_buff
2320 * Minimum buffer size for the limiter, in cells.
2323 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
2325 /* reg_sbmm_max_buff
2326 * When the pool associated to the port-pg/tclass is configured to
2327 * static, Maximum buffer size for the limiter configured in cells.
2328 * When the pool associated to the port-pg/tclass is configured to
2329 * dynamic, the max_buff holds the "alpha" parameter, supporting
2330 * the following values:
2332 * i: (1/128)*2^(i-1), for i=1..14
2336 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
2339 * Association of the port-priority to a pool.
2342 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
2344 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
2345 u32 max_buff, u8 pool)
2347 MLXSW_REG_ZERO(sbmm, payload);
2348 mlxsw_reg_sbmm_prio_set(payload, prio);
2349 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
2350 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
2351 mlxsw_reg_sbmm_pool_set(payload, pool);
2354 static inline const char *mlxsw_reg_id_str(u16 reg_id)
2357 case MLXSW_REG_SGCR_ID:
2359 case MLXSW_REG_SPAD_ID:
2361 case MLXSW_REG_SSPR_ID:
2363 case MLXSW_REG_SFDAT_ID:
2365 case MLXSW_REG_SFD_ID:
2367 case MLXSW_REG_SFN_ID:
2369 case MLXSW_REG_SPMS_ID:
2371 case MLXSW_REG_SPVID_ID:
2373 case MLXSW_REG_SPVM_ID:
2375 case MLXSW_REG_SFGC_ID:
2377 case MLXSW_REG_SFTR_ID:
2379 case MLXSW_REG_SPMLR_ID:
2381 case MLXSW_REG_SVFA_ID:
2383 case MLXSW_REG_SVPE_ID:
2385 case MLXSW_REG_SFMR_ID:
2387 case MLXSW_REG_SPVMLR_ID:
2389 case MLXSW_REG_PMLP_ID:
2391 case MLXSW_REG_PMTU_ID:
2393 case MLXSW_REG_PTYS_ID:
2395 case MLXSW_REG_PPAD_ID:
2397 case MLXSW_REG_PAOS_ID:
2399 case MLXSW_REG_PPCNT_ID:
2401 case MLXSW_REG_PBMC_ID:
2403 case MLXSW_REG_PSPA_ID:
2405 case MLXSW_REG_HTGT_ID:
2407 case MLXSW_REG_HPKT_ID:
2409 case MLXSW_REG_SBPR_ID:
2411 case MLXSW_REG_SBCM_ID:
2413 case MLXSW_REG_SBPM_ID:
2415 case MLXSW_REG_SBMM_ID:
2422 /* PUDE - Port Up / Down Event
2423 * ---------------------------
2424 * Reports the operational state change of a port.
2426 #define MLXSW_REG_PUDE_LEN 0x10
2429 * Switch partition ID with which to associate the port.
2432 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
2434 /* reg_pude_local_port
2435 * Local port number.
2438 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
2440 /* reg_pude_admin_status
2441 * Port administrative state (the desired state).
2444 * 3 - Up once. This means that in case of link failure, the port won't go
2445 * into polling mode, but will wait to be re-enabled by software.
2446 * 4 - Disabled by system. Can only be set by hardware.
2449 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
2451 /* reg_pude_oper_status
2452 * Port operatioanl state.
2455 * 3 - Down by port failure. This means that the device will not let the
2456 * port up again until explicitly specified by software.
2459 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);