drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  53 struct efx_ef10_dev_addr {
  54         u8 addr[ETH_ALEN];
  55         u16 id;
  56 };
  57
  58 struct efx_ef10_filter_table {
  59 /* The RX match field masks supported by this fw & hw, in order of priority */
  60         enum efx_filter_match_flags rx_match_flags[
  61                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  62         unsigned int rx_match_count;
  63
  64         struct {
  65                 unsigned long spec;     /* pointer to spec plus flag bits */
  66 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  67  * used to mark and sweep MAC filters for the device address lists.
  68  */
  69 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  70 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  71 #define EFX_EF10_FILTER_FLAGS           3UL
  72                 u64 handle;             /* firmware handle */
  73         } *entry;
  74         wait_queue_head_t waitq;
  75 /* Shadow of net_device address lists, guarded by mac_lock */
  76 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  77 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  78         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
  79         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  80         int dev_uc_count;
  81         int dev_mc_count;
  82 /* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
  83         u16 ucdef_id;
  84         u16 bcast_id;
  85         u16 mcdef_id;
  86 };
  87
  88 /* An arbitrary search limit for the software hash table */
  89 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  90
  91 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  92 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  93
  94 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  95 {
  96         efx_dword_t reg;
  97
  98         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  99         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 100                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 101 }
 102
 103 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 104 {
 105         int bar;
 106
 107         bar = efx->type->mem_bar;
 108         return resource_size(&efx->pci_dev->resource[bar]);
 109 }
 110
 111 static bool efx_ef10_is_vf(struct efx_nic *efx)
 112 {
 113         return efx->type->is_vf;
 114 }
 115
 116 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 117 {
 118         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 119         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 120         size_t outlen;
 121         int rc;
 122
 123         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 124                           sizeof(outbuf), &outlen);
 125         if (rc)
 126                 return rc;
 127         if (outlen < sizeof(outbuf))
 128                 return -EIO;
 129
 130         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 131         return 0;
 132 }
 133
 134 #ifdef CONFIG_SFC_SRIOV
 135 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 136 {
 137         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 138         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 139         size_t outlen;
 140         int rc;
 141
 142         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 143                           sizeof(outbuf), &outlen);
 144         if (rc)
 145                 return rc;
 146         if (outlen < sizeof(outbuf))
 147                 return -EIO;
 148
 149         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 150         return 0;
 151 }
 152 #endif
 153
 154 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 155 {
 156         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
 157         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 158         size_t outlen;
 159         int rc;
 160
 161         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 162
 163         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 164                           outbuf, sizeof(outbuf), &outlen);
 165         if (rc)
 166                 return rc;
 167         if (outlen < sizeof(outbuf)) {
 168                 netif_err(efx, drv, efx->net_dev,
 169                           "unable to read datapath firmware capabilities\n");
 170                 return -EIO;
 171         }
 172
 173         nic_data->datapath_caps =
 174                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 175
 176         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 177          */
 178         nic_data->rx_dpcpu_fw_id =
 179                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 180         nic_data->tx_dpcpu_fw_id =
 181                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 182
 183         if (!(nic_data->datapath_caps &
 184               (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
 185                 netif_err(efx, drv, efx->net_dev,
 186                           "current firmware does not support TSO\n");
 187                 return -ENODEV;
 188         }
 189
 190         if (!(nic_data->datapath_caps &
 191               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 192                 netif_err(efx, probe, efx->net_dev,
 193                           "current firmware does not support an RX prefix\n");
 194                 return -ENODEV;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 201 {
 202         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 203         int rc;
 204
 205         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 206                           outbuf, sizeof(outbuf), NULL);
 207         if (rc)
 208                 return rc;
 209         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 210         return rc > 0 ? rc : -ERANGE;
 211 }
 212
 213 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 214 {
 215         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 216         size_t outlen;
 217         int rc;
 218
 219         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 220
 221         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 222                           outbuf, sizeof(outbuf), &outlen);
 223         if (rc)
 224                 return rc;
 225         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 226                 return -EIO;
 227
 228         ether_addr_copy(mac_address,
 229                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 230         return 0;
 231 }
 232
 233 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 234 {
 235         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 236         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 237         size_t outlen;
 238         int num_addrs, rc;
 239
 240         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 241                        EVB_PORT_ID_ASSIGNED);
 242         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 243                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 244
 245         if (rc)
 246                 return rc;
 247         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 248                 return -EIO;
 249
 250         num_addrs = MCDI_DWORD(outbuf,
 251                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 252
 253         WARN_ON(num_addrs != 1);
 254
 255         ether_addr_copy(mac_address,
 256                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 257
 258         return 0;
 259 }
 260
 261 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 262                                                struct device_attribute *attr,
 263                                                char *buf)
 264 {
 265         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 266
 267         return sprintf(buf, "%d\n",
 268                        ((efx->mcdi->fn_flags) &
 269                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 270                        ? 1 : 0);
 271 }
 272
 273 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 274                                           struct device_attribute *attr,
 275                                           char *buf)
 276 {
 277         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 278
 279         return sprintf(buf, "%d\n",
 280                        ((efx->mcdi->fn_flags) &
 281                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 282                        ? 1 : 0);
 283 }
 284
 285 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 286                    NULL);
 287 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 288
 289 static int efx_ef10_probe(struct efx_nic *efx)
 290 {
 291         struct efx_ef10_nic_data *nic_data;
 292         struct net_device *net_dev = efx->net_dev;
 293         int i, rc;
 294
 295         /* We can have one VI for each 8K region.  However, until we
 296          * use TX option descriptors we need two TX queues per channel.
 297          */
 298         efx->max_channels = min_t(unsigned int,
 299                                   EFX_MAX_CHANNELS,
 300                                   efx_ef10_mem_map_size(efx) /
 301                                   (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 302         efx->max_tx_channels = efx->max_channels;
 303         if (WARN_ON(efx->max_channels == 0))
 304                 return -EIO;
 305
 306         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 307         if (!nic_data)
 308                 return -ENOMEM;
 309         efx->nic_data = nic_data;
 310
 311         /* we assume later that we can copy from this buffer in dwords */
 312         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 313
 314         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 315                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 316         if (rc)
 317                 goto fail1;
 318
 319         /* Get the MC's warm boot count.  In case it's rebooting right
 320          * now, be prepared to retry.
 321          */
 322         i = 0;
 323         for (;;) {
 324                 rc = efx_ef10_get_warm_boot_count(efx);
 325                 if (rc >= 0)
 326                         break;
 327                 if (++i == 5)
 328                         goto fail2;
 329                 ssleep(1);
 330         }
 331         nic_data->warm_boot_count = rc;
 332
 333         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 334
 335         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 336
 337         /* In case we're recovering from a crash (kexec), we want to
 338          * cancel any outstanding request by the previous user of this
 339          * function.  We send a special message using the least
 340          * significant bits of the 'high' (doorbell) register.
 341          */
 342         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 343
 344         rc = efx_mcdi_init(efx);
 345         if (rc)
 346                 goto fail2;
 347
 348         /* Reset (most) configuration for this function */
 349         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 350         if (rc)
 351                 goto fail3;
 352
 353         /* Enable event logging */
 354         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 355         if (rc)
 356                 goto fail3;
 357
 358         rc = device_create_file(&efx->pci_dev->dev,
 359                                 &dev_attr_link_control_flag);
 360         if (rc)
 361                 goto fail3;
 362
 363         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 364         if (rc)
 365                 goto fail4;
 366
 367         rc = efx_ef10_get_pf_index(efx);
 368         if (rc)
 369                 goto fail5;
 370
 371         rc = efx_ef10_init_datapath_caps(efx);
 372         if (rc < 0)
 373                 goto fail5;
 374
 375         efx->rx_packet_len_offset =
 376                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 377
 378         rc = efx_mcdi_port_get_number(efx);
 379         if (rc < 0)
 380                 goto fail5;
 381         efx->port_num = rc;
 382         net_dev->dev_port = rc;
 383
 384         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 385         if (rc)
 386                 goto fail5;
 387
 388         rc = efx_ef10_get_sysclk_freq(efx);
 389         if (rc < 0)
 390                 goto fail5;
 391         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 392
 393         /* Check whether firmware supports bug 35388 workaround.
 394          * First try to enable it, then if we get EPERM, just
 395          * ask if it's already enabled
 396          */
 397         rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
 398         if (rc == 0) {
 399                 nic_data->workaround_35388 = true;
 400         } else if (rc == -EPERM) {
 401                 unsigned int enabled;
 402
 403                 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
 404                 if (rc)
 405                         goto fail3;
 406                 nic_data->workaround_35388 = enabled &
 407                         MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
 408         } else if (rc != -ENOSYS && rc != -ENOENT) {
 409                 goto fail5;
 410         }
 411         netif_dbg(efx, probe, efx->net_dev,
 412                   "workaround for bug 35388 is %sabled\n",
 413                   nic_data->workaround_35388 ? "en" : "dis");
 414
 415         rc = efx_mcdi_mon_probe(efx);
 416         if (rc && rc != -EPERM)
 417                 goto fail5;
 418
 419         efx_ptp_probe(efx, NULL);
 420
 421 #ifdef CONFIG_SFC_SRIOV
 422         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 423                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 424                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 425
 426                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 427         } else
 428 #endif
 429                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 430
 431         return 0;
 432
 433 fail5:
 434         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 435 fail4:
 436         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 437 fail3:
 438         efx_mcdi_fini(efx);
 439 fail2:
 440         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 441 fail1:
 442         kfree(nic_data);
 443         efx->nic_data = NULL;
 444         return rc;
 445 }
 446
 447 static int efx_ef10_free_vis(struct efx_nic *efx)
 448 {
 449         MCDI_DECLARE_BUF_ERR(outbuf);
 450         size_t outlen;
 451         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 452                                     outbuf, sizeof(outbuf), &outlen);
 453
 454         /* -EALREADY means nothing to free, so ignore */
 455         if (rc == -EALREADY)
 456                 rc = 0;
 457         if (rc)
 458                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 459                                        rc);
 460         return rc;
 461 }
 462
 463 #ifdef EFX_USE_PIO
 464
 465 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 466 {
 467         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 468         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 469         unsigned int i;
 470         int rc;
 471
 472         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 473
 474         for (i = 0; i < nic_data->n_piobufs; i++) {
 475                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 476                                nic_data->piobuf_handle[i]);
 477                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 478                                   NULL, 0, NULL);
 479                 WARN_ON(rc);
 480         }
 481
 482         nic_data->n_piobufs = 0;
 483 }
 484
 485 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 486 {
 487         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 488         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 489         unsigned int i;
 490         size_t outlen;
 491         int rc = 0;
 492
 493         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 494
 495         for (i = 0; i < n; i++) {
 496                 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 497                                   outbuf, sizeof(outbuf), &outlen);
 498                 if (rc)
 499                         break;
 500                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 501                         rc = -EIO;
 502                         break;
 503                 }
 504                 nic_data->piobuf_handle[i] =
 505                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 506                 netif_dbg(efx, probe, efx->net_dev,
 507                           "allocated PIO buffer %u handle %x\n", i,
 508                           nic_data->piobuf_handle[i]);
 509         }
 510
 511         nic_data->n_piobufs = i;
 512         if (rc)
 513                 efx_ef10_free_piobufs(efx);
 514         return rc;
 515 }
 516
 517 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 518 {
 519         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 520         _MCDI_DECLARE_BUF(inbuf,
 521                           max(MC_CMD_LINK_PIOBUF_IN_LEN,
 522                               MC_CMD_UNLINK_PIOBUF_IN_LEN));
 523         struct efx_channel *channel;
 524         struct efx_tx_queue *tx_queue;
 525         unsigned int offset, index;
 526         int rc;
 527
 528         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 529         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 530
 531         memset(inbuf, 0, sizeof(inbuf));
 532
 533         /* Link a buffer to each VI in the write-combining mapping */
 534         for (index = 0; index < nic_data->n_piobufs; ++index) {
 535                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 536                                nic_data->piobuf_handle[index]);
 537                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 538                                nic_data->pio_write_vi_base + index);
 539                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 540                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 541                                   NULL, 0, NULL);
 542                 if (rc) {
 543                         netif_err(efx, drv, efx->net_dev,
 544                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 545                                   nic_data->pio_write_vi_base + index, index,
 546                                   rc);
 547                         goto fail;
 548                 }
 549                 netif_dbg(efx, probe, efx->net_dev,
 550                           "linked VI %u to PIO buffer %u\n",
 551                           nic_data->pio_write_vi_base + index, index);
 552         }
 553
 554         /* Link a buffer to each TX queue */
 555         efx_for_each_channel(channel, efx) {
 556                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 557                         /* We assign the PIO buffers to queues in
 558                          * reverse order to allow for the following
 559                          * special case.
 560                          */
 561                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 562                                    tx_queue->channel->channel - 1) *
 563                                   efx_piobuf_size);
 564                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 565                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 566
 567                         /* When the host page size is 4K, the first
 568                          * host page in the WC mapping may be within
 569                          * the same VI page as the last TX queue.  We
 570                          * can only link one buffer to each VI.
 571                          */
 572                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 573                                 BUG_ON(index != 0);
 574                                 rc = 0;
 575                         } else {
 576                                 MCDI_SET_DWORD(inbuf,
 577                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 578                                                nic_data->piobuf_handle[index]);
 579                                 MCDI_SET_DWORD(inbuf,
 580                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 581                                                tx_queue->queue);
 582                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 583                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 584                                                   NULL, 0, NULL);
 585                         }
 586
 587                         if (rc) {
 588                                 /* This is non-fatal; the TX path just
 589                                  * won't use PIO for this queue
 590                                  */
 591                                 netif_err(efx, drv, efx->net_dev,
 592                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 593                                           tx_queue->queue, index, rc);
 594                                 tx_queue->piobuf = NULL;
 595                         } else {
 596                                 tx_queue->piobuf =
 597                                         nic_data->pio_write_base +
 598                                         index * EFX_VI_PAGE_SIZE + offset;
 599                                 tx_queue->piobuf_offset = offset;
 600                                 netif_dbg(efx, probe, efx->net_dev,
 601                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 602                                           tx_queue->queue, index,
 603                                           tx_queue->piobuf_offset,
 604                                           tx_queue->piobuf);
 605                         }
 606                 }
 607         }
 608
 609         return 0;
 610
 611 fail:
 612         while (index--) {
 613                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 614                                nic_data->pio_write_vi_base + index);
 615                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 616                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 617                              NULL, 0, NULL);
 618         }
 619         return rc;
 620 }
 621
 622 #else /* !EFX_USE_PIO */
 623
 624 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 625 {
 626         return n == 0 ? 0 : -ENOBUFS;
 627 }
 628
 629 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 630 {
 631         return 0;
 632 }
 633
 634 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 635 {
 636 }
 637
 638 #endif /* EFX_USE_PIO */
 639
 640 static void efx_ef10_remove(struct efx_nic *efx)
 641 {
 642         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 643         int rc;
 644
 645 #ifdef CONFIG_SFC_SRIOV
 646         struct efx_ef10_nic_data *nic_data_pf;
 647         struct pci_dev *pci_dev_pf;
 648         struct efx_nic *efx_pf;
 649         struct ef10_vf *vf;
 650
 651         if (efx->pci_dev->is_virtfn) {
 652                 pci_dev_pf = efx->pci_dev->physfn;
 653                 if (pci_dev_pf) {
 654                         efx_pf = pci_get_drvdata(pci_dev_pf);
 655                         nic_data_pf = efx_pf->nic_data;
 656                         vf = nic_data_pf->vf + nic_data->vf_index;
 657                         vf->efx = NULL;
 658                 } else
 659                         netif_info(efx, drv, efx->net_dev,
 660                                    "Could not get the PF id from VF\n");
 661         }
 662 #endif
 663
 664         efx_ptp_remove(efx);
 665
 666         efx_mcdi_mon_remove(efx);
 667
 668         efx_ef10_rx_free_indir_table(efx);
 669
 670         if (nic_data->wc_membase)
 671                 iounmap(nic_data->wc_membase);
 672
 673         rc = efx_ef10_free_vis(efx);
 674         WARN_ON(rc != 0);
 675
 676         if (!nic_data->must_restore_piobufs)
 677                 efx_ef10_free_piobufs(efx);
 678
 679         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 680         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 681
 682         efx_mcdi_fini(efx);
 683         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 684         kfree(nic_data);
 685 }
 686
 687 static int efx_ef10_probe_pf(struct efx_nic *efx)
 688 {
 689         return efx_ef10_probe(efx);
 690 }
 691
 692 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
 693 {
 694         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
 695
 696         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
 697         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
 698                             NULL, 0, NULL);
 699 }
 700
 701 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
 702 {
 703         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
 704
 705         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
 706         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
 707                             NULL, 0, NULL);
 708 }
 709
 710 int efx_ef10_vport_add_mac(struct efx_nic *efx,
 711                            unsigned int port_id, u8 *mac)
 712 {
 713         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
 714
 715         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
 716         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
 717
 718         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
 719                             sizeof(inbuf), NULL, 0, NULL);
 720 }
 721
 722 int efx_ef10_vport_del_mac(struct efx_nic *efx,
 723                            unsigned int port_id, u8 *mac)
 724 {
 725         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
 726
 727         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
 728         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
 729
 730         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
 731                             sizeof(inbuf), NULL, 0, NULL);
 732 }
 733
 734 #ifdef CONFIG_SFC_SRIOV
 735 static int efx_ef10_probe_vf(struct efx_nic *efx)
 736 {
 737         int rc;
 738         struct pci_dev *pci_dev_pf;
 739
 740         /* If the parent PF has no VF data structure, it doesn't know about this
 741          * VF so fail probe.  The VF needs to be re-created.  This can happen
 742          * if the PF driver is unloaded while the VF is assigned to a guest.
 743          */
 744         pci_dev_pf = efx->pci_dev->physfn;
 745         if (pci_dev_pf) {
 746                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 747                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
 748
 749                 if (!nic_data_pf->vf) {
 750                         netif_info(efx, drv, efx->net_dev,
 751                                    "The VF cannot link to its parent PF; "
 752                                    "please destroy and re-create the VF\n");
 753                         return -EBUSY;
 754                 }
 755         }
 756
 757         rc = efx_ef10_probe(efx);
 758         if (rc)
 759                 return rc;
 760
 761         rc = efx_ef10_get_vf_index(efx);
 762         if (rc)
 763                 goto fail;
 764
 765         if (efx->pci_dev->is_virtfn) {
 766                 if (efx->pci_dev->physfn) {
 767                         struct efx_nic *efx_pf =
 768                                 pci_get_drvdata(efx->pci_dev->physfn);
 769                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
 770                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 771
 772                         nic_data_p->vf[nic_data->vf_index].efx = efx;
 773                         nic_data_p->vf[nic_data->vf_index].pci_dev =
 774                                 efx->pci_dev;
 775                 } else
 776                         netif_info(efx, drv, efx->net_dev,
 777                                    "Could not get the PF id from VF\n");
 778         }
 779
 780         return 0;
 781
 782 fail:
 783         efx_ef10_remove(efx);
 784         return rc;
 785 }
 786 #else
 787 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
 788 {
 789         return 0;
 790 }
 791 #endif
 792
 793 static int efx_ef10_alloc_vis(struct efx_nic *efx,
 794                               unsigned int min_vis, unsigned int max_vis)
 795 {
 796         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
 797         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
 798         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 799         size_t outlen;
 800         int rc;
 801
 802         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
 803         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
 804         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
 805                           outbuf, sizeof(outbuf), &outlen);
 806         if (rc != 0)
 807                 return rc;
 808
 809         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
 810                 return -EIO;
 811
 812         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
 813                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
 814
 815         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
 816         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
 817         return 0;
 818 }
 819
 820 /* Note that the failure path of this function does not free
 821  * resources, as this will be done by efx_ef10_remove().
 822  */
 823 static int efx_ef10_dimension_resources(struct efx_nic *efx)
 824 {
 825         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 826         unsigned int uc_mem_map_size, wc_mem_map_size;
 827         unsigned int min_vis = max(EFX_TXQ_TYPES,
 828                                    efx_separate_tx_channels ? 2 : 1);
 829         unsigned int channel_vis, pio_write_vi_base, max_vis;
 830         void __iomem *membase;
 831         int rc;
 832
 833         channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
 834
 835 #ifdef EFX_USE_PIO
 836         /* Try to allocate PIO buffers if wanted and if the full
 837          * number of PIO buffers would be sufficient to allocate one
 838          * copy-buffer per TX channel.  Failure is non-fatal, as there
 839          * are only a small number of PIO buffers shared between all
 840          * functions of the controller.
 841          */
 842         if (efx_piobuf_size != 0 &&
 843             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
 844             efx->n_tx_channels) {
 845                 unsigned int n_piobufs =
 846                         DIV_ROUND_UP(efx->n_tx_channels,
 847                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
 848
 849                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
 850                 if (rc)
 851                         netif_err(efx, probe, efx->net_dev,
 852                                   "failed to allocate PIO buffers (%d)\n", rc);
 853                 else
 854                         netif_dbg(efx, probe, efx->net_dev,
 855                                   "allocated %u PIO buffers\n", n_piobufs);
 856         }
 857 #else
 858         nic_data->n_piobufs = 0;
 859 #endif
 860
 861         /* PIO buffers should be mapped with write-combining enabled,
 862          * and we want to make single UC and WC mappings rather than
 863          * several of each (in fact that's the only option if host
 864          * page size is >4K).  So we may allocate some extra VIs just
 865          * for writing PIO buffers through.
 866          *
 867          * The UC mapping contains (channel_vis - 1) complete VIs and the
 868          * first half of the next VI.  Then the WC mapping begins with
 869          * the second half of this last VI.
 870          */
 871         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
 872                                      ER_DZ_TX_PIOBUF);
 873         if (nic_data->n_piobufs) {
 874                 /* pio_write_vi_base rounds down to give the number of complete
 875                  * VIs inside the UC mapping.
 876                  */
 877                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
 878                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
 879                                                nic_data->n_piobufs) *
 880                                               EFX_VI_PAGE_SIZE) -
 881                                    uc_mem_map_size);
 882                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
 883         } else {
 884                 pio_write_vi_base = 0;
 885                 wc_mem_map_size = 0;
 886                 max_vis = channel_vis;
 887         }
 888
 889         /* In case the last attached driver failed to free VIs, do it now */
 890         rc = efx_ef10_free_vis(efx);
 891         if (rc != 0)
 892                 return rc;
 893
 894         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
 895         if (rc != 0)
 896                 return rc;
 897
 898         if (nic_data->n_allocated_vis < channel_vis) {
 899                 netif_info(efx, drv, efx->net_dev,
 900                            "Could not allocate enough VIs to satisfy RSS"
 901                            " requirements. Performance may not be optimal.\n");
 902                 /* We didn't get the VIs to populate our channels.
 903                  * We could keep what we got but then we'd have more
 904                  * interrupts than we need.
 905                  * Instead calculate new max_channels and restart
 906                  */
 907                 efx->max_channels = nic_data->n_allocated_vis;
 908                 efx->max_tx_channels =
 909                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
 910
 911                 efx_ef10_free_vis(efx);
 912                 return -EAGAIN;
 913         }
 914
 915         /* If we didn't get enough VIs to map all the PIO buffers, free the
 916          * PIO buffers
 917          */
 918         if (nic_data->n_piobufs &&
 919             nic_data->n_allocated_vis <
 920             pio_write_vi_base + nic_data->n_piobufs) {
 921                 netif_dbg(efx, probe, efx->net_dev,
 922                           "%u VIs are not sufficient to map %u PIO buffers\n",
 923                           nic_data->n_allocated_vis, nic_data->n_piobufs);
 924                 efx_ef10_free_piobufs(efx);
 925         }
 926
 927         /* Shrink the original UC mapping of the memory BAR */
 928         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
 929         if (!membase) {
 930                 netif_err(efx, probe, efx->net_dev,
 931                           "could not shrink memory BAR to %x\n",
 932                           uc_mem_map_size);
 933                 return -ENOMEM;
 934         }
 935         iounmap(efx->membase);
 936         efx->membase = membase;
 937
 938         /* Set up the WC mapping if needed */
 939         if (wc_mem_map_size) {
 940                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
 941                                                   uc_mem_map_size,
 942                                                   wc_mem_map_size);
 943                 if (!nic_data->wc_membase) {
 944                         netif_err(efx, probe, efx->net_dev,
 945                                   "could not allocate WC mapping of size %x\n",
 946                                   wc_mem_map_size);
 947                         return -ENOMEM;
 948                 }
 949                 nic_data->pio_write_vi_base = pio_write_vi_base;
 950                 nic_data->pio_write_base =
 951                         nic_data->wc_membase +
 952                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
 953                          uc_mem_map_size);
 954
 955                 rc = efx_ef10_link_piobufs(efx);
 956                 if (rc)
 957                         efx_ef10_free_piobufs(efx);
 958         }
 959
 960         netif_dbg(efx, probe, efx->net_dev,
 961                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
 962                   &efx->membase_phys, efx->membase, uc_mem_map_size,
 963                   nic_data->wc_membase, wc_mem_map_size);
 964
 965         return 0;
 966 }
 967
 968 static int efx_ef10_init_nic(struct efx_nic *efx)
 969 {
 970         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 971         int rc;
 972
 973         if (nic_data->must_check_datapath_caps) {
 974                 rc = efx_ef10_init_datapath_caps(efx);
 975                 if (rc)
 976                         return rc;
 977                 nic_data->must_check_datapath_caps = false;
 978         }
 979
 980         if (nic_data->must_realloc_vis) {
 981                 /* We cannot let the number of VIs change now */
 982                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
 983                                         nic_data->n_allocated_vis);
 984                 if (rc)
 985                         return rc;
 986                 nic_data->must_realloc_vis = false;
 987         }
 988
 989         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
 990                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
 991                 if (rc == 0) {
 992                         rc = efx_ef10_link_piobufs(efx);
 993                         if (rc)
 994                                 efx_ef10_free_piobufs(efx);
 995                 }
 996
 997                 /* Log an error on failure, but this is non-fatal */
 998                 if (rc)
 999                         netif_err(efx, drv, efx->net_dev,
1000                                   "failed to restore PIO buffers (%d)\n", rc);
1001                 nic_data->must_restore_piobufs = false;
1002         }
1003
1004         /* don't fail init if RSS setup doesn't work */
1005         efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1006
1007         return 0;
1008 }
1009
1010 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1011 {
1012         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1013 #ifdef CONFIG_SFC_SRIOV
1014         unsigned int i;
1015 #endif
1016
1017         /* All our allocations have been reset */
1018         nic_data->must_realloc_vis = true;
1019         nic_data->must_restore_filters = true;
1020         nic_data->must_restore_piobufs = true;
1021         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1022
1023         /* Driver-created vswitches and vports must be re-created */
1024         nic_data->must_probe_vswitching = true;
1025         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1026 #ifdef CONFIG_SFC_SRIOV
1027         if (nic_data->vf)
1028                 for (i = 0; i < efx->vf_count; i++)
1029                         nic_data->vf[i].vport_id = 0;
1030 #endif
1031 }
1032
1033 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1034 {
1035         if (reason == RESET_TYPE_MC_FAILURE)
1036                 return RESET_TYPE_DATAPATH;
1037
1038         return efx_mcdi_map_reset_reason(reason);
1039 }
1040
1041 static int efx_ef10_map_reset_flags(u32 *flags)
1042 {
1043         enum {
1044                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1045                                    ETH_RESET_SHARED_SHIFT),
1046                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1047                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1048                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1049                                  ETH_RESET_SHARED_SHIFT)
1050         };
1051
1052         /* We assume for now that our PCI function is permitted to
1053          * reset everything.
1054          */
1055
1056         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1057                 *flags &= ~EF10_RESET_MC;
1058                 return RESET_TYPE_WORLD;
1059         }
1060
1061         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1062                 *flags &= ~EF10_RESET_PORT;
1063                 return RESET_TYPE_ALL;
1064         }
1065
1066         /* no invisible reset implemented */
1067
1068         return -EINVAL;
1069 }
1070
1071 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1072 {
1073         int rc = efx_mcdi_reset(efx, reset_type);
1074
1075         /* Unprivileged functions return -EPERM, but need to return success
1076          * here so that the datapath is brought back up.
1077          */
1078         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1079                 rc = 0;
1080
1081         /* If it was a port reset, trigger reallocation of MC resources.
1082          * Note that on an MC reset nothing needs to be done now because we'll
1083          * detect the MC reset later and handle it then.
1084          * For an FLR, we never get an MC reset event, but the MC has reset all
1085          * resources assigned to us, so we have to trigger reallocation now.
1086          */
1087         if ((reset_type == RESET_TYPE_ALL ||
1088              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1089                 efx_ef10_reset_mc_allocations(efx);
1090         return rc;
1091 }
1092
1093 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1094         [EF10_STAT_ ## ext_name] =                              \
1095         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1096 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1097         [EF10_STAT_ ## int_name] =                              \
1098         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1099 #define EF10_OTHER_STAT(ext_name)                               \
1100         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1101 #define GENERIC_SW_STAT(ext_name)                               \
1102         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1103
1104 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1105         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1106         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1107         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1108         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1109         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1110         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1111         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1112         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1113         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1114         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1115         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1116         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1117         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1118         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1119         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1120         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1121         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1122         EF10_OTHER_STAT(port_rx_good_bytes),
1123         EF10_OTHER_STAT(port_rx_bad_bytes),
1124         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1125         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1126         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1127         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1128         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1129         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1130         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1131         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1132         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1133         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1134         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1135         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1136         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1137         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1138         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1139         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1140         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1141         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1142         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1143         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1144         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1145         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1146         GENERIC_SW_STAT(rx_nodesc_trunc),
1147         GENERIC_SW_STAT(rx_noskb_drops),
1148         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1149         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1150         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1151         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1152         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1153         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1154         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1155         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1156         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1157         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1158         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1159         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1160         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1161         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1162         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1163         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1164         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1165         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1166         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1167         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1168         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1169         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1170         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1171         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1172         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1173         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1174         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1175         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1176         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1177         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1178 };
1179
1180 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1181                                (1ULL << EF10_STAT_port_tx_packets) |    \
1182                                (1ULL << EF10_STAT_port_tx_pause) |      \
1183                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1184                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1185                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1186                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1187                                (1ULL <<                                 \
1188                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1189                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1190                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1191                                (1ULL << EF10_STAT_port_rx_packets) |    \
1192                                (1ULL << EF10_STAT_port_rx_good) |       \
1193                                (1ULL << EF10_STAT_port_rx_bad) |        \
1194                                (1ULL << EF10_STAT_port_rx_pause) |      \
1195                                (1ULL << EF10_STAT_port_rx_control) |    \
1196                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1197                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1198                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1199                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1200                                (1ULL << EF10_STAT_port_rx_64) |         \
1201                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1202                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1203                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1204                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1205                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1206                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1207                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1208                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1209                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1210                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1211                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1212                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1213
1214 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
1215  * switchable port we do not expose these because they might not
1216  * include all the packets they should.
1217  */
1218 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1219                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1220                                  (1ULL << EF10_STAT_port_tx_64) |       \
1221                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1222                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1223                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1224                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1225                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1226                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1227
1228 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1229  * switchable port we do expose these because the errors will otherwise
1230  * be silent.
1231  */
1232 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1233                                   (1ULL << EF10_STAT_port_rx_length_error))
1234
1235 /* These statistics are only provided if the firmware supports the
1236  * capability PM_AND_RXDP_COUNTERS.
1237  */
1238 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1239         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1240         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1241         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1242         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1243         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1244         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1245         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1246         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1247         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1248         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1249         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1250         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1251
1252 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1253 {
1254         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1255         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1256         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1257
1258         if (!(efx->mcdi->fn_flags &
1259               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1260                 return 0;
1261
1262         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1263                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1264         else
1265                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1266
1267         if (nic_data->datapath_caps &
1268             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1269                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1270
1271         return raw_mask;
1272 }
1273
1274 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1275 {
1276         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1277         u64 raw_mask[2];
1278
1279         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1280
1281         /* Only show vadaptor stats when EVB capability is present */
1282         if (nic_data->datapath_caps &
1283             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1284                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1285                 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1286         } else {
1287                 raw_mask[1] = 0;
1288         }
1289
1290 #if BITS_PER_LONG == 64
1291         mask[0] = raw_mask[0];
1292         mask[1] = raw_mask[1];
1293 #else
1294         mask[0] = raw_mask[0] & 0xffffffff;
1295         mask[1] = raw_mask[0] >> 32;
1296         mask[2] = raw_mask[1] & 0xffffffff;
1297         mask[3] = raw_mask[1] >> 32;
1298 #endif
1299 }
1300
1301 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1302 {
1303         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1304
1305         efx_ef10_get_stat_mask(efx, mask);
1306         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1307                                       mask, names);
1308 }
1309
1310 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1311                                            struct rtnl_link_stats64 *core_stats)
1312 {
1313         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1314         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1315         u64 *stats = nic_data->stats;
1316         size_t stats_count = 0, index;
1317
1318         efx_ef10_get_stat_mask(efx, mask);
1319
1320         if (full_stats) {
1321                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1322                         if (efx_ef10_stat_desc[index].name) {
1323                                 *full_stats++ = stats[index];
1324                                 ++stats_count;
1325                         }
1326                 }
1327         }
1328
1329         if (!core_stats)
1330                 return stats_count;
1331
1332         if (nic_data->datapath_caps &
1333                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1334                 /* Use vadaptor stats. */
1335                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1336                                          stats[EF10_STAT_rx_multicast] +
1337                                          stats[EF10_STAT_rx_broadcast];
1338                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1339                                          stats[EF10_STAT_tx_multicast] +
1340                                          stats[EF10_STAT_tx_broadcast];
1341                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1342                                        stats[EF10_STAT_rx_multicast_bytes] +
1343                                        stats[EF10_STAT_rx_broadcast_bytes];
1344                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1345                                        stats[EF10_STAT_tx_multicast_bytes] +
1346                                        stats[EF10_STAT_tx_broadcast_bytes];
1347                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1348                                          stats[GENERIC_STAT_rx_noskb_drops];
1349                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1350                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1351                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1352                 core_stats->rx_errors = core_stats->rx_crc_errors;
1353                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1354         } else {
1355                 /* Use port stats. */
1356                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1357                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1358                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1359                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1360                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1361                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1362                                          stats[GENERIC_STAT_rx_noskb_drops];
1363                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1364                 core_stats->rx_length_errors =
1365                                 stats[EF10_STAT_port_rx_gtjumbo] +
1366                                 stats[EF10_STAT_port_rx_length_error];
1367                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1368                 core_stats->rx_frame_errors =
1369                                 stats[EF10_STAT_port_rx_align_error];
1370                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1371                 core_stats->rx_errors = (core_stats->rx_length_errors +
1372                                          core_stats->rx_crc_errors +
1373                                          core_stats->rx_frame_errors);
1374         }
1375
1376         return stats_count;
1377 }
1378
1379 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1380 {
1381         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1382         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1383         __le64 generation_start, generation_end;
1384         u64 *stats = nic_data->stats;
1385         __le64 *dma_stats;
1386
1387         efx_ef10_get_stat_mask(efx, mask);
1388
1389         dma_stats = efx->stats_buffer.addr;
1390         nic_data = efx->nic_data;
1391
1392         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1393         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1394                 return 0;
1395         rmb();
1396         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1397                              stats, efx->stats_buffer.addr, false);
1398         rmb();
1399         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1400         if (generation_end != generation_start)
1401                 return -EAGAIN;
1402
1403         /* Update derived statistics */
1404         efx_nic_fix_nodesc_drop_stat(efx,
1405                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1406         stats[EF10_STAT_port_rx_good_bytes] =
1407                 stats[EF10_STAT_port_rx_bytes] -
1408                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1409         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1410                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1411         efx_update_sw_stats(efx, stats);
1412         return 0;
1413 }
1414
1415
1416 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1417                                        struct rtnl_link_stats64 *core_stats)
1418 {
1419         int retry;
1420
1421         /* If we're unlucky enough to read statistics during the DMA, wait
1422          * up to 10ms for it to finish (typically takes <500us)
1423          */
1424         for (retry = 0; retry < 100; ++retry) {
1425                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1426                         break;
1427                 udelay(100);
1428         }
1429
1430         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1431 }
1432
1433 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1434 {
1435         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1436         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1437         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1438         __le64 generation_start, generation_end;
1439         u64 *stats = nic_data->stats;
1440         u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1441         struct efx_buffer stats_buf;
1442         __le64 *dma_stats;
1443         int rc;
1444
1445         spin_unlock_bh(&efx->stats_lock);
1446
1447         if (in_interrupt()) {
1448                 /* If in atomic context, cannot update stats.  Just update the
1449                  * software stats and return so the caller can continue.
1450                  */
1451                 spin_lock_bh(&efx->stats_lock);
1452                 efx_update_sw_stats(efx, stats);
1453                 return 0;
1454         }
1455
1456         efx_ef10_get_stat_mask(efx, mask);
1457
1458         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1459         if (rc) {
1460                 spin_lock_bh(&efx->stats_lock);
1461                 return rc;
1462         }
1463
1464         dma_stats = stats_buf.addr;
1465         dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1466
1467         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1468         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1469                               MAC_STATS_IN_DMA, 1);
1470         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1471         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1472
1473         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1474                                 NULL, 0, NULL);
1475         spin_lock_bh(&efx->stats_lock);
1476         if (rc) {
1477                 /* Expect ENOENT if DMA queues have not been set up */
1478                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1479                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1480                                                sizeof(inbuf), NULL, 0, rc);
1481                 goto out;
1482         }
1483
1484         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1485         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1486                 WARN_ON_ONCE(1);
1487                 goto out;
1488         }
1489         rmb();
1490         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1491                              stats, stats_buf.addr, false);
1492         rmb();
1493         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1494         if (generation_end != generation_start) {
1495                 rc = -EAGAIN;
1496                 goto out;
1497         }
1498
1499         efx_update_sw_stats(efx, stats);
1500 out:
1501         efx_nic_free_buffer(efx, &stats_buf);
1502         return rc;
1503 }
1504
1505 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1506                                        struct rtnl_link_stats64 *core_stats)
1507 {
1508         if (efx_ef10_try_update_nic_stats_vf(efx))
1509                 return 0;
1510
1511         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1512 }
1513
1514 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1515 {
1516         struct efx_nic *efx = channel->efx;
1517         unsigned int mode, value;
1518         efx_dword_t timer_cmd;
1519
1520         if (channel->irq_moderation) {
1521                 mode = 3;
1522                 value = channel->irq_moderation - 1;
1523         } else {
1524                 mode = 0;
1525                 value = 0;
1526         }
1527
1528         if (EFX_EF10_WORKAROUND_35388(efx)) {
1529                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1530                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1531                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1532                                      ERF_DD_EVQ_IND_TIMER_VAL, value);
1533                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1534                                 channel->channel);
1535         } else {
1536                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1537                                      ERF_DZ_TC_TIMER_VAL, value);
1538                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1539                                 channel->channel);
1540         }
1541 }
1542
1543 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1544                                 struct ethtool_wolinfo *wol) {}
1545
1546 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1547 {
1548         return -EOPNOTSUPP;
1549 }
1550
1551 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1552 {
1553         wol->supported = 0;
1554         wol->wolopts = 0;
1555         memset(&wol->sopass, 0, sizeof(wol->sopass));
1556 }
1557
1558 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1559 {
1560         if (type != 0)
1561                 return -EINVAL;
1562         return 0;
1563 }
1564
1565 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1566                                   const efx_dword_t *hdr, size_t hdr_len,
1567                                   const efx_dword_t *sdu, size_t sdu_len)
1568 {
1569         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1570         u8 *pdu = nic_data->mcdi_buf.addr;
1571
1572         memcpy(pdu, hdr, hdr_len);
1573         memcpy(pdu + hdr_len, sdu, sdu_len);
1574         wmb();
1575
1576         /* The hardware provides 'low' and 'high' (doorbell) registers
1577          * for passing the 64-bit address of an MCDI request to
1578          * firmware.  However the dwords are swapped by firmware.  The
1579          * least significant bits of the doorbell are then 0 for all
1580          * MCDI requests due to alignment.
1581          */
1582         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1583                     ER_DZ_MC_DB_LWRD);
1584         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1585                     ER_DZ_MC_DB_HWRD);
1586 }
1587
1588 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1589 {
1590         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1591         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1592
1593         rmb();
1594         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1595 }
1596
1597 static void
1598 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1599                             size_t offset, size_t outlen)
1600 {
1601         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1602         const u8 *pdu = nic_data->mcdi_buf.addr;
1603
1604         memcpy(outbuf, pdu + offset, outlen);
1605 }
1606
1607 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1608 {
1609         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1610         int rc;
1611
1612         rc = efx_ef10_get_warm_boot_count(efx);
1613         if (rc < 0) {
1614                 /* The firmware is presumably in the process of
1615                  * rebooting.  However, we are supposed to report each
1616                  * reboot just once, so we must only do that once we
1617                  * can read and store the updated warm boot count.
1618                  */
1619                 return 0;
1620         }
1621
1622         if (rc == nic_data->warm_boot_count)
1623                 return 0;
1624
1625         nic_data->warm_boot_count = rc;
1626
1627         /* All our allocations have been reset */
1628         efx_ef10_reset_mc_allocations(efx);
1629
1630         /* The datapath firmware might have been changed */
1631         nic_data->must_check_datapath_caps = true;
1632
1633         /* MAC statistics have been cleared on the NIC; clear the local
1634          * statistic that we update with efx_update_diff_stat().
1635          */
1636         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1637
1638         return -EIO;
1639 }
1640
1641 /* Handle an MSI interrupt
1642  *
1643  * Handle an MSI hardware interrupt.  This routine schedules event
1644  * queue processing.  No interrupt acknowledgement cycle is necessary.
1645  * Also, we never need to check that the interrupt is for us, since
1646  * MSI interrupts cannot be shared.
1647  */
1648 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1649 {
1650         struct efx_msi_context *context = dev_id;
1651         struct efx_nic *efx = context->efx;
1652
1653         netif_vdbg(efx, intr, efx->net_dev,
1654                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1655
1656         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1657                 /* Note test interrupts */
1658                 if (context->index == efx->irq_level)
1659                         efx->last_irq_cpu = raw_smp_processor_id();
1660
1661                 /* Schedule processing of the channel */
1662                 efx_schedule_channel_irq(efx->channel[context->index]);
1663         }
1664
1665         return IRQ_HANDLED;
1666 }
1667
1668 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1669 {
1670         struct efx_nic *efx = dev_id;
1671         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1672         struct efx_channel *channel;
1673         efx_dword_t reg;
1674         u32 queues;
1675
1676         /* Read the ISR which also ACKs the interrupts */
1677         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1678         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1679
1680         if (queues == 0)
1681                 return IRQ_NONE;
1682
1683         if (likely(soft_enabled)) {
1684                 /* Note test interrupts */
1685                 if (queues & (1U << efx->irq_level))
1686                         efx->last_irq_cpu = raw_smp_processor_id();
1687
1688                 efx_for_each_channel(channel, efx) {
1689                         if (queues & 1)
1690                                 efx_schedule_channel_irq(channel);
1691                         queues >>= 1;
1692                 }
1693         }
1694
1695         netif_vdbg(efx, intr, efx->net_dev,
1696                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1697                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1698
1699         return IRQ_HANDLED;
1700 }
1701
1702 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1703 {
1704         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1705
1706         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1707
1708         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1709         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1710                             inbuf, sizeof(inbuf), NULL, 0, NULL);
1711 }
1712
1713 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1714 {
1715         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1716                                     (tx_queue->ptr_mask + 1) *
1717                                     sizeof(efx_qword_t),
1718                                     GFP_KERNEL);
1719 }
1720
1721 /* This writes to the TX_DESC_WPTR and also pushes data */
1722 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1723                                          const efx_qword_t *txd)
1724 {
1725         unsigned int write_ptr;
1726         efx_oword_t reg;
1727
1728         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1729         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1730         reg.qword[0] = *txd;
1731         efx_writeo_page(tx_queue->efx, &reg,
1732                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
1733 }
1734
1735 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1736 {
1737         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1738                                                        EFX_BUF_SIZE));
1739         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1740         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1741         struct efx_channel *channel = tx_queue->channel;
1742         struct efx_nic *efx = tx_queue->efx;
1743         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1744         size_t inlen;
1745         dma_addr_t dma_addr;
1746         efx_qword_t *txd;
1747         int rc;
1748         int i;
1749         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1750
1751         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1752         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1753         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1754         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1755         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1756                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1757                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1758         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1759         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1760
1761         dma_addr = tx_queue->txd.buf.dma_addr;
1762
1763         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1764                   tx_queue->queue, entries, (u64)dma_addr);
1765
1766         for (i = 0; i < entries; ++i) {
1767                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1768                 dma_addr += EFX_BUF_SIZE;
1769         }
1770
1771         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1772
1773         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1774                           NULL, 0, NULL);
1775         if (rc)
1776                 goto fail;
1777
1778         /* A previous user of this TX queue might have set us up the
1779          * bomb by writing a descriptor to the TX push collector but
1780          * not the doorbell.  (Each collector belongs to a port, not a
1781          * queue or function, so cannot easily be reset.)  We must
1782          * attempt to push a no-op descriptor in its place.
1783          */
1784         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1785         tx_queue->insert_count = 1;
1786         txd = efx_tx_desc(tx_queue, 0);
1787         EFX_POPULATE_QWORD_4(*txd,
1788                              ESF_DZ_TX_DESC_IS_OPT, true,
1789                              ESF_DZ_TX_OPTION_TYPE,
1790                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1791                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1792                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1793         tx_queue->write_count = 1;
1794         wmb();
1795         efx_ef10_push_tx_desc(tx_queue, txd);
1796
1797         return;
1798
1799 fail:
1800         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1801                     tx_queue->queue);
1802 }
1803
1804 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1805 {
1806         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1807         MCDI_DECLARE_BUF_ERR(outbuf);
1808         struct efx_nic *efx = tx_queue->efx;
1809         size_t outlen;
1810         int rc;
1811
1812         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1813                        tx_queue->queue);
1814
1815         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1816                           outbuf, sizeof(outbuf), &outlen);
1817
1818         if (rc && rc != -EALREADY)
1819                 goto fail;
1820
1821         return;
1822
1823 fail:
1824         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1825                                outbuf, outlen, rc);
1826 }
1827
1828 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1829 {
1830         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1831 }
1832
1833 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1834 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1835 {
1836         unsigned int write_ptr;
1837         efx_dword_t reg;
1838
1839         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1840         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1841         efx_writed_page(tx_queue->efx, &reg,
1842                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1843 }
1844
1845 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1846 {
1847         unsigned int old_write_count = tx_queue->write_count;
1848         struct efx_tx_buffer *buffer;
1849         unsigned int write_ptr;
1850         efx_qword_t *txd;
1851
1852         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1853
1854         do {
1855                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1856                 buffer = &tx_queue->buffer[write_ptr];
1857                 txd = efx_tx_desc(tx_queue, write_ptr);
1858                 ++tx_queue->write_count;
1859
1860                 /* Create TX descriptor ring entry */
1861                 if (buffer->flags & EFX_TX_BUF_OPTION) {
1862                         *txd = buffer->option;
1863                 } else {
1864                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1865                         EFX_POPULATE_QWORD_3(
1866                                 *txd,
1867                                 ESF_DZ_TX_KER_CONT,
1868                                 buffer->flags & EFX_TX_BUF_CONT,
1869                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1870                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1871                 }
1872         } while (tx_queue->write_count != tx_queue->insert_count);
1873
1874         wmb(); /* Ensure descriptors are written before they are fetched */
1875
1876         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1877                 txd = efx_tx_desc(tx_queue,
1878                                   old_write_count & tx_queue->ptr_mask);
1879                 efx_ef10_push_tx_desc(tx_queue, txd);
1880                 ++tx_queue->pushes;
1881         } else {
1882                 efx_ef10_notify_tx_desc(tx_queue);
1883         }
1884 }
1885
1886 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1887                                       bool exclusive, unsigned *context_size)
1888 {
1889         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1890         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1891         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1892         size_t outlen;
1893         int rc;
1894         u32 alloc_type = exclusive ?
1895                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1896                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1897         unsigned rss_spread = exclusive ?
1898                                 efx->rss_spread :
1899                                 min(rounddown_pow_of_two(efx->rss_spread),
1900                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1901
1902         if (!exclusive && rss_spread == 1) {
1903                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1904                 if (context_size)
1905                         *context_size = 1;
1906                 return 0;
1907         }
1908
1909         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1910                        nic_data->vport_id);
1911         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1912         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
1913
1914         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1915                 outbuf, sizeof(outbuf), &outlen);
1916         if (rc != 0)
1917                 return rc;
1918
1919         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1920                 return -EIO;
1921
1922         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1923
1924         if (context_size)
1925                 *context_size = rss_spread;
1926
1927         return 0;
1928 }
1929
1930 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1931 {
1932         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1933         int rc;
1934
1935         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1936                        context);
1937
1938         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1939                             NULL, 0, NULL);
1940         WARN_ON(rc != 0);
1941 }
1942
1943 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1944                                        const u32 *rx_indir_table)
1945 {
1946         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1947         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1948         int i, rc;
1949
1950         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1951                        context);
1952         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1953                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1954
1955         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1956                 MCDI_PTR(tablebuf,
1957                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1958                                 (u8) rx_indir_table[i];
1959
1960         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1961                           sizeof(tablebuf), NULL, 0, NULL);
1962         if (rc != 0)
1963                 return rc;
1964
1965         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1966                        context);
1967         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1968                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1969         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1970                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1971                         efx->rx_hash_key[i];
1972
1973         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1974                             sizeof(keybuf), NULL, 0, NULL);
1975 }
1976
1977 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1978 {
1979         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1980
1981         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1982                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1983         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1984 }
1985
1986 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1987                                               unsigned *context_size)
1988 {
1989         u32 new_rx_rss_context;
1990         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1991         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1992                                             false, context_size);
1993
1994         if (rc != 0)
1995                 return rc;
1996
1997         nic_data->rx_rss_context = new_rx_rss_context;
1998         nic_data->rx_rss_context_exclusive = false;
1999         efx_set_default_rx_indir_table(efx);
2000         return 0;
2001 }
2002
2003 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2004                                                  const u32 *rx_indir_table)
2005 {
2006         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2007         int rc;
2008         u32 new_rx_rss_context;
2009
2010         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2011             !nic_data->rx_rss_context_exclusive) {
2012                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2013                                                 true, NULL);
2014                 if (rc == -EOPNOTSUPP)
2015                         return rc;
2016                 else if (rc != 0)
2017                         goto fail1;
2018         } else {
2019                 new_rx_rss_context = nic_data->rx_rss_context;
2020         }
2021
2022         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2023                                          rx_indir_table);
2024         if (rc != 0)
2025                 goto fail2;
2026
2027         if (nic_data->rx_rss_context != new_rx_rss_context)
2028                 efx_ef10_rx_free_indir_table(efx);
2029         nic_data->rx_rss_context = new_rx_rss_context;
2030         nic_data->rx_rss_context_exclusive = true;
2031         if (rx_indir_table != efx->rx_indir_table)
2032                 memcpy(efx->rx_indir_table, rx_indir_table,
2033                        sizeof(efx->rx_indir_table));
2034         return 0;
2035
2036 fail2:
2037         if (new_rx_rss_context != nic_data->rx_rss_context)
2038                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2039 fail1:
2040         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2041         return rc;
2042 }
2043
2044 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2045                                           const u32 *rx_indir_table)
2046 {
2047         int rc;
2048
2049         if (efx->rss_spread == 1)
2050                 return 0;
2051
2052         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2053
2054         if (rc == -ENOBUFS && !user) {
2055                 unsigned context_size;
2056                 bool mismatch = false;
2057                 size_t i;
2058
2059                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2060                      i++)
2061                         mismatch = rx_indir_table[i] !=
2062                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2063
2064                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2065                 if (rc == 0) {
2066                         if (context_size != efx->rss_spread)
2067                                 netif_warn(efx, probe, efx->net_dev,
2068                                            "Could not allocate an exclusive RSS"
2069                                            " context; allocated a shared one of"
2070                                            " different size."
2071                                            " Wanted %u, got %u.\n",
2072                                            efx->rss_spread, context_size);
2073                         else if (mismatch)
2074                                 netif_warn(efx, probe, efx->net_dev,
2075                                            "Could not allocate an exclusive RSS"
2076                                            " context; allocated a shared one but"
2077                                            " could not apply custom"
2078                                            " indirection.\n");
2079                         else
2080                                 netif_info(efx, probe, efx->net_dev,
2081                                            "Could not allocate an exclusive RSS"
2082                                            " context; allocated a shared one.\n");
2083                 }
2084         }
2085         return rc;
2086 }
2087
2088 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2089                                           const u32 *rx_indir_table
2090                                           __attribute__ ((unused)))
2091 {
2092         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2093
2094         if (user)
2095                 return -EOPNOTSUPP;
2096         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2097                 return 0;
2098         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2099 }
2100
2101 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2102 {
2103         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2104                                     (rx_queue->ptr_mask + 1) *
2105                                     sizeof(efx_qword_t),
2106                                     GFP_KERNEL);
2107 }
2108
2109 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2110 {
2111         MCDI_DECLARE_BUF(inbuf,
2112                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2113                                                 EFX_BUF_SIZE));
2114         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2115         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2116         struct efx_nic *efx = rx_queue->efx;
2117         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2118         size_t inlen;
2119         dma_addr_t dma_addr;
2120         int rc;
2121         int i;
2122         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2123
2124         rx_queue->scatter_n = 0;
2125         rx_queue->scatter_len = 0;
2126
2127         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2128         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2129         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2130         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2131                        efx_rx_queue_index(rx_queue));
2132         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2133                               INIT_RXQ_IN_FLAG_PREFIX, 1,
2134                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2135         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2136         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2137
2138         dma_addr = rx_queue->rxd.buf.dma_addr;
2139
2140         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2141                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2142
2143         for (i = 0; i < entries; ++i) {
2144                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2145                 dma_addr += EFX_BUF_SIZE;
2146         }
2147
2148         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2149
2150         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2151                           NULL, 0, NULL);
2152         if (rc)
2153                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2154                             efx_rx_queue_index(rx_queue));
2155 }
2156
2157 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2158 {
2159         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2160         MCDI_DECLARE_BUF_ERR(outbuf);
2161         struct efx_nic *efx = rx_queue->efx;
2162         size_t outlen;
2163         int rc;
2164
2165         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2166                        efx_rx_queue_index(rx_queue));
2167
2168         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2169                           outbuf, sizeof(outbuf), &outlen);
2170
2171         if (rc && rc != -EALREADY)
2172                 goto fail;
2173
2174         return;
2175
2176 fail:
2177         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2178                                outbuf, outlen, rc);
2179 }
2180
2181 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2182 {
2183         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2184 }
2185
2186 /* This creates an entry in the RX descriptor queue */
2187 static inline void
2188 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2189 {
2190         struct efx_rx_buffer *rx_buf;
2191         efx_qword_t *rxd;
2192
2193         rxd = efx_rx_desc(rx_queue, index);
2194         rx_buf = efx_rx_buffer(rx_queue, index);
2195         EFX_POPULATE_QWORD_2(*rxd,
2196                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2197                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2198 }
2199
2200 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2201 {
2202         struct efx_nic *efx = rx_queue->efx;
2203         unsigned int write_count;
2204         efx_dword_t reg;
2205
2206         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2207         write_count = rx_queue->added_count & ~7;
2208         if (rx_queue->notified_count == write_count)
2209                 return;
2210
2211         do
2212                 efx_ef10_build_rx_desc(
2213                         rx_queue,
2214                         rx_queue->notified_count & rx_queue->ptr_mask);
2215         while (++rx_queue->notified_count != write_count);
2216
2217         wmb();
2218         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2219                              write_count & rx_queue->ptr_mask);
2220         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2221                         efx_rx_queue_index(rx_queue));
2222 }
2223
2224 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2225
2226 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2227 {
2228         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2229         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2230         efx_qword_t event;
2231
2232         EFX_POPULATE_QWORD_2(event,
2233                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2234                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2235
2236         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2237
2238         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2239          * already swapped the data to little-endian order.
2240          */
2241         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2242                sizeof(efx_qword_t));
2243
2244         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2245                            inbuf, sizeof(inbuf), 0,
2246                            efx_ef10_rx_defer_refill_complete, 0);
2247 }
2248
2249 static void
2250 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2251                                   int rc, efx_dword_t *outbuf,
2252                                   size_t outlen_actual)
2253 {
2254         /* nothing to do */
2255 }
2256
2257 static int efx_ef10_ev_probe(struct efx_channel *channel)
2258 {
2259         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2260                                     (channel->eventq_mask + 1) *
2261                                     sizeof(efx_qword_t),
2262                                     GFP_KERNEL);
2263 }
2264
2265 static void efx_ef10_ev_fini(struct efx_channel *channel)
2266 {
2267         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2268         MCDI_DECLARE_BUF_ERR(outbuf);
2269         struct efx_nic *efx = channel->efx;
2270         size_t outlen;
2271         int rc;
2272
2273         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2274
2275         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2276                           outbuf, sizeof(outbuf), &outlen);
2277
2278         if (rc && rc != -EALREADY)
2279                 goto fail;
2280
2281         return;
2282
2283 fail:
2284         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2285                                outbuf, outlen, rc);
2286 }
2287
2288 static int efx_ef10_ev_init(struct efx_channel *channel)
2289 {
2290         MCDI_DECLARE_BUF(inbuf,
2291                          MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2292                                                 EFX_BUF_SIZE));
2293         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2294         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2295         struct efx_nic *efx = channel->efx;
2296         struct efx_ef10_nic_data *nic_data;
2297         bool supports_rx_merge;
2298         size_t inlen, outlen;
2299         unsigned int enabled, implemented;
2300         dma_addr_t dma_addr;
2301         int rc;
2302         int i;
2303
2304         nic_data = efx->nic_data;
2305         supports_rx_merge =
2306                 !!(nic_data->datapath_caps &
2307                    1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2308
2309         /* Fill event queue with all ones (i.e. empty events) */
2310         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2311
2312         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2313         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2314         /* INIT_EVQ expects index in vector table, not absolute */
2315         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2316         MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2317                               INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2318                               INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2319                               INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2320                               INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2321         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2322                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2323         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2324         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2325         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2326                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2327         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2328
2329         dma_addr = channel->eventq.buf.dma_addr;
2330         for (i = 0; i < entries; ++i) {
2331                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2332                 dma_addr += EFX_BUF_SIZE;
2333         }
2334
2335         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2336
2337         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2338                           outbuf, sizeof(outbuf), &outlen);
2339         /* IRQ return is ignored */
2340         if (channel->channel || rc)
2341                 return rc;
2342
2343         /* Successfully created event queue on channel 0 */
2344         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2345         if (rc == -ENOSYS) {
2346                 /* GET_WORKAROUNDS was implemented before the bug26807
2347                  * workaround, thus the latter must be unavailable in this fw
2348                  */
2349                 nic_data->workaround_26807 = false;
2350                 rc = 0;
2351         } else if (rc) {
2352                 goto fail;
2353         } else {
2354                 nic_data->workaround_26807 =
2355                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2356
2357                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2358                     !nic_data->workaround_26807) {
2359                         unsigned int flags;
2360
2361                         rc = efx_mcdi_set_workaround(efx,
2362                                                      MC_CMD_WORKAROUND_BUG26807,
2363                                                      true, &flags);
2364
2365                         if (!rc) {
2366                                 if (flags &
2367                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2368                                         netif_info(efx, drv, efx->net_dev,
2369                                                    "other functions on NIC have been reset\n");
2370                                         /* MC's boot count has incremented */
2371                                         ++nic_data->warm_boot_count;
2372                                 }
2373                                 nic_data->workaround_26807 = true;
2374                         } else if (rc == -EPERM) {
2375                                 rc = 0;
2376                         }
2377                 }
2378         }
2379
2380         if (!rc)
2381                 return 0;
2382
2383 fail:
2384         efx_ef10_ev_fini(channel);
2385         return rc;
2386 }
2387
2388 static void efx_ef10_ev_remove(struct efx_channel *channel)
2389 {
2390         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2391 }
2392
2393 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2394                                            unsigned int rx_queue_label)
2395 {
2396         struct efx_nic *efx = rx_queue->efx;
2397
2398         netif_info(efx, hw, efx->net_dev,
2399                    "rx event arrived on queue %d labeled as queue %u\n",
2400                    efx_rx_queue_index(rx_queue), rx_queue_label);
2401
2402         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2403 }
2404
2405 static void
2406 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2407                              unsigned int actual, unsigned int expected)
2408 {
2409         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2410         struct efx_nic *efx = rx_queue->efx;
2411
2412         netif_info(efx, hw, efx->net_dev,
2413                    "dropped %d events (index=%d expected=%d)\n",
2414                    dropped, actual, expected);
2415
2416         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2417 }
2418
2419 /* partially received RX was aborted. clean up. */
2420 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2421 {
2422         unsigned int rx_desc_ptr;
2423
2424         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2425                   "scattered RX aborted (dropping %u buffers)\n",
2426                   rx_queue->scatter_n);
2427
2428         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2429
2430         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2431                       0, EFX_RX_PKT_DISCARD);
2432
2433         rx_queue->removed_count += rx_queue->scatter_n;
2434         rx_queue->scatter_n = 0;
2435         rx_queue->scatter_len = 0;
2436         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2437 }
2438
2439 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2440                                     const efx_qword_t *event)
2441 {
2442         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2443         unsigned int n_descs, n_packets, i;
2444         struct efx_nic *efx = channel->efx;
2445         struct efx_rx_queue *rx_queue;
2446         bool rx_cont;
2447         u16 flags = 0;
2448
2449         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2450                 return 0;
2451
2452         /* Basic packet information */
2453         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2454         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2455         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2456         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2457         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2458
2459         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2460                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2461                             EFX_QWORD_FMT "\n",
2462                             EFX_QWORD_VAL(*event));
2463
2464         rx_queue = efx_channel_get_rx_queue(channel);
2465
2466         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2467                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2468
2469         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2470                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2471
2472         if (n_descs != rx_queue->scatter_n + 1) {
2473                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2474
2475                 /* detect rx abort */
2476                 if (unlikely(n_descs == rx_queue->scatter_n)) {
2477                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2478                                 netdev_WARN(efx->net_dev,
2479                                             "invalid RX abort: scatter_n=%u event="
2480                                             EFX_QWORD_FMT "\n",
2481                                             rx_queue->scatter_n,
2482                                             EFX_QWORD_VAL(*event));
2483                         efx_ef10_handle_rx_abort(rx_queue);
2484                         return 0;
2485                 }
2486
2487                 /* Check that RX completion merging is valid, i.e.
2488                  * the current firmware supports it and this is a
2489                  * non-scattered packet.
2490                  */
2491                 if (!(nic_data->datapath_caps &
2492                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2493                     rx_queue->scatter_n != 0 || rx_cont) {
2494                         efx_ef10_handle_rx_bad_lbits(
2495                                 rx_queue, next_ptr_lbits,
2496                                 (rx_queue->removed_count +
2497                                  rx_queue->scatter_n + 1) &
2498                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2499                         return 0;
2500                 }
2501
2502                 /* Merged completion for multiple non-scattered packets */
2503                 rx_queue->scatter_n = 1;
2504                 rx_queue->scatter_len = 0;
2505                 n_packets = n_descs;
2506                 ++channel->n_rx_merge_events;
2507                 channel->n_rx_merge_packets += n_packets;
2508                 flags |= EFX_RX_PKT_PREFIX_LEN;
2509         } else {
2510                 ++rx_queue->scatter_n;
2511                 rx_queue->scatter_len += rx_bytes;
2512                 if (rx_cont)
2513                         return 0;
2514                 n_packets = 1;
2515         }
2516
2517         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2518                 flags |= EFX_RX_PKT_DISCARD;
2519
2520         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2521                 channel->n_rx_ip_hdr_chksum_err += n_packets;
2522         } else if (unlikely(EFX_QWORD_FIELD(*event,
2523                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2524                 channel->n_rx_tcp_udp_chksum_err += n_packets;
2525         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2526                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2527                 flags |= EFX_RX_PKT_CSUMMED;
2528         }
2529
2530         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2531                 flags |= EFX_RX_PKT_TCP;
2532
2533         channel->irq_mod_score += 2 * n_packets;
2534
2535         /* Handle received packet(s) */
2536         for (i = 0; i < n_packets; i++) {
2537                 efx_rx_packet(rx_queue,
2538                               rx_queue->removed_count & rx_queue->ptr_mask,
2539                               rx_queue->scatter_n, rx_queue->scatter_len,
2540                               flags);
2541                 rx_queue->removed_count += rx_queue->scatter_n;
2542         }
2543
2544         rx_queue->scatter_n = 0;
2545         rx_queue->scatter_len = 0;
2546
2547         return n_packets;
2548 }
2549
2550 static int
2551 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2552 {
2553         struct efx_nic *efx = channel->efx;
2554         struct efx_tx_queue *tx_queue;
2555         unsigned int tx_ev_desc_ptr;
2556         unsigned int tx_ev_q_label;
2557         int tx_descs = 0;
2558
2559         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2560                 return 0;
2561
2562         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2563                 return 0;
2564
2565         /* Transmit completion */
2566         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2567         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2568         tx_queue = efx_channel_get_tx_queue(channel,
2569                                             tx_ev_q_label % EFX_TXQ_TYPES);
2570         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2571                     tx_queue->ptr_mask);
2572         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2573
2574         return tx_descs;
2575 }
2576
2577 static void
2578 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2579 {
2580         struct efx_nic *efx = channel->efx;
2581         int subcode;
2582
2583         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2584
2585         switch (subcode) {
2586         case ESE_DZ_DRV_TIMER_EV:
2587         case ESE_DZ_DRV_WAKE_UP_EV:
2588                 break;
2589         case ESE_DZ_DRV_START_UP_EV:
2590                 /* event queue init complete. ok. */
2591                 break;
2592         default:
2593                 netif_err(efx, hw, efx->net_dev,
2594                           "channel %d unknown driver event type %d"
2595                           " (data " EFX_QWORD_FMT ")\n",
2596                           channel->channel, subcode,
2597                           EFX_QWORD_VAL(*event));
2598
2599         }
2600 }
2601
2602 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2603                                                    efx_qword_t *event)
2604 {
2605         struct efx_nic *efx = channel->efx;
2606         u32 subcode;
2607
2608         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2609
2610         switch (subcode) {
2611         case EFX_EF10_TEST:
2612                 channel->event_test_cpu = raw_smp_processor_id();
2613                 break;
2614         case EFX_EF10_REFILL:
2615                 /* The queue must be empty, so we won't receive any rx
2616                  * events, so efx_process_channel() won't refill the
2617                  * queue. Refill it here
2618                  */
2619                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2620                 break;
2621         default:
2622                 netif_err(efx, hw, efx->net_dev,
2623                           "channel %d unknown driver event type %u"
2624                           " (data " EFX_QWORD_FMT ")\n",
2625                           channel->channel, (unsigned) subcode,
2626                           EFX_QWORD_VAL(*event));
2627         }
2628 }
2629
2630 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2631 {
2632         struct efx_nic *efx = channel->efx;
2633         efx_qword_t event, *p_event;
2634         unsigned int read_ptr;
2635         int ev_code;
2636         int tx_descs = 0;
2637         int spent = 0;
2638
2639         if (quota <= 0)
2640                 return spent;
2641
2642         read_ptr = channel->eventq_read_ptr;
2643
2644         for (;;) {
2645                 p_event = efx_event(channel, read_ptr);
2646                 event = *p_event;
2647
2648                 if (!efx_event_present(&event))
2649                         break;
2650
2651                 EFX_SET_QWORD(*p_event);
2652
2653                 ++read_ptr;
2654
2655                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2656
2657                 netif_vdbg(efx, drv, efx->net_dev,
2658                            "processing event on %d " EFX_QWORD_FMT "\n",
2659                            channel->channel, EFX_QWORD_VAL(event));
2660
2661                 switch (ev_code) {
2662                 case ESE_DZ_EV_CODE_MCDI_EV:
2663                         efx_mcdi_process_event(channel, &event);
2664                         break;
2665                 case ESE_DZ_EV_CODE_RX_EV:
2666                         spent += efx_ef10_handle_rx_event(channel, &event);
2667                         if (spent >= quota) {
2668                                 /* XXX can we split a merged event to
2669                                  * avoid going over-quota?
2670                                  */
2671                                 spent = quota;
2672                                 goto out;
2673                         }
2674                         break;
2675                 case ESE_DZ_EV_CODE_TX_EV:
2676                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
2677                         if (tx_descs > efx->txq_entries) {
2678                                 spent = quota;
2679                                 goto out;
2680                         } else if (++spent == quota) {
2681                                 goto out;
2682                         }
2683                         break;
2684                 case ESE_DZ_EV_CODE_DRIVER_EV:
2685                         efx_ef10_handle_driver_event(channel, &event);
2686                         if (++spent == quota)
2687                                 goto out;
2688                         break;
2689                 case EFX_EF10_DRVGEN_EV:
2690                         efx_ef10_handle_driver_generated_event(channel, &event);
2691                         break;
2692                 default:
2693                         netif_err(efx, hw, efx->net_dev,
2694                                   "channel %d unknown event type %d"
2695                                   " (data " EFX_QWORD_FMT ")\n",
2696                                   channel->channel, ev_code,
2697                                   EFX_QWORD_VAL(event));
2698                 }
2699         }
2700
2701 out:
2702         channel->eventq_read_ptr = read_ptr;
2703         return spent;
2704 }
2705
2706 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2707 {
2708         struct efx_nic *efx = channel->efx;
2709         efx_dword_t rptr;
2710
2711         if (EFX_EF10_WORKAROUND_35388(efx)) {
2712                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2713                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2714                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2715                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2716
2717                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2718                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2719                                      ERF_DD_EVQ_IND_RPTR,
2720                                      (channel->eventq_read_ptr &
2721                                       channel->eventq_mask) >>
2722                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
2723                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2724                                 channel->channel);
2725                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2726                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2727                                      ERF_DD_EVQ_IND_RPTR,
2728                                      channel->eventq_read_ptr &
2729                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2730                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2731                                 channel->channel);
2732         } else {
2733                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2734                                      channel->eventq_read_ptr &
2735                                      channel->eventq_mask);
2736                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2737         }
2738 }
2739
2740 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2741 {
2742         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2743         struct efx_nic *efx = channel->efx;
2744         efx_qword_t event;
2745         int rc;
2746
2747         EFX_POPULATE_QWORD_2(event,
2748                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2749                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
2750
2751         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2752
2753         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2754          * already swapped the data to little-endian order.
2755          */
2756         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2757                sizeof(efx_qword_t));
2758
2759         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2760                           NULL, 0, NULL);
2761         if (rc != 0)
2762                 goto fail;
2763
2764         return;
2765
2766 fail:
2767         WARN_ON(true);
2768         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2769 }
2770
2771 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2772 {
2773         if (atomic_dec_and_test(&efx->active_queues))
2774                 wake_up(&efx->flush_wq);
2775
2776         WARN_ON(atomic_read(&efx->active_queues) < 0);
2777 }
2778
2779 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2780 {
2781         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2782         struct efx_channel *channel;
2783         struct efx_tx_queue *tx_queue;
2784         struct efx_rx_queue *rx_queue;
2785         int pending;
2786
2787         /* If the MC has just rebooted, the TX/RX queues will have already been
2788          * torn down, but efx->active_queues needs to be set to zero.
2789          */
2790         if (nic_data->must_realloc_vis) {
2791                 atomic_set(&efx->active_queues, 0);
2792                 return 0;
2793         }
2794
2795         /* Do not attempt to write to the NIC during EEH recovery */
2796         if (efx->state != STATE_RECOVERY) {
2797                 efx_for_each_channel(channel, efx) {
2798                         efx_for_each_channel_rx_queue(rx_queue, channel)
2799                                 efx_ef10_rx_fini(rx_queue);
2800                         efx_for_each_channel_tx_queue(tx_queue, channel)
2801                                 efx_ef10_tx_fini(tx_queue);
2802                 }
2803
2804                 wait_event_timeout(efx->flush_wq,
2805                                    atomic_read(&efx->active_queues) == 0,
2806                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2807                 pending = atomic_read(&efx->active_queues);
2808                 if (pending) {
2809                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2810                                   pending);
2811                         return -ETIMEDOUT;
2812                 }
2813         }
2814
2815         return 0;
2816 }
2817
2818 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2819 {
2820         atomic_set(&efx->active_queues, 0);
2821 }
2822
2823 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2824                                   const struct efx_filter_spec *right)
2825 {
2826         if ((left->match_flags ^ right->match_flags) |
2827             ((left->flags ^ right->flags) &
2828              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2829                 return false;
2830
2831         return memcmp(&left->outer_vid, &right->outer_vid,
2832                       sizeof(struct efx_filter_spec) -
2833                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
2834 }
2835
2836 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2837 {
2838         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2839         return jhash2((const u32 *)&spec->outer_vid,
2840                       (sizeof(struct efx_filter_spec) -
2841                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
2842                       0);
2843         /* XXX should we randomise the initval? */
2844 }
2845
2846 /* Decide whether a filter should be exclusive or else should allow
2847  * delivery to additional recipients.  Currently we decide that
2848  * filters for specific local unicast MAC and IP addresses are
2849  * exclusive.
2850  */
2851 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2852 {
2853         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2854             !is_multicast_ether_addr(spec->loc_mac))
2855                 return true;
2856
2857         if ((spec->match_flags &
2858              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2859             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2860                 if (spec->ether_type == htons(ETH_P_IP) &&
2861                     !ipv4_is_multicast(spec->loc_host[0]))
2862                         return true;
2863                 if (spec->ether_type == htons(ETH_P_IPV6) &&
2864                     ((const u8 *)spec->loc_host)[0] != 0xff)
2865                         return true;
2866         }
2867
2868         return false;
2869 }
2870
2871 static struct efx_filter_spec *
2872 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2873                            unsigned int filter_idx)
2874 {
2875         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2876                                           ~EFX_EF10_FILTER_FLAGS);
2877 }
2878
2879 static unsigned int
2880 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2881                            unsigned int filter_idx)
2882 {
2883         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2884 }
2885
2886 static void
2887 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2888                           unsigned int filter_idx,
2889                           const struct efx_filter_spec *spec,
2890                           unsigned int flags)
2891 {
2892         table->entry[filter_idx].spec = (unsigned long)spec | flags;
2893 }
2894
2895 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2896                                       const struct efx_filter_spec *spec,
2897                                       efx_dword_t *inbuf, u64 handle,
2898                                       bool replacing)
2899 {
2900         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2901
2902         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2903
2904         if (replacing) {
2905                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2906                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
2907                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2908         } else {
2909                 u32 match_fields = 0;
2910
2911                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2912                                efx_ef10_filter_is_exclusive(spec) ?
2913                                MC_CMD_FILTER_OP_IN_OP_INSERT :
2914                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2915
2916                 /* Convert match flags and values.  Unlike almost
2917                  * everything else in MCDI, these fields are in
2918                  * network byte order.
2919                  */
2920                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2921                         match_fields |=
2922                                 is_multicast_ether_addr(spec->loc_mac) ?
2923                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2924                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2925 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
2926                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
2927                         match_fields |=                                      \
2928                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
2929                                 mcdi_field ## _LBN;                          \
2930                         BUILD_BUG_ON(                                        \
2931                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2932                                 sizeof(spec->gen_field));                    \
2933                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2934                                &spec->gen_field, sizeof(spec->gen_field));   \
2935                 }
2936                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2937                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2938                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2939                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2940                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2941                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2942                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2943                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2944                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2945                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2946 #undef COPY_FIELD
2947                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2948                                match_fields);
2949         }
2950
2951         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
2952         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2953                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2954                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2955                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2956         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
2957         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2958                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2959         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2960                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2961                        0 : spec->dmaq_id);
2962         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2963                        (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2964                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2965                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2966         if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2967                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2968                                spec->rss_context !=
2969                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2970                                spec->rss_context : nic_data->rx_rss_context);
2971 }
2972
2973 static int efx_ef10_filter_push(struct efx_nic *efx,
2974                                 const struct efx_filter_spec *spec,
2975                                 u64 *handle, bool replacing)
2976 {
2977         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2978         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2979         int rc;
2980
2981         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2982         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2983                           outbuf, sizeof(outbuf), NULL);
2984         if (rc == 0)
2985                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2986         if (rc == -ENOSPC)
2987                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2988         return rc;
2989 }
2990
2991 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2992                                         enum efx_filter_match_flags match_flags)
2993 {
2994         unsigned int match_pri;
2995
2996         for (match_pri = 0;
2997              match_pri < table->rx_match_count;
2998              match_pri++)
2999                 if (table->rx_match_flags[match_pri] == match_flags)
3000                         return match_pri;
3001
3002         return -EPROTONOSUPPORT;
3003 }
3004
3005 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3006                                   struct efx_filter_spec *spec,
3007                                   bool replace_equal)
3008 {
3009         struct efx_ef10_filter_table *table = efx->filter_state;
3010         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3011         struct efx_filter_spec *saved_spec;
3012         unsigned int match_pri, hash;
3013         unsigned int priv_flags;
3014         bool replacing = false;
3015         int ins_index = -1;
3016         DEFINE_WAIT(wait);
3017         bool is_mc_recip;
3018         s32 rc;
3019
3020         /* For now, only support RX filters */
3021         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3022             EFX_FILTER_FLAG_RX)
3023                 return -EINVAL;
3024
3025         rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
3026         if (rc < 0)
3027                 return rc;
3028         match_pri = rc;
3029
3030         hash = efx_ef10_filter_hash(spec);
3031         is_mc_recip = efx_filter_is_mc_recipient(spec);
3032         if (is_mc_recip)
3033                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3034
3035         /* Find any existing filters with the same match tuple or
3036          * else a free slot to insert at.  If any of them are busy,
3037          * we have to wait and retry.
3038          */
3039         for (;;) {
3040                 unsigned int depth = 1;
3041                 unsigned int i;
3042
3043                 spin_lock_bh(&efx->filter_lock);
3044
3045                 for (;;) {
3046                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3047                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3048
3049                         if (!saved_spec) {
3050                                 if (ins_index < 0)
3051                                         ins_index = i;
3052                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3053                                 if (table->entry[i].spec &
3054                                     EFX_EF10_FILTER_FLAG_BUSY)
3055                                         break;
3056                                 if (spec->priority < saved_spec->priority &&
3057                                     spec->priority != EFX_FILTER_PRI_AUTO) {
3058                                         rc = -EPERM;
3059                                         goto out_unlock;
3060                                 }
3061                                 if (!is_mc_recip) {
3062                                         /* This is the only one */
3063                                         if (spec->priority ==
3064                                             saved_spec->priority &&
3065                                             !replace_equal) {
3066                                                 rc = -EEXIST;
3067                                                 goto out_unlock;
3068                                         }
3069                                         ins_index = i;
3070                                         goto found;
3071                                 } else if (spec->priority >
3072                                            saved_spec->priority ||
3073                                            (spec->priority ==
3074                                             saved_spec->priority &&
3075                                             replace_equal)) {
3076                                         if (ins_index < 0)
3077                                                 ins_index = i;
3078                                         else
3079                                                 __set_bit(depth, mc_rem_map);
3080                                 }
3081                         }
3082
3083                         /* Once we reach the maximum search depth, use
3084                          * the first suitable slot or return -EBUSY if
3085                          * there was none
3086                          */
3087                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3088                                 if (ins_index < 0) {
3089                                         rc = -EBUSY;
3090                                         goto out_unlock;
3091                                 }
3092                                 goto found;
3093                         }
3094
3095                         ++depth;
3096                 }
3097
3098                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3099                 spin_unlock_bh(&efx->filter_lock);
3100                 schedule();
3101         }
3102
3103 found:
3104         /* Create a software table entry if necessary, and mark it
3105          * busy.  We might yet fail to insert, but any attempt to
3106          * insert a conflicting filter while we're waiting for the
3107          * firmware must find the busy entry.
3108          */
3109         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3110         if (saved_spec) {
3111                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3112                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3113                         /* Just make sure it won't be removed */
3114                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3115                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3116                         table->entry[ins_index].spec &=
3117                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3118                         rc = ins_index;
3119                         goto out_unlock;
3120                 }
3121                 replacing = true;
3122                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3123         } else {
3124                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3125                 if (!saved_spec) {
3126                         rc = -ENOMEM;
3127                         goto out_unlock;
3128                 }
3129                 *saved_spec = *spec;
3130                 priv_flags = 0;
3131         }
3132         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3133                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3134
3135         /* Mark lower-priority multicast recipients busy prior to removal */
3136         if (is_mc_recip) {
3137                 unsigned int depth, i;
3138
3139                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3140                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3141                         if (test_bit(depth, mc_rem_map))
3142                                 table->entry[i].spec |=
3143                                         EFX_EF10_FILTER_FLAG_BUSY;
3144                 }
3145         }
3146
3147         spin_unlock_bh(&efx->filter_lock);
3148
3149         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3150                                   replacing);
3151
3152         /* Finalise the software table entry */
3153         spin_lock_bh(&efx->filter_lock);
3154         if (rc == 0) {
3155                 if (replacing) {
3156                         /* Update the fields that may differ */
3157                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3158                                 saved_spec->flags |=
3159                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
3160                         saved_spec->priority = spec->priority;
3161                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3162                         saved_spec->flags |= spec->flags;
3163                         saved_spec->rss_context = spec->rss_context;
3164                         saved_spec->dmaq_id = spec->dmaq_id;
3165                 }
3166         } else if (!replacing) {
3167                 kfree(saved_spec);
3168                 saved_spec = NULL;
3169         }
3170         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3171
3172         /* Remove and finalise entries for lower-priority multicast
3173          * recipients
3174          */
3175         if (is_mc_recip) {
3176                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3177                 unsigned int depth, i;
3178
3179                 memset(inbuf, 0, sizeof(inbuf));
3180
3181                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3182                         if (!test_bit(depth, mc_rem_map))
3183                                 continue;
3184
3185                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3186                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3187                         priv_flags = efx_ef10_filter_entry_flags(table, i);
3188
3189                         if (rc == 0) {
3190                                 spin_unlock_bh(&efx->filter_lock);
3191                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3192                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3193                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3194                                                table->entry[i].handle);
3195                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3196                                                   inbuf, sizeof(inbuf),
3197                                                   NULL, 0, NULL);
3198                                 spin_lock_bh(&efx->filter_lock);
3199                         }
3200
3201                         if (rc == 0) {
3202                                 kfree(saved_spec);
3203                                 saved_spec = NULL;
3204                                 priv_flags = 0;
3205                         } else {
3206                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3207                         }
3208                         efx_ef10_filter_set_entry(table, i, saved_spec,
3209                                                   priv_flags);
3210                 }
3211         }
3212
3213         /* If successful, return the inserted filter ID */
3214         if (rc == 0)
3215                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3216
3217         wake_up_all(&table->waitq);
3218 out_unlock:
3219         spin_unlock_bh(&efx->filter_lock);
3220         finish_wait(&table->waitq, &wait);
3221         return rc;
3222 }
3223
3224 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3225 {
3226         /* no need to do anything here on EF10 */
3227 }
3228
3229 /* Remove a filter.
3230  * If !by_index, remove by ID
3231  * If by_index, remove by index
3232  * Filter ID may come from userland and must be range-checked.
3233  */
3234 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3235                                            unsigned int priority_mask,
3236                                            u32 filter_id, bool by_index)
3237 {
3238         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3239         struct efx_ef10_filter_table *table = efx->filter_state;
3240         MCDI_DECLARE_BUF(inbuf,
3241                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3242                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3243         struct efx_filter_spec *spec;
3244         DEFINE_WAIT(wait);
3245         int rc;
3246
3247         /* Find the software table entry and mark it busy.  Don't
3248          * remove it yet; any attempt to update while we're waiting
3249          * for the firmware must find the busy entry.
3250          */
3251         for (;;) {
3252                 spin_lock_bh(&efx->filter_lock);
3253                 if (!(table->entry[filter_idx].spec &
3254                       EFX_EF10_FILTER_FLAG_BUSY))
3255                         break;
3256                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3257                 spin_unlock_bh(&efx->filter_lock);
3258                 schedule();
3259         }
3260
3261         spec = efx_ef10_filter_entry_spec(table, filter_idx);
3262         if (!spec ||
3263             (!by_index &&
3264              efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3265              filter_id / HUNT_FILTER_TBL_ROWS)) {
3266                 rc = -ENOENT;
3267                 goto out_unlock;
3268         }
3269
3270         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3271             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3272                 /* Just remove flags */
3273                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3274                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3275                 rc = 0;
3276                 goto out_unlock;
3277         }
3278
3279         if (!(priority_mask & (1U << spec->priority))) {
3280                 rc = -ENOENT;
3281                 goto out_unlock;
3282         }
3283
3284         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3285         spin_unlock_bh(&efx->filter_lock);
3286
3287         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3288                 /* Reset to an automatic filter */
3289
3290                 struct efx_filter_spec new_spec = *spec;
3291
3292                 new_spec.priority = EFX_FILTER_PRI_AUTO;
3293                 new_spec.flags = (EFX_FILTER_FLAG_RX |
3294                                   EFX_FILTER_FLAG_RX_RSS);
3295                 new_spec.dmaq_id = 0;
3296                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3297                 rc = efx_ef10_filter_push(efx, &new_spec,
3298                                           &table->entry[filter_idx].handle,
3299                                           true);
3300
3301                 spin_lock_bh(&efx->filter_lock);
3302                 if (rc == 0)
3303                         *spec = new_spec;
3304         } else {
3305                 /* Really remove the filter */
3306
3307                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3308                                efx_ef10_filter_is_exclusive(spec) ?
3309                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3310                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3311                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3312                                table->entry[filter_idx].handle);
3313                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3314                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
3315
3316                 spin_lock_bh(&efx->filter_lock);
3317                 if (rc == 0) {
3318                         kfree(spec);
3319                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3320                 }
3321         }
3322
3323         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3324         wake_up_all(&table->waitq);
3325 out_unlock:
3326         spin_unlock_bh(&efx->filter_lock);
3327         finish_wait(&table->waitq, &wait);
3328         return rc;
3329 }
3330
3331 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3332                                        enum efx_filter_priority priority,
3333                                        u32 filter_id)
3334 {
3335         return efx_ef10_filter_remove_internal(efx, 1U << priority,
3336                                                filter_id, false);
3337 }
3338
3339 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3340 {
3341         return filter_id % HUNT_FILTER_TBL_ROWS;
3342 }
3343
3344 static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3345                                          enum efx_filter_priority priority,
3346                                          u32 filter_id)
3347 {
3348         return efx_ef10_filter_remove_internal(efx, 1U << priority,
3349                                                filter_id, true);
3350 }
3351
3352 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3353                                     enum efx_filter_priority priority,
3354                                     u32 filter_id, struct efx_filter_spec *spec)
3355 {
3356         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3357         struct efx_ef10_filter_table *table = efx->filter_state;
3358         const struct efx_filter_spec *saved_spec;
3359         int rc;
3360
3361         spin_lock_bh(&efx->filter_lock);
3362         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3363         if (saved_spec && saved_spec->priority == priority &&
3364             efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3365             filter_id / HUNT_FILTER_TBL_ROWS) {
3366                 *spec = *saved_spec;
3367                 rc = 0;
3368         } else {
3369                 rc = -ENOENT;
3370         }
3371         spin_unlock_bh(&efx->filter_lock);
3372         return rc;
3373 }
3374
3375 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3376                                      enum efx_filter_priority priority)
3377 {
3378         unsigned int priority_mask;
3379         unsigned int i;
3380         int rc;
3381
3382         priority_mask = (((1U << (priority + 1)) - 1) &
3383                          ~(1U << EFX_FILTER_PRI_AUTO));
3384
3385         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3386                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3387                                                      i, true);
3388                 if (rc && rc != -ENOENT)
3389                         return rc;
3390         }
3391
3392         return 0;
3393 }
3394
3395 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3396                                          enum efx_filter_priority priority)
3397 {
3398         struct efx_ef10_filter_table *table = efx->filter_state;
3399         unsigned int filter_idx;
3400         s32 count = 0;
3401
3402         spin_lock_bh(&efx->filter_lock);
3403         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3404                 if (table->entry[filter_idx].spec &&
3405                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3406                     priority)
3407                         ++count;
3408         }
3409         spin_unlock_bh(&efx->filter_lock);
3410         return count;
3411 }
3412
3413 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3414 {
3415         struct efx_ef10_filter_table *table = efx->filter_state;
3416
3417         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3418 }
3419
3420 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3421                                       enum efx_filter_priority priority,
3422                                       u32 *buf, u32 size)
3423 {
3424         struct efx_ef10_filter_table *table = efx->filter_state;
3425         struct efx_filter_spec *spec;
3426         unsigned int filter_idx;
3427         s32 count = 0;
3428
3429         spin_lock_bh(&efx->filter_lock);
3430         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3431                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3432                 if (spec && spec->priority == priority) {
3433                         if (count == size) {
3434                                 count = -EMSGSIZE;
3435                                 break;
3436                         }
3437                         buf[count++] = (efx_ef10_filter_rx_match_pri(
3438                                                 table, spec->match_flags) *
3439                                         HUNT_FILTER_TBL_ROWS +
3440                                         filter_idx);
3441                 }
3442         }
3443         spin_unlock_bh(&efx->filter_lock);
3444         return count;
3445 }
3446
3447 #ifdef CONFIG_RFS_ACCEL
3448
3449 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3450
3451 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3452                                       struct efx_filter_spec *spec)
3453 {
3454         struct efx_ef10_filter_table *table = efx->filter_state;
3455         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3456         struct efx_filter_spec *saved_spec;
3457         unsigned int hash, i, depth = 1;
3458         bool replacing = false;
3459         int ins_index = -1;
3460         u64 cookie;
3461         s32 rc;
3462
3463         /* Must be an RX filter without RSS and not for a multicast
3464          * destination address (RFS only works for connected sockets).
3465          * These restrictions allow us to pass only a tiny amount of
3466          * data through to the completion function.
3467          */
3468         EFX_WARN_ON_PARANOID(spec->flags !=
3469                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3470         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3471         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3472
3473         hash = efx_ef10_filter_hash(spec);
3474
3475         spin_lock_bh(&efx->filter_lock);
3476
3477         /* Find any existing filter with the same match tuple or else
3478          * a free slot to insert at.  If an existing filter is busy,
3479          * we have to give up.
3480          */
3481         for (;;) {
3482                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3483                 saved_spec = efx_ef10_filter_entry_spec(table, i);
3484
3485                 if (!saved_spec) {
3486                         if (ins_index < 0)
3487                                 ins_index = i;
3488                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3489                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3490                                 rc = -EBUSY;
3491                                 goto fail_unlock;
3492                         }
3493                         if (spec->priority < saved_spec->priority) {
3494                                 rc = -EPERM;
3495                                 goto fail_unlock;
3496                         }
3497                         ins_index = i;
3498                         break;
3499                 }
3500
3501                 /* Once we reach the maximum search depth, use the
3502                  * first suitable slot or return -EBUSY if there was
3503                  * none
3504                  */
3505                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3506                         if (ins_index < 0) {
3507                                 rc = -EBUSY;
3508                                 goto fail_unlock;
3509                         }
3510                         break;
3511                 }
3512
3513                 ++depth;
3514         }
3515
3516         /* Create a software table entry if necessary, and mark it
3517          * busy.  We might yet fail to insert, but any attempt to
3518          * insert a conflicting filter while we're waiting for the
3519          * firmware must find the busy entry.
3520          */
3521         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3522         if (saved_spec) {
3523                 replacing = true;
3524         } else {
3525                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3526                 if (!saved_spec) {
3527                         rc = -ENOMEM;
3528                         goto fail_unlock;
3529                 }
3530                 *saved_spec = *spec;
3531         }
3532         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3533                                   EFX_EF10_FILTER_FLAG_BUSY);
3534
3535         spin_unlock_bh(&efx->filter_lock);
3536
3537         /* Pack up the variables needed on completion */
3538         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3539
3540         efx_ef10_filter_push_prep(efx, spec, inbuf,
3541                                   table->entry[ins_index].handle, replacing);
3542         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3543                            MC_CMD_FILTER_OP_OUT_LEN,
3544                            efx_ef10_filter_rfs_insert_complete, cookie);
3545
3546         return ins_index;
3547
3548 fail_unlock:
3549         spin_unlock_bh(&efx->filter_lock);
3550         return rc;
3551 }
3552
3553 static void
3554 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3555                                     int rc, efx_dword_t *outbuf,
3556                                     size_t outlen_actual)
3557 {
3558         struct efx_ef10_filter_table *table = efx->filter_state;
3559         unsigned int ins_index, dmaq_id;
3560         struct efx_filter_spec *spec;
3561         bool replacing;
3562
3563         /* Unpack the cookie */
3564         replacing = cookie >> 31;
3565         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3566         dmaq_id = cookie & 0xffff;
3567
3568         spin_lock_bh(&efx->filter_lock);
3569         spec = efx_ef10_filter_entry_spec(table, ins_index);
3570         if (rc == 0) {
3571                 table->entry[ins_index].handle =
3572                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3573                 if (replacing)
3574                         spec->dmaq_id = dmaq_id;
3575         } else if (!replacing) {
3576                 kfree(spec);
3577                 spec = NULL;
3578         }
3579         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3580         spin_unlock_bh(&efx->filter_lock);
3581
3582         wake_up_all(&table->waitq);
3583 }
3584
3585 static void
3586 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3587                                     unsigned long filter_idx,
3588                                     int rc, efx_dword_t *outbuf,
3589                                     size_t outlen_actual);
3590
3591 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3592                                            unsigned int filter_idx)
3593 {
3594         struct efx_ef10_filter_table *table = efx->filter_state;
3595         struct efx_filter_spec *spec =
3596                 efx_ef10_filter_entry_spec(table, filter_idx);
3597         MCDI_DECLARE_BUF(inbuf,
3598                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3599                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3600
3601         if (!spec ||
3602             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3603             spec->priority != EFX_FILTER_PRI_HINT ||
3604             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3605                                  flow_id, filter_idx))
3606                 return false;
3607
3608         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3609                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
3610         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3611                        table->entry[filter_idx].handle);
3612         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3613                                efx_ef10_filter_rfs_expire_complete, filter_idx))
3614                 return false;
3615
3616         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3617         return true;
3618 }
3619
3620 static void
3621 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3622                                     unsigned long filter_idx,
3623                                     int rc, efx_dword_t *outbuf,
3624                                     size_t outlen_actual)
3625 {
3626         struct efx_ef10_filter_table *table = efx->filter_state;
3627         struct efx_filter_spec *spec =
3628                 efx_ef10_filter_entry_spec(table, filter_idx);
3629
3630         spin_lock_bh(&efx->filter_lock);
3631         if (rc == 0) {
3632                 kfree(spec);
3633                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3634         }
3635         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3636         wake_up_all(&table->waitq);
3637         spin_unlock_bh(&efx->filter_lock);
3638 }
3639
3640 #endif /* CONFIG_RFS_ACCEL */
3641
3642 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3643 {
3644         int match_flags = 0;
3645
3646 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
3647                 u32 old_mcdi_flags = mcdi_flags;                        \
3648                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
3649                                 mcdi_field ## _LBN);                    \
3650                 if (mcdi_flags != old_mcdi_flags)                       \
3651                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
3652         }
3653         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3654         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3655         MAP_FLAG(REM_HOST, SRC_IP);
3656         MAP_FLAG(LOC_HOST, DST_IP);
3657         MAP_FLAG(REM_MAC, SRC_MAC);
3658         MAP_FLAG(REM_PORT, SRC_PORT);
3659         MAP_FLAG(LOC_MAC, DST_MAC);
3660         MAP_FLAG(LOC_PORT, DST_PORT);
3661         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3662         MAP_FLAG(INNER_VID, INNER_VLAN);
3663         MAP_FLAG(OUTER_VID, OUTER_VLAN);
3664         MAP_FLAG(IP_PROTO, IP_PROTO);
3665 #undef MAP_FLAG
3666
3667         /* Did we map them all? */
3668         if (mcdi_flags)
3669                 return -EINVAL;
3670
3671         return match_flags;
3672 }
3673
3674 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3675 {
3676         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3677         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3678         unsigned int pd_match_pri, pd_match_count;
3679         struct efx_ef10_filter_table *table;
3680         size_t outlen;
3681         int rc;
3682
3683         table = kzalloc(sizeof(*table), GFP_KERNEL);
3684         if (!table)
3685                 return -ENOMEM;
3686
3687         /* Find out which RX filter types are supported, and their priorities */
3688         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3689                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3690         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3691                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3692                           &outlen);
3693         if (rc)
3694                 goto fail;
3695         pd_match_count = MCDI_VAR_ARRAY_LEN(
3696                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3697         table->rx_match_count = 0;
3698
3699         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3700                 u32 mcdi_flags =
3701                         MCDI_ARRAY_DWORD(
3702                                 outbuf,
3703                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3704                                 pd_match_pri);
3705                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3706                 if (rc < 0) {
3707                         netif_dbg(efx, probe, efx->net_dev,
3708                                   "%s: fw flags %#x pri %u not supported in driver\n",
3709                                   __func__, mcdi_flags, pd_match_pri);
3710                 } else {
3711                         netif_dbg(efx, probe, efx->net_dev,
3712                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3713                                   __func__, mcdi_flags, pd_match_pri,
3714                                   rc, table->rx_match_count);
3715                         table->rx_match_flags[table->rx_match_count++] = rc;
3716                 }
3717         }
3718
3719         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3720         if (!table->entry) {
3721                 rc = -ENOMEM;
3722                 goto fail;
3723         }
3724
3725         table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3726         table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3727         table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3728
3729         efx->filter_state = table;
3730         init_waitqueue_head(&table->waitq);
3731         return 0;
3732
3733 fail:
3734         kfree(table);
3735         return rc;
3736 }
3737
3738 /* Caller must hold efx->filter_sem for read if race against
3739  * efx_ef10_filter_table_remove() is possible
3740  */
3741 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3742 {
3743         struct efx_ef10_filter_table *table = efx->filter_state;
3744         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3745         struct efx_filter_spec *spec;
3746         unsigned int filter_idx;
3747         bool failed = false;
3748         int rc;
3749
3750         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3751
3752         if (!nic_data->must_restore_filters)
3753                 return;
3754
3755         if (!table)
3756                 return;
3757
3758         spin_lock_bh(&efx->filter_lock);
3759
3760         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3761                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3762                 if (!spec)
3763                         continue;
3764
3765                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3766                 spin_unlock_bh(&efx->filter_lock);
3767
3768                 rc = efx_ef10_filter_push(efx, spec,
3769                                           &table->entry[filter_idx].handle,
3770                                           false);
3771                 if (rc)
3772                         failed = true;
3773
3774                 spin_lock_bh(&efx->filter_lock);
3775                 if (rc) {
3776                         kfree(spec);
3777                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3778                 } else {
3779                         table->entry[filter_idx].spec &=
3780                                 ~EFX_EF10_FILTER_FLAG_BUSY;
3781                 }
3782         }
3783
3784         spin_unlock_bh(&efx->filter_lock);
3785
3786         if (failed)
3787                 netif_err(efx, hw, efx->net_dev,
3788                           "unable to restore all filters\n");
3789         else
3790                 nic_data->must_restore_filters = false;
3791 }
3792
3793 /* Caller must hold efx->filter_sem for write */
3794 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3795 {
3796         struct efx_ef10_filter_table *table = efx->filter_state;
3797         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3798         struct efx_filter_spec *spec;
3799         unsigned int filter_idx;
3800         int rc;
3801
3802         efx->filter_state = NULL;
3803         if (!table)
3804                 return;
3805
3806         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3807                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3808                 if (!spec)
3809                         continue;
3810
3811                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3812                                efx_ef10_filter_is_exclusive(spec) ?
3813                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3814                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3815                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3816                                table->entry[filter_idx].handle);
3817                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3818                                   NULL, 0, NULL);
3819                 if (rc)
3820                         netdev_WARN(efx->net_dev,
3821                                     "filter_idx=%#x handle=%#llx\n",
3822                                     filter_idx,
3823                                     table->entry[filter_idx].handle);
3824                 kfree(spec);
3825         }
3826
3827         vfree(table->entry);
3828         kfree(table);
3829 }
3830
3831 #define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3832                 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3833                         filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3834                         WARN_ON(!table->entry[filter_idx].spec); \
3835                         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \
3836                 }
3837 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
3838 {
3839         struct efx_ef10_filter_table *table = efx->filter_state;
3840         unsigned int filter_idx, i;
3841
3842         if (!table)
3843                 return;
3844
3845         /* Mark old filters that may need to be removed */
3846         spin_lock_bh(&efx->filter_lock);
3847         for (i = 0; i < table->dev_uc_count; i++)
3848                 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3849         for (i = 0; i < table->dev_mc_count; i++)
3850                 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3851         EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3852         EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3853         EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
3854         spin_unlock_bh(&efx->filter_lock);
3855 }
3856 #undef EFX_EF10_FILTER_DO_MARK_OLD
3857
3858 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3859 {
3860         struct efx_ef10_filter_table *table = efx->filter_state;
3861         struct net_device *net_dev = efx->net_dev;
3862         struct netdev_hw_addr *uc;
3863         int addr_count;
3864         unsigned int i;
3865
3866         table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3867         addr_count = netdev_uc_count(net_dev);
3868         if (net_dev->flags & IFF_PROMISC)
3869                 *promisc = true;
3870         table->dev_uc_count = 1 + addr_count;
3871         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3872         i = 1;
3873         netdev_for_each_uc_addr(uc, net_dev) {
3874                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3875                         *promisc = true;
3876                         break;
3877                 }
3878                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3879                 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3880                 i++;
3881         }
3882 }
3883
3884 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3885 {
3886         struct efx_ef10_filter_table *table = efx->filter_state;
3887         struct net_device *net_dev = efx->net_dev;
3888         struct netdev_hw_addr *mc;
3889         unsigned int i, addr_count;
3890
3891         table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3892         table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3893         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
3894                 *promisc = true;
3895
3896         addr_count = netdev_mc_count(net_dev);
3897         i = 0;
3898         netdev_for_each_mc_addr(mc, net_dev) {
3899                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3900                         *promisc = true;
3901                         break;
3902                 }
3903                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3904                 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3905                 i++;
3906         }
3907
3908         table->dev_mc_count = i;
3909 }
3910
3911 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3912                                              bool multicast, bool rollback)
3913 {
3914         struct efx_ef10_filter_table *table = efx->filter_state;
3915         struct efx_ef10_dev_addr *addr_list;
3916         struct efx_filter_spec spec;
3917         u8 baddr[ETH_ALEN];
3918         unsigned int i, j;
3919         int addr_count;
3920         int rc;
3921
3922         if (multicast) {
3923                 addr_list = table->dev_mc_list;
3924                 addr_count = table->dev_mc_count;
3925         } else {
3926                 addr_list = table->dev_uc_list;
3927                 addr_count = table->dev_uc_count;
3928         }
3929
3930         /* Insert/renew filters */
3931         for (i = 0; i < addr_count; i++) {
3932                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3933                                    EFX_FILTER_FLAG_RX_RSS,
3934                                    0);
3935                 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3936                                          addr_list[i].addr);
3937                 rc = efx_ef10_filter_insert(efx, &spec, true);
3938                 if (rc < 0) {
3939                         if (rollback) {
3940                                 netif_info(efx, drv, efx->net_dev,
3941                                            "efx_ef10_filter_insert failed rc=%d\n",
3942                                            rc);
3943                                 /* Fall back to promiscuous */
3944                                 for (j = 0; j < i; j++) {
3945                                         if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3946                                                 continue;
3947                                         efx_ef10_filter_remove_unsafe(
3948                                                 efx, EFX_FILTER_PRI_AUTO,
3949                                                 addr_list[j].id);
3950                                         addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3951                                 }
3952                                 return rc;
3953                         } else {
3954                                 /* mark as not inserted, and carry on */
3955                                 rc = EFX_EF10_FILTER_ID_INVALID;
3956                         }
3957                 }
3958                 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
3959         }
3960
3961         if (multicast && rollback) {
3962                 /* Also need an Ethernet broadcast filter */
3963                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3964                                    EFX_FILTER_FLAG_RX_RSS,
3965                                    0);
3966                 eth_broadcast_addr(baddr);
3967                 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
3968                 rc = efx_ef10_filter_insert(efx, &spec, true);
3969                 if (rc < 0) {
3970                         netif_warn(efx, drv, efx->net_dev,
3971                                    "Broadcast filter insert failed rc=%d\n", rc);
3972                         /* Fall back to promiscuous */
3973                         for (j = 0; j < i; j++) {
3974                                 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3975                                         continue;
3976                                 efx_ef10_filter_remove_unsafe(
3977                                         efx, EFX_FILTER_PRI_AUTO,
3978                                         addr_list[j].id);
3979                                 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3980                         }
3981                         return rc;
3982                 } else {
3983                         table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3984                 }
3985         }
3986
3987         return 0;
3988 }
3989
3990 static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
3991                                       bool rollback)
3992 {
3993         struct efx_ef10_filter_table *table = efx->filter_state;
3994         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3995         struct efx_filter_spec spec;
3996         u8 baddr[ETH_ALEN];
3997         int rc;
3998
3999         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4000                            EFX_FILTER_FLAG_RX_RSS,
4001                            0);
4002
4003         if (multicast)
4004                 efx_filter_set_mc_def(&spec);
4005         else
4006                 efx_filter_set_uc_def(&spec);
4007
4008         rc = efx_ef10_filter_insert(efx, &spec, true);
4009         if (rc < 0) {
4010                 netif_warn(efx, drv, efx->net_dev,
4011                            "%scast mismatch filter insert failed rc=%d\n",
4012                            multicast ? "Multi" : "Uni", rc);
4013         } else if (multicast) {
4014                 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4015                 if (!nic_data->workaround_26807) {
4016                         /* Also need an Ethernet broadcast filter */
4017                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4018                                            EFX_FILTER_FLAG_RX_RSS,
4019                                            0);
4020                         eth_broadcast_addr(baddr);
4021                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
4022                                                  baddr);
4023                         rc = efx_ef10_filter_insert(efx, &spec, true);
4024                         if (rc < 0) {
4025                                 netif_warn(efx, drv, efx->net_dev,
4026                                            "Broadcast filter insert failed rc=%d\n",
4027                                            rc);
4028                                 if (rollback) {
4029                                         /* Roll back the mc_def filter */
4030                                         efx_ef10_filter_remove_unsafe(
4031                                                         efx, EFX_FILTER_PRI_AUTO,
4032                                                         table->mcdef_id);
4033                                         table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
4034                                         return rc;
4035                                 }
4036                         } else {
4037                                 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4038                         }
4039                 }
4040                 rc = 0;
4041         } else {
4042                 table->ucdef_id = rc;
4043                 rc = 0;
4044         }
4045         return rc;
4046 }
4047
4048 /* Remove filters that weren't renewed.  Since nothing else changes the AUTO_OLD
4049  * flag or removes these filters, we don't need to hold the filter_lock while
4050  * scanning for these filters.
4051  */
4052 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4053 {
4054         struct efx_ef10_filter_table *table = efx->filter_state;
4055         bool remove_failed = false;
4056         int i;
4057
4058         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4059                 if (ACCESS_ONCE(table->entry[i].spec) &
4060                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4061                         if (efx_ef10_filter_remove_internal(
4062                                     efx, 1U << EFX_FILTER_PRI_AUTO,
4063                                     i, true) < 0)
4064                                 remove_failed = true;
4065                 }
4066         }
4067         WARN_ON(remove_failed);
4068 }
4069
4070 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4071 {
4072         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4073         u8 mac_old[ETH_ALEN];
4074         int rc, rc2;
4075
4076         /* Only reconfigure a PF-created vport */
4077         if (is_zero_ether_addr(nic_data->vport_mac))
4078                 return 0;
4079
4080         efx_device_detach_sync(efx);
4081         efx_net_stop(efx->net_dev);
4082         down_write(&efx->filter_sem);
4083         efx_ef10_filter_table_remove(efx);
4084         up_write(&efx->filter_sem);
4085
4086         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4087         if (rc)
4088                 goto restore_filters;
4089
4090         ether_addr_copy(mac_old, nic_data->vport_mac);
4091         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4092                                     nic_data->vport_mac);
4093         if (rc)
4094                 goto restore_vadaptor;
4095
4096         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4097                                     efx->net_dev->dev_addr);
4098         if (!rc) {
4099                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4100         } else {
4101                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4102                 if (rc2) {
4103                         /* Failed to add original MAC, so clear vport_mac */
4104                         eth_zero_addr(nic_data->vport_mac);
4105                         goto reset_nic;
4106                 }
4107         }
4108
4109 restore_vadaptor:
4110         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4111         if (rc2)
4112                 goto reset_nic;
4113 restore_filters:
4114         down_write(&efx->filter_sem);
4115         rc2 = efx_ef10_filter_table_probe(efx);
4116         up_write(&efx->filter_sem);
4117         if (rc2)
4118                 goto reset_nic;
4119
4120         rc2 = efx_net_open(efx->net_dev);
4121         if (rc2)
4122                 goto reset_nic;
4123
4124         netif_device_attach(efx->net_dev);
4125
4126         return rc;
4127
4128 reset_nic:
4129         netif_err(efx, drv, efx->net_dev,
4130                   "Failed to restore when changing MAC address - scheduling reset\n");
4131         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4132
4133         return rc ? rc : rc2;
4134 }
4135
4136 /* Caller must hold efx->filter_sem for read if race against
4137  * efx_ef10_filter_table_remove() is possible
4138  */
4139 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4140 {
4141         struct efx_ef10_filter_table *table = efx->filter_state;
4142         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4143         struct net_device *net_dev = efx->net_dev;
4144         bool uc_promisc = false, mc_promisc = false;
4145
4146         if (!efx_dev_registered(efx))
4147                 return;
4148
4149         if (!table)
4150                 return;
4151
4152         efx_ef10_filter_mark_old(efx);
4153
4154         /* Copy/convert the address lists; add the primary station
4155          * address and broadcast address
4156          */
4157         netif_addr_lock_bh(net_dev);
4158         efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4159         efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4160         netif_addr_unlock_bh(net_dev);
4161
4162         /* Insert/renew unicast filters */
4163         if (uc_promisc) {
4164                 efx_ef10_filter_insert_def(efx, false, false);
4165                 efx_ef10_filter_insert_addr_list(efx, false, false);
4166         } else {
4167                 /* If any of the filters failed to insert, fall back to
4168                  * promiscuous mode - add in the uc_def filter.  But keep
4169                  * our individual unicast filters.
4170                  */
4171                 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4172                         efx_ef10_filter_insert_def(efx, false, false);
4173         }
4174
4175         /* Insert/renew multicast filters */
4176         /* If changing promiscuous state with cascaded multicast filters, remove
4177          * old filters first, so that packets are dropped rather than duplicated
4178          */
4179         if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4180                 efx_ef10_filter_remove_old(efx);
4181         if (mc_promisc) {
4182                 if (nic_data->workaround_26807) {
4183                         /* If we failed to insert promiscuous filters, rollback
4184                          * and fall back to individual multicast filters
4185                          */
4186                         if (efx_ef10_filter_insert_def(efx, true, true)) {
4187                                 /* Changing promisc state, so remove old filters */
4188                                 efx_ef10_filter_remove_old(efx);
4189                                 efx_ef10_filter_insert_addr_list(efx, true, false);
4190                         }
4191                 } else {
4192                         /* If we failed to insert promiscuous filters, don't
4193                          * rollback.  Regardless, also insert the mc_list
4194                          */
4195                         efx_ef10_filter_insert_def(efx, true, false);
4196                         efx_ef10_filter_insert_addr_list(efx, true, false);
4197                 }
4198         } else {
4199                 /* If any filters failed to insert, rollback and fall back to
4200                  * promiscuous mode - mc_def filter and maybe broadcast.  If
4201                  * that fails, roll back again and insert as many of our
4202                  * individual multicast filters as we can.
4203                  */
4204                 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4205                         /* Changing promisc state, so remove old filters */
4206                         if (nic_data->workaround_26807)
4207                                 efx_ef10_filter_remove_old(efx);
4208                         if (efx_ef10_filter_insert_def(efx, true, true))
4209                                 efx_ef10_filter_insert_addr_list(efx, true, false);
4210                 }
4211         }
4212
4213         efx_ef10_filter_remove_old(efx);
4214         efx->mc_promisc = mc_promisc;
4215 }
4216
4217 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4218 {
4219         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4220         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4221         bool was_enabled = efx->port_enabled;
4222         int rc;
4223
4224         efx_device_detach_sync(efx);
4225         efx_net_stop(efx->net_dev);
4226         down_write(&efx->filter_sem);
4227         efx_ef10_filter_table_remove(efx);
4228
4229         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4230                         efx->net_dev->dev_addr);
4231         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4232                        nic_data->vport_id);
4233         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4234                                 sizeof(inbuf), NULL, 0, NULL);
4235
4236         efx_ef10_filter_table_probe(efx);
4237         up_write(&efx->filter_sem);
4238         if (was_enabled)
4239                 efx_net_open(efx->net_dev);
4240         netif_device_attach(efx->net_dev);
4241
4242 #ifdef CONFIG_SFC_SRIOV
4243         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4244                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4245
4246                 if (rc == -EPERM) {
4247                         struct efx_nic *efx_pf;
4248
4249                         /* Switch to PF and change MAC address on vport */
4250                         efx_pf = pci_get_drvdata(pci_dev_pf);
4251
4252                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4253                                                        nic_data->vf_index,
4254                                                        efx->net_dev->dev_addr);
4255                 } else if (!rc) {
4256                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4257                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4258                         unsigned int i;
4259
4260                         /* MAC address successfully changed by VF (with MAC
4261                          * spoofing) so update the parent PF if possible.
4262                          */
4263                         for (i = 0; i < efx_pf->vf_count; ++i) {
4264                                 struct ef10_vf *vf = nic_data->vf + i;
4265
4266                                 if (vf->efx == efx) {
4267                                         ether_addr_copy(vf->mac,
4268                                                         efx->net_dev->dev_addr);
4269                                         return 0;
4270                                 }
4271                         }
4272                 }
4273         } else
4274 #endif
4275         if (rc == -EPERM) {
4276                 netif_err(efx, drv, efx->net_dev,
4277                           "Cannot change MAC address; use sfboot to enable"
4278                           " mac-spoofing on this interface\n");
4279         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4280                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4281                  * fall-back to the method of changing the MAC address on the
4282                  * vport.  This only applies to PFs because such versions of
4283                  * MCFW do not support VFs.
4284                  */
4285                 rc = efx_ef10_vport_set_mac_address(efx);
4286         } else {
4287                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4288                                        sizeof(inbuf), NULL, 0, rc);
4289         }
4290
4291         return rc;
4292 }
4293
4294 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4295 {
4296         efx_ef10_filter_sync_rx_mode(efx);
4297
4298         return efx_mcdi_set_mac(efx);
4299 }
4300
4301 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4302 {
4303         efx_ef10_filter_sync_rx_mode(efx);
4304
4305         return 0;
4306 }
4307
4308 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4309 {
4310         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4311
4312         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4313         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4314                             NULL, 0, NULL);
4315 }
4316
4317 /* MC BISTs follow a different poll mechanism to phy BISTs.
4318  * The BIST is done in the poll handler on the MC, and the MCDI command
4319  * will block until the BIST is done.
4320  */
4321 static int efx_ef10_poll_bist(struct efx_nic *efx)
4322 {
4323         int rc;
4324         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4325         size_t outlen;
4326         u32 result;
4327
4328         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4329                            outbuf, sizeof(outbuf), &outlen);
4330         if (rc != 0)
4331                 return rc;
4332
4333         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4334                 return -EIO;
4335
4336         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4337         switch (result) {
4338         case MC_CMD_POLL_BIST_PASSED:
4339                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4340                 return 0;
4341         case MC_CMD_POLL_BIST_TIMEOUT:
4342                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4343                 return -EIO;
4344         case MC_CMD_POLL_BIST_FAILED:
4345                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4346                 return -EIO;
4347         default:
4348                 netif_err(efx, hw, efx->net_dev,
4349                           "BIST returned unknown result %u", result);
4350                 return -EIO;
4351         }
4352 }
4353
4354 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4355 {
4356         int rc;
4357
4358         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4359
4360         rc = efx_ef10_start_bist(efx, bist_type);
4361         if (rc != 0)
4362                 return rc;
4363
4364         return efx_ef10_poll_bist(efx);
4365 }
4366
4367 static int
4368 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4369 {
4370         int rc, rc2;
4371
4372         efx_reset_down(efx, RESET_TYPE_WORLD);
4373
4374         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4375                           NULL, 0, NULL, 0, NULL);
4376         if (rc != 0)
4377                 goto out;
4378
4379         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4380         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4381
4382         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4383
4384 out:
4385         if (rc == -EPERM)
4386                 rc = 0;
4387         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4388         return rc ? rc : rc2;
4389 }
4390
4391 #ifdef CONFIG_SFC_MTD
4392
4393 struct efx_ef10_nvram_type_info {
4394         u16 type, type_mask;
4395         u8 port;
4396         const char *name;
4397 };
4398
4399 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4400         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
4401         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
4402         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
4403         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
4404         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
4405         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
4406         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
4407         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
4408         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
4409         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
4410         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
4411 };
4412
4413 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4414                                         struct efx_mcdi_mtd_partition *part,
4415                                         unsigned int type)
4416 {
4417         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4418         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4419         const struct efx_ef10_nvram_type_info *info;
4420         size_t size, erase_size, outlen;
4421         bool protected;
4422         int rc;
4423
4424         for (info = efx_ef10_nvram_types; ; info++) {
4425                 if (info ==
4426                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4427                         return -ENODEV;
4428                 if ((type & ~info->type_mask) == info->type)
4429                         break;
4430         }
4431         if (info->port != efx_port_num(efx))
4432                 return -ENODEV;
4433
4434         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4435         if (rc)
4436                 return rc;
4437         if (protected)
4438                 return -ENODEV; /* hide it */
4439
4440         part->nvram_type = type;
4441
4442         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4443         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4444                           outbuf, sizeof(outbuf), &outlen);
4445         if (rc)
4446                 return rc;
4447         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4448                 return -EIO;
4449         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4450             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4451                 part->fw_subtype = MCDI_DWORD(outbuf,
4452                                               NVRAM_METADATA_OUT_SUBTYPE);
4453
4454         part->common.dev_type_name = "EF10 NVRAM manager";
4455         part->common.type_name = info->name;
4456
4457         part->common.mtd.type = MTD_NORFLASH;
4458         part->common.mtd.flags = MTD_CAP_NORFLASH;
4459         part->common.mtd.size = size;
4460         part->common.mtd.erasesize = erase_size;
4461
4462         return 0;
4463 }
4464
4465 static int efx_ef10_mtd_probe(struct efx_nic *efx)
4466 {
4467         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4468         struct efx_mcdi_mtd_partition *parts;
4469         size_t outlen, n_parts_total, i, n_parts;
4470         unsigned int type;
4471         int rc;
4472
4473         ASSERT_RTNL();
4474
4475         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4476         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4477                           outbuf, sizeof(outbuf), &outlen);
4478         if (rc)
4479                 return rc;
4480         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4481                 return -EIO;
4482
4483         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4484         if (n_parts_total >
4485             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4486                 return -EIO;
4487
4488         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4489         if (!parts)
4490                 return -ENOMEM;
4491
4492         n_parts = 0;
4493         for (i = 0; i < n_parts_total; i++) {
4494                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4495                                         i);
4496                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4497                 if (rc == 0)
4498                         n_parts++;
4499                 else if (rc != -ENODEV)
4500                         goto fail;
4501         }
4502
4503         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4504 fail:
4505         if (rc)
4506                 kfree(parts);
4507         return rc;
4508 }
4509
4510 #endif /* CONFIG_SFC_MTD */
4511
4512 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4513 {
4514         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4515 }
4516
4517 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4518                                             u32 host_time) {}
4519
4520 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4521                                            bool temp)
4522 {
4523         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4524         int rc;
4525
4526         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4527             channel->sync_events_state == SYNC_EVENTS_VALID ||
4528             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4529                 return 0;
4530         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4531
4532         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4533         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4534         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4535                        channel->channel);
4536
4537         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4538                           inbuf, sizeof(inbuf), NULL, 0, NULL);
4539
4540         if (rc != 0)
4541                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4542                                                     SYNC_EVENTS_DISABLED;
4543
4544         return rc;
4545 }
4546
4547 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4548                                             bool temp)
4549 {
4550         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4551         int rc;
4552
4553         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4554             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4555                 return 0;
4556         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4557                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4558                 return 0;
4559         }
4560         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4561                                             SYNC_EVENTS_DISABLED;
4562
4563         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4564         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4565         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4566                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4567         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4568                        channel->channel);
4569
4570         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4571                           inbuf, sizeof(inbuf), NULL, 0, NULL);
4572
4573         return rc;
4574 }
4575
4576 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4577                                            bool temp)
4578 {
4579         int (*set)(struct efx_channel *channel, bool temp);
4580         struct efx_channel *channel;
4581
4582         set = en ?
4583               efx_ef10_rx_enable_timestamping :
4584               efx_ef10_rx_disable_timestamping;
4585
4586         efx_for_each_channel(channel, efx) {
4587                 int rc = set(channel, temp);
4588                 if (en && rc != 0) {
4589                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4590                         return rc;
4591                 }
4592         }
4593
4594         return 0;
4595 }
4596
4597 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4598                                          struct hwtstamp_config *init)
4599 {
4600         return -EOPNOTSUPP;
4601 }
4602
4603 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4604                                       struct hwtstamp_config *init)
4605 {
4606         int rc;
4607
4608         switch (init->rx_filter) {
4609         case HWTSTAMP_FILTER_NONE:
4610                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4611                 /* if TX timestamping is still requested then leave PTP on */
4612                 return efx_ptp_change_mode(efx,
4613                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
4614         case HWTSTAMP_FILTER_ALL:
4615         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4616         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4617         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4618         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4619         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4620         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4621         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4622         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4623         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4624         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4625         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4626         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4627                 init->rx_filter = HWTSTAMP_FILTER_ALL;
4628                 rc = efx_ptp_change_mode(efx, true, 0);
4629                 if (!rc)
4630                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4631                 if (rc)
4632                         efx_ptp_change_mode(efx, false, 0);
4633                 return rc;
4634         default:
4635                 return -ERANGE;
4636         }
4637 }
4638
4639 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
4640         .is_vf = true,
4641         .mem_bar = EFX_MEM_VF_BAR,
4642         .mem_map_size = efx_ef10_mem_map_size,
4643         .probe = efx_ef10_probe_vf,
4644         .remove = efx_ef10_remove,
4645         .dimension_resources = efx_ef10_dimension_resources,
4646         .init = efx_ef10_init_nic,
4647         .fini = efx_port_dummy_op_void,
4648         .map_reset_reason = efx_ef10_map_reset_reason,
4649         .map_reset_flags = efx_ef10_map_reset_flags,
4650         .reset = efx_ef10_reset,
4651         .probe_port = efx_mcdi_port_probe,
4652         .remove_port = efx_mcdi_port_remove,
4653         .fini_dmaq = efx_ef10_fini_dmaq,
4654         .prepare_flr = efx_ef10_prepare_flr,
4655         .finish_flr = efx_port_dummy_op_void,
4656         .describe_stats = efx_ef10_describe_stats,
4657         .update_stats = efx_ef10_update_stats_vf,
4658         .start_stats = efx_port_dummy_op_void,
4659         .pull_stats = efx_port_dummy_op_void,
4660         .stop_stats = efx_port_dummy_op_void,
4661         .set_id_led = efx_mcdi_set_id_led,
4662         .push_irq_moderation = efx_ef10_push_irq_moderation,
4663         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
4664         .check_mac_fault = efx_mcdi_mac_check_fault,
4665         .reconfigure_port = efx_mcdi_port_reconfigure,
4666         .get_wol = efx_ef10_get_wol_vf,
4667         .set_wol = efx_ef10_set_wol_vf,
4668         .resume_wol = efx_port_dummy_op_void,
4669         .mcdi_request = efx_ef10_mcdi_request,
4670         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4671         .mcdi_read_response = efx_ef10_mcdi_read_response,
4672         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4673         .irq_enable_master = efx_port_dummy_op_void,
4674         .irq_test_generate = efx_ef10_irq_test_generate,
4675         .irq_disable_non_ev = efx_port_dummy_op_void,
4676         .irq_handle_msi = efx_ef10_msi_interrupt,
4677         .irq_handle_legacy = efx_ef10_legacy_interrupt,
4678         .tx_probe = efx_ef10_tx_probe,
4679         .tx_init = efx_ef10_tx_init,
4680         .tx_remove = efx_ef10_tx_remove,
4681         .tx_write = efx_ef10_tx_write,
4682         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
4683         .rx_probe = efx_ef10_rx_probe,
4684         .rx_init = efx_ef10_rx_init,
4685         .rx_remove = efx_ef10_rx_remove,
4686         .rx_write = efx_ef10_rx_write,
4687         .rx_defer_refill = efx_ef10_rx_defer_refill,
4688         .ev_probe = efx_ef10_ev_probe,
4689         .ev_init = efx_ef10_ev_init,
4690         .ev_fini = efx_ef10_ev_fini,
4691         .ev_remove = efx_ef10_ev_remove,
4692         .ev_process = efx_ef10_ev_process,
4693         .ev_read_ack = efx_ef10_ev_read_ack,
4694         .ev_test_generate = efx_ef10_ev_test_generate,
4695         .filter_table_probe = efx_ef10_filter_table_probe,
4696         .filter_table_restore = efx_ef10_filter_table_restore,
4697         .filter_table_remove = efx_ef10_filter_table_remove,
4698         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4699         .filter_insert = efx_ef10_filter_insert,
4700         .filter_remove_safe = efx_ef10_filter_remove_safe,
4701         .filter_get_safe = efx_ef10_filter_get_safe,
4702         .filter_clear_rx = efx_ef10_filter_clear_rx,
4703         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4704         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4705         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4706 #ifdef CONFIG_RFS_ACCEL
4707         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4708         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4709 #endif
4710 #ifdef CONFIG_SFC_MTD
4711         .mtd_probe = efx_port_dummy_op_int,
4712 #endif
4713         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4714         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4715 #ifdef CONFIG_SFC_SRIOV
4716         .vswitching_probe = efx_ef10_vswitching_probe_vf,
4717         .vswitching_restore = efx_ef10_vswitching_restore_vf,
4718         .vswitching_remove = efx_ef10_vswitching_remove_vf,
4719         .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
4720 #endif
4721         .get_mac_address = efx_ef10_get_mac_address_vf,
4722         .set_mac_address = efx_ef10_set_mac_address,
4723
4724         .revision = EFX_REV_HUNT_A0,
4725         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4726         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4727         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4728         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4729         .can_rx_scatter = true,
4730         .always_rx_scatter = true,
4731         .max_interrupt_mode = EFX_INT_MODE_MSIX,
4732         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4733         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4734                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
4735         .mcdi_max_ver = 2,
4736         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4737         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4738                             1 << HWTSTAMP_FILTER_ALL,
4739 };
4740
4741 const struct efx_nic_type efx_hunt_a0_nic_type = {
4742         .is_vf = false,
4743         .mem_bar = EFX_MEM_BAR,
4744         .mem_map_size = efx_ef10_mem_map_size,
4745         .probe = efx_ef10_probe_pf,
4746         .remove = efx_ef10_remove,
4747         .dimension_resources = efx_ef10_dimension_resources,
4748         .init = efx_ef10_init_nic,
4749         .fini = efx_port_dummy_op_void,
4750         .map_reset_reason = efx_ef10_map_reset_reason,
4751         .map_reset_flags = efx_ef10_map_reset_flags,
4752         .reset = efx_ef10_reset,
4753         .probe_port = efx_mcdi_port_probe,
4754         .remove_port = efx_mcdi_port_remove,
4755         .fini_dmaq = efx_ef10_fini_dmaq,
4756         .prepare_flr = efx_ef10_prepare_flr,
4757         .finish_flr = efx_port_dummy_op_void,
4758         .describe_stats = efx_ef10_describe_stats,
4759         .update_stats = efx_ef10_update_stats_pf,
4760         .start_stats = efx_mcdi_mac_start_stats,
4761         .pull_stats = efx_mcdi_mac_pull_stats,
4762         .stop_stats = efx_mcdi_mac_stop_stats,
4763         .set_id_led = efx_mcdi_set_id_led,
4764         .push_irq_moderation = efx_ef10_push_irq_moderation,
4765         .reconfigure_mac = efx_ef10_mac_reconfigure,
4766         .check_mac_fault = efx_mcdi_mac_check_fault,
4767         .reconfigure_port = efx_mcdi_port_reconfigure,
4768         .get_wol = efx_ef10_get_wol,
4769         .set_wol = efx_ef10_set_wol,
4770         .resume_wol = efx_port_dummy_op_void,
4771         .test_chip = efx_ef10_test_chip,
4772         .test_nvram = efx_mcdi_nvram_test_all,
4773         .mcdi_request = efx_ef10_mcdi_request,
4774         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4775         .mcdi_read_response = efx_ef10_mcdi_read_response,
4776         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4777         .irq_enable_master = efx_port_dummy_op_void,
4778         .irq_test_generate = efx_ef10_irq_test_generate,
4779         .irq_disable_non_ev = efx_port_dummy_op_void,
4780         .irq_handle_msi = efx_ef10_msi_interrupt,
4781         .irq_handle_legacy = efx_ef10_legacy_interrupt,
4782         .tx_probe = efx_ef10_tx_probe,
4783         .tx_init = efx_ef10_tx_init,
4784         .tx_remove = efx_ef10_tx_remove,
4785         .tx_write = efx_ef10_tx_write,
4786         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
4787         .rx_probe = efx_ef10_rx_probe,
4788         .rx_init = efx_ef10_rx_init,
4789         .rx_remove = efx_ef10_rx_remove,
4790         .rx_write = efx_ef10_rx_write,
4791         .rx_defer_refill = efx_ef10_rx_defer_refill,
4792         .ev_probe = efx_ef10_ev_probe,
4793         .ev_init = efx_ef10_ev_init,
4794         .ev_fini = efx_ef10_ev_fini,
4795         .ev_remove = efx_ef10_ev_remove,
4796         .ev_process = efx_ef10_ev_process,
4797         .ev_read_ack = efx_ef10_ev_read_ack,
4798         .ev_test_generate = efx_ef10_ev_test_generate,
4799         .filter_table_probe = efx_ef10_filter_table_probe,
4800         .filter_table_restore = efx_ef10_filter_table_restore,
4801         .filter_table_remove = efx_ef10_filter_table_remove,
4802         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4803         .filter_insert = efx_ef10_filter_insert,
4804         .filter_remove_safe = efx_ef10_filter_remove_safe,
4805         .filter_get_safe = efx_ef10_filter_get_safe,
4806         .filter_clear_rx = efx_ef10_filter_clear_rx,
4807         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4808         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4809         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4810 #ifdef CONFIG_RFS_ACCEL
4811         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4812         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4813 #endif
4814 #ifdef CONFIG_SFC_MTD
4815         .mtd_probe = efx_ef10_mtd_probe,
4816         .mtd_rename = efx_mcdi_mtd_rename,
4817         .mtd_read = efx_mcdi_mtd_read,
4818         .mtd_erase = efx_mcdi_mtd_erase,
4819         .mtd_write = efx_mcdi_mtd_write,
4820         .mtd_sync = efx_mcdi_mtd_sync,
4821 #endif
4822         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4823         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4824         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4825 #ifdef CONFIG_SFC_SRIOV
4826         .sriov_configure = efx_ef10_sriov_configure,
4827         .sriov_init = efx_ef10_sriov_init,
4828         .sriov_fini = efx_ef10_sriov_fini,
4829         .sriov_wanted = efx_ef10_sriov_wanted,
4830         .sriov_reset = efx_ef10_sriov_reset,
4831         .sriov_flr = efx_ef10_sriov_flr,
4832         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4833         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4834         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4835         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4836         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
4837         .vswitching_probe = efx_ef10_vswitching_probe_pf,
4838         .vswitching_restore = efx_ef10_vswitching_restore_pf,
4839         .vswitching_remove = efx_ef10_vswitching_remove_pf,
4840 #endif
4841         .get_mac_address = efx_ef10_get_mac_address_pf,
4842         .set_mac_address = efx_ef10_set_mac_address,
4843
4844         .revision = EFX_REV_HUNT_A0,
4845         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4846         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4847         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4848         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4849         .can_rx_scatter = true,
4850         .always_rx_scatter = true,
4851         .max_interrupt_mode = EFX_INT_MODE_MSIX,
4852         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4853         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4854                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
4855         .mcdi_max_ver = 2,
4856         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4857         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4858                             1 << HWTSTAMP_FILTER_ALL,
4859 };