drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include "cpsw.h"
  40 #include "cpsw_ale.h"
  41 #include "cpts.h"
  42 #include "davinci_cpdma.h"
  43
  44 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  45                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  46                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  47                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  48                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  49                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  50                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  51                          NETIF_MSG_RX_STATUS)
  52
  53 #define cpsw_info(priv, type, format, ...)              \
  54 do {                                                            \
  55         if (netif_msg_##type(priv) && net_ratelimit())          \
  56                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  57 } while (0)
  58
  59 #define cpsw_err(priv, type, format, ...)               \
  60 do {                                                            \
  61         if (netif_msg_##type(priv) && net_ratelimit())          \
  62                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  63 } while (0)
  64
  65 #define cpsw_dbg(priv, type, format, ...)               \
  66 do {                                                            \
  67         if (netif_msg_##type(priv) && net_ratelimit())          \
  68                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  69 } while (0)
  70
  71 #define cpsw_notice(priv, type, format, ...)            \
  72 do {                                                            \
  73         if (netif_msg_##type(priv) && net_ratelimit())          \
  74                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  75 } while (0)
  76
  77 #define ALE_ALL_PORTS           0x7
  78
  79 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  80 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  81 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  82
  83 #define CPSW_VERSION_1          0x19010a
  84 #define CPSW_VERSION_2          0x19010c
  85 #define CPSW_VERSION_3          0x19010f
  86 #define CPSW_VERSION_4          0x190112
  87
  88 #define HOST_PORT_NUM           0
  89 #define SLIVER_SIZE             0x40
  90
  91 #define CPSW1_HOST_PORT_OFFSET  0x028
  92 #define CPSW1_SLAVE_OFFSET      0x050
  93 #define CPSW1_SLAVE_SIZE        0x040
  94 #define CPSW1_CPDMA_OFFSET      0x100
  95 #define CPSW1_STATERAM_OFFSET   0x200
  96 #define CPSW1_HW_STATS          0x400
  97 #define CPSW1_CPTS_OFFSET       0x500
  98 #define CPSW1_ALE_OFFSET        0x600
  99 #define CPSW1_SLIVER_OFFSET     0x700
 100
 101 #define CPSW2_HOST_PORT_OFFSET  0x108
 102 #define CPSW2_SLAVE_OFFSET      0x200
 103 #define CPSW2_SLAVE_SIZE        0x100
 104 #define CPSW2_CPDMA_OFFSET      0x800
 105 #define CPSW2_HW_STATS          0x900
 106 #define CPSW2_STATERAM_OFFSET   0xa00
 107 #define CPSW2_CPTS_OFFSET       0xc00
 108 #define CPSW2_ALE_OFFSET        0xd00
 109 #define CPSW2_SLIVER_OFFSET     0xd80
 110 #define CPSW2_BD_OFFSET         0x2000
 111
 112 #define CPDMA_RXTHRESH          0x0c0
 113 #define CPDMA_RXFREE            0x0e0
 114 #define CPDMA_TXHDP             0x00
 115 #define CPDMA_RXHDP             0x20
 116 #define CPDMA_TXCP              0x40
 117 #define CPDMA_RXCP              0x60
 118
 119 #define CPSW_POLL_WEIGHT        64
 120 #define CPSW_MIN_PACKET_SIZE    60
 121 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 122
 123 #define RX_PRIORITY_MAPPING     0x76543210
 124 #define TX_PRIORITY_MAPPING     0x33221100
 125 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 126
 127 #define CPSW_VLAN_AWARE         BIT(1)
 128 #define CPSW_ALE_VLAN_AWARE     1
 129
 130 #define CPSW_FIFO_NORMAL_MODE           (0 << 15)
 131 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 15)
 132 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 15)
 133
 134 #define CPSW_INTPACEEN          (0x3f << 16)
 135 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 136 #define CPSW_CMINTMAX_CNT       63
 137 #define CPSW_CMINTMIN_CNT       2
 138 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 139 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 140
 141 #define cpsw_enable_irq(priv)   \
 142         do {                    \
 143                 u32 i;          \
 144                 for (i = 0; i < priv->num_irqs; i++) \
 145                         enable_irq(priv->irqs_table[i]); \
 146         } while (0);
 147 #define cpsw_disable_irq(priv)  \
 148         do {                    \
 149                 u32 i;          \
 150                 for (i = 0; i < priv->num_irqs; i++) \
 151                         disable_irq_nosync(priv->irqs_table[i]); \
 152         } while (0);
 153
 154 #define cpsw_slave_index(priv)                          \
 155                 ((priv->data.dual_emac) ? priv->emac_port :     \
 156                 priv->data.active_slave)
 157
 158 static int debug_level;
 159 module_param(debug_level, int, 0);
 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 161
 162 static int ale_ageout = 10;
 163 module_param(ale_ageout, int, 0);
 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 165
 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 167 module_param(rx_packet_max, int, 0);
 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 169
 170 struct cpsw_wr_regs {
 171         u32     id_ver;
 172         u32     soft_reset;
 173         u32     control;
 174         u32     int_control;
 175         u32     rx_thresh_en;
 176         u32     rx_en;
 177         u32     tx_en;
 178         u32     misc_en;
 179         u32     mem_allign1[8];
 180         u32     rx_thresh_stat;
 181         u32     rx_stat;
 182         u32     tx_stat;
 183         u32     misc_stat;
 184         u32     mem_allign2[8];
 185         u32     rx_imax;
 186         u32     tx_imax;
 187
 188 };
 189
 190 struct cpsw_ss_regs {
 191         u32     id_ver;
 192         u32     control;
 193         u32     soft_reset;
 194         u32     stat_port_en;
 195         u32     ptype;
 196         u32     soft_idle;
 197         u32     thru_rate;
 198         u32     gap_thresh;
 199         u32     tx_start_wds;
 200         u32     flow_control;
 201         u32     vlan_ltype;
 202         u32     ts_ltype;
 203         u32     dlr_ltype;
 204 };
 205
 206 /* CPSW_PORT_V1 */
 207 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 208 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 210 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 211 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 213 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 214 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 215
 216 /* CPSW_PORT_V2 */
 217 #define CPSW2_CONTROL       0x00 /* Control Register */
 218 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 219 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 220 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 221 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 222 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 223 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 224
 225 /* CPSW_PORT_V1 and V2 */
 226 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 227 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 228 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 229
 230 /* CPSW_PORT_V2 only */
 231 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 236 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 237 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 238 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 239
 240 /* Bit definitions for the CPSW2_CONTROL register */
 241 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 242 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 243 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 244 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 245 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 246 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 247 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 248 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 249 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 250 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 251 #define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
 252 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 253 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 254 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 255 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 256 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 257
 258 #define CTRL_TS_BITS \
 259         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
 260          TS_ANNEX_D_EN | TS_LTYPE1_EN)
 261
 262 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 263 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
 264 #define CTRL_RX_TS_BITS  (CTRL_TS_BITS | TS_RX_EN)
 265
 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 267 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 268 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 269 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 270 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 271
 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 274
 275 /* Bit definitions for the CPSW1_TS_CTL register */
 276 #define CPSW_V1_TS_RX_EN                BIT(0)
 277 #define CPSW_V1_TS_TX_EN                BIT(4)
 278 #define CPSW_V1_MSG_TYPE_OFS            16
 279
 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 282
 283 struct cpsw_host_regs {
 284         u32     max_blks;
 285         u32     blk_cnt;
 286         u32     tx_in_ctl;
 287         u32     port_vlan;
 288         u32     tx_pri_map;
 289         u32     cpdma_tx_pri_map;
 290         u32     cpdma_rx_chan_map;
 291 };
 292
 293 struct cpsw_sliver_regs {
 294         u32     id_ver;
 295         u32     mac_control;
 296         u32     mac_status;
 297         u32     soft_reset;
 298         u32     rx_maxlen;
 299         u32     __reserved_0;
 300         u32     rx_pause;
 301         u32     tx_pause;
 302         u32     __reserved_1;
 303         u32     rx_pri_map;
 304 };
 305
 306 struct cpsw_hw_stats {
 307         u32     rxgoodframes;
 308         u32     rxbroadcastframes;
 309         u32     rxmulticastframes;
 310         u32     rxpauseframes;
 311         u32     rxcrcerrors;
 312         u32     rxaligncodeerrors;
 313         u32     rxoversizedframes;
 314         u32     rxjabberframes;
 315         u32     rxundersizedframes;
 316         u32     rxfragments;
 317         u32     __pad_0[2];
 318         u32     rxoctets;
 319         u32     txgoodframes;
 320         u32     txbroadcastframes;
 321         u32     txmulticastframes;
 322         u32     txpauseframes;
 323         u32     txdeferredframes;
 324         u32     txcollisionframes;
 325         u32     txsinglecollframes;
 326         u32     txmultcollframes;
 327         u32     txexcessivecollisions;
 328         u32     txlatecollisions;
 329         u32     txunderrun;
 330         u32     txcarriersenseerrors;
 331         u32     txoctets;
 332         u32     octetframes64;
 333         u32     octetframes65t127;
 334         u32     octetframes128t255;
 335         u32     octetframes256t511;
 336         u32     octetframes512t1023;
 337         u32     octetframes1024tup;
 338         u32     netoctets;
 339         u32     rxsofoverruns;
 340         u32     rxmofoverruns;
 341         u32     rxdmaoverruns;
 342 };
 343
 344 struct cpsw_slave {
 345         void __iomem                    *regs;
 346         struct cpsw_sliver_regs __iomem *sliver;
 347         int                             slave_num;
 348         u32                             mac_control;
 349         struct cpsw_slave_data          *data;
 350         struct phy_device               *phy;
 351         struct net_device               *ndev;
 352         u32                             port_vlan;
 353         u32                             open_stat;
 354 };
 355
 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 357 {
 358         return __raw_readl(slave->regs + offset);
 359 }
 360
 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 362 {
 363         __raw_writel(val, slave->regs + offset);
 364 }
 365
 366 struct cpsw_priv {
 367         spinlock_t                      lock;
 368         struct platform_device          *pdev;
 369         struct net_device               *ndev;
 370         struct napi_struct              napi;
 371         struct device                   *dev;
 372         struct cpsw_platform_data       data;
 373         struct cpsw_ss_regs __iomem     *regs;
 374         struct cpsw_wr_regs __iomem     *wr_regs;
 375         u8 __iomem                      *hw_stats;
 376         struct cpsw_host_regs __iomem   *host_port_regs;
 377         u32                             msg_enable;
 378         u32                             version;
 379         u32                             coal_intvl;
 380         u32                             bus_freq_mhz;
 381         struct net_device_stats         stats;
 382         int                             rx_packet_max;
 383         int                             host_port;
 384         struct clk                      *clk;
 385         u8                              mac_addr[ETH_ALEN];
 386         struct cpsw_slave               *slaves;
 387         struct cpdma_ctlr               *dma;
 388         struct cpdma_chan               *txch, *rxch;
 389         struct cpsw_ale                 *ale;
 390         /* snapshot of IRQ numbers */
 391         u32 irqs_table[4];
 392         u32 num_irqs;
 393         bool irq_enabled;
 394         struct cpts *cpts;
 395         u32 emac_port;
 396 };
 397
 398 struct cpsw_stats {
 399         char stat_string[ETH_GSTRING_LEN];
 400         int type;
 401         int sizeof_stat;
 402         int stat_offset;
 403 };
 404
 405 enum {
 406         CPSW_STATS,
 407         CPDMA_RX_STATS,
 408         CPDMA_TX_STATS,
 409 };
 410
 411 #define CPSW_STAT(m)            CPSW_STATS,                             \
 412                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 413                                 offsetof(struct cpsw_hw_stats, m)
 414 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 415                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 416                                 offsetof(struct cpdma_chan_stats, m)
 417 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 418                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 419                                 offsetof(struct cpdma_chan_stats, m)
 420
 421 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 422         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 423         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 424         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 425         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 426         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 427         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 428         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 429         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 430         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 431         { "Rx Fragments", CPSW_STAT(rxfragments) },
 432         { "Rx Octets", CPSW_STAT(rxoctets) },
 433         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 434         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 435         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 436         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 437         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 438         { "Collisions", CPSW_STAT(txcollisionframes) },
 439         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 440         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 441         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 442         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 443         { "Tx Underrun", CPSW_STAT(txunderrun) },
 444         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 445         { "Tx Octets", CPSW_STAT(txoctets) },
 446         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 447         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 448         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 449         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 450         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 451         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 452         { "Net Octets", CPSW_STAT(netoctets) },
 453         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 454         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 455         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 456         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 457         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 458         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 459         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 460         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 461         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 462         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 463         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 464         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 465         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 466         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 467         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 468         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 469         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 470         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 471         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 472         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 473         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 474         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 475         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 476         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 477         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 478         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 479         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 480         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 481         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 482 };
 483
 484 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 485
 486 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 487 #define for_each_slave(priv, func, arg...)                              \
 488         do {                                                            \
 489                 struct cpsw_slave *slave;                               \
 490                 int n;                                                  \
 491                 if (priv->data.dual_emac)                               \
 492                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 493                 else                                                    \
 494                         for (n = (priv)->data.slaves,                   \
 495                                         slave = (priv)->slaves;         \
 496                                         n; n--)                         \
 497                                 (func)(slave++, ##arg);                 \
 498         } while (0)
 499 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 500         (priv->slaves[__slave_no__].ndev)
 501 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 502         ((priv->slaves[__slave_no__].ndev) ?                            \
 503                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 504
 505 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 506         do {                                                            \
 507                 if (!priv->data.dual_emac)                              \
 508                         break;                                          \
 509                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 510                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 511                         priv = netdev_priv(ndev);                       \
 512                         skb->dev = ndev;                                \
 513                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 514                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 515                         priv = netdev_priv(ndev);                       \
 516                         skb->dev = ndev;                                \
 517                 }                                                       \
 518         } while (0)
 519 #define cpsw_add_mcast(priv, addr)                                      \
 520         do {                                                            \
 521                 if (priv->data.dual_emac) {                             \
 522                         struct cpsw_slave *slave = priv->slaves +       \
 523                                                 priv->emac_port;        \
 524                         int slave_port = cpsw_get_slave_port(priv,      \
 525                                                 slave->slave_num);      \
 526                         cpsw_ale_add_mcast(priv->ale, addr,             \
 527                                 1 << slave_port | 1 << priv->host_port, \
 528                                 ALE_VLAN, slave->port_vlan, 0);         \
 529                 } else {                                                \
 530                         cpsw_ale_add_mcast(priv->ale, addr,             \
 531                                 ALE_ALL_PORTS << priv->host_port,       \
 532                                 0, 0, 0);                               \
 533                 }                                                       \
 534         } while (0)
 535
 536 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 537 {
 538         if (priv->host_port == 0)
 539                 return slave_num + 1;
 540         else
 541                 return slave_num;
 542 }
 543
 544 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 545 {
 546         struct cpsw_priv *priv = netdev_priv(ndev);
 547
 548         if (ndev->flags & IFF_PROMISC) {
 549                 /* Enable promiscuous mode */
 550                 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
 551                 return;
 552         }
 553
 554         /* Clear all mcast from ALE */
 555         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 556
 557         if (!netdev_mc_empty(ndev)) {
 558                 struct netdev_hw_addr *ha;
 559
 560                 /* program multicast address list into ALE register */
 561                 netdev_for_each_mc_addr(ha, ndev) {
 562                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 563                 }
 564         }
 565 }
 566
 567 static void cpsw_intr_enable(struct cpsw_priv *priv)
 568 {
 569         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 570         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 571
 572         cpdma_ctlr_int_ctrl(priv->dma, true);
 573         return;
 574 }
 575
 576 static void cpsw_intr_disable(struct cpsw_priv *priv)
 577 {
 578         __raw_writel(0, &priv->wr_regs->tx_en);
 579         __raw_writel(0, &priv->wr_regs->rx_en);
 580
 581         cpdma_ctlr_int_ctrl(priv->dma, false);
 582         return;
 583 }
 584
 585 void cpsw_tx_handler(void *token, int len, int status)
 586 {
 587         struct sk_buff          *skb = token;
 588         struct net_device       *ndev = skb->dev;
 589         struct cpsw_priv        *priv = netdev_priv(ndev);
 590
 591         /* Check whether the queue is stopped due to stalled tx dma, if the
 592          * queue is stopped then start the queue as we have free desc for tx
 593          */
 594         if (unlikely(netif_queue_stopped(ndev)))
 595                 netif_wake_queue(ndev);
 596         cpts_tx_timestamp(priv->cpts, skb);
 597         priv->stats.tx_packets++;
 598         priv->stats.tx_bytes += len;
 599         dev_kfree_skb_any(skb);
 600 }
 601
 602 void cpsw_rx_handler(void *token, int len, int status)
 603 {
 604         struct sk_buff          *skb = token;
 605         struct sk_buff          *new_skb;
 606         struct net_device       *ndev = skb->dev;
 607         struct cpsw_priv        *priv = netdev_priv(ndev);
 608         int                     ret = 0;
 609
 610         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 611
 612         if (unlikely(status < 0)) {
 613                 /* the interface is going down, skbs are purged */
 614                 dev_kfree_skb_any(skb);
 615                 return;
 616         }
 617
 618         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 619         if (new_skb) {
 620                 skb_put(skb, len);
 621                 cpts_rx_timestamp(priv->cpts, skb);
 622                 skb->protocol = eth_type_trans(skb, ndev);
 623                 netif_receive_skb(skb);
 624                 priv->stats.rx_bytes += len;
 625                 priv->stats.rx_packets++;
 626         } else {
 627                 priv->stats.rx_dropped++;
 628                 new_skb = skb;
 629         }
 630
 631         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 632                         skb_tailroom(new_skb), 0);
 633         if (WARN_ON(ret < 0))
 634                 dev_kfree_skb_any(new_skb);
 635 }
 636
 637 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 638 {
 639         struct cpsw_priv *priv = dev_id;
 640         u32 rx, tx, rx_thresh;
 641
 642         rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat);
 643         rx = __raw_readl(&priv->wr_regs->rx_stat);
 644         tx = __raw_readl(&priv->wr_regs->tx_stat);
 645         if (!rx_thresh && !rx && !tx)
 646                 return IRQ_NONE;
 647
 648         cpsw_intr_disable(priv);
 649         if (priv->irq_enabled == true) {
 650                 cpsw_disable_irq(priv);
 651                 priv->irq_enabled = false;
 652         }
 653
 654         if (netif_running(priv->ndev)) {
 655                 napi_schedule(&priv->napi);
 656                 return IRQ_HANDLED;
 657         }
 658
 659         priv = cpsw_get_slave_priv(priv, 1);
 660         if (!priv)
 661                 return IRQ_NONE;
 662
 663         if (netif_running(priv->ndev)) {
 664                 napi_schedule(&priv->napi);
 665                 return IRQ_HANDLED;
 666         }
 667         return IRQ_NONE;
 668 }
 669
 670 static int cpsw_poll(struct napi_struct *napi, int budget)
 671 {
 672         struct cpsw_priv        *priv = napi_to_priv(napi);
 673         int                     num_tx, num_rx;
 674
 675         num_tx = cpdma_chan_process(priv->txch, 128);
 676         if (num_tx)
 677                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 678
 679         num_rx = cpdma_chan_process(priv->rxch, budget);
 680         if (num_rx < budget) {
 681                 struct cpsw_priv *prim_cpsw;
 682
 683                 napi_complete(napi);
 684                 cpsw_intr_enable(priv);
 685                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 686                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
 687                 if (prim_cpsw->irq_enabled == false) {
 688                         prim_cpsw->irq_enabled = true;
 689                         cpsw_enable_irq(priv);
 690                 }
 691         }
 692
 693         if (num_rx || num_tx)
 694                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 695                          num_rx, num_tx);
 696
 697         return num_rx;
 698 }
 699
 700 static inline void soft_reset(const char *module, void __iomem *reg)
 701 {
 702         unsigned long timeout = jiffies + HZ;
 703
 704         __raw_writel(1, reg);
 705         do {
 706                 cpu_relax();
 707         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 708
 709         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 710 }
 711
 712 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 713                          ((mac)[2] << 16) | ((mac)[3] << 24))
 714 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 715
 716 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 717                                struct cpsw_priv *priv)
 718 {
 719         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 720         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 721 }
 722
 723 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 724                               struct cpsw_priv *priv, bool *link)
 725 {
 726         struct phy_device       *phy = slave->phy;
 727         u32                     mac_control = 0;
 728         u32                     slave_port;
 729
 730         if (!phy)
 731                 return;
 732
 733         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 734
 735         if (phy->link) {
 736                 mac_control = priv->data.mac_control;
 737
 738                 /* enable forwarding */
 739                 cpsw_ale_control_set(priv->ale, slave_port,
 740                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 741
 742                 if (phy->speed == 1000)
 743                         mac_control |= BIT(7);  /* GIGABITEN    */
 744                 if (phy->duplex)
 745                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 746
 747                 /* set speed_in input in case RMII mode is used in 100Mbps */
 748                 if (phy->speed == 100)
 749                         mac_control |= BIT(15);
 750
 751                 *link = true;
 752         } else {
 753                 mac_control = 0;
 754                 /* disable forwarding */
 755                 cpsw_ale_control_set(priv->ale, slave_port,
 756                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 757         }
 758
 759         if (mac_control != slave->mac_control) {
 760                 phy_print_status(phy);
 761                 __raw_writel(mac_control, &slave->sliver->mac_control);
 762         }
 763
 764         slave->mac_control = mac_control;
 765 }
 766
 767 static void cpsw_adjust_link(struct net_device *ndev)
 768 {
 769         struct cpsw_priv        *priv = netdev_priv(ndev);
 770         bool                    link = false;
 771
 772         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 773
 774         if (link) {
 775                 netif_carrier_on(ndev);
 776                 if (netif_running(ndev))
 777                         netif_wake_queue(ndev);
 778         } else {
 779                 netif_carrier_off(ndev);
 780                 netif_stop_queue(ndev);
 781         }
 782 }
 783
 784 static int cpsw_get_coalesce(struct net_device *ndev,
 785                                 struct ethtool_coalesce *coal)
 786 {
 787         struct cpsw_priv *priv = netdev_priv(ndev);
 788
 789         coal->rx_coalesce_usecs = priv->coal_intvl;
 790         return 0;
 791 }
 792
 793 static int cpsw_set_coalesce(struct net_device *ndev,
 794                                 struct ethtool_coalesce *coal)
 795 {
 796         struct cpsw_priv *priv = netdev_priv(ndev);
 797         u32 int_ctrl;
 798         u32 num_interrupts = 0;
 799         u32 prescale = 0;
 800         u32 addnl_dvdr = 1;
 801         u32 coal_intvl = 0;
 802
 803         if (!coal->rx_coalesce_usecs)
 804                 return -EINVAL;
 805
 806         coal_intvl = coal->rx_coalesce_usecs;
 807
 808         int_ctrl =  readl(&priv->wr_regs->int_control);
 809         prescale = priv->bus_freq_mhz * 4;
 810
 811         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 812                 coal_intvl = CPSW_CMINTMIN_INTVL;
 813
 814         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 815                 /* Interrupt pacer works with 4us Pulse, we can
 816                  * throttle further by dilating the 4us pulse.
 817                  */
 818                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 819
 820                 if (addnl_dvdr > 1) {
 821                         prescale *= addnl_dvdr;
 822                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 823                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 824                                                 * addnl_dvdr);
 825                 } else {
 826                         addnl_dvdr = 1;
 827                         coal_intvl = CPSW_CMINTMAX_INTVL;
 828                 }
 829         }
 830
 831         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 832         writel(num_interrupts, &priv->wr_regs->rx_imax);
 833         writel(num_interrupts, &priv->wr_regs->tx_imax);
 834
 835         int_ctrl |= CPSW_INTPACEEN;
 836         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 837         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 838         writel(int_ctrl, &priv->wr_regs->int_control);
 839
 840         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 841         if (priv->data.dual_emac) {
 842                 int i;
 843
 844                 for (i = 0; i < priv->data.slaves; i++) {
 845                         priv = netdev_priv(priv->slaves[i].ndev);
 846                         priv->coal_intvl = coal_intvl;
 847                 }
 848         } else {
 849                 priv->coal_intvl = coal_intvl;
 850         }
 851
 852         return 0;
 853 }
 854
 855 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 856 {
 857         switch (sset) {
 858         case ETH_SS_STATS:
 859                 return CPSW_STATS_LEN;
 860         default:
 861                 return -EOPNOTSUPP;
 862         }
 863 }
 864
 865 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 866 {
 867         u8 *p = data;
 868         int i;
 869
 870         switch (stringset) {
 871         case ETH_SS_STATS:
 872                 for (i = 0; i < CPSW_STATS_LEN; i++) {
 873                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
 874                                ETH_GSTRING_LEN);
 875                         p += ETH_GSTRING_LEN;
 876                 }
 877                 break;
 878         }
 879 }
 880
 881 static void cpsw_get_ethtool_stats(struct net_device *ndev,
 882                                     struct ethtool_stats *stats, u64 *data)
 883 {
 884         struct cpsw_priv *priv = netdev_priv(ndev);
 885         struct cpdma_chan_stats rx_stats;
 886         struct cpdma_chan_stats tx_stats;
 887         u32 val;
 888         u8 *p;
 889         int i;
 890
 891         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
 892         cpdma_chan_get_stats(priv->rxch, &rx_stats);
 893         cpdma_chan_get_stats(priv->txch, &tx_stats);
 894
 895         for (i = 0; i < CPSW_STATS_LEN; i++) {
 896                 switch (cpsw_gstrings_stats[i].type) {
 897                 case CPSW_STATS:
 898                         val = readl(priv->hw_stats +
 899                                     cpsw_gstrings_stats[i].stat_offset);
 900                         data[i] = val;
 901                         break;
 902
 903                 case CPDMA_RX_STATS:
 904                         p = (u8 *)&rx_stats +
 905                                 cpsw_gstrings_stats[i].stat_offset;
 906                         data[i] = *(u32 *)p;
 907                         break;
 908
 909                 case CPDMA_TX_STATS:
 910                         p = (u8 *)&tx_stats +
 911                                 cpsw_gstrings_stats[i].stat_offset;
 912                         data[i] = *(u32 *)p;
 913                         break;
 914                 }
 915         }
 916 }
 917
 918 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
 919 {
 920         static char *leader = "........................................";
 921
 922         if (!val)
 923                 return 0;
 924         else
 925                 return snprintf(buf, maxlen, "%s %s %10d\n", name,
 926                                 leader + strlen(name), val);
 927 }
 928
 929 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
 930 {
 931         u32 i;
 932         u32 usage_count = 0;
 933
 934         if (!priv->data.dual_emac)
 935                 return 0;
 936
 937         for (i = 0; i < priv->data.slaves; i++)
 938                 if (priv->slaves[i].open_stat)
 939                         usage_count++;
 940
 941         return usage_count;
 942 }
 943
 944 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
 945                         struct cpsw_priv *priv, struct sk_buff *skb)
 946 {
 947         if (!priv->data.dual_emac)
 948                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 949                                   skb->len, 0);
 950
 951         if (ndev == cpsw_get_slave_ndev(priv, 0))
 952                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 953                                   skb->len, 1);
 954         else
 955                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 956                                   skb->len, 2);
 957 }
 958
 959 static inline void cpsw_add_dual_emac_def_ale_entries(
 960                 struct cpsw_priv *priv, struct cpsw_slave *slave,
 961                 u32 slave_port)
 962 {
 963         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
 964
 965         if (priv->version == CPSW_VERSION_1)
 966                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
 967         else
 968                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
 969         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
 970                           port_mask, port_mask, 0);
 971         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 972                            port_mask, ALE_VLAN, slave->port_vlan, 0);
 973         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
 974                 priv->host_port, ALE_VLAN, slave->port_vlan);
 975 }
 976
 977 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
 978 {
 979         char name[32];
 980         u32 slave_port;
 981
 982         sprintf(name, "slave-%d", slave->slave_num);
 983
 984         soft_reset(name, &slave->sliver->soft_reset);
 985
 986         /* setup priority mapping */
 987         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
 988
 989         switch (priv->version) {
 990         case CPSW_VERSION_1:
 991                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
 992                 break;
 993         case CPSW_VERSION_2:
 994         case CPSW_VERSION_3:
 995         case CPSW_VERSION_4:
 996                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
 997                 break;
 998         }
 999
1000         /* setup max packet size, and mac address */
1001         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1002         cpsw_set_slave_mac(slave, priv);
1003
1004         slave->mac_control = 0; /* no link yet */
1005
1006         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1007
1008         if (priv->data.dual_emac)
1009                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1010         else
1011                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1012                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1013
1014         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1015                                  &cpsw_adjust_link, slave->data->phy_if);
1016         if (IS_ERR(slave->phy)) {
1017                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1018                         slave->data->phy_id, slave->slave_num);
1019                 slave->phy = NULL;
1020         } else {
1021                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1022                          slave->phy->phy_id);
1023                 phy_start(slave->phy);
1024
1025                 /* Configure GMII_SEL register */
1026                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1027                              slave->slave_num);
1028         }
1029 }
1030
1031 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1032 {
1033         const int vlan = priv->data.default_vlan;
1034         const int port = priv->host_port;
1035         u32 reg;
1036         int i;
1037
1038         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1039                CPSW2_PORT_VLAN;
1040
1041         writel(vlan, &priv->host_port_regs->port_vlan);
1042
1043         for (i = 0; i < priv->data.slaves; i++)
1044                 slave_write(priv->slaves + i, vlan, reg);
1045
1046         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1047                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1048                           (ALE_PORT_1 | ALE_PORT_2) << port);
1049 }
1050
1051 static void cpsw_init_host_port(struct cpsw_priv *priv)
1052 {
1053         u32 control_reg;
1054         u32 fifo_mode;
1055
1056         /* soft reset the controller and initialize ale */
1057         soft_reset("cpsw", &priv->regs->soft_reset);
1058         cpsw_ale_start(priv->ale);
1059
1060         /* switch to vlan unaware mode */
1061         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1062                              CPSW_ALE_VLAN_AWARE);
1063         control_reg = readl(&priv->regs->control);
1064         control_reg |= CPSW_VLAN_AWARE;
1065         writel(control_reg, &priv->regs->control);
1066         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1067                      CPSW_FIFO_NORMAL_MODE;
1068         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1069
1070         /* setup host port priority mapping */
1071         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1072                      &priv->host_port_regs->cpdma_tx_pri_map);
1073         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1074
1075         cpsw_ale_control_set(priv->ale, priv->host_port,
1076                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1077
1078         if (!priv->data.dual_emac) {
1079                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1080                                    0, 0);
1081                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1082                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1083         }
1084 }
1085
1086 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1087 {
1088         if (!slave->phy)
1089                 return;
1090         phy_stop(slave->phy);
1091         phy_disconnect(slave->phy);
1092         slave->phy = NULL;
1093 }
1094
1095 static int cpsw_ndo_open(struct net_device *ndev)
1096 {
1097         struct cpsw_priv *priv = netdev_priv(ndev);
1098         struct cpsw_priv *prim_cpsw;
1099         int i, ret;
1100         u32 reg;
1101
1102         if (!cpsw_common_res_usage_state(priv))
1103                 cpsw_intr_disable(priv);
1104         netif_carrier_off(ndev);
1105
1106         pm_runtime_get_sync(&priv->pdev->dev);
1107
1108         reg = priv->version;
1109
1110         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1111                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1112                  CPSW_RTL_VERSION(reg));
1113
1114         /* initialize host and slave ports */
1115         if (!cpsw_common_res_usage_state(priv))
1116                 cpsw_init_host_port(priv);
1117         for_each_slave(priv, cpsw_slave_open, priv);
1118
1119         /* Add default VLAN */
1120         if (!priv->data.dual_emac)
1121                 cpsw_add_default_vlan(priv);
1122
1123         if (!cpsw_common_res_usage_state(priv)) {
1124                 /* setup tx dma to fixed prio and zero offset */
1125                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1126                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1127
1128                 /* disable priority elevation */
1129                 __raw_writel(0, &priv->regs->ptype);
1130
1131                 /* enable statistics collection only on all ports */
1132                 __raw_writel(0x7, &priv->regs->stat_port_en);
1133
1134                 if (WARN_ON(!priv->data.rx_descs))
1135                         priv->data.rx_descs = 128;
1136
1137                 for (i = 0; i < priv->data.rx_descs; i++) {
1138                         struct sk_buff *skb;
1139
1140                         ret = -ENOMEM;
1141                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1142                                         priv->rx_packet_max, GFP_KERNEL);
1143                         if (!skb)
1144                                 goto err_cleanup;
1145                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1146                                         skb_tailroom(skb), 0);
1147                         if (ret < 0) {
1148                                 kfree_skb(skb);
1149                                 goto err_cleanup;
1150                         }
1151                 }
1152                 /* continue even if we didn't manage to submit all
1153                  * receive descs
1154                  */
1155                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1156         }
1157
1158         /* Enable Interrupt pacing if configured */
1159         if (priv->coal_intvl != 0) {
1160                 struct ethtool_coalesce coal;
1161
1162                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1163                 cpsw_set_coalesce(ndev, &coal);
1164         }
1165
1166         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1167         if (prim_cpsw->irq_enabled == false) {
1168                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1169                         prim_cpsw->irq_enabled = true;
1170                         cpsw_enable_irq(prim_cpsw);
1171                 }
1172         }
1173
1174         cpdma_ctlr_start(priv->dma);
1175         cpsw_intr_enable(priv);
1176         napi_enable(&priv->napi);
1177         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1178         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1179
1180         if (priv->data.dual_emac)
1181                 priv->slaves[priv->emac_port].open_stat = true;
1182         return 0;
1183
1184 err_cleanup:
1185         cpdma_ctlr_stop(priv->dma);
1186         for_each_slave(priv, cpsw_slave_stop, priv);
1187         pm_runtime_put_sync(&priv->pdev->dev);
1188         netif_carrier_off(priv->ndev);
1189         return ret;
1190 }
1191
1192 static int cpsw_ndo_stop(struct net_device *ndev)
1193 {
1194         struct cpsw_priv *priv = netdev_priv(ndev);
1195
1196         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1197         netif_stop_queue(priv->ndev);
1198         napi_disable(&priv->napi);
1199         netif_carrier_off(priv->ndev);
1200
1201         if (cpsw_common_res_usage_state(priv) <= 1) {
1202                 cpsw_intr_disable(priv);
1203                 cpdma_ctlr_int_ctrl(priv->dma, false);
1204                 cpdma_ctlr_stop(priv->dma);
1205                 cpsw_ale_stop(priv->ale);
1206         }
1207         for_each_slave(priv, cpsw_slave_stop, priv);
1208         pm_runtime_put_sync(&priv->pdev->dev);
1209         if (priv->data.dual_emac)
1210                 priv->slaves[priv->emac_port].open_stat = false;
1211         return 0;
1212 }
1213
1214 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1215                                        struct net_device *ndev)
1216 {
1217         struct cpsw_priv *priv = netdev_priv(ndev);
1218         int ret;
1219
1220         ndev->trans_start = jiffies;
1221
1222         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1223                 cpsw_err(priv, tx_err, "packet pad failed\n");
1224                 priv->stats.tx_dropped++;
1225                 return NETDEV_TX_OK;
1226         }
1227
1228         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1229                                 priv->cpts->tx_enable)
1230                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1231
1232         skb_tx_timestamp(skb);
1233
1234         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1235         if (unlikely(ret != 0)) {
1236                 cpsw_err(priv, tx_err, "desc submit failed\n");
1237                 goto fail;
1238         }
1239
1240         /* If there is no more tx desc left free then we need to
1241          * tell the kernel to stop sending us tx frames.
1242          */
1243         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1244                 netif_stop_queue(ndev);
1245
1246         return NETDEV_TX_OK;
1247 fail:
1248         priv->stats.tx_dropped++;
1249         netif_stop_queue(ndev);
1250         return NETDEV_TX_BUSY;
1251 }
1252
1253 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1254 {
1255         /*
1256          * The switch cannot operate in promiscuous mode without substantial
1257          * headache.  For promiscuous mode to work, we would need to put the
1258          * ALE in bypass mode and route all traffic to the host port.
1259          * Subsequently, the host will need to operate as a "bridge", learn,
1260          * and flood as needed.  For now, we simply complain here and
1261          * do nothing about it :-)
1262          */
1263         if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1264                 dev_err(&ndev->dev, "promiscuity ignored!\n");
1265
1266         /*
1267          * The switch cannot filter multicast traffic unless it is configured
1268          * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
1269          * whole bunch of additional logic that this driver does not implement
1270          * at present.
1271          */
1272         if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1273                 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1274 }
1275
1276 #ifdef CONFIG_TI_CPTS
1277
1278 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1279 {
1280         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1281         u32 ts_en, seq_id;
1282
1283         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1284                 slave_write(slave, 0, CPSW1_TS_CTL);
1285                 return;
1286         }
1287
1288         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1289         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1290
1291         if (priv->cpts->tx_enable)
1292                 ts_en |= CPSW_V1_TS_TX_EN;
1293
1294         if (priv->cpts->rx_enable)
1295                 ts_en |= CPSW_V1_TS_RX_EN;
1296
1297         slave_write(slave, ts_en, CPSW1_TS_CTL);
1298         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1299 }
1300
1301 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1302 {
1303         struct cpsw_slave *slave;
1304         u32 ctrl, mtype;
1305
1306         if (priv->data.dual_emac)
1307                 slave = &priv->slaves[priv->emac_port];
1308         else
1309                 slave = &priv->slaves[priv->data.active_slave];
1310
1311         ctrl = slave_read(slave, CPSW2_CONTROL);
1312         ctrl &= ~CTRL_ALL_TS_MASK;
1313
1314         if (priv->cpts->tx_enable)
1315                 ctrl |= CTRL_TX_TS_BITS;
1316
1317         if (priv->cpts->rx_enable)
1318                 ctrl |= CTRL_RX_TS_BITS;
1319
1320         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1321
1322         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1323         slave_write(slave, ctrl, CPSW2_CONTROL);
1324         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1325 }
1326
1327 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
1328 {
1329         struct cpsw_priv *priv = netdev_priv(dev);
1330         struct cpts *cpts = priv->cpts;
1331         struct hwtstamp_config cfg;
1332
1333         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1334                 return -EFAULT;
1335
1336         /* reserved for future extensions */
1337         if (cfg.flags)
1338                 return -EINVAL;
1339
1340         switch (cfg.tx_type) {
1341         case HWTSTAMP_TX_OFF:
1342                 cpts->tx_enable = 0;
1343                 break;
1344         case HWTSTAMP_TX_ON:
1345                 cpts->tx_enable = 1;
1346                 break;
1347         default:
1348                 return -ERANGE;
1349         }
1350
1351         switch (cfg.rx_filter) {
1352         case HWTSTAMP_FILTER_NONE:
1353                 cpts->rx_enable = 0;
1354                 break;
1355         case HWTSTAMP_FILTER_ALL:
1356         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1357         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1358         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1359                 return -ERANGE;
1360         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1361         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1362         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1363         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1364         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1365         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1366         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1367         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1368         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1369                 cpts->rx_enable = 1;
1370                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1371                 break;
1372         default:
1373                 return -ERANGE;
1374         }
1375
1376         switch (priv->version) {
1377         case CPSW_VERSION_1:
1378                 cpsw_hwtstamp_v1(priv);
1379                 break;
1380         case CPSW_VERSION_2:
1381                 cpsw_hwtstamp_v2(priv);
1382                 break;
1383         default:
1384                 return -ENOTSUPP;
1385         }
1386
1387         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1388 }
1389
1390 #endif /*CONFIG_TI_CPTS*/
1391
1392 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1393 {
1394         struct cpsw_priv *priv = netdev_priv(dev);
1395         struct mii_ioctl_data *data = if_mii(req);
1396         int slave_no = cpsw_slave_index(priv);
1397
1398         if (!netif_running(dev))
1399                 return -EINVAL;
1400
1401         switch (cmd) {
1402 #ifdef CONFIG_TI_CPTS
1403         case SIOCSHWTSTAMP:
1404                 return cpsw_hwtstamp_ioctl(dev, req);
1405 #endif
1406         case SIOCGMIIPHY:
1407                 data->phy_id = priv->slaves[slave_no].phy->addr;
1408                 break;
1409         default:
1410                 return -ENOTSUPP;
1411         }
1412
1413         return 0;
1414 }
1415
1416 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1417 {
1418         struct cpsw_priv *priv = netdev_priv(ndev);
1419
1420         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1421         priv->stats.tx_errors++;
1422         cpsw_intr_disable(priv);
1423         cpdma_ctlr_int_ctrl(priv->dma, false);
1424         cpdma_chan_stop(priv->txch);
1425         cpdma_chan_start(priv->txch);
1426         cpdma_ctlr_int_ctrl(priv->dma, true);
1427         cpsw_intr_enable(priv);
1428         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1429         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1430
1431 }
1432
1433 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1434 {
1435         struct cpsw_priv *priv = netdev_priv(ndev);
1436         struct sockaddr *addr = (struct sockaddr *)p;
1437         int flags = 0;
1438         u16 vid = 0;
1439
1440         if (!is_valid_ether_addr(addr->sa_data))
1441                 return -EADDRNOTAVAIL;
1442
1443         if (priv->data.dual_emac) {
1444                 vid = priv->slaves[priv->emac_port].port_vlan;
1445                 flags = ALE_VLAN;
1446         }
1447
1448         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1449                            flags, vid);
1450         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1451                            flags, vid);
1452
1453         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1454         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1455         for_each_slave(priv, cpsw_set_slave_mac, priv);
1456
1457         return 0;
1458 }
1459
1460 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1461 {
1462         struct cpsw_priv *priv = netdev_priv(ndev);
1463         return &priv->stats;
1464 }
1465
1466 #ifdef CONFIG_NET_POLL_CONTROLLER
1467 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1468 {
1469         struct cpsw_priv *priv = netdev_priv(ndev);
1470
1471         cpsw_intr_disable(priv);
1472         cpdma_ctlr_int_ctrl(priv->dma, false);
1473         cpsw_interrupt(ndev->irq, priv);
1474         cpdma_ctlr_int_ctrl(priv->dma, true);
1475         cpsw_intr_enable(priv);
1476         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1477         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1478
1479 }
1480 #endif
1481
1482 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1483                                 unsigned short vid)
1484 {
1485         int ret;
1486
1487         ret = cpsw_ale_add_vlan(priv->ale, vid,
1488                                 ALE_ALL_PORTS << priv->host_port,
1489                                 0, ALE_ALL_PORTS << priv->host_port,
1490                                 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1491         if (ret != 0)
1492                 return ret;
1493
1494         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1495                                  priv->host_port, ALE_VLAN, vid);
1496         if (ret != 0)
1497                 goto clean_vid;
1498
1499         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1500                                  ALE_ALL_PORTS << priv->host_port,
1501                                  ALE_VLAN, vid, 0);
1502         if (ret != 0)
1503                 goto clean_vlan_ucast;
1504         return 0;
1505
1506 clean_vlan_ucast:
1507         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1508                             priv->host_port, ALE_VLAN, vid);
1509 clean_vid:
1510         cpsw_ale_del_vlan(priv->ale, vid, 0);
1511         return ret;
1512 }
1513
1514 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1515                                     __be16 proto, u16 vid)
1516 {
1517         struct cpsw_priv *priv = netdev_priv(ndev);
1518
1519         if (vid == priv->data.default_vlan)
1520                 return 0;
1521
1522         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1523         return cpsw_add_vlan_ale_entry(priv, vid);
1524 }
1525
1526 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1527                                      __be16 proto, u16 vid)
1528 {
1529         struct cpsw_priv *priv = netdev_priv(ndev);
1530         int ret;
1531
1532         if (vid == priv->data.default_vlan)
1533                 return 0;
1534
1535         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1536         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1537         if (ret != 0)
1538                 return ret;
1539
1540         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1541                                  priv->host_port, ALE_VLAN, vid);
1542         if (ret != 0)
1543                 return ret;
1544
1545         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1546                                   0, ALE_VLAN, vid);
1547 }
1548
1549 static const struct net_device_ops cpsw_netdev_ops = {
1550         .ndo_open               = cpsw_ndo_open,
1551         .ndo_stop               = cpsw_ndo_stop,
1552         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1553         .ndo_change_rx_flags    = cpsw_ndo_change_rx_flags,
1554         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1555         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1556         .ndo_validate_addr      = eth_validate_addr,
1557         .ndo_change_mtu         = eth_change_mtu,
1558         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1559         .ndo_get_stats          = cpsw_ndo_get_stats,
1560         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1561 #ifdef CONFIG_NET_POLL_CONTROLLER
1562         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1563 #endif
1564         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1565         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1566 };
1567
1568 static void cpsw_get_drvinfo(struct net_device *ndev,
1569                              struct ethtool_drvinfo *info)
1570 {
1571         struct cpsw_priv *priv = netdev_priv(ndev);
1572
1573         strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1574         strlcpy(info->version, "1.0", sizeof(info->version));
1575         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1576 }
1577
1578 static u32 cpsw_get_msglevel(struct net_device *ndev)
1579 {
1580         struct cpsw_priv *priv = netdev_priv(ndev);
1581         return priv->msg_enable;
1582 }
1583
1584 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1585 {
1586         struct cpsw_priv *priv = netdev_priv(ndev);
1587         priv->msg_enable = value;
1588 }
1589
1590 static int cpsw_get_ts_info(struct net_device *ndev,
1591                             struct ethtool_ts_info *info)
1592 {
1593 #ifdef CONFIG_TI_CPTS
1594         struct cpsw_priv *priv = netdev_priv(ndev);
1595
1596         info->so_timestamping =
1597                 SOF_TIMESTAMPING_TX_HARDWARE |
1598                 SOF_TIMESTAMPING_TX_SOFTWARE |
1599                 SOF_TIMESTAMPING_RX_HARDWARE |
1600                 SOF_TIMESTAMPING_RX_SOFTWARE |
1601                 SOF_TIMESTAMPING_SOFTWARE |
1602                 SOF_TIMESTAMPING_RAW_HARDWARE;
1603         info->phc_index = priv->cpts->phc_index;
1604         info->tx_types =
1605                 (1 << HWTSTAMP_TX_OFF) |
1606                 (1 << HWTSTAMP_TX_ON);
1607         info->rx_filters =
1608                 (1 << HWTSTAMP_FILTER_NONE) |
1609                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1610 #else
1611         info->so_timestamping =
1612                 SOF_TIMESTAMPING_TX_SOFTWARE |
1613                 SOF_TIMESTAMPING_RX_SOFTWARE |
1614                 SOF_TIMESTAMPING_SOFTWARE;
1615         info->phc_index = -1;
1616         info->tx_types = 0;
1617         info->rx_filters = 0;
1618 #endif
1619         return 0;
1620 }
1621
1622 static int cpsw_get_settings(struct net_device *ndev,
1623                              struct ethtool_cmd *ecmd)
1624 {
1625         struct cpsw_priv *priv = netdev_priv(ndev);
1626         int slave_no = cpsw_slave_index(priv);
1627
1628         if (priv->slaves[slave_no].phy)
1629                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1630         else
1631                 return -EOPNOTSUPP;
1632 }
1633
1634 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1635 {
1636         struct cpsw_priv *priv = netdev_priv(ndev);
1637         int slave_no = cpsw_slave_index(priv);
1638
1639         if (priv->slaves[slave_no].phy)
1640                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1641         else
1642                 return -EOPNOTSUPP;
1643 }
1644
1645 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1646 {
1647         struct cpsw_priv *priv = netdev_priv(ndev);
1648         int slave_no = cpsw_slave_index(priv);
1649
1650         wol->supported = 0;
1651         wol->wolopts = 0;
1652
1653         if (priv->slaves[slave_no].phy)
1654                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1655 }
1656
1657 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1658 {
1659         struct cpsw_priv *priv = netdev_priv(ndev);
1660         int slave_no = cpsw_slave_index(priv);
1661
1662         if (priv->slaves[slave_no].phy)
1663                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1664         else
1665                 return -EOPNOTSUPP;
1666 }
1667
1668 static const struct ethtool_ops cpsw_ethtool_ops = {
1669         .get_drvinfo    = cpsw_get_drvinfo,
1670         .get_msglevel   = cpsw_get_msglevel,
1671         .set_msglevel   = cpsw_set_msglevel,
1672         .get_link       = ethtool_op_get_link,
1673         .get_ts_info    = cpsw_get_ts_info,
1674         .get_settings   = cpsw_get_settings,
1675         .set_settings   = cpsw_set_settings,
1676         .get_coalesce   = cpsw_get_coalesce,
1677         .set_coalesce   = cpsw_set_coalesce,
1678         .get_sset_count         = cpsw_get_sset_count,
1679         .get_strings            = cpsw_get_strings,
1680         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1681         .get_wol        = cpsw_get_wol,
1682         .set_wol        = cpsw_set_wol,
1683 };
1684
1685 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1686                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1687 {
1688         void __iomem            *regs = priv->regs;
1689         int                     slave_num = slave->slave_num;
1690         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1691
1692         slave->data     = data;
1693         slave->regs     = regs + slave_reg_ofs;
1694         slave->sliver   = regs + sliver_reg_ofs;
1695         slave->port_vlan = data->dual_emac_res_vlan;
1696 }
1697
1698 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1699                          struct platform_device *pdev)
1700 {
1701         struct device_node *node = pdev->dev.of_node;
1702         struct device_node *slave_node;
1703         int i = 0, ret;
1704         u32 prop;
1705
1706         if (!node)
1707                 return -EINVAL;
1708
1709         if (of_property_read_u32(node, "slaves", &prop)) {
1710                 pr_err("Missing slaves property in the DT.\n");
1711                 return -EINVAL;
1712         }
1713         data->slaves = prop;
1714
1715         if (of_property_read_u32(node, "active_slave", &prop)) {
1716                 pr_err("Missing active_slave property in the DT.\n");
1717                 return -EINVAL;
1718         }
1719         data->active_slave = prop;
1720
1721         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1722                 pr_err("Missing cpts_clock_mult property in the DT.\n");
1723                 return -EINVAL;
1724         }
1725         data->cpts_clock_mult = prop;
1726
1727         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1728                 pr_err("Missing cpts_clock_shift property in the DT.\n");
1729                 return -EINVAL;
1730         }
1731         data->cpts_clock_shift = prop;
1732
1733         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1734                                         * sizeof(struct cpsw_slave_data),
1735                                         GFP_KERNEL);
1736         if (!data->slave_data)
1737                 return -ENOMEM;
1738
1739         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1740                 pr_err("Missing cpdma_channels property in the DT.\n");
1741                 return -EINVAL;
1742         }
1743         data->channels = prop;
1744
1745         if (of_property_read_u32(node, "ale_entries", &prop)) {
1746                 pr_err("Missing ale_entries property in the DT.\n");
1747                 return -EINVAL;
1748         }
1749         data->ale_entries = prop;
1750
1751         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1752                 pr_err("Missing bd_ram_size property in the DT.\n");
1753                 return -EINVAL;
1754         }
1755         data->bd_ram_size = prop;
1756
1757         if (of_property_read_u32(node, "rx_descs", &prop)) {
1758                 pr_err("Missing rx_descs property in the DT.\n");
1759                 return -EINVAL;
1760         }
1761         data->rx_descs = prop;
1762
1763         if (of_property_read_u32(node, "mac_control", &prop)) {
1764                 pr_err("Missing mac_control property in the DT.\n");
1765                 return -EINVAL;
1766         }
1767         data->mac_control = prop;
1768
1769         if (of_property_read_bool(node, "dual_emac"))
1770                 data->dual_emac = 1;
1771
1772         /*
1773          * Populate all the child nodes here...
1774          */
1775         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1776         /* We do not want to force this, as in some cases may not have child */
1777         if (ret)
1778                 pr_warn("Doesn't have any child node\n");
1779
1780         for_each_child_of_node(node, slave_node) {
1781                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1782                 const void *mac_addr = NULL;
1783                 u32 phyid;
1784                 int lenp;
1785                 const __be32 *parp;
1786                 struct device_node *mdio_node;
1787                 struct platform_device *mdio;
1788
1789                 /* This is no slave child node, continue */
1790                 if (strcmp(slave_node->name, "slave"))
1791                         continue;
1792
1793                 parp = of_get_property(slave_node, "phy_id", &lenp);
1794                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1795                         pr_err("Missing slave[%d] phy_id property\n", i);
1796                         return -EINVAL;
1797                 }
1798                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1799                 phyid = be32_to_cpup(parp+1);
1800                 mdio = of_find_device_by_node(mdio_node);
1801                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1802                          PHY_ID_FMT, mdio->name, phyid);
1803
1804                 mac_addr = of_get_mac_address(slave_node);
1805                 if (mac_addr)
1806                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1807
1808                 slave_data->phy_if = of_get_phy_mode(slave_node);
1809
1810                 if (data->dual_emac) {
1811                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1812                                                  &prop)) {
1813                                 pr_err("Missing dual_emac_res_vlan in DT.\n");
1814                                 slave_data->dual_emac_res_vlan = i+1;
1815                                 pr_err("Using %d as Reserved VLAN for %d slave\n",
1816                                        slave_data->dual_emac_res_vlan, i);
1817                         } else {
1818                                 slave_data->dual_emac_res_vlan = prop;
1819                         }
1820                 }
1821
1822                 i++;
1823         }
1824
1825         return 0;
1826 }
1827
1828 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1829                                 struct cpsw_priv *priv)
1830 {
1831         struct cpsw_platform_data       *data = &priv->data;
1832         struct net_device               *ndev;
1833         struct cpsw_priv                *priv_sl2;
1834         int ret = 0, i;
1835
1836         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1837         if (!ndev) {
1838                 pr_err("cpsw: error allocating net_device\n");
1839                 return -ENOMEM;
1840         }
1841
1842         priv_sl2 = netdev_priv(ndev);
1843         spin_lock_init(&priv_sl2->lock);
1844         priv_sl2->data = *data;
1845         priv_sl2->pdev = pdev;
1846         priv_sl2->ndev = ndev;
1847         priv_sl2->dev  = &ndev->dev;
1848         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1849         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1850
1851         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1852                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1853                         ETH_ALEN);
1854                 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1855         } else {
1856                 random_ether_addr(priv_sl2->mac_addr);
1857                 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1858         }
1859         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1860
1861         priv_sl2->slaves = priv->slaves;
1862         priv_sl2->clk = priv->clk;
1863
1864         priv_sl2->coal_intvl = 0;
1865         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1866
1867         priv_sl2->regs = priv->regs;
1868         priv_sl2->host_port = priv->host_port;
1869         priv_sl2->host_port_regs = priv->host_port_regs;
1870         priv_sl2->wr_regs = priv->wr_regs;
1871         priv_sl2->hw_stats = priv->hw_stats;
1872         priv_sl2->dma = priv->dma;
1873         priv_sl2->txch = priv->txch;
1874         priv_sl2->rxch = priv->rxch;
1875         priv_sl2->ale = priv->ale;
1876         priv_sl2->emac_port = 1;
1877         priv->slaves[1].ndev = ndev;
1878         priv_sl2->cpts = priv->cpts;
1879         priv_sl2->version = priv->version;
1880
1881         for (i = 0; i < priv->num_irqs; i++) {
1882                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1883                 priv_sl2->num_irqs = priv->num_irqs;
1884         }
1885         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1886
1887         ndev->netdev_ops = &cpsw_netdev_ops;
1888         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1889         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1890
1891         /* register the network device */
1892         SET_NETDEV_DEV(ndev, &pdev->dev);
1893         ret = register_netdev(ndev);
1894         if (ret) {
1895                 pr_err("cpsw: error registering net device\n");
1896                 free_netdev(ndev);
1897                 ret = -ENODEV;
1898         }
1899
1900         return ret;
1901 }
1902
1903 static int cpsw_probe(struct platform_device *pdev)
1904 {
1905         struct cpsw_platform_data       *data;
1906         struct net_device               *ndev;
1907         struct cpsw_priv                *priv;
1908         struct cpdma_params             dma_params;
1909         struct cpsw_ale_params          ale_params;
1910         void __iomem                    *ss_regs;
1911         struct resource                 *res, *ss_res;
1912         u32 slave_offset, sliver_offset, slave_size;
1913         int ret = 0, i, k = 0;
1914
1915         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1916         if (!ndev) {
1917                 pr_err("error allocating net_device\n");
1918                 return -ENOMEM;
1919         }
1920
1921         platform_set_drvdata(pdev, ndev);
1922         priv = netdev_priv(ndev);
1923         spin_lock_init(&priv->lock);
1924         priv->pdev = pdev;
1925         priv->ndev = ndev;
1926         priv->dev  = &ndev->dev;
1927         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1928         priv->rx_packet_max = max(rx_packet_max, 128);
1929         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
1930         priv->irq_enabled = true;
1931         if (!priv->cpts) {
1932                 pr_err("error allocating cpts\n");
1933                 goto clean_ndev_ret;
1934         }
1935
1936         /*
1937          * This may be required here for child devices.
1938          */
1939         pm_runtime_enable(&pdev->dev);
1940
1941         /* Select default pin state */
1942         pinctrl_pm_select_default_state(&pdev->dev);
1943
1944         if (cpsw_probe_dt(&priv->data, pdev)) {
1945                 pr_err("cpsw: platform data missing\n");
1946                 ret = -ENODEV;
1947                 goto clean_runtime_disable_ret;
1948         }
1949         data = &priv->data;
1950
1951         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1952                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1953                 pr_info("Detected MACID = %pM\n", priv->mac_addr);
1954         } else {
1955                 eth_random_addr(priv->mac_addr);
1956                 pr_info("Random MACID = %pM\n", priv->mac_addr);
1957         }
1958
1959         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1960
1961         priv->slaves = devm_kzalloc(&pdev->dev,
1962                                     sizeof(struct cpsw_slave) * data->slaves,
1963                                     GFP_KERNEL);
1964         if (!priv->slaves) {
1965                 ret = -ENOMEM;
1966                 goto clean_runtime_disable_ret;
1967         }
1968         for (i = 0; i < data->slaves; i++)
1969                 priv->slaves[i].slave_num = i;
1970
1971         priv->slaves[0].ndev = ndev;
1972         priv->emac_port = 0;
1973
1974         priv->clk = devm_clk_get(&pdev->dev, "fck");
1975         if (IS_ERR(priv->clk)) {
1976                 dev_err(priv->dev, "fck is not found\n");
1977                 ret = -ENODEV;
1978                 goto clean_runtime_disable_ret;
1979         }
1980         priv->coal_intvl = 0;
1981         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
1982
1983         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1984         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
1985         if (IS_ERR(ss_regs)) {
1986                 ret = PTR_ERR(ss_regs);
1987                 goto clean_runtime_disable_ret;
1988         }
1989         priv->regs = ss_regs;
1990         priv->version = __raw_readl(&priv->regs->id_ver);
1991         priv->host_port = HOST_PORT_NUM;
1992
1993         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1994         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
1995         if (IS_ERR(priv->wr_regs)) {
1996                 ret = PTR_ERR(priv->wr_regs);
1997                 goto clean_runtime_disable_ret;
1998         }
1999
2000         memset(&dma_params, 0, sizeof(dma_params));
2001         memset(&ale_params, 0, sizeof(ale_params));
2002
2003         switch (priv->version) {
2004         case CPSW_VERSION_1:
2005                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2006                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2007                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2008                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2009                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2010                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2011                 slave_offset         = CPSW1_SLAVE_OFFSET;
2012                 slave_size           = CPSW1_SLAVE_SIZE;
2013                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2014                 dma_params.desc_mem_phys = 0;
2015                 break;
2016         case CPSW_VERSION_2:
2017         case CPSW_VERSION_3:
2018         case CPSW_VERSION_4:
2019                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2020                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2021                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2022                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2023                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2024                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2025                 slave_offset         = CPSW2_SLAVE_OFFSET;
2026                 slave_size           = CPSW2_SLAVE_SIZE;
2027                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2028                 dma_params.desc_mem_phys =
2029                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2030                 break;
2031         default:
2032                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2033                 ret = -ENODEV;
2034                 goto clean_runtime_disable_ret;
2035         }
2036         for (i = 0; i < priv->data.slaves; i++) {
2037                 struct cpsw_slave *slave = &priv->slaves[i];
2038                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2039                 slave_offset  += slave_size;
2040                 sliver_offset += SLIVER_SIZE;
2041         }
2042
2043         dma_params.dev          = &pdev->dev;
2044         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2045         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2046         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2047         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2048         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2049
2050         dma_params.num_chan             = data->channels;
2051         dma_params.has_soft_reset       = true;
2052         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2053         dma_params.desc_mem_size        = data->bd_ram_size;
2054         dma_params.desc_align           = 16;
2055         dma_params.has_ext_regs         = true;
2056         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2057
2058         priv->dma = cpdma_ctlr_create(&dma_params);
2059         if (!priv->dma) {
2060                 dev_err(priv->dev, "error initializing dma\n");
2061                 ret = -ENOMEM;
2062                 goto clean_runtime_disable_ret;
2063         }
2064
2065         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2066                                        cpsw_tx_handler);
2067         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2068                                        cpsw_rx_handler);
2069
2070         if (WARN_ON(!priv->txch || !priv->rxch)) {
2071                 dev_err(priv->dev, "error initializing dma channels\n");
2072                 ret = -ENOMEM;
2073                 goto clean_dma_ret;
2074         }
2075
2076         ale_params.dev                  = &ndev->dev;
2077         ale_params.ale_ageout           = ale_ageout;
2078         ale_params.ale_entries          = data->ale_entries;
2079         ale_params.ale_ports            = data->slaves;
2080
2081         priv->ale = cpsw_ale_create(&ale_params);
2082         if (!priv->ale) {
2083                 dev_err(priv->dev, "error initializing ale engine\n");
2084                 ret = -ENODEV;
2085                 goto clean_dma_ret;
2086         }
2087
2088         ndev->irq = platform_get_irq(pdev, 0);
2089         if (ndev->irq < 0) {
2090                 dev_err(priv->dev, "error getting irq resource\n");
2091                 ret = -ENOENT;
2092                 goto clean_ale_ret;
2093         }
2094
2095         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2096                 for (i = res->start; i <= res->end; i++) {
2097                         if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0,
2098                                              dev_name(priv->dev), priv)) {
2099                                 dev_err(priv->dev, "error attaching irq\n");
2100                                 goto clean_ale_ret;
2101                         }
2102                         priv->irqs_table[k] = i;
2103                         priv->num_irqs = k + 1;
2104                 }
2105                 k++;
2106         }
2107
2108         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2109
2110         ndev->netdev_ops = &cpsw_netdev_ops;
2111         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
2112         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2113
2114         /* register the network device */
2115         SET_NETDEV_DEV(ndev, &pdev->dev);
2116         ret = register_netdev(ndev);
2117         if (ret) {
2118                 dev_err(priv->dev, "error registering net device\n");
2119                 ret = -ENODEV;
2120                 goto clean_ale_ret;
2121         }
2122
2123         if (cpts_register(&pdev->dev, priv->cpts,
2124                           data->cpts_clock_mult, data->cpts_clock_shift))
2125                 dev_err(priv->dev, "error registering cpts device\n");
2126
2127         cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
2128                     ss_res->start, ndev->irq);
2129
2130         if (priv->data.dual_emac) {
2131                 ret = cpsw_probe_dual_emac(pdev, priv);
2132                 if (ret) {
2133                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2134                         goto clean_ale_ret;
2135                 }
2136         }
2137
2138         return 0;
2139
2140 clean_ale_ret:
2141         cpsw_ale_destroy(priv->ale);
2142 clean_dma_ret:
2143         cpdma_chan_destroy(priv->txch);
2144         cpdma_chan_destroy(priv->rxch);
2145         cpdma_ctlr_destroy(priv->dma);
2146 clean_runtime_disable_ret:
2147         pm_runtime_disable(&pdev->dev);
2148 clean_ndev_ret:
2149         free_netdev(priv->ndev);
2150         return ret;
2151 }
2152
2153 static int cpsw_remove(struct platform_device *pdev)
2154 {
2155         struct net_device *ndev = platform_get_drvdata(pdev);
2156         struct cpsw_priv *priv = netdev_priv(ndev);
2157
2158         if (priv->data.dual_emac)
2159                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2160         unregister_netdev(ndev);
2161
2162         cpts_unregister(priv->cpts);
2163
2164         cpsw_ale_destroy(priv->ale);
2165         cpdma_chan_destroy(priv->txch);
2166         cpdma_chan_destroy(priv->rxch);
2167         cpdma_ctlr_destroy(priv->dma);
2168         pm_runtime_disable(&pdev->dev);
2169         if (priv->data.dual_emac)
2170                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2171         free_netdev(ndev);
2172         return 0;
2173 }
2174
2175 static int cpsw_suspend(struct device *dev)
2176 {
2177         struct platform_device  *pdev = to_platform_device(dev);
2178         struct net_device       *ndev = platform_get_drvdata(pdev);
2179         struct cpsw_priv        *priv = netdev_priv(ndev);
2180
2181         if (netif_running(ndev))
2182                 cpsw_ndo_stop(ndev);
2183         soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset);
2184         soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
2185         pm_runtime_put_sync(&pdev->dev);
2186
2187         /* Select sleep pin state */
2188         pinctrl_pm_select_sleep_state(&pdev->dev);
2189
2190         return 0;
2191 }
2192
2193 static int cpsw_resume(struct device *dev)
2194 {
2195         struct platform_device  *pdev = to_platform_device(dev);
2196         struct net_device       *ndev = platform_get_drvdata(pdev);
2197
2198         pm_runtime_get_sync(&pdev->dev);
2199
2200         /* Select default pin state */
2201         pinctrl_pm_select_default_state(&pdev->dev);
2202
2203         if (netif_running(ndev))
2204                 cpsw_ndo_open(ndev);
2205         return 0;
2206 }
2207
2208 static const struct dev_pm_ops cpsw_pm_ops = {
2209         .suspend        = cpsw_suspend,
2210         .resume         = cpsw_resume,
2211 };
2212
2213 static const struct of_device_id cpsw_of_mtable[] = {
2214         { .compatible = "ti,cpsw", },
2215         { /* sentinel */ },
2216 };
2217 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2218
2219 static struct platform_driver cpsw_driver = {
2220         .driver = {
2221                 .name    = "cpsw",
2222                 .owner   = THIS_MODULE,
2223                 .pm      = &cpsw_pm_ops,
2224                 .of_match_table = cpsw_of_mtable,
2225         },
2226         .probe = cpsw_probe,
2227         .remove = cpsw_remove,
2228 };
2229
2230 static int __init cpsw_init(void)
2231 {
2232         return platform_driver_register(&cpsw_driver);
2233 }
2234 late_initcall(cpsw_init);
2235
2236 static void __exit cpsw_exit(void)
2237 {
2238         platform_driver_unregister(&cpsw_driver);
2239 }
2240 module_exit(cpsw_exit);
2241
2242 MODULE_LICENSE("GPL");
2243 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2244 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2245 MODULE_DESCRIPTION("TI CPSW Ethernet driver");