drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include "cpsw.h"
  40 #include "cpsw_ale.h"
  41 #include "cpts.h"
  42 #include "davinci_cpdma.h"
  43
  44 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  45                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  46                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  47                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  48                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  49                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  50                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  51                          NETIF_MSG_RX_STATUS)
  52
  53 #define cpsw_info(priv, type, format, ...)              \
  54 do {                                                            \
  55         if (netif_msg_##type(priv) && net_ratelimit())          \
  56                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  57 } while (0)
  58
  59 #define cpsw_err(priv, type, format, ...)               \
  60 do {                                                            \
  61         if (netif_msg_##type(priv) && net_ratelimit())          \
  62                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  63 } while (0)
  64
  65 #define cpsw_dbg(priv, type, format, ...)               \
  66 do {                                                            \
  67         if (netif_msg_##type(priv) && net_ratelimit())          \
  68                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  69 } while (0)
  70
  71 #define cpsw_notice(priv, type, format, ...)            \
  72 do {                                                            \
  73         if (netif_msg_##type(priv) && net_ratelimit())          \
  74                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  75 } while (0)
  76
  77 #define ALE_ALL_PORTS           0x7
  78
  79 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  80 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  81 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  82
  83 #define CPSW_VERSION_1          0x19010a
  84 #define CPSW_VERSION_2          0x19010c
  85 #define CPSW_VERSION_3          0x19010f
  86 #define CPSW_VERSION_4          0x190112
  87
  88 #define HOST_PORT_NUM           0
  89 #define SLIVER_SIZE             0x40
  90
  91 #define CPSW1_HOST_PORT_OFFSET  0x028
  92 #define CPSW1_SLAVE_OFFSET      0x050
  93 #define CPSW1_SLAVE_SIZE        0x040
  94 #define CPSW1_CPDMA_OFFSET      0x100
  95 #define CPSW1_STATERAM_OFFSET   0x200
  96 #define CPSW1_HW_STATS          0x400
  97 #define CPSW1_CPTS_OFFSET       0x500
  98 #define CPSW1_ALE_OFFSET        0x600
  99 #define CPSW1_SLIVER_OFFSET     0x700
 100
 101 #define CPSW2_HOST_PORT_OFFSET  0x108
 102 #define CPSW2_SLAVE_OFFSET      0x200
 103 #define CPSW2_SLAVE_SIZE        0x100
 104 #define CPSW2_CPDMA_OFFSET      0x800
 105 #define CPSW2_HW_STATS          0x900
 106 #define CPSW2_STATERAM_OFFSET   0xa00
 107 #define CPSW2_CPTS_OFFSET       0xc00
 108 #define CPSW2_ALE_OFFSET        0xd00
 109 #define CPSW2_SLIVER_OFFSET     0xd80
 110 #define CPSW2_BD_OFFSET         0x2000
 111
 112 #define CPDMA_RXTHRESH          0x0c0
 113 #define CPDMA_RXFREE            0x0e0
 114 #define CPDMA_TXHDP             0x00
 115 #define CPDMA_RXHDP             0x20
 116 #define CPDMA_TXCP              0x40
 117 #define CPDMA_RXCP              0x60
 118
 119 #define CPSW_POLL_WEIGHT        64
 120 #define CPSW_MIN_PACKET_SIZE    60
 121 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 122
 123 #define RX_PRIORITY_MAPPING     0x76543210
 124 #define TX_PRIORITY_MAPPING     0x33221100
 125 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 126
 127 #define CPSW_VLAN_AWARE         BIT(1)
 128 #define CPSW_ALE_VLAN_AWARE     1
 129
 130 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 131 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 132 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 133
 134 #define CPSW_INTPACEEN          (0x3f << 16)
 135 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 136 #define CPSW_CMINTMAX_CNT       63
 137 #define CPSW_CMINTMIN_CNT       2
 138 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 139 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 140
 141 #define cpsw_enable_irq(priv)   \
 142         do {                    \
 143                 u32 i;          \
 144                 for (i = 0; i < priv->num_irqs; i++) \
 145                         enable_irq(priv->irqs_table[i]); \
 146         } while (0)
 147 #define cpsw_disable_irq(priv)  \
 148         do {                    \
 149                 u32 i;          \
 150                 for (i = 0; i < priv->num_irqs; i++) \
 151                         disable_irq_nosync(priv->irqs_table[i]); \
 152         } while (0)
 153
 154 #define cpsw_slave_index(priv)                          \
 155                 ((priv->data.dual_emac) ? priv->emac_port :     \
 156                 priv->data.active_slave)
 157
 158 static int debug_level;
 159 module_param(debug_level, int, 0);
 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 161
 162 static int ale_ageout = 10;
 163 module_param(ale_ageout, int, 0);
 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 165
 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 167 module_param(rx_packet_max, int, 0);
 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 169
 170 struct cpsw_wr_regs {
 171         u32     id_ver;
 172         u32     soft_reset;
 173         u32     control;
 174         u32     int_control;
 175         u32     rx_thresh_en;
 176         u32     rx_en;
 177         u32     tx_en;
 178         u32     misc_en;
 179         u32     mem_allign1[8];
 180         u32     rx_thresh_stat;
 181         u32     rx_stat;
 182         u32     tx_stat;
 183         u32     misc_stat;
 184         u32     mem_allign2[8];
 185         u32     rx_imax;
 186         u32     tx_imax;
 187
 188 };
 189
 190 struct cpsw_ss_regs {
 191         u32     id_ver;
 192         u32     control;
 193         u32     soft_reset;
 194         u32     stat_port_en;
 195         u32     ptype;
 196         u32     soft_idle;
 197         u32     thru_rate;
 198         u32     gap_thresh;
 199         u32     tx_start_wds;
 200         u32     flow_control;
 201         u32     vlan_ltype;
 202         u32     ts_ltype;
 203         u32     dlr_ltype;
 204 };
 205
 206 /* CPSW_PORT_V1 */
 207 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 208 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 210 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 211 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 213 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 214 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 215
 216 /* CPSW_PORT_V2 */
 217 #define CPSW2_CONTROL       0x00 /* Control Register */
 218 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 219 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 220 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 221 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 222 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 223 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 224
 225 /* CPSW_PORT_V1 and V2 */
 226 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 227 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 228 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 229
 230 /* CPSW_PORT_V2 only */
 231 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 236 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 237 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 238 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 239
 240 /* Bit definitions for the CPSW2_CONTROL register */
 241 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 242 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 243 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 244 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 245 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 246 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 247 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 248 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 249 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 250 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 251 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 252 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 253 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 254 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 255 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 256 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 257 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 258
 259 #define CTRL_V2_TS_BITS \
 260         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 261          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 262
 263 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 264 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 265 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 266
 267
 268 #define CTRL_V3_TS_BITS \
 269         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 270          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 271          TS_LTYPE1_EN)
 272
 273 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 274 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 275 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 276
 277 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 278 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 279 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 280 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 281 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 282
 283 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 284 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 285
 286 /* Bit definitions for the CPSW1_TS_CTL register */
 287 #define CPSW_V1_TS_RX_EN                BIT(0)
 288 #define CPSW_V1_TS_TX_EN                BIT(4)
 289 #define CPSW_V1_MSG_TYPE_OFS            16
 290
 291 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 292 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 293
 294 struct cpsw_host_regs {
 295         u32     max_blks;
 296         u32     blk_cnt;
 297         u32     tx_in_ctl;
 298         u32     port_vlan;
 299         u32     tx_pri_map;
 300         u32     cpdma_tx_pri_map;
 301         u32     cpdma_rx_chan_map;
 302 };
 303
 304 struct cpsw_sliver_regs {
 305         u32     id_ver;
 306         u32     mac_control;
 307         u32     mac_status;
 308         u32     soft_reset;
 309         u32     rx_maxlen;
 310         u32     __reserved_0;
 311         u32     rx_pause;
 312         u32     tx_pause;
 313         u32     __reserved_1;
 314         u32     rx_pri_map;
 315 };
 316
 317 struct cpsw_hw_stats {
 318         u32     rxgoodframes;
 319         u32     rxbroadcastframes;
 320         u32     rxmulticastframes;
 321         u32     rxpauseframes;
 322         u32     rxcrcerrors;
 323         u32     rxaligncodeerrors;
 324         u32     rxoversizedframes;
 325         u32     rxjabberframes;
 326         u32     rxundersizedframes;
 327         u32     rxfragments;
 328         u32     __pad_0[2];
 329         u32     rxoctets;
 330         u32     txgoodframes;
 331         u32     txbroadcastframes;
 332         u32     txmulticastframes;
 333         u32     txpauseframes;
 334         u32     txdeferredframes;
 335         u32     txcollisionframes;
 336         u32     txsinglecollframes;
 337         u32     txmultcollframes;
 338         u32     txexcessivecollisions;
 339         u32     txlatecollisions;
 340         u32     txunderrun;
 341         u32     txcarriersenseerrors;
 342         u32     txoctets;
 343         u32     octetframes64;
 344         u32     octetframes65t127;
 345         u32     octetframes128t255;
 346         u32     octetframes256t511;
 347         u32     octetframes512t1023;
 348         u32     octetframes1024tup;
 349         u32     netoctets;
 350         u32     rxsofoverruns;
 351         u32     rxmofoverruns;
 352         u32     rxdmaoverruns;
 353 };
 354
 355 struct cpsw_slave {
 356         void __iomem                    *regs;
 357         struct cpsw_sliver_regs __iomem *sliver;
 358         int                             slave_num;
 359         u32                             mac_control;
 360         struct cpsw_slave_data          *data;
 361         struct phy_device               *phy;
 362         struct net_device               *ndev;
 363         u32                             port_vlan;
 364         u32                             open_stat;
 365 };
 366
 367 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 368 {
 369         return __raw_readl(slave->regs + offset);
 370 }
 371
 372 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 373 {
 374         __raw_writel(val, slave->regs + offset);
 375 }
 376
 377 struct cpsw_priv {
 378         spinlock_t                      lock;
 379         struct platform_device          *pdev;
 380         struct net_device               *ndev;
 381         struct napi_struct              napi;
 382         struct device                   *dev;
 383         struct cpsw_platform_data       data;
 384         struct cpsw_ss_regs __iomem     *regs;
 385         struct cpsw_wr_regs __iomem     *wr_regs;
 386         u8 __iomem                      *hw_stats;
 387         struct cpsw_host_regs __iomem   *host_port_regs;
 388         u32                             msg_enable;
 389         u32                             version;
 390         u32                             coal_intvl;
 391         u32                             bus_freq_mhz;
 392         int                             rx_packet_max;
 393         int                             host_port;
 394         struct clk                      *clk;
 395         u8                              mac_addr[ETH_ALEN];
 396         struct cpsw_slave               *slaves;
 397         struct cpdma_ctlr               *dma;
 398         struct cpdma_chan               *txch, *rxch;
 399         struct cpsw_ale                 *ale;
 400         bool                            rx_pause;
 401         bool                            tx_pause;
 402         /* snapshot of IRQ numbers */
 403         u32 irqs_table[4];
 404         u32 num_irqs;
 405         bool irq_enabled;
 406         struct cpts *cpts;
 407         u32 emac_port;
 408 };
 409
 410 struct cpsw_stats {
 411         char stat_string[ETH_GSTRING_LEN];
 412         int type;
 413         int sizeof_stat;
 414         int stat_offset;
 415 };
 416
 417 enum {
 418         CPSW_STATS,
 419         CPDMA_RX_STATS,
 420         CPDMA_TX_STATS,
 421 };
 422
 423 #define CPSW_STAT(m)            CPSW_STATS,                             \
 424                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 425                                 offsetof(struct cpsw_hw_stats, m)
 426 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 427                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 428                                 offsetof(struct cpdma_chan_stats, m)
 429 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 430                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 431                                 offsetof(struct cpdma_chan_stats, m)
 432
 433 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 434         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 435         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 436         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 437         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 438         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 439         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 440         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 441         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 442         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 443         { "Rx Fragments", CPSW_STAT(rxfragments) },
 444         { "Rx Octets", CPSW_STAT(rxoctets) },
 445         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 446         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 447         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 448         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 449         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 450         { "Collisions", CPSW_STAT(txcollisionframes) },
 451         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 452         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 453         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 454         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 455         { "Tx Underrun", CPSW_STAT(txunderrun) },
 456         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 457         { "Tx Octets", CPSW_STAT(txoctets) },
 458         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 459         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 460         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 461         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 462         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 463         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 464         { "Net Octets", CPSW_STAT(netoctets) },
 465         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 466         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 467         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 468         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 469         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 470         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 471         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 472         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 473         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 474         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 475         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 476         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 477         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 478         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 479         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 480         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 481         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 482         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 483         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 484         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 485         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 486         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 487         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 488         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 489         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 490         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 491         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 492         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 493         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 494 };
 495
 496 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 497
 498 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 499 #define for_each_slave(priv, func, arg...)                              \
 500         do {                                                            \
 501                 struct cpsw_slave *slave;                               \
 502                 int n;                                                  \
 503                 if (priv->data.dual_emac)                               \
 504                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 505                 else                                                    \
 506                         for (n = (priv)->data.slaves,                   \
 507                                         slave = (priv)->slaves;         \
 508                                         n; n--)                         \
 509                                 (func)(slave++, ##arg);                 \
 510         } while (0)
 511 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 512         (priv->slaves[__slave_no__].ndev)
 513 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 514         ((priv->slaves[__slave_no__].ndev) ?                            \
 515                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 516
 517 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 518         do {                                                            \
 519                 if (!priv->data.dual_emac)                              \
 520                         break;                                          \
 521                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 522                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 523                         priv = netdev_priv(ndev);                       \
 524                         skb->dev = ndev;                                \
 525                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 526                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 527                         priv = netdev_priv(ndev);                       \
 528                         skb->dev = ndev;                                \
 529                 }                                                       \
 530         } while (0)
 531 #define cpsw_add_mcast(priv, addr)                                      \
 532         do {                                                            \
 533                 if (priv->data.dual_emac) {                             \
 534                         struct cpsw_slave *slave = priv->slaves +       \
 535                                                 priv->emac_port;        \
 536                         int slave_port = cpsw_get_slave_port(priv,      \
 537                                                 slave->slave_num);      \
 538                         cpsw_ale_add_mcast(priv->ale, addr,             \
 539                                 1 << slave_port | 1 << priv->host_port, \
 540                                 ALE_VLAN, slave->port_vlan, 0);         \
 541                 } else {                                                \
 542                         cpsw_ale_add_mcast(priv->ale, addr,             \
 543                                 ALE_ALL_PORTS << priv->host_port,       \
 544                                 0, 0, 0);                               \
 545                 }                                                       \
 546         } while (0)
 547
 548 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 549 {
 550         if (priv->host_port == 0)
 551                 return slave_num + 1;
 552         else
 553                 return slave_num;
 554 }
 555
 556 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 557 {
 558         struct cpsw_priv *priv = netdev_priv(ndev);
 559         struct cpsw_ale *ale = priv->ale;
 560         int i;
 561
 562         if (priv->data.dual_emac) {
 563                 bool flag = false;
 564
 565                 /* Enabling promiscuous mode for one interface will be
 566                  * common for both the interface as the interface shares
 567                  * the same hardware resource.
 568                  */
 569                 for (i = 0; i < priv->data.slaves; i++)
 570                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 571                                 flag = true;
 572
 573                 if (!enable && flag) {
 574                         enable = true;
 575                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 576                 }
 577
 578                 if (enable) {
 579                         /* Enable Bypass */
 580                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 581
 582                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 583                 } else {
 584                         /* Disable Bypass */
 585                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 586                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 587                 }
 588         } else {
 589                 if (enable) {
 590                         unsigned long timeout = jiffies + HZ;
 591
 592                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 593                         for (i = 0; i <= priv->data.slaves; i++) {
 594                                 cpsw_ale_control_set(ale, i,
 595                                                      ALE_PORT_NOLEARN, 1);
 596                                 cpsw_ale_control_set(ale, i,
 597                                                      ALE_PORT_NO_SA_UPDATE, 1);
 598                         }
 599
 600                         /* Clear All Untouched entries */
 601                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 602                         do {
 603                                 cpu_relax();
 604                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 605                                         break;
 606                         } while (time_after(timeout, jiffies));
 607                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 608
 609                         /* Clear all mcast from ALE */
 610                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 611                                                  priv->host_port, -1);
 612
 613                         /* Flood All Unicast Packets to Host port */
 614                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 615                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 616                 } else {
 617                         /* Don't Flood All Unicast Packets to Host port */
 618                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 619
 620                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 621                         for (i = 0; i <= priv->data.slaves; i++) {
 622                                 cpsw_ale_control_set(ale, i,
 623                                                      ALE_PORT_NOLEARN, 0);
 624                                 cpsw_ale_control_set(ale, i,
 625                                                      ALE_PORT_NO_SA_UPDATE, 0);
 626                         }
 627                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 628                 }
 629         }
 630 }
 631
 632 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 633 {
 634         struct cpsw_priv *priv = netdev_priv(ndev);
 635         int vid;
 636
 637         if (priv->data.dual_emac)
 638                 vid = priv->slaves[priv->emac_port].port_vlan;
 639         else
 640                 vid = priv->data.default_vlan;
 641
 642         if (ndev->flags & IFF_PROMISC) {
 643                 /* Enable promiscuous mode */
 644                 cpsw_set_promiscious(ndev, true);
 645                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 646                 return;
 647         } else {
 648                 /* Disable promiscuous mode */
 649                 cpsw_set_promiscious(ndev, false);
 650         }
 651
 652         /* Restore allmulti on vlans if necessary */
 653         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 654
 655         /* Clear all mcast from ALE */
 656         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
 657                                  vid);
 658
 659         if (!netdev_mc_empty(ndev)) {
 660                 struct netdev_hw_addr *ha;
 661
 662                 /* program multicast address list into ALE register */
 663                 netdev_for_each_mc_addr(ha, ndev) {
 664                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 665                 }
 666         }
 667 }
 668
 669 static void cpsw_intr_enable(struct cpsw_priv *priv)
 670 {
 671         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 672         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 673
 674         cpdma_ctlr_int_ctrl(priv->dma, true);
 675         return;
 676 }
 677
 678 static void cpsw_intr_disable(struct cpsw_priv *priv)
 679 {
 680         __raw_writel(0, &priv->wr_regs->tx_en);
 681         __raw_writel(0, &priv->wr_regs->rx_en);
 682
 683         cpdma_ctlr_int_ctrl(priv->dma, false);
 684         return;
 685 }
 686
 687 static void cpsw_tx_handler(void *token, int len, int status)
 688 {
 689         struct sk_buff          *skb = token;
 690         struct net_device       *ndev = skb->dev;
 691         struct cpsw_priv        *priv = netdev_priv(ndev);
 692
 693         /* Check whether the queue is stopped due to stalled tx dma, if the
 694          * queue is stopped then start the queue as we have free desc for tx
 695          */
 696         if (unlikely(netif_queue_stopped(ndev)))
 697                 netif_wake_queue(ndev);
 698         cpts_tx_timestamp(priv->cpts, skb);
 699         ndev->stats.tx_packets++;
 700         ndev->stats.tx_bytes += len;
 701         dev_kfree_skb_any(skb);
 702 }
 703
 704 static void cpsw_rx_handler(void *token, int len, int status)
 705 {
 706         struct sk_buff          *skb = token;
 707         struct sk_buff          *new_skb;
 708         struct net_device       *ndev = skb->dev;
 709         struct cpsw_priv        *priv = netdev_priv(ndev);
 710         int                     ret = 0;
 711
 712         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 713
 714         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 715                 bool ndev_status = false;
 716                 struct cpsw_slave *slave = priv->slaves;
 717                 int n;
 718
 719                 if (priv->data.dual_emac) {
 720                         /* In dual emac mode check for all interfaces */
 721                         for (n = priv->data.slaves; n; n--, slave++)
 722                                 if (netif_running(slave->ndev))
 723                                         ndev_status = true;
 724                 }
 725
 726                 if (ndev_status && (status >= 0)) {
 727                         /* The packet received is for the interface which
 728                          * is already down and the other interface is up
 729                          * and running, instead of freeing which results
 730                          * in reducing of the number of rx descriptor in
 731                          * DMA engine, requeue skb back to cpdma.
 732                          */
 733                         new_skb = skb;
 734                         goto requeue;
 735                 }
 736
 737                 /* the interface is going down, skbs are purged */
 738                 dev_kfree_skb_any(skb);
 739                 return;
 740         }
 741
 742         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 743         if (new_skb) {
 744                 skb_put(skb, len);
 745                 cpts_rx_timestamp(priv->cpts, skb);
 746                 skb->protocol = eth_type_trans(skb, ndev);
 747                 netif_receive_skb(skb);
 748                 ndev->stats.rx_bytes += len;
 749                 ndev->stats.rx_packets++;
 750         } else {
 751                 ndev->stats.rx_dropped++;
 752                 new_skb = skb;
 753         }
 754
 755 requeue:
 756         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 757                         skb_tailroom(new_skb), 0);
 758         if (WARN_ON(ret < 0))
 759                 dev_kfree_skb_any(new_skb);
 760 }
 761
 762 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 763 {
 764         struct cpsw_priv *priv = dev_id;
 765
 766         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 767         cpdma_chan_process(priv->txch, 128);
 768
 769         priv = cpsw_get_slave_priv(priv, 1);
 770         if (priv)
 771                 cpdma_chan_process(priv->txch, 128);
 772
 773         return IRQ_HANDLED;
 774 }
 775
 776 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 777 {
 778         struct cpsw_priv *priv = dev_id;
 779
 780         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 781
 782         cpsw_intr_disable(priv);
 783         if (priv->irq_enabled == true) {
 784                 cpsw_disable_irq(priv);
 785                 priv->irq_enabled = false;
 786         }
 787
 788         if (netif_running(priv->ndev)) {
 789                 napi_schedule(&priv->napi);
 790                 return IRQ_HANDLED;
 791         }
 792
 793         priv = cpsw_get_slave_priv(priv, 1);
 794         if (!priv)
 795                 return IRQ_NONE;
 796
 797         if (netif_running(priv->ndev)) {
 798                 napi_schedule(&priv->napi);
 799                 return IRQ_HANDLED;
 800         }
 801         return IRQ_NONE;
 802 }
 803
 804 static int cpsw_poll(struct napi_struct *napi, int budget)
 805 {
 806         struct cpsw_priv        *priv = napi_to_priv(napi);
 807         int                     num_tx, num_rx;
 808
 809         num_tx = cpdma_chan_process(priv->txch, 128);
 810
 811         num_rx = cpdma_chan_process(priv->rxch, budget);
 812         if (num_rx < budget) {
 813                 struct cpsw_priv *prim_cpsw;
 814
 815                 napi_complete(napi);
 816                 cpsw_intr_enable(priv);
 817                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
 818                 if (prim_cpsw->irq_enabled == false) {
 819                         prim_cpsw->irq_enabled = true;
 820                         cpsw_enable_irq(priv);
 821                 }
 822         }
 823
 824         if (num_rx || num_tx)
 825                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 826                          num_rx, num_tx);
 827
 828         return num_rx;
 829 }
 830
 831 static inline void soft_reset(const char *module, void __iomem *reg)
 832 {
 833         unsigned long timeout = jiffies + HZ;
 834
 835         __raw_writel(1, reg);
 836         do {
 837                 cpu_relax();
 838         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 839
 840         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 841 }
 842
 843 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 844                          ((mac)[2] << 16) | ((mac)[3] << 24))
 845 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 846
 847 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 848                                struct cpsw_priv *priv)
 849 {
 850         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 851         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 852 }
 853
 854 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 855                               struct cpsw_priv *priv, bool *link)
 856 {
 857         struct phy_device       *phy = slave->phy;
 858         u32                     mac_control = 0;
 859         u32                     slave_port;
 860
 861         if (!phy)
 862                 return;
 863
 864         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 865
 866         if (phy->link) {
 867                 mac_control = priv->data.mac_control;
 868
 869                 /* enable forwarding */
 870                 cpsw_ale_control_set(priv->ale, slave_port,
 871                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 872
 873                 if (phy->speed == 1000)
 874                         mac_control |= BIT(7);  /* GIGABITEN    */
 875                 if (phy->duplex)
 876                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 877
 878                 /* set speed_in input in case RMII mode is used in 100Mbps */
 879                 if (phy->speed == 100)
 880                         mac_control |= BIT(15);
 881                 else if (phy->speed == 10)
 882                         mac_control |= BIT(18); /* In Band mode */
 883
 884                 if (priv->rx_pause)
 885                         mac_control |= BIT(3);
 886
 887                 if (priv->tx_pause)
 888                         mac_control |= BIT(4);
 889
 890                 *link = true;
 891         } else {
 892                 mac_control = 0;
 893                 /* disable forwarding */
 894                 cpsw_ale_control_set(priv->ale, slave_port,
 895                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 896         }
 897
 898         if (mac_control != slave->mac_control) {
 899                 phy_print_status(phy);
 900                 __raw_writel(mac_control, &slave->sliver->mac_control);
 901         }
 902
 903         slave->mac_control = mac_control;
 904 }
 905
 906 static void cpsw_adjust_link(struct net_device *ndev)
 907 {
 908         struct cpsw_priv        *priv = netdev_priv(ndev);
 909         bool                    link = false;
 910
 911         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 912
 913         if (link) {
 914                 netif_carrier_on(ndev);
 915                 if (netif_running(ndev))
 916                         netif_wake_queue(ndev);
 917         } else {
 918                 netif_carrier_off(ndev);
 919                 netif_stop_queue(ndev);
 920         }
 921 }
 922
 923 static int cpsw_get_coalesce(struct net_device *ndev,
 924                                 struct ethtool_coalesce *coal)
 925 {
 926         struct cpsw_priv *priv = netdev_priv(ndev);
 927
 928         coal->rx_coalesce_usecs = priv->coal_intvl;
 929         return 0;
 930 }
 931
 932 static int cpsw_set_coalesce(struct net_device *ndev,
 933                                 struct ethtool_coalesce *coal)
 934 {
 935         struct cpsw_priv *priv = netdev_priv(ndev);
 936         u32 int_ctrl;
 937         u32 num_interrupts = 0;
 938         u32 prescale = 0;
 939         u32 addnl_dvdr = 1;
 940         u32 coal_intvl = 0;
 941
 942         coal_intvl = coal->rx_coalesce_usecs;
 943
 944         int_ctrl =  readl(&priv->wr_regs->int_control);
 945         prescale = priv->bus_freq_mhz * 4;
 946
 947         if (!coal->rx_coalesce_usecs) {
 948                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 949                 goto update_return;
 950         }
 951
 952         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 953                 coal_intvl = CPSW_CMINTMIN_INTVL;
 954
 955         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 956                 /* Interrupt pacer works with 4us Pulse, we can
 957                  * throttle further by dilating the 4us pulse.
 958                  */
 959                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 960
 961                 if (addnl_dvdr > 1) {
 962                         prescale *= addnl_dvdr;
 963                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 964                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 965                                                 * addnl_dvdr);
 966                 } else {
 967                         addnl_dvdr = 1;
 968                         coal_intvl = CPSW_CMINTMAX_INTVL;
 969                 }
 970         }
 971
 972         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 973         writel(num_interrupts, &priv->wr_regs->rx_imax);
 974         writel(num_interrupts, &priv->wr_regs->tx_imax);
 975
 976         int_ctrl |= CPSW_INTPACEEN;
 977         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 978         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 979
 980 update_return:
 981         writel(int_ctrl, &priv->wr_regs->int_control);
 982
 983         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 984         if (priv->data.dual_emac) {
 985                 int i;
 986
 987                 for (i = 0; i < priv->data.slaves; i++) {
 988                         priv = netdev_priv(priv->slaves[i].ndev);
 989                         priv->coal_intvl = coal_intvl;
 990                 }
 991         } else {
 992                 priv->coal_intvl = coal_intvl;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 999 {
1000         switch (sset) {
1001         case ETH_SS_STATS:
1002                 return CPSW_STATS_LEN;
1003         default:
1004                 return -EOPNOTSUPP;
1005         }
1006 }
1007
1008 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1009 {
1010         u8 *p = data;
1011         int i;
1012
1013         switch (stringset) {
1014         case ETH_SS_STATS:
1015                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1016                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1017                                ETH_GSTRING_LEN);
1018                         p += ETH_GSTRING_LEN;
1019                 }
1020                 break;
1021         }
1022 }
1023
1024 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1025                                     struct ethtool_stats *stats, u64 *data)
1026 {
1027         struct cpsw_priv *priv = netdev_priv(ndev);
1028         struct cpdma_chan_stats rx_stats;
1029         struct cpdma_chan_stats tx_stats;
1030         u32 val;
1031         u8 *p;
1032         int i;
1033
1034         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1035         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1036         cpdma_chan_get_stats(priv->txch, &tx_stats);
1037
1038         for (i = 0; i < CPSW_STATS_LEN; i++) {
1039                 switch (cpsw_gstrings_stats[i].type) {
1040                 case CPSW_STATS:
1041                         val = readl(priv->hw_stats +
1042                                     cpsw_gstrings_stats[i].stat_offset);
1043                         data[i] = val;
1044                         break;
1045
1046                 case CPDMA_RX_STATS:
1047                         p = (u8 *)&rx_stats +
1048                                 cpsw_gstrings_stats[i].stat_offset;
1049                         data[i] = *(u32 *)p;
1050                         break;
1051
1052                 case CPDMA_TX_STATS:
1053                         p = (u8 *)&tx_stats +
1054                                 cpsw_gstrings_stats[i].stat_offset;
1055                         data[i] = *(u32 *)p;
1056                         break;
1057                 }
1058         }
1059 }
1060
1061 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1062 {
1063         u32 i;
1064         u32 usage_count = 0;
1065
1066         if (!priv->data.dual_emac)
1067                 return 0;
1068
1069         for (i = 0; i < priv->data.slaves; i++)
1070                 if (priv->slaves[i].open_stat)
1071                         usage_count++;
1072
1073         return usage_count;
1074 }
1075
1076 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1077                         struct cpsw_priv *priv, struct sk_buff *skb)
1078 {
1079         if (!priv->data.dual_emac)
1080                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1081                                   skb->len, 0);
1082
1083         if (ndev == cpsw_get_slave_ndev(priv, 0))
1084                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1085                                   skb->len, 1);
1086         else
1087                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1088                                   skb->len, 2);
1089 }
1090
1091 static inline void cpsw_add_dual_emac_def_ale_entries(
1092                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1093                 u32 slave_port)
1094 {
1095         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1096
1097         if (priv->version == CPSW_VERSION_1)
1098                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1099         else
1100                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1101         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1102                           port_mask, port_mask, 0);
1103         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1104                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1105         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1106                 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1107 }
1108
1109 static void soft_reset_slave(struct cpsw_slave *slave)
1110 {
1111         char name[32];
1112
1113         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1114         soft_reset(name, &slave->sliver->soft_reset);
1115 }
1116
1117 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1118 {
1119         u32 slave_port;
1120
1121         soft_reset_slave(slave);
1122
1123         /* setup priority mapping */
1124         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1125
1126         switch (priv->version) {
1127         case CPSW_VERSION_1:
1128                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1129                 break;
1130         case CPSW_VERSION_2:
1131         case CPSW_VERSION_3:
1132         case CPSW_VERSION_4:
1133                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1134                 break;
1135         }
1136
1137         /* setup max packet size, and mac address */
1138         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1139         cpsw_set_slave_mac(slave, priv);
1140
1141         slave->mac_control = 0; /* no link yet */
1142
1143         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1144
1145         if (priv->data.dual_emac)
1146                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1147         else
1148                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1149                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1150
1151         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1152                                  &cpsw_adjust_link, slave->data->phy_if);
1153         if (IS_ERR(slave->phy)) {
1154                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1155                         slave->data->phy_id, slave->slave_num);
1156                 slave->phy = NULL;
1157         } else {
1158                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1159                          slave->phy->phy_id);
1160                 phy_start(slave->phy);
1161
1162                 /* Configure GMII_SEL register */
1163                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1164                              slave->slave_num);
1165         }
1166 }
1167
1168 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1169 {
1170         const int vlan = priv->data.default_vlan;
1171         const int port = priv->host_port;
1172         u32 reg;
1173         int i;
1174         int unreg_mcast_mask;
1175
1176         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1177                CPSW2_PORT_VLAN;
1178
1179         writel(vlan, &priv->host_port_regs->port_vlan);
1180
1181         for (i = 0; i < priv->data.slaves; i++)
1182                 slave_write(priv->slaves + i, vlan, reg);
1183
1184         if (priv->ndev->flags & IFF_ALLMULTI)
1185                 unreg_mcast_mask = ALE_ALL_PORTS;
1186         else
1187                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1188
1189         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1190                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1191                           unreg_mcast_mask << port);
1192 }
1193
1194 static void cpsw_init_host_port(struct cpsw_priv *priv)
1195 {
1196         u32 control_reg;
1197         u32 fifo_mode;
1198
1199         /* soft reset the controller and initialize ale */
1200         soft_reset("cpsw", &priv->regs->soft_reset);
1201         cpsw_ale_start(priv->ale);
1202
1203         /* switch to vlan unaware mode */
1204         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1205                              CPSW_ALE_VLAN_AWARE);
1206         control_reg = readl(&priv->regs->control);
1207         control_reg |= CPSW_VLAN_AWARE;
1208         writel(control_reg, &priv->regs->control);
1209         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1210                      CPSW_FIFO_NORMAL_MODE;
1211         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1212
1213         /* setup host port priority mapping */
1214         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1215                      &priv->host_port_regs->cpdma_tx_pri_map);
1216         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1217
1218         cpsw_ale_control_set(priv->ale, priv->host_port,
1219                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1220
1221         if (!priv->data.dual_emac) {
1222                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1223                                    0, 0);
1224                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1225                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1226         }
1227 }
1228
1229 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1230 {
1231         u32 slave_port;
1232
1233         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1234
1235         if (!slave->phy)
1236                 return;
1237         phy_stop(slave->phy);
1238         phy_disconnect(slave->phy);
1239         slave->phy = NULL;
1240         cpsw_ale_control_set(priv->ale, slave_port,
1241                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1242 }
1243
1244 static int cpsw_ndo_open(struct net_device *ndev)
1245 {
1246         struct cpsw_priv *priv = netdev_priv(ndev);
1247         struct cpsw_priv *prim_cpsw;
1248         int i, ret;
1249         u32 reg;
1250
1251         if (!cpsw_common_res_usage_state(priv))
1252                 cpsw_intr_disable(priv);
1253         netif_carrier_off(ndev);
1254
1255         pm_runtime_get_sync(&priv->pdev->dev);
1256
1257         reg = priv->version;
1258
1259         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1260                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1261                  CPSW_RTL_VERSION(reg));
1262
1263         /* initialize host and slave ports */
1264         if (!cpsw_common_res_usage_state(priv))
1265                 cpsw_init_host_port(priv);
1266         for_each_slave(priv, cpsw_slave_open, priv);
1267
1268         /* Add default VLAN */
1269         if (!priv->data.dual_emac)
1270                 cpsw_add_default_vlan(priv);
1271         else
1272                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1273                                   ALE_ALL_PORTS << priv->host_port,
1274                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1275
1276         if (!cpsw_common_res_usage_state(priv)) {
1277                 /* setup tx dma to fixed prio and zero offset */
1278                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1279                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1280
1281                 /* disable priority elevation */
1282                 __raw_writel(0, &priv->regs->ptype);
1283
1284                 /* enable statistics collection only on all ports */
1285                 __raw_writel(0x7, &priv->regs->stat_port_en);
1286
1287                 /* Enable internal fifo flow control */
1288                 writel(0x7, &priv->regs->flow_control);
1289
1290                 if (WARN_ON(!priv->data.rx_descs))
1291                         priv->data.rx_descs = 128;
1292
1293                 for (i = 0; i < priv->data.rx_descs; i++) {
1294                         struct sk_buff *skb;
1295
1296                         ret = -ENOMEM;
1297                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1298                                         priv->rx_packet_max, GFP_KERNEL);
1299                         if (!skb)
1300                                 goto err_cleanup;
1301                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1302                                         skb_tailroom(skb), 0);
1303                         if (ret < 0) {
1304                                 kfree_skb(skb);
1305                                 goto err_cleanup;
1306                         }
1307                 }
1308                 /* continue even if we didn't manage to submit all
1309                  * receive descs
1310                  */
1311                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1312
1313                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1314                                   priv->data.cpts_clock_mult,
1315                                   priv->data.cpts_clock_shift))
1316                         dev_err(priv->dev, "error registering cpts device\n");
1317
1318         }
1319
1320         /* Enable Interrupt pacing if configured */
1321         if (priv->coal_intvl != 0) {
1322                 struct ethtool_coalesce coal;
1323
1324                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1325                 cpsw_set_coalesce(ndev, &coal);
1326         }
1327
1328         napi_enable(&priv->napi);
1329         cpdma_ctlr_start(priv->dma);
1330         cpsw_intr_enable(priv);
1331
1332         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1333         if (prim_cpsw->irq_enabled == false) {
1334                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1335                         prim_cpsw->irq_enabled = true;
1336                         cpsw_enable_irq(prim_cpsw);
1337                 }
1338         }
1339
1340         if (priv->data.dual_emac)
1341                 priv->slaves[priv->emac_port].open_stat = true;
1342         return 0;
1343
1344 err_cleanup:
1345         cpdma_ctlr_stop(priv->dma);
1346         for_each_slave(priv, cpsw_slave_stop, priv);
1347         pm_runtime_put_sync(&priv->pdev->dev);
1348         netif_carrier_off(priv->ndev);
1349         return ret;
1350 }
1351
1352 static int cpsw_ndo_stop(struct net_device *ndev)
1353 {
1354         struct cpsw_priv *priv = netdev_priv(ndev);
1355
1356         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1357         netif_stop_queue(priv->ndev);
1358         napi_disable(&priv->napi);
1359         netif_carrier_off(priv->ndev);
1360
1361         if (cpsw_common_res_usage_state(priv) <= 1) {
1362                 cpts_unregister(priv->cpts);
1363                 cpsw_intr_disable(priv);
1364                 cpdma_ctlr_stop(priv->dma);
1365                 cpsw_ale_stop(priv->ale);
1366         }
1367         for_each_slave(priv, cpsw_slave_stop, priv);
1368         pm_runtime_put_sync(&priv->pdev->dev);
1369         if (priv->data.dual_emac)
1370                 priv->slaves[priv->emac_port].open_stat = false;
1371         return 0;
1372 }
1373
1374 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1375                                        struct net_device *ndev)
1376 {
1377         struct cpsw_priv *priv = netdev_priv(ndev);
1378         int ret;
1379
1380         ndev->trans_start = jiffies;
1381
1382         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1383                 cpsw_err(priv, tx_err, "packet pad failed\n");
1384                 ndev->stats.tx_dropped++;
1385                 return NETDEV_TX_OK;
1386         }
1387
1388         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1389                                 priv->cpts->tx_enable)
1390                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1391
1392         skb_tx_timestamp(skb);
1393
1394         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1395         if (unlikely(ret != 0)) {
1396                 cpsw_err(priv, tx_err, "desc submit failed\n");
1397                 goto fail;
1398         }
1399
1400         /* If there is no more tx desc left free then we need to
1401          * tell the kernel to stop sending us tx frames.
1402          */
1403         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1404                 netif_stop_queue(ndev);
1405
1406         return NETDEV_TX_OK;
1407 fail:
1408         ndev->stats.tx_dropped++;
1409         netif_stop_queue(ndev);
1410         return NETDEV_TX_BUSY;
1411 }
1412
1413 #ifdef CONFIG_TI_CPTS
1414
1415 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1416 {
1417         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1418         u32 ts_en, seq_id;
1419
1420         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1421                 slave_write(slave, 0, CPSW1_TS_CTL);
1422                 return;
1423         }
1424
1425         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1426         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1427
1428         if (priv->cpts->tx_enable)
1429                 ts_en |= CPSW_V1_TS_TX_EN;
1430
1431         if (priv->cpts->rx_enable)
1432                 ts_en |= CPSW_V1_TS_RX_EN;
1433
1434         slave_write(slave, ts_en, CPSW1_TS_CTL);
1435         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1436 }
1437
1438 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1439 {
1440         struct cpsw_slave *slave;
1441         u32 ctrl, mtype;
1442
1443         if (priv->data.dual_emac)
1444                 slave = &priv->slaves[priv->emac_port];
1445         else
1446                 slave = &priv->slaves[priv->data.active_slave];
1447
1448         ctrl = slave_read(slave, CPSW2_CONTROL);
1449         switch (priv->version) {
1450         case CPSW_VERSION_2:
1451                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1452
1453                 if (priv->cpts->tx_enable)
1454                         ctrl |= CTRL_V2_TX_TS_BITS;
1455
1456                 if (priv->cpts->rx_enable)
1457                         ctrl |= CTRL_V2_RX_TS_BITS;
1458                 break;
1459         case CPSW_VERSION_3:
1460         default:
1461                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1462
1463                 if (priv->cpts->tx_enable)
1464                         ctrl |= CTRL_V3_TX_TS_BITS;
1465
1466                 if (priv->cpts->rx_enable)
1467                         ctrl |= CTRL_V3_RX_TS_BITS;
1468                 break;
1469         }
1470
1471         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1472
1473         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1474         slave_write(slave, ctrl, CPSW2_CONTROL);
1475         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1476 }
1477
1478 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1479 {
1480         struct cpsw_priv *priv = netdev_priv(dev);
1481         struct cpts *cpts = priv->cpts;
1482         struct hwtstamp_config cfg;
1483
1484         if (priv->version != CPSW_VERSION_1 &&
1485             priv->version != CPSW_VERSION_2 &&
1486             priv->version != CPSW_VERSION_3)
1487                 return -EOPNOTSUPP;
1488
1489         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1490                 return -EFAULT;
1491
1492         /* reserved for future extensions */
1493         if (cfg.flags)
1494                 return -EINVAL;
1495
1496         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1497                 return -ERANGE;
1498
1499         switch (cfg.rx_filter) {
1500         case HWTSTAMP_FILTER_NONE:
1501                 cpts->rx_enable = 0;
1502                 break;
1503         case HWTSTAMP_FILTER_ALL:
1504         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1505         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1506         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1507                 return -ERANGE;
1508         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1509         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1510         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1511         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1512         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1513         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1514         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1515         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1516         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1517                 cpts->rx_enable = 1;
1518                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1519                 break;
1520         default:
1521                 return -ERANGE;
1522         }
1523
1524         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1525
1526         switch (priv->version) {
1527         case CPSW_VERSION_1:
1528                 cpsw_hwtstamp_v1(priv);
1529                 break;
1530         case CPSW_VERSION_2:
1531         case CPSW_VERSION_3:
1532                 cpsw_hwtstamp_v2(priv);
1533                 break;
1534         default:
1535                 WARN_ON(1);
1536         }
1537
1538         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1539 }
1540
1541 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1542 {
1543         struct cpsw_priv *priv = netdev_priv(dev);
1544         struct cpts *cpts = priv->cpts;
1545         struct hwtstamp_config cfg;
1546
1547         if (priv->version != CPSW_VERSION_1 &&
1548             priv->version != CPSW_VERSION_2 &&
1549             priv->version != CPSW_VERSION_3)
1550                 return -EOPNOTSUPP;
1551
1552         cfg.flags = 0;
1553         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1554         cfg.rx_filter = (cpts->rx_enable ?
1555                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1556
1557         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1558 }
1559
1560 #endif /*CONFIG_TI_CPTS*/
1561
1562 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1563 {
1564         struct cpsw_priv *priv = netdev_priv(dev);
1565         int slave_no = cpsw_slave_index(priv);
1566
1567         if (!netif_running(dev))
1568                 return -EINVAL;
1569
1570         switch (cmd) {
1571 #ifdef CONFIG_TI_CPTS
1572         case SIOCSHWTSTAMP:
1573                 return cpsw_hwtstamp_set(dev, req);
1574         case SIOCGHWTSTAMP:
1575                 return cpsw_hwtstamp_get(dev, req);
1576 #endif
1577         }
1578
1579         if (!priv->slaves[slave_no].phy)
1580                 return -EOPNOTSUPP;
1581         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1582 }
1583
1584 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1585 {
1586         struct cpsw_priv *priv = netdev_priv(ndev);
1587
1588         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1589         ndev->stats.tx_errors++;
1590         cpsw_intr_disable(priv);
1591         cpdma_chan_stop(priv->txch);
1592         cpdma_chan_start(priv->txch);
1593         cpsw_intr_enable(priv);
1594 }
1595
1596 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1597 {
1598         struct cpsw_priv *priv = netdev_priv(ndev);
1599         struct sockaddr *addr = (struct sockaddr *)p;
1600         int flags = 0;
1601         u16 vid = 0;
1602
1603         if (!is_valid_ether_addr(addr->sa_data))
1604                 return -EADDRNOTAVAIL;
1605
1606         if (priv->data.dual_emac) {
1607                 vid = priv->slaves[priv->emac_port].port_vlan;
1608                 flags = ALE_VLAN;
1609         }
1610
1611         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1612                            flags, vid);
1613         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1614                            flags, vid);
1615
1616         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1617         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1618         for_each_slave(priv, cpsw_set_slave_mac, priv);
1619
1620         return 0;
1621 }
1622
1623 #ifdef CONFIG_NET_POLL_CONTROLLER
1624 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1625 {
1626         struct cpsw_priv *priv = netdev_priv(ndev);
1627
1628         cpsw_intr_disable(priv);
1629         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1630         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1631         cpsw_intr_enable(priv);
1632 }
1633 #endif
1634
1635 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1636                                 unsigned short vid)
1637 {
1638         int ret;
1639         int unreg_mcast_mask = 0;
1640         u32 port_mask;
1641
1642         if (priv->data.dual_emac) {
1643                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1644
1645                 if (priv->ndev->flags & IFF_ALLMULTI)
1646                         unreg_mcast_mask = port_mask;
1647         } else {
1648                 port_mask = ALE_ALL_PORTS;
1649
1650                 if (priv->ndev->flags & IFF_ALLMULTI)
1651                         unreg_mcast_mask = ALE_ALL_PORTS;
1652                 else
1653                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1654         }
1655
1656         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1657                                 unreg_mcast_mask << priv->host_port);
1658         if (ret != 0)
1659                 return ret;
1660
1661         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1662                                  priv->host_port, ALE_VLAN, vid);
1663         if (ret != 0)
1664                 goto clean_vid;
1665
1666         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1667                                  port_mask, ALE_VLAN, vid, 0);
1668         if (ret != 0)
1669                 goto clean_vlan_ucast;
1670         return 0;
1671
1672 clean_vlan_ucast:
1673         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1674                             priv->host_port, ALE_VLAN, vid);
1675 clean_vid:
1676         cpsw_ale_del_vlan(priv->ale, vid, 0);
1677         return ret;
1678 }
1679
1680 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1681                                     __be16 proto, u16 vid)
1682 {
1683         struct cpsw_priv *priv = netdev_priv(ndev);
1684
1685         if (vid == priv->data.default_vlan)
1686                 return 0;
1687
1688         if (priv->data.dual_emac) {
1689                 /* In dual EMAC, reserved VLAN id should not be used for
1690                  * creating VLAN interfaces as this can break the dual
1691                  * EMAC port separation
1692                  */
1693                 int i;
1694
1695                 for (i = 0; i < priv->data.slaves; i++) {
1696                         if (vid == priv->slaves[i].port_vlan)
1697                                 return -EINVAL;
1698                 }
1699         }
1700
1701         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1702         return cpsw_add_vlan_ale_entry(priv, vid);
1703 }
1704
1705 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1706                                      __be16 proto, u16 vid)
1707 {
1708         struct cpsw_priv *priv = netdev_priv(ndev);
1709         int ret;
1710
1711         if (vid == priv->data.default_vlan)
1712                 return 0;
1713
1714         if (priv->data.dual_emac) {
1715                 int i;
1716
1717                 for (i = 0; i < priv->data.slaves; i++) {
1718                         if (vid == priv->slaves[i].port_vlan)
1719                                 return -EINVAL;
1720                 }
1721         }
1722
1723         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1724         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1725         if (ret != 0)
1726                 return ret;
1727
1728         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1729                                  priv->host_port, ALE_VLAN, vid);
1730         if (ret != 0)
1731                 return ret;
1732
1733         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1734                                   0, ALE_VLAN, vid);
1735 }
1736
1737 static const struct net_device_ops cpsw_netdev_ops = {
1738         .ndo_open               = cpsw_ndo_open,
1739         .ndo_stop               = cpsw_ndo_stop,
1740         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1741         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1742         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1743         .ndo_validate_addr      = eth_validate_addr,
1744         .ndo_change_mtu         = eth_change_mtu,
1745         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1746         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1747 #ifdef CONFIG_NET_POLL_CONTROLLER
1748         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1749 #endif
1750         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1751         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1752 };
1753
1754 static int cpsw_get_regs_len(struct net_device *ndev)
1755 {
1756         struct cpsw_priv *priv = netdev_priv(ndev);
1757
1758         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1759 }
1760
1761 static void cpsw_get_regs(struct net_device *ndev,
1762                           struct ethtool_regs *regs, void *p)
1763 {
1764         struct cpsw_priv *priv = netdev_priv(ndev);
1765         u32 *reg = p;
1766
1767         /* update CPSW IP version */
1768         regs->version = priv->version;
1769
1770         cpsw_ale_dump(priv->ale, reg);
1771 }
1772
1773 static void cpsw_get_drvinfo(struct net_device *ndev,
1774                              struct ethtool_drvinfo *info)
1775 {
1776         struct cpsw_priv *priv = netdev_priv(ndev);
1777
1778         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1779         strlcpy(info->version, "1.0", sizeof(info->version));
1780         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1781         info->regdump_len = cpsw_get_regs_len(ndev);
1782 }
1783
1784 static u32 cpsw_get_msglevel(struct net_device *ndev)
1785 {
1786         struct cpsw_priv *priv = netdev_priv(ndev);
1787         return priv->msg_enable;
1788 }
1789
1790 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1791 {
1792         struct cpsw_priv *priv = netdev_priv(ndev);
1793         priv->msg_enable = value;
1794 }
1795
1796 static int cpsw_get_ts_info(struct net_device *ndev,
1797                             struct ethtool_ts_info *info)
1798 {
1799 #ifdef CONFIG_TI_CPTS
1800         struct cpsw_priv *priv = netdev_priv(ndev);
1801
1802         info->so_timestamping =
1803                 SOF_TIMESTAMPING_TX_HARDWARE |
1804                 SOF_TIMESTAMPING_TX_SOFTWARE |
1805                 SOF_TIMESTAMPING_RX_HARDWARE |
1806                 SOF_TIMESTAMPING_RX_SOFTWARE |
1807                 SOF_TIMESTAMPING_SOFTWARE |
1808                 SOF_TIMESTAMPING_RAW_HARDWARE;
1809         info->phc_index = priv->cpts->phc_index;
1810         info->tx_types =
1811                 (1 << HWTSTAMP_TX_OFF) |
1812                 (1 << HWTSTAMP_TX_ON);
1813         info->rx_filters =
1814                 (1 << HWTSTAMP_FILTER_NONE) |
1815                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1816 #else
1817         info->so_timestamping =
1818                 SOF_TIMESTAMPING_TX_SOFTWARE |
1819                 SOF_TIMESTAMPING_RX_SOFTWARE |
1820                 SOF_TIMESTAMPING_SOFTWARE;
1821         info->phc_index = -1;
1822         info->tx_types = 0;
1823         info->rx_filters = 0;
1824 #endif
1825         return 0;
1826 }
1827
1828 static int cpsw_get_settings(struct net_device *ndev,
1829                              struct ethtool_cmd *ecmd)
1830 {
1831         struct cpsw_priv *priv = netdev_priv(ndev);
1832         int slave_no = cpsw_slave_index(priv);
1833
1834         if (priv->slaves[slave_no].phy)
1835                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1836         else
1837                 return -EOPNOTSUPP;
1838 }
1839
1840 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1841 {
1842         struct cpsw_priv *priv = netdev_priv(ndev);
1843         int slave_no = cpsw_slave_index(priv);
1844
1845         if (priv->slaves[slave_no].phy)
1846                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1847         else
1848                 return -EOPNOTSUPP;
1849 }
1850
1851 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1852 {
1853         struct cpsw_priv *priv = netdev_priv(ndev);
1854         int slave_no = cpsw_slave_index(priv);
1855
1856         wol->supported = 0;
1857         wol->wolopts = 0;
1858
1859         if (priv->slaves[slave_no].phy)
1860                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1861 }
1862
1863 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1864 {
1865         struct cpsw_priv *priv = netdev_priv(ndev);
1866         int slave_no = cpsw_slave_index(priv);
1867
1868         if (priv->slaves[slave_no].phy)
1869                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1870         else
1871                 return -EOPNOTSUPP;
1872 }
1873
1874 static void cpsw_get_pauseparam(struct net_device *ndev,
1875                                 struct ethtool_pauseparam *pause)
1876 {
1877         struct cpsw_priv *priv = netdev_priv(ndev);
1878
1879         pause->autoneg = AUTONEG_DISABLE;
1880         pause->rx_pause = priv->rx_pause ? true : false;
1881         pause->tx_pause = priv->tx_pause ? true : false;
1882 }
1883
1884 static int cpsw_set_pauseparam(struct net_device *ndev,
1885                                struct ethtool_pauseparam *pause)
1886 {
1887         struct cpsw_priv *priv = netdev_priv(ndev);
1888         bool link;
1889
1890         priv->rx_pause = pause->rx_pause ? true : false;
1891         priv->tx_pause = pause->tx_pause ? true : false;
1892
1893         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1894
1895         return 0;
1896 }
1897
1898 static const struct ethtool_ops cpsw_ethtool_ops = {
1899         .get_drvinfo    = cpsw_get_drvinfo,
1900         .get_msglevel   = cpsw_get_msglevel,
1901         .set_msglevel   = cpsw_set_msglevel,
1902         .get_link       = ethtool_op_get_link,
1903         .get_ts_info    = cpsw_get_ts_info,
1904         .get_settings   = cpsw_get_settings,
1905         .set_settings   = cpsw_set_settings,
1906         .get_coalesce   = cpsw_get_coalesce,
1907         .set_coalesce   = cpsw_set_coalesce,
1908         .get_sset_count         = cpsw_get_sset_count,
1909         .get_strings            = cpsw_get_strings,
1910         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1911         .get_pauseparam         = cpsw_get_pauseparam,
1912         .set_pauseparam         = cpsw_set_pauseparam,
1913         .get_wol        = cpsw_get_wol,
1914         .set_wol        = cpsw_set_wol,
1915         .get_regs_len   = cpsw_get_regs_len,
1916         .get_regs       = cpsw_get_regs,
1917 };
1918
1919 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1920                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1921 {
1922         void __iomem            *regs = priv->regs;
1923         int                     slave_num = slave->slave_num;
1924         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1925
1926         slave->data     = data;
1927         slave->regs     = regs + slave_reg_ofs;
1928         slave->sliver   = regs + sliver_reg_ofs;
1929         slave->port_vlan = data->dual_emac_res_vlan;
1930 }
1931
1932 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1933                          struct platform_device *pdev)
1934 {
1935         struct device_node *node = pdev->dev.of_node;
1936         struct device_node *slave_node;
1937         int i = 0, ret;
1938         u32 prop;
1939
1940         if (!node)
1941                 return -EINVAL;
1942
1943         if (of_property_read_u32(node, "slaves", &prop)) {
1944                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1945                 return -EINVAL;
1946         }
1947         data->slaves = prop;
1948
1949         if (of_property_read_u32(node, "active_slave", &prop)) {
1950                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1951                 return -EINVAL;
1952         }
1953         data->active_slave = prop;
1954
1955         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1956                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1957                 return -EINVAL;
1958         }
1959         data->cpts_clock_mult = prop;
1960
1961         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1962                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1963                 return -EINVAL;
1964         }
1965         data->cpts_clock_shift = prop;
1966
1967         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1968                                         * sizeof(struct cpsw_slave_data),
1969                                         GFP_KERNEL);
1970         if (!data->slave_data)
1971                 return -ENOMEM;
1972
1973         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1974                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1975                 return -EINVAL;
1976         }
1977         data->channels = prop;
1978
1979         if (of_property_read_u32(node, "ale_entries", &prop)) {
1980                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1981                 return -EINVAL;
1982         }
1983         data->ale_entries = prop;
1984
1985         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1986                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1987                 return -EINVAL;
1988         }
1989         data->bd_ram_size = prop;
1990
1991         if (of_property_read_u32(node, "rx_descs", &prop)) {
1992                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1993                 return -EINVAL;
1994         }
1995         data->rx_descs = prop;
1996
1997         if (of_property_read_u32(node, "mac_control", &prop)) {
1998                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1999                 return -EINVAL;
2000         }
2001         data->mac_control = prop;
2002
2003         if (of_property_read_bool(node, "dual_emac"))
2004                 data->dual_emac = 1;
2005
2006         /*
2007          * Populate all the child nodes here...
2008          */
2009         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2010         /* We do not want to force this, as in some cases may not have child */
2011         if (ret)
2012                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2013
2014         for_each_child_of_node(node, slave_node) {
2015                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2016                 const void *mac_addr = NULL;
2017                 u32 phyid;
2018                 int lenp;
2019                 const __be32 *parp;
2020                 struct device_node *mdio_node;
2021                 struct platform_device *mdio;
2022
2023                 /* This is no slave child node, continue */
2024                 if (strcmp(slave_node->name, "slave"))
2025                         continue;
2026
2027                 parp = of_get_property(slave_node, "phy_id", &lenp);
2028                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2029                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2030                         goto no_phy_slave;
2031                 }
2032                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2033                 phyid = be32_to_cpup(parp+1);
2034                 mdio = of_find_device_by_node(mdio_node);
2035                 of_node_put(mdio_node);
2036                 if (!mdio) {
2037                         dev_err(&pdev->dev, "Missing mdio platform device\n");
2038                         return -EINVAL;
2039                 }
2040                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2041                          PHY_ID_FMT, mdio->name, phyid);
2042
2043                 slave_data->phy_if = of_get_phy_mode(slave_node);
2044                 if (slave_data->phy_if < 0) {
2045                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2046                                 i);
2047                         return slave_data->phy_if;
2048                 }
2049
2050 no_phy_slave:
2051                 mac_addr = of_get_mac_address(slave_node);
2052                 if (mac_addr) {
2053                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2054                 } else {
2055                         if (of_machine_is_compatible("ti,am33xx")) {
2056                                 ret = cpsw_am33xx_cm_get_macid(&pdev->dev,
2057                                                         0x630, i,
2058                                                         slave_data->mac_addr);
2059                                 if (ret)
2060                                         return ret;
2061                         }
2062                 }
2063                 if (data->dual_emac) {
2064                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2065                                                  &prop)) {
2066                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2067                                 slave_data->dual_emac_res_vlan = i+1;
2068                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2069                                         slave_data->dual_emac_res_vlan, i);
2070                         } else {
2071                                 slave_data->dual_emac_res_vlan = prop;
2072                         }
2073                 }
2074
2075                 i++;
2076                 if (i == data->slaves)
2077                         break;
2078         }
2079
2080         return 0;
2081 }
2082
2083 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2084                                 struct cpsw_priv *priv)
2085 {
2086         struct cpsw_platform_data       *data = &priv->data;
2087         struct net_device               *ndev;
2088         struct cpsw_priv                *priv_sl2;
2089         int ret = 0, i;
2090
2091         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2092         if (!ndev) {
2093                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2094                 return -ENOMEM;
2095         }
2096
2097         priv_sl2 = netdev_priv(ndev);
2098         spin_lock_init(&priv_sl2->lock);
2099         priv_sl2->data = *data;
2100         priv_sl2->pdev = pdev;
2101         priv_sl2->ndev = ndev;
2102         priv_sl2->dev  = &ndev->dev;
2103         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2104         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2105
2106         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2107                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2108                         ETH_ALEN);
2109                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2110         } else {
2111                 random_ether_addr(priv_sl2->mac_addr);
2112                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2113         }
2114         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2115
2116         priv_sl2->slaves = priv->slaves;
2117         priv_sl2->clk = priv->clk;
2118
2119         priv_sl2->coal_intvl = 0;
2120         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2121
2122         priv_sl2->regs = priv->regs;
2123         priv_sl2->host_port = priv->host_port;
2124         priv_sl2->host_port_regs = priv->host_port_regs;
2125         priv_sl2->wr_regs = priv->wr_regs;
2126         priv_sl2->hw_stats = priv->hw_stats;
2127         priv_sl2->dma = priv->dma;
2128         priv_sl2->txch = priv->txch;
2129         priv_sl2->rxch = priv->rxch;
2130         priv_sl2->ale = priv->ale;
2131         priv_sl2->emac_port = 1;
2132         priv->slaves[1].ndev = ndev;
2133         priv_sl2->cpts = priv->cpts;
2134         priv_sl2->version = priv->version;
2135
2136         for (i = 0; i < priv->num_irqs; i++) {
2137                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2138                 priv_sl2->num_irqs = priv->num_irqs;
2139         }
2140         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2141
2142         ndev->netdev_ops = &cpsw_netdev_ops;
2143         ndev->ethtool_ops = &cpsw_ethtool_ops;
2144         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2145
2146         /* register the network device */
2147         SET_NETDEV_DEV(ndev, &pdev->dev);
2148         ret = register_netdev(ndev);
2149         if (ret) {
2150                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2151                 free_netdev(ndev);
2152                 ret = -ENODEV;
2153         }
2154
2155         return ret;
2156 }
2157
2158 static int cpsw_probe(struct platform_device *pdev)
2159 {
2160         struct cpsw_platform_data       *data;
2161         struct net_device               *ndev;
2162         struct cpsw_priv                *priv;
2163         struct cpdma_params             dma_params;
2164         struct cpsw_ale_params          ale_params;
2165         void __iomem                    *ss_regs;
2166         struct resource                 *res, *ss_res;
2167         u32 slave_offset, sliver_offset, slave_size;
2168         int ret = 0, i;
2169         int irq;
2170
2171         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2172         if (!ndev) {
2173                 dev_err(&pdev->dev, "error allocating net_device\n");
2174                 return -ENOMEM;
2175         }
2176
2177         platform_set_drvdata(pdev, ndev);
2178         priv = netdev_priv(ndev);
2179         spin_lock_init(&priv->lock);
2180         priv->pdev = pdev;
2181         priv->ndev = ndev;
2182         priv->dev  = &ndev->dev;
2183         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2184         priv->rx_packet_max = max(rx_packet_max, 128);
2185         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2186         priv->irq_enabled = true;
2187         if (!priv->cpts) {
2188                 dev_err(&pdev->dev, "error allocating cpts\n");
2189                 ret = -ENOMEM;
2190                 goto clean_ndev_ret;
2191         }
2192
2193         /*
2194          * This may be required here for child devices.
2195          */
2196         pm_runtime_enable(&pdev->dev);
2197
2198         /* Select default pin state */
2199         pinctrl_pm_select_default_state(&pdev->dev);
2200
2201         if (cpsw_probe_dt(&priv->data, pdev)) {
2202                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2203                 ret = -ENODEV;
2204                 goto clean_runtime_disable_ret;
2205         }
2206         data = &priv->data;
2207
2208         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2209                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2210                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2211         } else {
2212                 eth_random_addr(priv->mac_addr);
2213                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2214         }
2215
2216         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2217
2218         priv->slaves = devm_kzalloc(&pdev->dev,
2219                                     sizeof(struct cpsw_slave) * data->slaves,
2220                                     GFP_KERNEL);
2221         if (!priv->slaves) {
2222                 ret = -ENOMEM;
2223                 goto clean_runtime_disable_ret;
2224         }
2225         for (i = 0; i < data->slaves; i++)
2226                 priv->slaves[i].slave_num = i;
2227
2228         priv->slaves[0].ndev = ndev;
2229         priv->emac_port = 0;
2230
2231         priv->clk = devm_clk_get(&pdev->dev, "fck");
2232         if (IS_ERR(priv->clk)) {
2233                 dev_err(priv->dev, "fck is not found\n");
2234                 ret = -ENODEV;
2235                 goto clean_runtime_disable_ret;
2236         }
2237         priv->coal_intvl = 0;
2238         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2239
2240         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2241         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2242         if (IS_ERR(ss_regs)) {
2243                 ret = PTR_ERR(ss_regs);
2244                 goto clean_runtime_disable_ret;
2245         }
2246         priv->regs = ss_regs;
2247         priv->host_port = HOST_PORT_NUM;
2248
2249         /* Need to enable clocks with runtime PM api to access module
2250          * registers
2251          */
2252         pm_runtime_get_sync(&pdev->dev);
2253         priv->version = readl(&priv->regs->id_ver);
2254         pm_runtime_put_sync(&pdev->dev);
2255
2256         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2257         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2258         if (IS_ERR(priv->wr_regs)) {
2259                 ret = PTR_ERR(priv->wr_regs);
2260                 goto clean_runtime_disable_ret;
2261         }
2262
2263         memset(&dma_params, 0, sizeof(dma_params));
2264         memset(&ale_params, 0, sizeof(ale_params));
2265
2266         switch (priv->version) {
2267         case CPSW_VERSION_1:
2268                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2269                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2270                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2271                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2272                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2273                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2274                 slave_offset         = CPSW1_SLAVE_OFFSET;
2275                 slave_size           = CPSW1_SLAVE_SIZE;
2276                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2277                 dma_params.desc_mem_phys = 0;
2278                 break;
2279         case CPSW_VERSION_2:
2280         case CPSW_VERSION_3:
2281         case CPSW_VERSION_4:
2282                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2283                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2284                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2285                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2286                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2287                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2288                 slave_offset         = CPSW2_SLAVE_OFFSET;
2289                 slave_size           = CPSW2_SLAVE_SIZE;
2290                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2291                 dma_params.desc_mem_phys =
2292                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2293                 break;
2294         default:
2295                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2296                 ret = -ENODEV;
2297                 goto clean_runtime_disable_ret;
2298         }
2299         for (i = 0; i < priv->data.slaves; i++) {
2300                 struct cpsw_slave *slave = &priv->slaves[i];
2301                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2302                 slave_offset  += slave_size;
2303                 sliver_offset += SLIVER_SIZE;
2304         }
2305
2306         dma_params.dev          = &pdev->dev;
2307         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2308         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2309         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2310         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2311         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2312
2313         dma_params.num_chan             = data->channels;
2314         dma_params.has_soft_reset       = true;
2315         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2316         dma_params.desc_mem_size        = data->bd_ram_size;
2317         dma_params.desc_align           = 16;
2318         dma_params.has_ext_regs         = true;
2319         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2320
2321         priv->dma = cpdma_ctlr_create(&dma_params);
2322         if (!priv->dma) {
2323                 dev_err(priv->dev, "error initializing dma\n");
2324                 ret = -ENOMEM;
2325                 goto clean_runtime_disable_ret;
2326         }
2327
2328         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2329                                        cpsw_tx_handler);
2330         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2331                                        cpsw_rx_handler);
2332
2333         if (WARN_ON(!priv->txch || !priv->rxch)) {
2334                 dev_err(priv->dev, "error initializing dma channels\n");
2335                 ret = -ENOMEM;
2336                 goto clean_dma_ret;
2337         }
2338
2339         ale_params.dev                  = &ndev->dev;
2340         ale_params.ale_ageout           = ale_ageout;
2341         ale_params.ale_entries          = data->ale_entries;
2342         ale_params.ale_ports            = data->slaves;
2343
2344         priv->ale = cpsw_ale_create(&ale_params);
2345         if (!priv->ale) {
2346                 dev_err(priv->dev, "error initializing ale engine\n");
2347                 ret = -ENODEV;
2348                 goto clean_dma_ret;
2349         }
2350
2351         ndev->irq = platform_get_irq(pdev, 1);
2352         if (ndev->irq < 0) {
2353                 dev_err(priv->dev, "error getting irq resource\n");
2354                 ret = -ENOENT;
2355                 goto clean_ale_ret;
2356         }
2357
2358         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2359          * MISC IRQs which are always kept disabled with this driver so
2360          * we will not request them.
2361          *
2362          * If anyone wants to implement support for those, make sure to
2363          * first request and append them to irqs_table array.
2364          */
2365
2366         /* RX IRQ */
2367         irq = platform_get_irq(pdev, 1);
2368         if (irq < 0)
2369                 goto clean_ale_ret;
2370
2371         priv->irqs_table[0] = irq;
2372         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2373                                0, dev_name(&pdev->dev), priv);
2374         if (ret < 0) {
2375                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2376                 goto clean_ale_ret;
2377         }
2378
2379         /* TX IRQ */
2380         irq = platform_get_irq(pdev, 2);
2381         if (irq < 0)
2382                 goto clean_ale_ret;
2383
2384         priv->irqs_table[1] = irq;
2385         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2386                                0, dev_name(&pdev->dev), priv);
2387         if (ret < 0) {
2388                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2389                 goto clean_ale_ret;
2390         }
2391         priv->num_irqs = 2;
2392
2393         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2394
2395         ndev->netdev_ops = &cpsw_netdev_ops;
2396         ndev->ethtool_ops = &cpsw_ethtool_ops;
2397         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2398
2399         /* register the network device */
2400         SET_NETDEV_DEV(ndev, &pdev->dev);
2401         ret = register_netdev(ndev);
2402         if (ret) {
2403                 dev_err(priv->dev, "error registering net device\n");
2404                 ret = -ENODEV;
2405                 goto clean_ale_ret;
2406         }
2407
2408         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2409                     &ss_res->start, ndev->irq);
2410
2411         if (priv->data.dual_emac) {
2412                 ret = cpsw_probe_dual_emac(pdev, priv);
2413                 if (ret) {
2414                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2415                         goto clean_ale_ret;
2416                 }
2417         }
2418
2419         return 0;
2420
2421 clean_ale_ret:
2422         cpsw_ale_destroy(priv->ale);
2423 clean_dma_ret:
2424         cpdma_chan_destroy(priv->txch);
2425         cpdma_chan_destroy(priv->rxch);
2426         cpdma_ctlr_destroy(priv->dma);
2427 clean_runtime_disable_ret:
2428         pm_runtime_disable(&pdev->dev);
2429 clean_ndev_ret:
2430         free_netdev(priv->ndev);
2431         return ret;
2432 }
2433
2434 static int cpsw_remove_child_device(struct device *dev, void *c)
2435 {
2436         struct platform_device *pdev = to_platform_device(dev);
2437
2438         of_device_unregister(pdev);
2439
2440         return 0;
2441 }
2442
2443 static int cpsw_remove(struct platform_device *pdev)
2444 {
2445         struct net_device *ndev = platform_get_drvdata(pdev);
2446         struct cpsw_priv *priv = netdev_priv(ndev);
2447
2448         if (priv->data.dual_emac)
2449                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2450         unregister_netdev(ndev);
2451
2452         cpsw_ale_destroy(priv->ale);
2453         cpdma_chan_destroy(priv->txch);
2454         cpdma_chan_destroy(priv->rxch);
2455         cpdma_ctlr_destroy(priv->dma);
2456         pm_runtime_disable(&pdev->dev);
2457         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2458         if (priv->data.dual_emac)
2459                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2460         free_netdev(ndev);
2461         return 0;
2462 }
2463
2464 #ifdef CONFIG_PM_SLEEP
2465 static int cpsw_suspend(struct device *dev)
2466 {
2467         struct platform_device  *pdev = to_platform_device(dev);
2468         struct net_device       *ndev = platform_get_drvdata(pdev);
2469         struct cpsw_priv        *priv = netdev_priv(ndev);
2470
2471         if (priv->data.dual_emac) {
2472                 int i;
2473
2474                 for (i = 0; i < priv->data.slaves; i++) {
2475                         if (netif_running(priv->slaves[i].ndev))
2476                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2477                         soft_reset_slave(priv->slaves + i);
2478                 }
2479         } else {
2480                 if (netif_running(ndev))
2481                         cpsw_ndo_stop(ndev);
2482                 for_each_slave(priv, soft_reset_slave);
2483         }
2484
2485         pm_runtime_put_sync(&pdev->dev);
2486
2487         /* Select sleep pin state */
2488         pinctrl_pm_select_sleep_state(&pdev->dev);
2489
2490         return 0;
2491 }
2492
2493 static int cpsw_resume(struct device *dev)
2494 {
2495         struct platform_device  *pdev = to_platform_device(dev);
2496         struct net_device       *ndev = platform_get_drvdata(pdev);
2497         struct cpsw_priv        *priv = netdev_priv(ndev);
2498
2499         pm_runtime_get_sync(&pdev->dev);
2500
2501         /* Select default pin state */
2502         pinctrl_pm_select_default_state(&pdev->dev);
2503
2504         if (priv->data.dual_emac) {
2505                 int i;
2506
2507                 for (i = 0; i < priv->data.slaves; i++) {
2508                         if (netif_running(priv->slaves[i].ndev))
2509                                 cpsw_ndo_open(priv->slaves[i].ndev);
2510                 }
2511         } else {
2512                 if (netif_running(ndev))
2513                         cpsw_ndo_open(ndev);
2514         }
2515         return 0;
2516 }
2517 #endif
2518
2519 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2520
2521 static const struct of_device_id cpsw_of_mtable[] = {
2522         { .compatible = "ti,cpsw", },
2523         { /* sentinel */ },
2524 };
2525 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2526
2527 static struct platform_driver cpsw_driver = {
2528         .driver = {
2529                 .name    = "cpsw",
2530                 .pm      = &cpsw_pm_ops,
2531                 .of_match_table = cpsw_of_mtable,
2532         },
2533         .probe = cpsw_probe,
2534         .remove = cpsw_remove,
2535 };
2536
2537 static int __init cpsw_init(void)
2538 {
2539         return platform_driver_register(&cpsw_driver);
2540 }
2541 late_initcall(cpsw_init);
2542
2543 static void __exit cpsw_exit(void)
2544 {
2545         platform_driver_unregister(&cpsw_driver);
2546 }
2547 module_exit(cpsw_exit);
2548
2549 MODULE_LICENSE("GPL");
2550 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2551 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2552 MODULE_DESCRIPTION("TI CPSW Ethernet driver");