2 * Driver for the National Semiconductor DP83640 PHYTER
4 * Copyright (C) 2010 OMICRON electronics GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/crc32.h>
24 #include <linux/ethtool.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/mii.h>
28 #include <linux/module.h>
29 #include <linux/net_tstamp.h>
30 #include <linux/netdevice.h>
31 #include <linux/if_vlan.h>
32 #include <linux/phy.h>
33 #include <linux/ptp_classify.h>
34 #include <linux/ptp_clock_kernel.h>
36 #include "dp83640_reg.h"
38 #define DP83640_PHY_ID 0x20005ce1
46 #define PSF_EVNT 0x4000
52 #define DP83640_N_PINS 12
54 #define MII_DP83640_MICR 0x11
55 #define MII_DP83640_MISR 0x12
57 #define MII_DP83640_MICR_OE 0x1
58 #define MII_DP83640_MICR_IE 0x2
60 #define MII_DP83640_MISR_RHF_INT_EN 0x01
61 #define MII_DP83640_MISR_FHF_INT_EN 0x02
62 #define MII_DP83640_MISR_ANC_INT_EN 0x04
63 #define MII_DP83640_MISR_DUP_INT_EN 0x08
64 #define MII_DP83640_MISR_SPD_INT_EN 0x10
65 #define MII_DP83640_MISR_LINK_INT_EN 0x20
66 #define MII_DP83640_MISR_ED_INT_EN 0x40
67 #define MII_DP83640_MISR_LQ_INT_EN 0x80
69 /* phyter seems to miss the mark by 16 ns */
70 #define ADJTIME_FIX 16
72 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */
74 #if defined(__BIG_ENDIAN)
76 #elif defined(__LITTLE_ENDIAN)
77 #define ENDIAN_FLAG PSF_ENDIAN
80 struct dp83640_skb_info {
86 u16 ns_lo; /* ns[15:0] */
87 u16 ns_hi; /* overflow[1:0], ns[29:16] */
88 u16 sec_lo; /* sec[15:0] */
89 u16 sec_hi; /* sec[31:16] */
90 u16 seqid; /* sequenceId[15:0] */
91 u16 msgtype; /* messageType[3:0], hash[11:0] */
95 u16 ns_lo; /* ns[15:0] */
96 u16 ns_hi; /* overflow[1:0], ns[29:16] */
97 u16 sec_lo; /* sec[15:0] */
98 u16 sec_hi; /* sec[31:16] */
102 struct list_head list;
110 struct dp83640_clock;
112 struct dp83640_private {
113 struct list_head list;
114 struct dp83640_clock *clock;
115 struct phy_device *phydev;
116 struct delayed_work ts_work;
121 /* remember state of cfg0 during calibration */
123 /* remember the last event time stamp */
124 struct phy_txts edata;
125 /* list of rx timestamps */
126 struct list_head rxts;
127 struct list_head rxpool;
128 struct rxts rx_pool_data[MAX_RXTS];
129 /* protects above three fields from concurrent access */
131 /* queues of incoming and outgoing packets */
132 struct sk_buff_head rx_queue;
133 struct sk_buff_head tx_queue;
136 struct dp83640_clock {
137 /* keeps the instance in the 'phyter_clocks' list */
138 struct list_head list;
139 /* we create one clock instance per MII bus */
141 /* protects extended registers from concurrent access */
142 struct mutex extreg_lock;
143 /* remembers which page was last selected */
145 /* our advertised capabilities */
146 struct ptp_clock_info caps;
147 /* protects the three fields below from concurrent access */
148 struct mutex clock_lock;
149 /* the one phyter from which we shall read */
150 struct dp83640_private *chosen;
151 /* list of the other attached phyters, not chosen */
152 struct list_head phylist;
153 /* reference to our PTP hardware clock */
154 struct ptp_clock *ptp_clock;
171 static int chosen_phy = -1;
172 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
173 1, 2, 3, 4, 8, 9, 10, 11
176 module_param(chosen_phy, int, 0444);
177 module_param_array(gpio_tab, ushort, NULL, 0444);
179 MODULE_PARM_DESC(chosen_phy, \
180 "The address of the PHY to use for the ancillary clock features");
181 MODULE_PARM_DESC(gpio_tab, \
182 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
184 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
188 for (i = 0; i < DP83640_N_PINS; i++) {
189 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
193 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
194 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
195 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
200 index = gpio_tab[CALIBRATE_GPIO] - 1;
201 pd[index].func = PTP_PF_PHYSYNC;
204 index = gpio_tab[PEROUT_GPIO] - 1;
205 pd[index].func = PTP_PF_PEROUT;
208 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
209 index = gpio_tab[i] - 1;
210 pd[index].func = PTP_PF_EXTTS;
211 pd[index].chan = i - EXTTS0_GPIO;
215 /* a list of clocks and a mutex to protect it */
216 static LIST_HEAD(phyter_clocks);
217 static DEFINE_MUTEX(phyter_clocks_lock);
219 static void rx_timestamp_work(struct work_struct *work);
221 /* extended register access functions */
223 #define BROADCAST_ADDR 31
225 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
227 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
230 /* Caller must hold extreg_lock. */
231 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
233 struct dp83640_private *dp83640 = phydev->priv;
236 if (dp83640->clock->page != page) {
237 broadcast_write(phydev->bus, PAGESEL, page);
238 dp83640->clock->page = page;
240 val = phy_read(phydev, regnum);
245 /* Caller must hold extreg_lock. */
246 static void ext_write(int broadcast, struct phy_device *phydev,
247 int page, u32 regnum, u16 val)
249 struct dp83640_private *dp83640 = phydev->priv;
251 if (dp83640->clock->page != page) {
252 broadcast_write(phydev->bus, PAGESEL, page);
253 dp83640->clock->page = page;
256 broadcast_write(phydev->bus, regnum, val);
258 phy_write(phydev, regnum, val);
261 /* Caller must hold extreg_lock. */
262 static int tdr_write(int bc, struct phy_device *dev,
263 const struct timespec64 *ts, u16 cmd)
265 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
266 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
267 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
268 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
270 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
275 /* convert phy timestamps into driver timestamps */
277 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
282 sec |= p->sec_hi << 16;
285 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
286 rxts->ns += ((u64)sec) * 1000000000ULL;
287 rxts->seqid = p->seqid;
288 rxts->msgtype = (p->msgtype >> 12) & 0xf;
289 rxts->hash = p->msgtype & 0x0fff;
290 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
293 static u64 phy2txts(struct phy_txts *p)
299 sec |= p->sec_hi << 16;
302 ns |= (p->ns_hi & 0x3fff) << 16;
303 ns += ((u64)sec) * 1000000000ULL;
308 static int periodic_output(struct dp83640_clock *clock,
309 struct ptp_clock_request *clkreq, bool on,
312 struct dp83640_private *dp83640 = clock->chosen;
313 struct phy_device *phydev = dp83640->phydev;
314 u32 sec, nsec, pwidth;
315 u16 gpio, ptp_trig, val;
318 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
327 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
328 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
332 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
336 mutex_lock(&clock->extreg_lock);
337 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
338 ext_write(0, phydev, PAGE4, PTP_CTL, val);
339 mutex_unlock(&clock->extreg_lock);
343 sec = clkreq->perout.start.sec;
344 nsec = clkreq->perout.start.nsec;
345 pwidth = clkreq->perout.period.sec * 1000000000UL;
346 pwidth += clkreq->perout.period.nsec;
349 mutex_lock(&clock->extreg_lock);
351 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
355 ext_write(0, phydev, PAGE4, PTP_CTL, val);
356 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
357 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
358 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
359 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
361 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
362 /* Triggers 0 and 1 has programmable pulsewidth2 */
364 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
365 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
371 ext_write(0, phydev, PAGE4, PTP_CTL, val);
373 mutex_unlock(&clock->extreg_lock);
377 /* ptp clock methods */
379 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
381 struct dp83640_clock *clock =
382 container_of(ptp, struct dp83640_clock, caps);
383 struct phy_device *phydev = clock->chosen->phydev;
394 rate = div_u64(rate, 1953125);
396 hi = (rate >> 16) & PTP_RATE_HI_MASK;
402 mutex_lock(&clock->extreg_lock);
404 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
405 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
407 mutex_unlock(&clock->extreg_lock);
412 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
414 struct dp83640_clock *clock =
415 container_of(ptp, struct dp83640_clock, caps);
416 struct phy_device *phydev = clock->chosen->phydev;
417 struct timespec64 ts;
420 delta += ADJTIME_FIX;
422 ts = ns_to_timespec64(delta);
424 mutex_lock(&clock->extreg_lock);
426 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
428 mutex_unlock(&clock->extreg_lock);
433 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
434 struct timespec64 *ts)
436 struct dp83640_clock *clock =
437 container_of(ptp, struct dp83640_clock, caps);
438 struct phy_device *phydev = clock->chosen->phydev;
441 mutex_lock(&clock->extreg_lock);
443 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
445 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
446 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
447 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
448 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
450 mutex_unlock(&clock->extreg_lock);
452 ts->tv_nsec = val[0] | (val[1] << 16);
453 ts->tv_sec = val[2] | (val[3] << 16);
458 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
459 const struct timespec64 *ts)
461 struct dp83640_clock *clock =
462 container_of(ptp, struct dp83640_clock, caps);
463 struct phy_device *phydev = clock->chosen->phydev;
466 mutex_lock(&clock->extreg_lock);
468 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
470 mutex_unlock(&clock->extreg_lock);
475 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
476 struct ptp_clock_request *rq, int on)
478 struct dp83640_clock *clock =
479 container_of(ptp, struct dp83640_clock, caps);
480 struct phy_device *phydev = clock->chosen->phydev;
482 u16 evnt, event_num, gpio_num;
485 case PTP_CLK_REQ_EXTTS:
486 index = rq->extts.index;
487 if (index >= N_EXT_TS)
489 event_num = EXT_EVENT + index;
490 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
492 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
493 PTP_PF_EXTTS, index);
496 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
497 if (rq->extts.flags & PTP_FALLING_EDGE)
502 mutex_lock(&clock->extreg_lock);
503 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
504 mutex_unlock(&clock->extreg_lock);
507 case PTP_CLK_REQ_PEROUT:
508 if (rq->perout.index >= N_PER_OUT)
510 return periodic_output(clock, rq, on, rq->perout.index);
519 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
520 enum ptp_pin_function func, unsigned int chan)
522 struct dp83640_clock *clock =
523 container_of(ptp, struct dp83640_clock, caps);
525 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
526 !list_empty(&clock->phylist))
529 if (func == PTP_PF_PHYSYNC)
535 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
536 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
538 static void enable_status_frames(struct phy_device *phydev, bool on)
540 struct dp83640_private *dp83640 = phydev->priv;
541 struct dp83640_clock *clock = dp83640->clock;
545 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
547 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
549 mutex_lock(&clock->extreg_lock);
551 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
552 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
554 mutex_unlock(&clock->extreg_lock);
556 if (!phydev->attached_dev) {
557 pr_warn("expected to find an attached netdevice\n");
562 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
563 pr_warn("failed to add mc address\n");
565 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
566 pr_warn("failed to delete mc address\n");
570 static bool is_status_frame(struct sk_buff *skb, int type)
572 struct ethhdr *h = eth_hdr(skb);
574 if (PTP_CLASS_V2_L2 == type &&
575 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
581 static int expired(struct rxts *rxts)
583 return time_after(jiffies, rxts->tmo);
586 /* Caller must hold rx_lock. */
587 static void prune_rx_ts(struct dp83640_private *dp83640)
589 struct list_head *this, *next;
592 list_for_each_safe(this, next, &dp83640->rxts) {
593 rxts = list_entry(this, struct rxts, list);
595 list_del_init(&rxts->list);
596 list_add(&rxts->list, &dp83640->rxpool);
601 /* synchronize the phyters so they act as one clock */
603 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
606 phy_write(phydev, PAGESEL, 0);
607 val = phy_read(phydev, PHYCR2);
612 phy_write(phydev, PHYCR2, val);
613 phy_write(phydev, PAGESEL, init_page);
616 static void recalibrate(struct dp83640_clock *clock)
619 struct phy_txts event_ts;
620 struct timespec64 ts;
621 struct list_head *this;
622 struct dp83640_private *tmp;
623 struct phy_device *master = clock->chosen->phydev;
624 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
626 trigger = CAL_TRIGGER;
627 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
629 pr_err("PHY calibration pin not available - PHY is not calibrated.");
633 mutex_lock(&clock->extreg_lock);
636 * enable broadcast, disable status frames, enable ptp clock
638 list_for_each(this, &clock->phylist) {
639 tmp = list_entry(this, struct dp83640_private, list);
640 enable_broadcast(tmp->phydev, clock->page, 1);
641 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
642 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
643 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
645 enable_broadcast(master, clock->page, 1);
646 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
647 ext_write(0, master, PAGE5, PSF_CFG0, 0);
648 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
651 * enable an event timestamp
653 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
654 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
655 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
657 list_for_each(this, &clock->phylist) {
658 tmp = list_entry(this, struct dp83640_private, list);
659 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
661 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
664 * configure a trigger
666 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
667 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
668 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
669 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
672 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
674 ext_write(0, master, PAGE4, PTP_CTL, val);
679 ext_write(0, master, PAGE4, PTP_CTL, val);
681 /* disable trigger */
682 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
684 ext_write(0, master, PAGE4, PTP_CTL, val);
687 * read out and correct offsets
689 val = ext_read(master, PAGE4, PTP_STS);
690 pr_info("master PTP_STS 0x%04hx\n", val);
691 val = ext_read(master, PAGE4, PTP_ESTS);
692 pr_info("master PTP_ESTS 0x%04hx\n", val);
693 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
694 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
695 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
696 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
697 now = phy2txts(&event_ts);
699 list_for_each(this, &clock->phylist) {
700 tmp = list_entry(this, struct dp83640_private, list);
701 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
702 pr_info("slave PTP_STS 0x%04hx\n", val);
703 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
704 pr_info("slave PTP_ESTS 0x%04hx\n", val);
705 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
706 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
707 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
708 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
709 diff = now - (s64) phy2txts(&event_ts);
710 pr_info("slave offset %lld nanoseconds\n", diff);
712 ts = ns_to_timespec64(diff);
713 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
717 * restore status frames
719 list_for_each(this, &clock->phylist) {
720 tmp = list_entry(this, struct dp83640_private, list);
721 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
723 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
725 mutex_unlock(&clock->extreg_lock);
728 /* time stamping methods */
730 static inline u16 exts_chan_to_edata(int ch)
732 return 1 << ((ch + EXT_EVENT) * 2);
735 static int decode_evnt(struct dp83640_private *dp83640,
736 void *data, int len, u16 ests)
738 struct phy_txts *phy_txts;
739 struct ptp_clock_event event;
741 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
744 /* calculate length of the event timestamp status message */
745 if (ests & MULT_EVNT)
746 parsed = (words + 2) * sizeof(u16);
748 parsed = (words + 1) * sizeof(u16);
750 /* check if enough data is available */
754 if (ests & MULT_EVNT) {
755 ext_status = *(u16 *) data;
756 data += sizeof(ext_status);
761 switch (words) { /* fall through in every case */
763 dp83640->edata.sec_hi = phy_txts->sec_hi;
765 dp83640->edata.sec_lo = phy_txts->sec_lo;
767 dp83640->edata.ns_hi = phy_txts->ns_hi;
769 dp83640->edata.ns_lo = phy_txts->ns_lo;
773 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
774 ext_status = exts_chan_to_edata(i);
777 event.type = PTP_CLOCK_EXTTS;
778 event.timestamp = phy2txts(&dp83640->edata);
780 /* Compensate for input path and synchronization delays */
781 event.timestamp -= 35;
783 for (i = 0; i < N_EXT_TS; i++) {
784 if (ext_status & exts_chan_to_edata(i)) {
786 ptp_clock_event(dp83640->clock->ptp_clock, &event);
793 #define DP83640_PACKET_HASH_OFFSET 20
794 #define DP83640_PACKET_HASH_LEN 10
796 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
799 unsigned int offset = 0;
800 u8 *msgtype, *data = skb_mac_header(skb);
802 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
804 if (type & PTP_CLASS_VLAN)
807 switch (type & PTP_CLASS_PMASK) {
809 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
812 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
821 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
824 if (unlikely(type & PTP_CLASS_V1))
825 msgtype = data + offset + OFF_PTP_CONTROL;
827 msgtype = data + offset;
828 if (rxts->msgtype != (*msgtype & 0xf))
831 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
832 if (rxts->seqid != ntohs(*seqid))
835 hash = ether_crc(DP83640_PACKET_HASH_LEN,
836 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
837 if (rxts->hash != hash)
843 static void decode_rxts(struct dp83640_private *dp83640,
844 struct phy_rxts *phy_rxts)
847 struct skb_shared_hwtstamps *shhwtstamps = NULL;
851 spin_lock_irqsave(&dp83640->rx_lock, flags);
853 prune_rx_ts(dp83640);
855 if (list_empty(&dp83640->rxpool)) {
856 pr_debug("rx timestamp pool is empty\n");
859 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
860 list_del_init(&rxts->list);
861 phy2rxts(phy_rxts, rxts);
863 spin_lock(&dp83640->rx_queue.lock);
864 skb_queue_walk(&dp83640->rx_queue, skb) {
865 struct dp83640_skb_info *skb_info;
867 skb_info = (struct dp83640_skb_info *)skb->cb;
868 if (match(skb, skb_info->ptp_type, rxts)) {
869 __skb_unlink(skb, &dp83640->rx_queue);
870 shhwtstamps = skb_hwtstamps(skb);
871 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
872 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
874 list_add(&rxts->list, &dp83640->rxpool);
878 spin_unlock(&dp83640->rx_queue.lock);
881 list_add_tail(&rxts->list, &dp83640->rxts);
883 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
886 static void decode_txts(struct dp83640_private *dp83640,
887 struct phy_txts *phy_txts)
889 struct skb_shared_hwtstamps shhwtstamps;
893 /* We must already have the skb that triggered this. */
895 skb = skb_dequeue(&dp83640->tx_queue);
898 pr_debug("have timestamp but tx_queue empty\n");
901 ns = phy2txts(phy_txts);
902 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
903 shhwtstamps.hwtstamp = ns_to_ktime(ns);
904 skb_complete_tx_timestamp(skb, &shhwtstamps);
907 static void decode_status_frame(struct dp83640_private *dp83640,
910 struct phy_rxts *phy_rxts;
911 struct phy_txts *phy_txts;
918 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
921 ests = type & 0x0fff;
922 type = type & 0xf000;
926 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
928 phy_rxts = (struct phy_rxts *) ptr;
929 decode_rxts(dp83640, phy_rxts);
930 size = sizeof(*phy_rxts);
932 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
934 phy_txts = (struct phy_txts *) ptr;
935 decode_txts(dp83640, phy_txts);
936 size = sizeof(*phy_txts);
938 } else if (PSF_EVNT == type) {
940 size = decode_evnt(dp83640, ptr, len, ests);
950 static int is_sync(struct sk_buff *skb, int type)
952 u8 *data = skb->data, *msgtype;
953 unsigned int offset = 0;
955 if (type & PTP_CLASS_VLAN)
958 switch (type & PTP_CLASS_PMASK) {
960 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
963 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
972 if (type & PTP_CLASS_V1)
973 offset += OFF_PTP_CONTROL;
975 if (skb->len < offset + 1)
978 msgtype = data + offset;
980 return (*msgtype & 0xf) == 0;
983 static void dp83640_free_clocks(void)
985 struct dp83640_clock *clock;
986 struct list_head *this, *next;
988 mutex_lock(&phyter_clocks_lock);
990 list_for_each_safe(this, next, &phyter_clocks) {
991 clock = list_entry(this, struct dp83640_clock, list);
992 if (!list_empty(&clock->phylist)) {
993 pr_warn("phy list non-empty while unloading\n");
996 list_del(&clock->list);
997 mutex_destroy(&clock->extreg_lock);
998 mutex_destroy(&clock->clock_lock);
999 put_device(&clock->bus->dev);
1000 kfree(clock->caps.pin_config);
1004 mutex_unlock(&phyter_clocks_lock);
1007 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1009 INIT_LIST_HEAD(&clock->list);
1011 mutex_init(&clock->extreg_lock);
1012 mutex_init(&clock->clock_lock);
1013 INIT_LIST_HEAD(&clock->phylist);
1014 clock->caps.owner = THIS_MODULE;
1015 sprintf(clock->caps.name, "dp83640 timer");
1016 clock->caps.max_adj = 1953124;
1017 clock->caps.n_alarm = 0;
1018 clock->caps.n_ext_ts = N_EXT_TS;
1019 clock->caps.n_per_out = N_PER_OUT;
1020 clock->caps.n_pins = DP83640_N_PINS;
1021 clock->caps.pps = 0;
1022 clock->caps.adjfreq = ptp_dp83640_adjfreq;
1023 clock->caps.adjtime = ptp_dp83640_adjtime;
1024 clock->caps.gettime64 = ptp_dp83640_gettime;
1025 clock->caps.settime64 = ptp_dp83640_settime;
1026 clock->caps.enable = ptp_dp83640_enable;
1027 clock->caps.verify = ptp_dp83640_verify;
1029 * Convert the module param defaults into a dynamic pin configuration.
1031 dp83640_gpio_defaults(clock->caps.pin_config);
1033 * Get a reference to this bus instance.
1035 get_device(&bus->dev);
1038 static int choose_this_phy(struct dp83640_clock *clock,
1039 struct phy_device *phydev)
1041 if (chosen_phy == -1 && !clock->chosen)
1044 if (chosen_phy == phydev->addr)
1050 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1053 mutex_lock(&clock->clock_lock);
1058 * Look up and lock a clock by bus instance.
1059 * If there is no clock for this bus, then create it first.
1061 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1063 struct dp83640_clock *clock = NULL, *tmp;
1064 struct list_head *this;
1066 mutex_lock(&phyter_clocks_lock);
1068 list_for_each(this, &phyter_clocks) {
1069 tmp = list_entry(this, struct dp83640_clock, list);
1070 if (tmp->bus == bus) {
1078 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1082 clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) *
1083 DP83640_N_PINS, GFP_KERNEL);
1084 if (!clock->caps.pin_config) {
1089 dp83640_clock_init(clock, bus);
1090 list_add_tail(&phyter_clocks, &clock->list);
1092 mutex_unlock(&phyter_clocks_lock);
1094 return dp83640_clock_get(clock);
1097 static void dp83640_clock_put(struct dp83640_clock *clock)
1099 mutex_unlock(&clock->clock_lock);
1102 static int dp83640_probe(struct phy_device *phydev)
1104 struct dp83640_clock *clock;
1105 struct dp83640_private *dp83640;
1106 int err = -ENOMEM, i;
1108 if (phydev->addr == BROADCAST_ADDR)
1111 clock = dp83640_clock_get_bus(phydev->bus);
1115 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1119 dp83640->phydev = phydev;
1120 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1122 INIT_LIST_HEAD(&dp83640->rxts);
1123 INIT_LIST_HEAD(&dp83640->rxpool);
1124 for (i = 0; i < MAX_RXTS; i++)
1125 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1127 phydev->priv = dp83640;
1129 spin_lock_init(&dp83640->rx_lock);
1130 skb_queue_head_init(&dp83640->rx_queue);
1131 skb_queue_head_init(&dp83640->tx_queue);
1133 dp83640->clock = clock;
1135 if (choose_this_phy(clock, phydev)) {
1136 clock->chosen = dp83640;
1137 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev);
1138 if (IS_ERR(clock->ptp_clock)) {
1139 err = PTR_ERR(clock->ptp_clock);
1143 list_add_tail(&dp83640->list, &clock->phylist);
1145 dp83640_clock_put(clock);
1149 clock->chosen = NULL;
1152 dp83640_clock_put(clock);
1157 static void dp83640_remove(struct phy_device *phydev)
1159 struct dp83640_clock *clock;
1160 struct list_head *this, *next;
1161 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1163 if (phydev->addr == BROADCAST_ADDR)
1166 enable_status_frames(phydev, false);
1167 cancel_delayed_work_sync(&dp83640->ts_work);
1169 skb_queue_purge(&dp83640->rx_queue);
1170 skb_queue_purge(&dp83640->tx_queue);
1172 clock = dp83640_clock_get(dp83640->clock);
1174 if (dp83640 == clock->chosen) {
1175 ptp_clock_unregister(clock->ptp_clock);
1176 clock->chosen = NULL;
1178 list_for_each_safe(this, next, &clock->phylist) {
1179 tmp = list_entry(this, struct dp83640_private, list);
1180 if (tmp == dp83640) {
1181 list_del_init(&tmp->list);
1187 dp83640_clock_put(clock);
1191 static int dp83640_config_init(struct phy_device *phydev)
1193 struct dp83640_private *dp83640 = phydev->priv;
1194 struct dp83640_clock *clock = dp83640->clock;
1196 if (clock->chosen && !list_empty(&clock->phylist))
1199 mutex_lock(&clock->extreg_lock);
1200 enable_broadcast(phydev, clock->page, 1);
1201 mutex_unlock(&clock->extreg_lock);
1204 enable_status_frames(phydev, true);
1206 mutex_lock(&clock->extreg_lock);
1207 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1208 mutex_unlock(&clock->extreg_lock);
1213 static int dp83640_ack_interrupt(struct phy_device *phydev)
1215 int err = phy_read(phydev, MII_DP83640_MISR);
1223 static int dp83640_config_intr(struct phy_device *phydev)
1229 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1230 misr = phy_read(phydev, MII_DP83640_MISR);
1234 (MII_DP83640_MISR_ANC_INT_EN |
1235 MII_DP83640_MISR_DUP_INT_EN |
1236 MII_DP83640_MISR_SPD_INT_EN |
1237 MII_DP83640_MISR_LINK_INT_EN);
1238 err = phy_write(phydev, MII_DP83640_MISR, misr);
1242 micr = phy_read(phydev, MII_DP83640_MICR);
1246 (MII_DP83640_MICR_OE |
1247 MII_DP83640_MICR_IE);
1248 return phy_write(phydev, MII_DP83640_MICR, micr);
1250 micr = phy_read(phydev, MII_DP83640_MICR);
1254 ~(MII_DP83640_MICR_OE |
1255 MII_DP83640_MICR_IE);
1256 err = phy_write(phydev, MII_DP83640_MICR, micr);
1260 misr = phy_read(phydev, MII_DP83640_MISR);
1264 ~(MII_DP83640_MISR_ANC_INT_EN |
1265 MII_DP83640_MISR_DUP_INT_EN |
1266 MII_DP83640_MISR_SPD_INT_EN |
1267 MII_DP83640_MISR_LINK_INT_EN);
1268 return phy_write(phydev, MII_DP83640_MISR, misr);
1272 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1274 struct dp83640_private *dp83640 = phydev->priv;
1275 struct hwtstamp_config cfg;
1278 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1281 if (cfg.flags) /* reserved for future extensions */
1284 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1287 dp83640->hwts_tx_en = cfg.tx_type;
1289 switch (cfg.rx_filter) {
1290 case HWTSTAMP_FILTER_NONE:
1291 dp83640->hwts_rx_en = 0;
1293 dp83640->version = 0;
1295 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1296 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1297 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1298 dp83640->hwts_rx_en = 1;
1299 dp83640->layer = LAYER4;
1300 dp83640->version = 1;
1302 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1303 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1304 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1305 dp83640->hwts_rx_en = 1;
1306 dp83640->layer = LAYER4;
1307 dp83640->version = 2;
1309 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1310 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1311 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1312 dp83640->hwts_rx_en = 1;
1313 dp83640->layer = LAYER2;
1314 dp83640->version = 2;
1316 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1317 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1318 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1319 dp83640->hwts_rx_en = 1;
1320 dp83640->layer = LAYER4|LAYER2;
1321 dp83640->version = 2;
1327 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1328 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1330 if (dp83640->layer & LAYER2) {
1334 if (dp83640->layer & LAYER4) {
1335 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1336 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1339 if (dp83640->hwts_tx_en)
1342 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1343 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1345 if (dp83640->hwts_rx_en)
1348 mutex_lock(&dp83640->clock->extreg_lock);
1350 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1351 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1353 mutex_unlock(&dp83640->clock->extreg_lock);
1355 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1358 static void rx_timestamp_work(struct work_struct *work)
1360 struct dp83640_private *dp83640 =
1361 container_of(work, struct dp83640_private, ts_work.work);
1362 struct sk_buff *skb;
1364 /* Deliver expired packets. */
1365 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1366 struct dp83640_skb_info *skb_info;
1368 skb_info = (struct dp83640_skb_info *)skb->cb;
1369 if (!time_after(jiffies, skb_info->tmo)) {
1370 skb_queue_head(&dp83640->rx_queue, skb);
1377 if (!skb_queue_empty(&dp83640->rx_queue))
1378 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1381 static bool dp83640_rxtstamp(struct phy_device *phydev,
1382 struct sk_buff *skb, int type)
1384 struct dp83640_private *dp83640 = phydev->priv;
1385 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1386 struct list_head *this, *next;
1388 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1389 unsigned long flags;
1391 if (is_status_frame(skb, type)) {
1392 decode_status_frame(dp83640, skb);
1397 if (!dp83640->hwts_rx_en)
1400 spin_lock_irqsave(&dp83640->rx_lock, flags);
1401 prune_rx_ts(dp83640);
1402 list_for_each_safe(this, next, &dp83640->rxts) {
1403 rxts = list_entry(this, struct rxts, list);
1404 if (match(skb, type, rxts)) {
1405 shhwtstamps = skb_hwtstamps(skb);
1406 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1407 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1409 list_del_init(&rxts->list);
1410 list_add(&rxts->list, &dp83640->rxpool);
1414 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1417 skb_info->ptp_type = type;
1418 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1419 skb_queue_tail(&dp83640->rx_queue, skb);
1420 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1428 static void dp83640_txtstamp(struct phy_device *phydev,
1429 struct sk_buff *skb, int type)
1431 struct dp83640_private *dp83640 = phydev->priv;
1433 switch (dp83640->hwts_tx_en) {
1435 case HWTSTAMP_TX_ONESTEP_SYNC:
1436 if (is_sync(skb, type)) {
1441 case HWTSTAMP_TX_ON:
1442 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1443 skb_queue_tail(&dp83640->tx_queue, skb);
1446 case HWTSTAMP_TX_OFF:
1453 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1455 struct dp83640_private *dp83640 = dev->priv;
1457 info->so_timestamping =
1458 SOF_TIMESTAMPING_TX_HARDWARE |
1459 SOF_TIMESTAMPING_RX_HARDWARE |
1460 SOF_TIMESTAMPING_RAW_HARDWARE;
1461 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1463 (1 << HWTSTAMP_TX_OFF) |
1464 (1 << HWTSTAMP_TX_ON) |
1465 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1467 (1 << HWTSTAMP_FILTER_NONE) |
1468 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1469 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1470 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1471 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1475 static struct phy_driver dp83640_driver = {
1476 .phy_id = DP83640_PHY_ID,
1477 .phy_id_mask = 0xfffffff0,
1478 .name = "NatSemi DP83640",
1479 .features = PHY_BASIC_FEATURES,
1480 .flags = PHY_HAS_INTERRUPT,
1481 .probe = dp83640_probe,
1482 .remove = dp83640_remove,
1483 .config_init = dp83640_config_init,
1484 .config_aneg = genphy_config_aneg,
1485 .read_status = genphy_read_status,
1486 .ack_interrupt = dp83640_ack_interrupt,
1487 .config_intr = dp83640_config_intr,
1488 .ts_info = dp83640_ts_info,
1489 .hwtstamp = dp83640_hwtstamp,
1490 .rxtstamp = dp83640_rxtstamp,
1491 .txtstamp = dp83640_txtstamp,
1492 .driver = {.owner = THIS_MODULE,}
1495 static int __init dp83640_init(void)
1497 return phy_driver_register(&dp83640_driver);
1500 static void __exit dp83640_exit(void)
1502 dp83640_free_clocks();
1503 phy_driver_unregister(&dp83640_driver);
1506 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1507 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1508 MODULE_LICENSE("GPL");
1510 module_init(dp83640_init);
1511 module_exit(dp83640_exit);
1513 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1514 { DP83640_PHY_ID, 0xfffffff0 },
1518 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);