drivers/net/phy/dp83640.c

   1 /*
   2  * Driver for the National Semiconductor DP83640 PHYTER
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/crc32.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/kernel.h>
  26 #include <linux/list.h>
  27 #include <linux/mii.h>
  28 #include <linux/module.h>
  29 #include <linux/net_tstamp.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/if_vlan.h>
  32 #include <linux/phy.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/ptp_clock_kernel.h>
  35
  36 #include "dp83640_reg.h"
  37
  38 #define DP83640_PHY_ID  0x20005ce1
  39 #define PAGESEL         0x13
  40 #define LAYER4          0x02
  41 #define LAYER2          0x01
  42 #define MAX_RXTS        64
  43 #define N_EXT_TS        6
  44 #define N_PER_OUT       7
  45 #define PSF_PTPVER      2
  46 #define PSF_EVNT        0x4000
  47 #define PSF_RX          0x2000
  48 #define PSF_TX          0x1000
  49 #define EXT_EVENT       1
  50 #define CAL_EVENT       7
  51 #define CAL_TRIGGER     1
  52 #define DP83640_N_PINS  12
  53
  54 #define MII_DP83640_MICR 0x11
  55 #define MII_DP83640_MISR 0x12
  56
  57 #define MII_DP83640_MICR_OE 0x1
  58 #define MII_DP83640_MICR_IE 0x2
  59
  60 #define MII_DP83640_MISR_RHF_INT_EN 0x01
  61 #define MII_DP83640_MISR_FHF_INT_EN 0x02
  62 #define MII_DP83640_MISR_ANC_INT_EN 0x04
  63 #define MII_DP83640_MISR_DUP_INT_EN 0x08
  64 #define MII_DP83640_MISR_SPD_INT_EN 0x10
  65 #define MII_DP83640_MISR_LINK_INT_EN 0x20
  66 #define MII_DP83640_MISR_ED_INT_EN 0x40
  67 #define MII_DP83640_MISR_LQ_INT_EN 0x80
  68
  69 /* phyter seems to miss the mark by 16 ns */
  70 #define ADJTIME_FIX     16
  71
  72 #define SKB_TIMESTAMP_TIMEOUT   2 /* jiffies */
  73
  74 #if defined(__BIG_ENDIAN)
  75 #define ENDIAN_FLAG     0
  76 #elif defined(__LITTLE_ENDIAN)
  77 #define ENDIAN_FLAG     PSF_ENDIAN
  78 #endif
  79
  80 struct dp83640_skb_info {
  81         int ptp_type;
  82         unsigned long tmo;
  83 };
  84
  85 struct phy_rxts {
  86         u16 ns_lo;   /* ns[15:0] */
  87         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  88         u16 sec_lo;  /* sec[15:0] */
  89         u16 sec_hi;  /* sec[31:16] */
  90         u16 seqid;   /* sequenceId[15:0] */
  91         u16 msgtype; /* messageType[3:0], hash[11:0] */
  92 };
  93
  94 struct phy_txts {
  95         u16 ns_lo;   /* ns[15:0] */
  96         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  97         u16 sec_lo;  /* sec[15:0] */
  98         u16 sec_hi;  /* sec[31:16] */
  99 };
 100
 101 struct rxts {
 102         struct list_head list;
 103         unsigned long tmo;
 104         u64 ns;
 105         u16 seqid;
 106         u8  msgtype;
 107         u16 hash;
 108 };
 109
 110 struct dp83640_clock;
 111
 112 struct dp83640_private {
 113         struct list_head list;
 114         struct dp83640_clock *clock;
 115         struct phy_device *phydev;
 116         struct delayed_work ts_work;
 117         int hwts_tx_en;
 118         int hwts_rx_en;
 119         int layer;
 120         int version;
 121         /* remember state of cfg0 during calibration */
 122         int cfg0;
 123         /* remember the last event time stamp */
 124         struct phy_txts edata;
 125         /* list of rx timestamps */
 126         struct list_head rxts;
 127         struct list_head rxpool;
 128         struct rxts rx_pool_data[MAX_RXTS];
 129         /* protects above three fields from concurrent access */
 130         spinlock_t rx_lock;
 131         /* queues of incoming and outgoing packets */
 132         struct sk_buff_head rx_queue;
 133         struct sk_buff_head tx_queue;
 134 };
 135
 136 struct dp83640_clock {
 137         /* keeps the instance in the 'phyter_clocks' list */
 138         struct list_head list;
 139         /* we create one clock instance per MII bus */
 140         struct mii_bus *bus;
 141         /* protects extended registers from concurrent access */
 142         struct mutex extreg_lock;
 143         /* remembers which page was last selected */
 144         int page;
 145         /* our advertised capabilities */
 146         struct ptp_clock_info caps;
 147         /* protects the three fields below from concurrent access */
 148         struct mutex clock_lock;
 149         /* the one phyter from which we shall read */
 150         struct dp83640_private *chosen;
 151         /* list of the other attached phyters, not chosen */
 152         struct list_head phylist;
 153         /* reference to our PTP hardware clock */
 154         struct ptp_clock *ptp_clock;
 155 };
 156
 157 /* globals */
 158
 159 enum {
 160         CALIBRATE_GPIO,
 161         PEROUT_GPIO,
 162         EXTTS0_GPIO,
 163         EXTTS1_GPIO,
 164         EXTTS2_GPIO,
 165         EXTTS3_GPIO,
 166         EXTTS4_GPIO,
 167         EXTTS5_GPIO,
 168         GPIO_TABLE_SIZE
 169 };
 170
 171 static int chosen_phy = -1;
 172 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
 173         1, 2, 3, 4, 8, 9, 10, 11
 174 };
 175
 176 module_param(chosen_phy, int, 0444);
 177 module_param_array(gpio_tab, ushort, NULL, 0444);
 178
 179 MODULE_PARM_DESC(chosen_phy, \
 180         "The address of the PHY to use for the ancillary clock features");
 181 MODULE_PARM_DESC(gpio_tab, \
 182         "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
 183
 184 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
 185 {
 186         int i, index;
 187
 188         for (i = 0; i < DP83640_N_PINS; i++) {
 189                 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
 190                 pd[i].index = i;
 191         }
 192
 193         for (i = 0; i < GPIO_TABLE_SIZE; i++) {
 194                 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
 195                         pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
 196                         return;
 197                 }
 198         }
 199
 200         index = gpio_tab[CALIBRATE_GPIO] - 1;
 201         pd[index].func = PTP_PF_PHYSYNC;
 202         pd[index].chan = 0;
 203
 204         index = gpio_tab[PEROUT_GPIO] - 1;
 205         pd[index].func = PTP_PF_PEROUT;
 206         pd[index].chan = 0;
 207
 208         for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
 209                 index = gpio_tab[i] - 1;
 210                 pd[index].func = PTP_PF_EXTTS;
 211                 pd[index].chan = i - EXTTS0_GPIO;
 212         }
 213 }
 214
 215 /* a list of clocks and a mutex to protect it */
 216 static LIST_HEAD(phyter_clocks);
 217 static DEFINE_MUTEX(phyter_clocks_lock);
 218
 219 static void rx_timestamp_work(struct work_struct *work);
 220
 221 /* extended register access functions */
 222
 223 #define BROADCAST_ADDR 31
 224
 225 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
 226 {
 227         return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
 228 }
 229
 230 /* Caller must hold extreg_lock. */
 231 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
 232 {
 233         struct dp83640_private *dp83640 = phydev->priv;
 234         int val;
 235
 236         if (dp83640->clock->page != page) {
 237                 broadcast_write(phydev->bus, PAGESEL, page);
 238                 dp83640->clock->page = page;
 239         }
 240         val = phy_read(phydev, regnum);
 241
 242         return val;
 243 }
 244
 245 /* Caller must hold extreg_lock. */
 246 static void ext_write(int broadcast, struct phy_device *phydev,
 247                       int page, u32 regnum, u16 val)
 248 {
 249         struct dp83640_private *dp83640 = phydev->priv;
 250
 251         if (dp83640->clock->page != page) {
 252                 broadcast_write(phydev->bus, PAGESEL, page);
 253                 dp83640->clock->page = page;
 254         }
 255         if (broadcast)
 256                 broadcast_write(phydev->bus, regnum, val);
 257         else
 258                 phy_write(phydev, regnum, val);
 259 }
 260
 261 /* Caller must hold extreg_lock. */
 262 static int tdr_write(int bc, struct phy_device *dev,
 263                      const struct timespec64 *ts, u16 cmd)
 264 {
 265         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0]  */
 266         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);   /* ns[31:16] */
 267         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
 268         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);    /* sec[31:16]*/
 269
 270         ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
 271
 272         return 0;
 273 }
 274
 275 /* convert phy timestamps into driver timestamps */
 276
 277 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
 278 {
 279         u32 sec;
 280
 281         sec = p->sec_lo;
 282         sec |= p->sec_hi << 16;
 283
 284         rxts->ns = p->ns_lo;
 285         rxts->ns |= (p->ns_hi & 0x3fff) << 16;
 286         rxts->ns += ((u64)sec) * 1000000000ULL;
 287         rxts->seqid = p->seqid;
 288         rxts->msgtype = (p->msgtype >> 12) & 0xf;
 289         rxts->hash = p->msgtype & 0x0fff;
 290         rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
 291 }
 292
 293 static u64 phy2txts(struct phy_txts *p)
 294 {
 295         u64 ns;
 296         u32 sec;
 297
 298         sec = p->sec_lo;
 299         sec |= p->sec_hi << 16;
 300
 301         ns = p->ns_lo;
 302         ns |= (p->ns_hi & 0x3fff) << 16;
 303         ns += ((u64)sec) * 1000000000ULL;
 304
 305         return ns;
 306 }
 307
 308 static int periodic_output(struct dp83640_clock *clock,
 309                            struct ptp_clock_request *clkreq, bool on,
 310                            int trigger)
 311 {
 312         struct dp83640_private *dp83640 = clock->chosen;
 313         struct phy_device *phydev = dp83640->phydev;
 314         u32 sec, nsec, pwidth;
 315         u16 gpio, ptp_trig, val;
 316
 317         if (on) {
 318                 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
 319                                         trigger);
 320                 if (gpio < 1)
 321                         return -EINVAL;
 322         } else {
 323                 gpio = 0;
 324         }
 325
 326         ptp_trig = TRIG_WR |
 327                 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
 328                 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
 329                 TRIG_PER |
 330                 TRIG_PULSE;
 331
 332         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 333
 334         if (!on) {
 335                 val |= TRIG_DIS;
 336                 mutex_lock(&clock->extreg_lock);
 337                 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
 338                 ext_write(0, phydev, PAGE4, PTP_CTL, val);
 339                 mutex_unlock(&clock->extreg_lock);
 340                 return 0;
 341         }
 342
 343         sec = clkreq->perout.start.sec;
 344         nsec = clkreq->perout.start.nsec;
 345         pwidth = clkreq->perout.period.sec * 1000000000UL;
 346         pwidth += clkreq->perout.period.nsec;
 347         pwidth /= 2;
 348
 349         mutex_lock(&clock->extreg_lock);
 350
 351         ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
 352
 353         /*load trigger*/
 354         val |= TRIG_LOAD;
 355         ext_write(0, phydev, PAGE4, PTP_CTL, val);
 356         ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff);   /* ns[15:0] */
 357         ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16);      /* ns[31:16] */
 358         ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff);    /* sec[15:0] */
 359         ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16);       /* sec[31:16] */
 360         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
 361         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);    /* ns[31:16] */
 362         /* Triggers 0 and 1 has programmable pulsewidth2 */
 363         if (trigger < 2) {
 364                 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
 365                 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
 366         }
 367
 368         /*enable trigger*/
 369         val &= ~TRIG_LOAD;
 370         val |= TRIG_EN;
 371         ext_write(0, phydev, PAGE4, PTP_CTL, val);
 372
 373         mutex_unlock(&clock->extreg_lock);
 374         return 0;
 375 }
 376
 377 /* ptp clock methods */
 378
 379 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 380 {
 381         struct dp83640_clock *clock =
 382                 container_of(ptp, struct dp83640_clock, caps);
 383         struct phy_device *phydev = clock->chosen->phydev;
 384         u64 rate;
 385         int neg_adj = 0;
 386         u16 hi, lo;
 387
 388         if (ppb < 0) {
 389                 neg_adj = 1;
 390                 ppb = -ppb;
 391         }
 392         rate = ppb;
 393         rate <<= 26;
 394         rate = div_u64(rate, 1953125);
 395
 396         hi = (rate >> 16) & PTP_RATE_HI_MASK;
 397         if (neg_adj)
 398                 hi |= PTP_RATE_DIR;
 399
 400         lo = rate & 0xffff;
 401
 402         mutex_lock(&clock->extreg_lock);
 403
 404         ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
 405         ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
 406
 407         mutex_unlock(&clock->extreg_lock);
 408
 409         return 0;
 410 }
 411
 412 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
 413 {
 414         struct dp83640_clock *clock =
 415                 container_of(ptp, struct dp83640_clock, caps);
 416         struct phy_device *phydev = clock->chosen->phydev;
 417         struct timespec64 ts;
 418         int err;
 419
 420         delta += ADJTIME_FIX;
 421
 422         ts = ns_to_timespec64(delta);
 423
 424         mutex_lock(&clock->extreg_lock);
 425
 426         err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
 427
 428         mutex_unlock(&clock->extreg_lock);
 429
 430         return err;
 431 }
 432
 433 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
 434                                struct timespec64 *ts)
 435 {
 436         struct dp83640_clock *clock =
 437                 container_of(ptp, struct dp83640_clock, caps);
 438         struct phy_device *phydev = clock->chosen->phydev;
 439         unsigned int val[4];
 440
 441         mutex_lock(&clock->extreg_lock);
 442
 443         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
 444
 445         val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
 446         val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
 447         val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
 448         val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
 449
 450         mutex_unlock(&clock->extreg_lock);
 451
 452         ts->tv_nsec = val[0] | (val[1] << 16);
 453         ts->tv_sec  = val[2] | (val[3] << 16);
 454
 455         return 0;
 456 }
 457
 458 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
 459                                const struct timespec64 *ts)
 460 {
 461         struct dp83640_clock *clock =
 462                 container_of(ptp, struct dp83640_clock, caps);
 463         struct phy_device *phydev = clock->chosen->phydev;
 464         int err;
 465
 466         mutex_lock(&clock->extreg_lock);
 467
 468         err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
 469
 470         mutex_unlock(&clock->extreg_lock);
 471
 472         return err;
 473 }
 474
 475 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
 476                               struct ptp_clock_request *rq, int on)
 477 {
 478         struct dp83640_clock *clock =
 479                 container_of(ptp, struct dp83640_clock, caps);
 480         struct phy_device *phydev = clock->chosen->phydev;
 481         unsigned int index;
 482         u16 evnt, event_num, gpio_num;
 483
 484         switch (rq->type) {
 485         case PTP_CLK_REQ_EXTTS:
 486                 index = rq->extts.index;
 487                 if (index >= N_EXT_TS)
 488                         return -EINVAL;
 489                 event_num = EXT_EVENT + index;
 490                 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 491                 if (on) {
 492                         gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
 493                                                     PTP_PF_EXTTS, index);
 494                         if (gpio_num < 1)
 495                                 return -EINVAL;
 496                         evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 497                         if (rq->extts.flags & PTP_FALLING_EDGE)
 498                                 evnt |= EVNT_FALL;
 499                         else
 500                                 evnt |= EVNT_RISE;
 501                 }
 502                 mutex_lock(&clock->extreg_lock);
 503                 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
 504                 mutex_unlock(&clock->extreg_lock);
 505                 return 0;
 506
 507         case PTP_CLK_REQ_PEROUT:
 508                 if (rq->perout.index >= N_PER_OUT)
 509                         return -EINVAL;
 510                 return periodic_output(clock, rq, on, rq->perout.index);
 511
 512         default:
 513                 break;
 514         }
 515
 516         return -EOPNOTSUPP;
 517 }
 518
 519 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
 520                               enum ptp_pin_function func, unsigned int chan)
 521 {
 522         struct dp83640_clock *clock =
 523                 container_of(ptp, struct dp83640_clock, caps);
 524
 525         if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
 526             !list_empty(&clock->phylist))
 527                 return 1;
 528
 529         if (func == PTP_PF_PHYSYNC)
 530                 return 1;
 531
 532         return 0;
 533 }
 534
 535 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
 536 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
 537
 538 static void enable_status_frames(struct phy_device *phydev, bool on)
 539 {
 540         struct dp83640_private *dp83640 = phydev->priv;
 541         struct dp83640_clock *clock = dp83640->clock;
 542         u16 cfg0 = 0, ver;
 543
 544         if (on)
 545                 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
 546
 547         ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
 548
 549         mutex_lock(&clock->extreg_lock);
 550
 551         ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
 552         ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
 553
 554         mutex_unlock(&clock->extreg_lock);
 555
 556         if (!phydev->attached_dev) {
 557                 pr_warn("expected to find an attached netdevice\n");
 558                 return;
 559         }
 560
 561         if (on) {
 562                 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
 563                         pr_warn("failed to add mc address\n");
 564         } else {
 565                 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
 566                         pr_warn("failed to delete mc address\n");
 567         }
 568 }
 569
 570 static bool is_status_frame(struct sk_buff *skb, int type)
 571 {
 572         struct ethhdr *h = eth_hdr(skb);
 573
 574         if (PTP_CLASS_V2_L2 == type &&
 575             !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
 576                 return true;
 577         else
 578                 return false;
 579 }
 580
 581 static int expired(struct rxts *rxts)
 582 {
 583         return time_after(jiffies, rxts->tmo);
 584 }
 585
 586 /* Caller must hold rx_lock. */
 587 static void prune_rx_ts(struct dp83640_private *dp83640)
 588 {
 589         struct list_head *this, *next;
 590         struct rxts *rxts;
 591
 592         list_for_each_safe(this, next, &dp83640->rxts) {
 593                 rxts = list_entry(this, struct rxts, list);
 594                 if (expired(rxts)) {
 595                         list_del_init(&rxts->list);
 596                         list_add(&rxts->list, &dp83640->rxpool);
 597                 }
 598         }
 599 }
 600
 601 /* synchronize the phyters so they act as one clock */
 602
 603 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
 604 {
 605         int val;
 606         phy_write(phydev, PAGESEL, 0);
 607         val = phy_read(phydev, PHYCR2);
 608         if (on)
 609                 val |= BC_WRITE;
 610         else
 611                 val &= ~BC_WRITE;
 612         phy_write(phydev, PHYCR2, val);
 613         phy_write(phydev, PAGESEL, init_page);
 614 }
 615
 616 static void recalibrate(struct dp83640_clock *clock)
 617 {
 618         s64 now, diff;
 619         struct phy_txts event_ts;
 620         struct timespec64 ts;
 621         struct list_head *this;
 622         struct dp83640_private *tmp;
 623         struct phy_device *master = clock->chosen->phydev;
 624         u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
 625
 626         trigger = CAL_TRIGGER;
 627         cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
 628         if (cal_gpio < 1) {
 629                 pr_err("PHY calibration pin not available - PHY is not calibrated.");
 630                 return;
 631         }
 632
 633         mutex_lock(&clock->extreg_lock);
 634
 635         /*
 636          * enable broadcast, disable status frames, enable ptp clock
 637          */
 638         list_for_each(this, &clock->phylist) {
 639                 tmp = list_entry(this, struct dp83640_private, list);
 640                 enable_broadcast(tmp->phydev, clock->page, 1);
 641                 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
 642                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
 643                 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
 644         }
 645         enable_broadcast(master, clock->page, 1);
 646         cfg0 = ext_read(master, PAGE5, PSF_CFG0);
 647         ext_write(0, master, PAGE5, PSF_CFG0, 0);
 648         ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
 649
 650         /*
 651          * enable an event timestamp
 652          */
 653         evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
 654         evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 655         evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 656
 657         list_for_each(this, &clock->phylist) {
 658                 tmp = list_entry(this, struct dp83640_private, list);
 659                 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
 660         }
 661         ext_write(0, master, PAGE5, PTP_EVNT, evnt);
 662
 663         /*
 664          * configure a trigger
 665          */
 666         ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
 667         ptp_trig |= (trigger  & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
 668         ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
 669         ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
 670
 671         /* load trigger */
 672         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 673         val |= TRIG_LOAD;
 674         ext_write(0, master, PAGE4, PTP_CTL, val);
 675
 676         /* enable trigger */
 677         val &= ~TRIG_LOAD;
 678         val |= TRIG_EN;
 679         ext_write(0, master, PAGE4, PTP_CTL, val);
 680
 681         /* disable trigger */
 682         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 683         val |= TRIG_DIS;
 684         ext_write(0, master, PAGE4, PTP_CTL, val);
 685
 686         /*
 687          * read out and correct offsets
 688          */
 689         val = ext_read(master, PAGE4, PTP_STS);
 690         pr_info("master PTP_STS  0x%04hx\n", val);
 691         val = ext_read(master, PAGE4, PTP_ESTS);
 692         pr_info("master PTP_ESTS 0x%04hx\n", val);
 693         event_ts.ns_lo  = ext_read(master, PAGE4, PTP_EDATA);
 694         event_ts.ns_hi  = ext_read(master, PAGE4, PTP_EDATA);
 695         event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
 696         event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
 697         now = phy2txts(&event_ts);
 698
 699         list_for_each(this, &clock->phylist) {
 700                 tmp = list_entry(this, struct dp83640_private, list);
 701                 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
 702                 pr_info("slave  PTP_STS  0x%04hx\n", val);
 703                 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
 704                 pr_info("slave  PTP_ESTS 0x%04hx\n", val);
 705                 event_ts.ns_lo  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 706                 event_ts.ns_hi  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 707                 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 708                 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 709                 diff = now - (s64) phy2txts(&event_ts);
 710                 pr_info("slave offset %lld nanoseconds\n", diff);
 711                 diff += ADJTIME_FIX;
 712                 ts = ns_to_timespec64(diff);
 713                 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
 714         }
 715
 716         /*
 717          * restore status frames
 718          */
 719         list_for_each(this, &clock->phylist) {
 720                 tmp = list_entry(this, struct dp83640_private, list);
 721                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
 722         }
 723         ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
 724
 725         mutex_unlock(&clock->extreg_lock);
 726 }
 727
 728 /* time stamping methods */
 729
 730 static inline u16 exts_chan_to_edata(int ch)
 731 {
 732         return 1 << ((ch + EXT_EVENT) * 2);
 733 }
 734
 735 static int decode_evnt(struct dp83640_private *dp83640,
 736                        void *data, int len, u16 ests)
 737 {
 738         struct phy_txts *phy_txts;
 739         struct ptp_clock_event event;
 740         int i, parsed;
 741         int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
 742         u16 ext_status = 0;
 743
 744         /* calculate length of the event timestamp status message */
 745         if (ests & MULT_EVNT)
 746                 parsed = (words + 2) * sizeof(u16);
 747         else
 748                 parsed = (words + 1) * sizeof(u16);
 749
 750         /* check if enough data is available */
 751         if (len < parsed)
 752                 return len;
 753
 754         if (ests & MULT_EVNT) {
 755                 ext_status = *(u16 *) data;
 756                 data += sizeof(ext_status);
 757         }
 758
 759         phy_txts = data;
 760
 761         switch (words) { /* fall through in every case */
 762         case 3:
 763                 dp83640->edata.sec_hi = phy_txts->sec_hi;
 764         case 2:
 765                 dp83640->edata.sec_lo = phy_txts->sec_lo;
 766         case 1:
 767                 dp83640->edata.ns_hi = phy_txts->ns_hi;
 768         case 0:
 769                 dp83640->edata.ns_lo = phy_txts->ns_lo;
 770         }
 771
 772         if (!ext_status) {
 773                 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
 774                 ext_status = exts_chan_to_edata(i);
 775         }
 776
 777         event.type = PTP_CLOCK_EXTTS;
 778         event.timestamp = phy2txts(&dp83640->edata);
 779
 780         /* Compensate for input path and synchronization delays */
 781         event.timestamp -= 35;
 782
 783         for (i = 0; i < N_EXT_TS; i++) {
 784                 if (ext_status & exts_chan_to_edata(i)) {
 785                         event.index = i;
 786                         ptp_clock_event(dp83640->clock->ptp_clock, &event);
 787                 }
 788         }
 789
 790         return parsed;
 791 }
 792
 793 #define DP83640_PACKET_HASH_OFFSET      20
 794 #define DP83640_PACKET_HASH_LEN         10
 795
 796 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
 797 {
 798         u16 *seqid, hash;
 799         unsigned int offset = 0;
 800         u8 *msgtype, *data = skb_mac_header(skb);
 801
 802         /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
 803
 804         if (type & PTP_CLASS_VLAN)
 805                 offset += VLAN_HLEN;
 806
 807         switch (type & PTP_CLASS_PMASK) {
 808         case PTP_CLASS_IPV4:
 809                 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
 810                 break;
 811         case PTP_CLASS_IPV6:
 812                 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
 813                 break;
 814         case PTP_CLASS_L2:
 815                 offset += ETH_HLEN;
 816                 break;
 817         default:
 818                 return 0;
 819         }
 820
 821         if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
 822                 return 0;
 823
 824         if (unlikely(type & PTP_CLASS_V1))
 825                 msgtype = data + offset + OFF_PTP_CONTROL;
 826         else
 827                 msgtype = data + offset;
 828         if (rxts->msgtype != (*msgtype & 0xf))
 829                 return 0;
 830
 831         seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 832         if (rxts->seqid != ntohs(*seqid))
 833                 return 0;
 834
 835         hash = ether_crc(DP83640_PACKET_HASH_LEN,
 836                          data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
 837         if (rxts->hash != hash)
 838                 return 0;
 839
 840         return 1;
 841 }
 842
 843 static void decode_rxts(struct dp83640_private *dp83640,
 844                         struct phy_rxts *phy_rxts)
 845 {
 846         struct rxts *rxts;
 847         struct skb_shared_hwtstamps *shhwtstamps = NULL;
 848         struct sk_buff *skb;
 849         unsigned long flags;
 850
 851         spin_lock_irqsave(&dp83640->rx_lock, flags);
 852
 853         prune_rx_ts(dp83640);
 854
 855         if (list_empty(&dp83640->rxpool)) {
 856                 pr_debug("rx timestamp pool is empty\n");
 857                 goto out;
 858         }
 859         rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
 860         list_del_init(&rxts->list);
 861         phy2rxts(phy_rxts, rxts);
 862
 863         spin_lock(&dp83640->rx_queue.lock);
 864         skb_queue_walk(&dp83640->rx_queue, skb) {
 865                 struct dp83640_skb_info *skb_info;
 866
 867                 skb_info = (struct dp83640_skb_info *)skb->cb;
 868                 if (match(skb, skb_info->ptp_type, rxts)) {
 869                         __skb_unlink(skb, &dp83640->rx_queue);
 870                         shhwtstamps = skb_hwtstamps(skb);
 871                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 872                         shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
 873                         netif_rx_ni(skb);
 874                         list_add(&rxts->list, &dp83640->rxpool);
 875                         break;
 876                 }
 877         }
 878         spin_unlock(&dp83640->rx_queue.lock);
 879
 880         if (!shhwtstamps)
 881                 list_add_tail(&rxts->list, &dp83640->rxts);
 882 out:
 883         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
 884 }
 885
 886 static void decode_txts(struct dp83640_private *dp83640,
 887                         struct phy_txts *phy_txts)
 888 {
 889         struct skb_shared_hwtstamps shhwtstamps;
 890         struct sk_buff *skb;
 891         u64 ns;
 892
 893         /* We must already have the skb that triggered this. */
 894
 895         skb = skb_dequeue(&dp83640->tx_queue);
 896
 897         if (!skb) {
 898                 pr_debug("have timestamp but tx_queue empty\n");
 899                 return;
 900         }
 901         ns = phy2txts(phy_txts);
 902         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 903         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 904         skb_complete_tx_timestamp(skb, &shhwtstamps);
 905 }
 906
 907 static void decode_status_frame(struct dp83640_private *dp83640,
 908                                 struct sk_buff *skb)
 909 {
 910         struct phy_rxts *phy_rxts;
 911         struct phy_txts *phy_txts;
 912         u8 *ptr;
 913         int len, size;
 914         u16 ests, type;
 915
 916         ptr = skb->data + 2;
 917
 918         for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
 919
 920                 type = *(u16 *)ptr;
 921                 ests = type & 0x0fff;
 922                 type = type & 0xf000;
 923                 len -= sizeof(type);
 924                 ptr += sizeof(type);
 925
 926                 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
 927
 928                         phy_rxts = (struct phy_rxts *) ptr;
 929                         decode_rxts(dp83640, phy_rxts);
 930                         size = sizeof(*phy_rxts);
 931
 932                 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
 933
 934                         phy_txts = (struct phy_txts *) ptr;
 935                         decode_txts(dp83640, phy_txts);
 936                         size = sizeof(*phy_txts);
 937
 938                 } else if (PSF_EVNT == type) {
 939
 940                         size = decode_evnt(dp83640, ptr, len, ests);
 941
 942                 } else {
 943                         size = 0;
 944                         break;
 945                 }
 946                 ptr += size;
 947         }
 948 }
 949
 950 static int is_sync(struct sk_buff *skb, int type)
 951 {
 952         u8 *data = skb->data, *msgtype;
 953         unsigned int offset = 0;
 954
 955         if (type & PTP_CLASS_VLAN)
 956                 offset += VLAN_HLEN;
 957
 958         switch (type & PTP_CLASS_PMASK) {
 959         case PTP_CLASS_IPV4:
 960                 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
 961                 break;
 962         case PTP_CLASS_IPV6:
 963                 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
 964                 break;
 965         case PTP_CLASS_L2:
 966                 offset += ETH_HLEN;
 967                 break;
 968         default:
 969                 return 0;
 970         }
 971
 972         if (type & PTP_CLASS_V1)
 973                 offset += OFF_PTP_CONTROL;
 974
 975         if (skb->len < offset + 1)
 976                 return 0;
 977
 978         msgtype = data + offset;
 979
 980         return (*msgtype & 0xf) == 0;
 981 }
 982
 983 static void dp83640_free_clocks(void)
 984 {
 985         struct dp83640_clock *clock;
 986         struct list_head *this, *next;
 987
 988         mutex_lock(&phyter_clocks_lock);
 989
 990         list_for_each_safe(this, next, &phyter_clocks) {
 991                 clock = list_entry(this, struct dp83640_clock, list);
 992                 if (!list_empty(&clock->phylist)) {
 993                         pr_warn("phy list non-empty while unloading\n");
 994                         BUG();
 995                 }
 996                 list_del(&clock->list);
 997                 mutex_destroy(&clock->extreg_lock);
 998                 mutex_destroy(&clock->clock_lock);
 999                 put_device(&clock->bus->dev);
1000                 kfree(clock->caps.pin_config);
1001                 kfree(clock);
1002         }
1003
1004         mutex_unlock(&phyter_clocks_lock);
1005 }
1006
1007 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1008 {
1009         INIT_LIST_HEAD(&clock->list);
1010         clock->bus = bus;
1011         mutex_init(&clock->extreg_lock);
1012         mutex_init(&clock->clock_lock);
1013         INIT_LIST_HEAD(&clock->phylist);
1014         clock->caps.owner = THIS_MODULE;
1015         sprintf(clock->caps.name, "dp83640 timer");
1016         clock->caps.max_adj     = 1953124;
1017         clock->caps.n_alarm     = 0;
1018         clock->caps.n_ext_ts    = N_EXT_TS;
1019         clock->caps.n_per_out   = N_PER_OUT;
1020         clock->caps.n_pins      = DP83640_N_PINS;
1021         clock->caps.pps         = 0;
1022         clock->caps.adjfreq     = ptp_dp83640_adjfreq;
1023         clock->caps.adjtime     = ptp_dp83640_adjtime;
1024         clock->caps.gettime64   = ptp_dp83640_gettime;
1025         clock->caps.settime64   = ptp_dp83640_settime;
1026         clock->caps.enable      = ptp_dp83640_enable;
1027         clock->caps.verify      = ptp_dp83640_verify;
1028         /*
1029          * Convert the module param defaults into a dynamic pin configuration.
1030          */
1031         dp83640_gpio_defaults(clock->caps.pin_config);
1032         /*
1033          * Get a reference to this bus instance.
1034          */
1035         get_device(&bus->dev);
1036 }
1037
1038 static int choose_this_phy(struct dp83640_clock *clock,
1039                            struct phy_device *phydev)
1040 {
1041         if (chosen_phy == -1 && !clock->chosen)
1042                 return 1;
1043
1044         if (chosen_phy == phydev->addr)
1045                 return 1;
1046
1047         return 0;
1048 }
1049
1050 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1051 {
1052         if (clock)
1053                 mutex_lock(&clock->clock_lock);
1054         return clock;
1055 }
1056
1057 /*
1058  * Look up and lock a clock by bus instance.
1059  * If there is no clock for this bus, then create it first.
1060  */
1061 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1062 {
1063         struct dp83640_clock *clock = NULL, *tmp;
1064         struct list_head *this;
1065
1066         mutex_lock(&phyter_clocks_lock);
1067
1068         list_for_each(this, &phyter_clocks) {
1069                 tmp = list_entry(this, struct dp83640_clock, list);
1070                 if (tmp->bus == bus) {
1071                         clock = tmp;
1072                         break;
1073                 }
1074         }
1075         if (clock)
1076                 goto out;
1077
1078         clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1079         if (!clock)
1080                 goto out;
1081
1082         clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) *
1083                                          DP83640_N_PINS, GFP_KERNEL);
1084         if (!clock->caps.pin_config) {
1085                 kfree(clock);
1086                 clock = NULL;
1087                 goto out;
1088         }
1089         dp83640_clock_init(clock, bus);
1090         list_add_tail(&phyter_clocks, &clock->list);
1091 out:
1092         mutex_unlock(&phyter_clocks_lock);
1093
1094         return dp83640_clock_get(clock);
1095 }
1096
1097 static void dp83640_clock_put(struct dp83640_clock *clock)
1098 {
1099         mutex_unlock(&clock->clock_lock);
1100 }
1101
1102 static int dp83640_probe(struct phy_device *phydev)
1103 {
1104         struct dp83640_clock *clock;
1105         struct dp83640_private *dp83640;
1106         int err = -ENOMEM, i;
1107
1108         if (phydev->addr == BROADCAST_ADDR)
1109                 return 0;
1110
1111         clock = dp83640_clock_get_bus(phydev->bus);
1112         if (!clock)
1113                 goto no_clock;
1114
1115         dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1116         if (!dp83640)
1117                 goto no_memory;
1118
1119         dp83640->phydev = phydev;
1120         INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1121
1122         INIT_LIST_HEAD(&dp83640->rxts);
1123         INIT_LIST_HEAD(&dp83640->rxpool);
1124         for (i = 0; i < MAX_RXTS; i++)
1125                 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1126
1127         phydev->priv = dp83640;
1128
1129         spin_lock_init(&dp83640->rx_lock);
1130         skb_queue_head_init(&dp83640->rx_queue);
1131         skb_queue_head_init(&dp83640->tx_queue);
1132
1133         dp83640->clock = clock;
1134
1135         if (choose_this_phy(clock, phydev)) {
1136                 clock->chosen = dp83640;
1137                 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev);
1138                 if (IS_ERR(clock->ptp_clock)) {
1139                         err = PTR_ERR(clock->ptp_clock);
1140                         goto no_register;
1141                 }
1142         } else
1143                 list_add_tail(&dp83640->list, &clock->phylist);
1144
1145         dp83640_clock_put(clock);
1146         return 0;
1147
1148 no_register:
1149         clock->chosen = NULL;
1150         kfree(dp83640);
1151 no_memory:
1152         dp83640_clock_put(clock);
1153 no_clock:
1154         return err;
1155 }
1156
1157 static void dp83640_remove(struct phy_device *phydev)
1158 {
1159         struct dp83640_clock *clock;
1160         struct list_head *this, *next;
1161         struct dp83640_private *tmp, *dp83640 = phydev->priv;
1162
1163         if (phydev->addr == BROADCAST_ADDR)
1164                 return;
1165
1166         enable_status_frames(phydev, false);
1167         cancel_delayed_work_sync(&dp83640->ts_work);
1168
1169         skb_queue_purge(&dp83640->rx_queue);
1170         skb_queue_purge(&dp83640->tx_queue);
1171
1172         clock = dp83640_clock_get(dp83640->clock);
1173
1174         if (dp83640 == clock->chosen) {
1175                 ptp_clock_unregister(clock->ptp_clock);
1176                 clock->chosen = NULL;
1177         } else {
1178                 list_for_each_safe(this, next, &clock->phylist) {
1179                         tmp = list_entry(this, struct dp83640_private, list);
1180                         if (tmp == dp83640) {
1181                                 list_del_init(&tmp->list);
1182                                 break;
1183                         }
1184                 }
1185         }
1186
1187         dp83640_clock_put(clock);
1188         kfree(dp83640);
1189 }
1190
1191 static int dp83640_config_init(struct phy_device *phydev)
1192 {
1193         struct dp83640_private *dp83640 = phydev->priv;
1194         struct dp83640_clock *clock = dp83640->clock;
1195
1196         if (clock->chosen && !list_empty(&clock->phylist))
1197                 recalibrate(clock);
1198         else {
1199                 mutex_lock(&clock->extreg_lock);
1200                 enable_broadcast(phydev, clock->page, 1);
1201                 mutex_unlock(&clock->extreg_lock);
1202         }
1203
1204         enable_status_frames(phydev, true);
1205
1206         mutex_lock(&clock->extreg_lock);
1207         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1208         mutex_unlock(&clock->extreg_lock);
1209
1210         return 0;
1211 }
1212
1213 static int dp83640_ack_interrupt(struct phy_device *phydev)
1214 {
1215         int err = phy_read(phydev, MII_DP83640_MISR);
1216
1217         if (err < 0)
1218                 return err;
1219
1220         return 0;
1221 }
1222
1223 static int dp83640_config_intr(struct phy_device *phydev)
1224 {
1225         int micr;
1226         int misr;
1227         int err;
1228
1229         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1230                 misr = phy_read(phydev, MII_DP83640_MISR);
1231                 if (misr < 0)
1232                         return misr;
1233                 misr |=
1234                         (MII_DP83640_MISR_ANC_INT_EN |
1235                         MII_DP83640_MISR_DUP_INT_EN |
1236                         MII_DP83640_MISR_SPD_INT_EN |
1237                         MII_DP83640_MISR_LINK_INT_EN);
1238                 err = phy_write(phydev, MII_DP83640_MISR, misr);
1239                 if (err < 0)
1240                         return err;
1241
1242                 micr = phy_read(phydev, MII_DP83640_MICR);
1243                 if (micr < 0)
1244                         return micr;
1245                 micr |=
1246                         (MII_DP83640_MICR_OE |
1247                         MII_DP83640_MICR_IE);
1248                 return phy_write(phydev, MII_DP83640_MICR, micr);
1249         } else {
1250                 micr = phy_read(phydev, MII_DP83640_MICR);
1251                 if (micr < 0)
1252                         return micr;
1253                 micr &=
1254                         ~(MII_DP83640_MICR_OE |
1255                         MII_DP83640_MICR_IE);
1256                 err = phy_write(phydev, MII_DP83640_MICR, micr);
1257                 if (err < 0)
1258                         return err;
1259
1260                 misr = phy_read(phydev, MII_DP83640_MISR);
1261                 if (misr < 0)
1262                         return misr;
1263                 misr &=
1264                         ~(MII_DP83640_MISR_ANC_INT_EN |
1265                         MII_DP83640_MISR_DUP_INT_EN |
1266                         MII_DP83640_MISR_SPD_INT_EN |
1267                         MII_DP83640_MISR_LINK_INT_EN);
1268                 return phy_write(phydev, MII_DP83640_MISR, misr);
1269         }
1270 }
1271
1272 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1273 {
1274         struct dp83640_private *dp83640 = phydev->priv;
1275         struct hwtstamp_config cfg;
1276         u16 txcfg0, rxcfg0;
1277
1278         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1279                 return -EFAULT;
1280
1281         if (cfg.flags) /* reserved for future extensions */
1282                 return -EINVAL;
1283
1284         if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1285                 return -ERANGE;
1286
1287         dp83640->hwts_tx_en = cfg.tx_type;
1288
1289         switch (cfg.rx_filter) {
1290         case HWTSTAMP_FILTER_NONE:
1291                 dp83640->hwts_rx_en = 0;
1292                 dp83640->layer = 0;
1293                 dp83640->version = 0;
1294                 break;
1295         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1296         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1297         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1298                 dp83640->hwts_rx_en = 1;
1299                 dp83640->layer = LAYER4;
1300                 dp83640->version = 1;
1301                 break;
1302         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1303         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1304         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1305                 dp83640->hwts_rx_en = 1;
1306                 dp83640->layer = LAYER4;
1307                 dp83640->version = 2;
1308                 break;
1309         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1310         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1311         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1312                 dp83640->hwts_rx_en = 1;
1313                 dp83640->layer = LAYER2;
1314                 dp83640->version = 2;
1315                 break;
1316         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1317         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1318         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1319                 dp83640->hwts_rx_en = 1;
1320                 dp83640->layer = LAYER4|LAYER2;
1321                 dp83640->version = 2;
1322                 break;
1323         default:
1324                 return -ERANGE;
1325         }
1326
1327         txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1328         rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1329
1330         if (dp83640->layer & LAYER2) {
1331                 txcfg0 |= TX_L2_EN;
1332                 rxcfg0 |= RX_L2_EN;
1333         }
1334         if (dp83640->layer & LAYER4) {
1335                 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1336                 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1337         }
1338
1339         if (dp83640->hwts_tx_en)
1340                 txcfg0 |= TX_TS_EN;
1341
1342         if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1343                 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1344
1345         if (dp83640->hwts_rx_en)
1346                 rxcfg0 |= RX_TS_EN;
1347
1348         mutex_lock(&dp83640->clock->extreg_lock);
1349
1350         ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1351         ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1352
1353         mutex_unlock(&dp83640->clock->extreg_lock);
1354
1355         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1356 }
1357
1358 static void rx_timestamp_work(struct work_struct *work)
1359 {
1360         struct dp83640_private *dp83640 =
1361                 container_of(work, struct dp83640_private, ts_work.work);
1362         struct sk_buff *skb;
1363
1364         /* Deliver expired packets. */
1365         while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1366                 struct dp83640_skb_info *skb_info;
1367
1368                 skb_info = (struct dp83640_skb_info *)skb->cb;
1369                 if (!time_after(jiffies, skb_info->tmo)) {
1370                         skb_queue_head(&dp83640->rx_queue, skb);
1371                         break;
1372                 }
1373
1374                 netif_rx_ni(skb);
1375         }
1376
1377         if (!skb_queue_empty(&dp83640->rx_queue))
1378                 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1379 }
1380
1381 static bool dp83640_rxtstamp(struct phy_device *phydev,
1382                              struct sk_buff *skb, int type)
1383 {
1384         struct dp83640_private *dp83640 = phydev->priv;
1385         struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1386         struct list_head *this, *next;
1387         struct rxts *rxts;
1388         struct skb_shared_hwtstamps *shhwtstamps = NULL;
1389         unsigned long flags;
1390
1391         if (is_status_frame(skb, type)) {
1392                 decode_status_frame(dp83640, skb);
1393                 kfree_skb(skb);
1394                 return true;
1395         }
1396
1397         if (!dp83640->hwts_rx_en)
1398                 return false;
1399
1400         spin_lock_irqsave(&dp83640->rx_lock, flags);
1401         list_for_each_safe(this, next, &dp83640->rxts) {
1402                 rxts = list_entry(this, struct rxts, list);
1403                 if (match(skb, type, rxts)) {
1404                         shhwtstamps = skb_hwtstamps(skb);
1405                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1406                         shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1407                         netif_rx_ni(skb);
1408                         list_del_init(&rxts->list);
1409                         list_add(&rxts->list, &dp83640->rxpool);
1410                         break;
1411                 }
1412         }
1413         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1414
1415         if (!shhwtstamps) {
1416                 skb_info->ptp_type = type;
1417                 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1418                 skb_queue_tail(&dp83640->rx_queue, skb);
1419                 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1420         } else {
1421                 netif_rx_ni(skb);
1422         }
1423
1424         return true;
1425 }
1426
1427 static void dp83640_txtstamp(struct phy_device *phydev,
1428                              struct sk_buff *skb, int type)
1429 {
1430         struct dp83640_private *dp83640 = phydev->priv;
1431
1432         switch (dp83640->hwts_tx_en) {
1433
1434         case HWTSTAMP_TX_ONESTEP_SYNC:
1435                 if (is_sync(skb, type)) {
1436                         kfree_skb(skb);
1437                         return;
1438                 }
1439                 /* fall through */
1440         case HWTSTAMP_TX_ON:
1441                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1442                 skb_queue_tail(&dp83640->tx_queue, skb);
1443                 break;
1444
1445         case HWTSTAMP_TX_OFF:
1446         default:
1447                 kfree_skb(skb);
1448                 break;
1449         }
1450 }
1451
1452 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1453 {
1454         struct dp83640_private *dp83640 = dev->priv;
1455
1456         info->so_timestamping =
1457                 SOF_TIMESTAMPING_TX_HARDWARE |
1458                 SOF_TIMESTAMPING_RX_HARDWARE |
1459                 SOF_TIMESTAMPING_RAW_HARDWARE;
1460         info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1461         info->tx_types =
1462                 (1 << HWTSTAMP_TX_OFF) |
1463                 (1 << HWTSTAMP_TX_ON) |
1464                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1465         info->rx_filters =
1466                 (1 << HWTSTAMP_FILTER_NONE) |
1467                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1468                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1469                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1470                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1471         return 0;
1472 }
1473
1474 static struct phy_driver dp83640_driver = {
1475         .phy_id         = DP83640_PHY_ID,
1476         .phy_id_mask    = 0xfffffff0,
1477         .name           = "NatSemi DP83640",
1478         .features       = PHY_BASIC_FEATURES,
1479         .flags          = PHY_HAS_INTERRUPT,
1480         .probe          = dp83640_probe,
1481         .remove         = dp83640_remove,
1482         .config_init    = dp83640_config_init,
1483         .config_aneg    = genphy_config_aneg,
1484         .read_status    = genphy_read_status,
1485         .ack_interrupt  = dp83640_ack_interrupt,
1486         .config_intr    = dp83640_config_intr,
1487         .ts_info        = dp83640_ts_info,
1488         .hwtstamp       = dp83640_hwtstamp,
1489         .rxtstamp       = dp83640_rxtstamp,
1490         .txtstamp       = dp83640_txtstamp,
1491         .driver         = {.owner = THIS_MODULE,}
1492 };
1493
1494 static int __init dp83640_init(void)
1495 {
1496         return phy_driver_register(&dp83640_driver);
1497 }
1498
1499 static void __exit dp83640_exit(void)
1500 {
1501         dp83640_free_clocks();
1502         phy_driver_unregister(&dp83640_driver);
1503 }
1504
1505 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1506 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1507 MODULE_LICENSE("GPL");
1508
1509 module_init(dp83640_init);
1510 module_exit(dp83640_exit);
1511
1512 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1513         { DP83640_PHY_ID, 0xfffffff0 },
1514         { }
1515 };
1516
1517 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);