drivers/net/phy/vitesse.c

   1 /*
   2  * Driver for Vitesse PHYs
   3  *
   4  * Author: Kriston Carson
   5  *
   6  * Copyright (c) 2005, 2009, 2011 Freescale Semiconductor, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mii.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20
  21 /* Vitesse Extended Page Magic Register(s) */
  22 #define MII_VSC82X4_EXT_PAGE_16E        0x10
  23 #define MII_VSC82X4_EXT_PAGE_17E        0x11
  24 #define MII_VSC82X4_EXT_PAGE_18E        0x12
  25
  26 /* Vitesse Extended Control Register 1 */
  27 #define MII_VSC8244_EXT_CON1           0x17
  28 #define MII_VSC8244_EXTCON1_INIT       0x0000
  29 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK        0x0c00
  30 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK        0x0300
  31 #define MII_VSC8244_EXTCON1_TX_SKEW     0x0800
  32 #define MII_VSC8244_EXTCON1_RX_SKEW     0x0200
  33
  34 /* Vitesse Interrupt Mask Register */
  35 #define MII_VSC8244_IMASK               0x19
  36 #define MII_VSC8244_IMASK_IEN           0x8000
  37 #define MII_VSC8244_IMASK_SPEED         0x4000
  38 #define MII_VSC8244_IMASK_LINK          0x2000
  39 #define MII_VSC8244_IMASK_DUPLEX        0x1000
  40 #define MII_VSC8244_IMASK_MASK          0xf000
  41
  42 #define MII_VSC8221_IMASK_MASK          0xa000
  43
  44 /* Vitesse Interrupt Status Register */
  45 #define MII_VSC8244_ISTAT               0x1a
  46 #define MII_VSC8244_ISTAT_STATUS        0x8000
  47 #define MII_VSC8244_ISTAT_SPEED         0x4000
  48 #define MII_VSC8244_ISTAT_LINK          0x2000
  49 #define MII_VSC8244_ISTAT_DUPLEX        0x1000
  50
  51 /* Vitesse Auxiliary Control/Status Register */
  52 #define MII_VSC8244_AUX_CONSTAT         0x1c
  53 #define MII_VSC8244_AUXCONSTAT_INIT     0x0000
  54 #define MII_VSC8244_AUXCONSTAT_DUPLEX   0x0020
  55 #define MII_VSC8244_AUXCONSTAT_SPEED    0x0018
  56 #define MII_VSC8244_AUXCONSTAT_GBIT     0x0010
  57 #define MII_VSC8244_AUXCONSTAT_100      0x0008
  58
  59 #define MII_VSC8221_AUXCONSTAT_INIT     0x0004 /* need to set this bit? */
  60 #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
  61
  62 /* Vitesse Extended Page Access Register */
  63 #define MII_VSC82X4_EXT_PAGE_ACCESS     0x1f
  64
  65 #define PHY_ID_VSC8234                  0x000fc620
  66 #define PHY_ID_VSC8244                  0x000fc6c0
  67 #define PHY_ID_VSC8514                  0x00070670
  68 #define PHY_ID_VSC8574                  0x000704a0
  69 #define PHY_ID_VSC8641                  0x00070431
  70 #define PHY_ID_VSC8662                  0x00070660
  71 #define PHY_ID_VSC8221                  0x000fc550
  72 #define PHY_ID_VSC8211                  0x000fc4b0
  73
  74 MODULE_DESCRIPTION("Vitesse PHY driver");
  75 MODULE_AUTHOR("Kriston Carson");
  76 MODULE_LICENSE("GPL");
  77
  78 static int vsc824x_add_skew(struct phy_device *phydev)
  79 {
  80         int err;
  81         int extcon;
  82
  83         extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
  84
  85         if (extcon < 0)
  86                 return extcon;
  87
  88         extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
  89                         MII_VSC8244_EXTCON1_RX_SKEW_MASK);
  90
  91         extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
  92                         MII_VSC8244_EXTCON1_RX_SKEW);
  93
  94         err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
  95
  96         return err;
  97 }
  98
  99 static int vsc824x_config_init(struct phy_device *phydev)
 100 {
 101         int err;
 102
 103         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
 104                         MII_VSC8244_AUXCONSTAT_INIT);
 105         if (err < 0)
 106                 return err;
 107
 108         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 109                 err = vsc824x_add_skew(phydev);
 110
 111         return err;
 112 }
 113
 114 static int vsc824x_ack_interrupt(struct phy_device *phydev)
 115 {
 116         int err = 0;
 117
 118         /* Don't bother to ACK the interrupts if interrupts
 119          * are disabled.  The 824x cannot clear the interrupts
 120          * if they are disabled.
 121          */
 122         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 123                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 124
 125         return (err < 0) ? err : 0;
 126 }
 127
 128 static int vsc82xx_config_intr(struct phy_device *phydev)
 129 {
 130         int err;
 131
 132         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 133                 err = phy_write(phydev, MII_VSC8244_IMASK,
 134                         (phydev->drv->phy_id == PHY_ID_VSC8234 ||
 135                          phydev->drv->phy_id == PHY_ID_VSC8244 ||
 136                          phydev->drv->phy_id == PHY_ID_VSC8514 ||
 137                          phydev->drv->phy_id == PHY_ID_VSC8574) ?
 138                                 MII_VSC8244_IMASK_MASK :
 139                                 MII_VSC8221_IMASK_MASK);
 140         else {
 141                 /* The Vitesse PHY cannot clear the interrupt
 142                  * once it has disabled them, so we clear them first
 143                  */
 144                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 145
 146                 if (err < 0)
 147                         return err;
 148
 149                 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
 150         }
 151
 152         return err;
 153 }
 154
 155 static int vsc8221_config_init(struct phy_device *phydev)
 156 {
 157         int err;
 158
 159         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
 160                         MII_VSC8221_AUXCONSTAT_INIT);
 161         return err;
 162
 163         /* Perhaps we should set EXT_CON1 based on the interface?
 164          * Options are 802.3Z SerDes or SGMII
 165          */
 166 }
 167
 168 /* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links
 169  * @phydev: target phy_device struct
 170  *
 171  * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing
 172  * special values in the VSC8234/VSC8244 extended reserved registers
 173  */
 174 static int vsc82x4_config_autocross_enable(struct phy_device *phydev)
 175 {
 176         int ret;
 177
 178         if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100)
 179                 return 0;
 180
 181         /* map extended registers set 0x10 - 0x1e */
 182         ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);
 183         if (ret >= 0)
 184                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);
 185         if (ret >= 0)
 186                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);
 187         if (ret >= 0)
 188                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);
 189         /* map standard registers set 0x10 - 0x1e */
 190         if (ret >= 0)
 191                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
 192         else
 193                 phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
 194
 195         return ret;
 196 }
 197
 198 /* vsc82x4_config_aneg - restart auto-negotiation or write BMCR
 199  * @phydev: target phy_device struct
 200  *
 201  * Description: If auto-negotiation is enabled, we configure the
 202  *   advertising, and then restart auto-negotiation.  If it is not
 203  *   enabled, then we write the BMCR and also start the auto
 204  *   MDI/MDI-X feature
 205  */
 206 static int vsc82x4_config_aneg(struct phy_device *phydev)
 207 {
 208         int ret;
 209
 210         /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by
 211          * writing special values in the VSC8234 extended reserved registers
 212          */
 213         if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) {
 214                 ret = genphy_setup_forced(phydev);
 215
 216                 if (ret < 0) /* error */
 217                         return ret;
 218
 219                 return vsc82x4_config_autocross_enable(phydev);
 220         }
 221
 222         return genphy_config_aneg(phydev);
 223 }
 224
 225 /* Vitesse 82xx */
 226 static struct phy_driver vsc82xx_driver[] = {
 227 {
 228         .phy_id         = PHY_ID_VSC8234,
 229         .name           = "Vitesse VSC8234",
 230         .phy_id_mask    = 0x000ffff0,
 231         .features       = PHY_GBIT_FEATURES,
 232         .flags          = PHY_HAS_INTERRUPT,
 233         .config_init    = &vsc824x_config_init,
 234         .config_aneg    = &vsc82x4_config_aneg,
 235         .read_status    = &genphy_read_status,
 236         .ack_interrupt  = &vsc824x_ack_interrupt,
 237         .config_intr    = &vsc82xx_config_intr,
 238         .driver         = { .owner = THIS_MODULE,},
 239 }, {
 240         .phy_id         = PHY_ID_VSC8244,
 241         .name           = "Vitesse VSC8244",
 242         .phy_id_mask    = 0x000fffc0,
 243         .features       = PHY_GBIT_FEATURES,
 244         .flags          = PHY_HAS_INTERRUPT,
 245         .config_init    = &vsc824x_config_init,
 246         .config_aneg    = &vsc82x4_config_aneg,
 247         .read_status    = &genphy_read_status,
 248         .ack_interrupt  = &vsc824x_ack_interrupt,
 249         .config_intr    = &vsc82xx_config_intr,
 250         .driver         = { .owner = THIS_MODULE,},
 251 }, {
 252         .phy_id         = PHY_ID_VSC8514,
 253         .name           = "Vitesse VSC8514",
 254         .phy_id_mask    = 0x000ffff0,
 255         .features       = PHY_GBIT_FEATURES,
 256         .flags          = PHY_HAS_INTERRUPT,
 257         .config_init    = &vsc824x_config_init,
 258         .config_aneg    = &vsc82x4_config_aneg,
 259         .read_status    = &genphy_read_status,
 260         .ack_interrupt  = &vsc824x_ack_interrupt,
 261         .config_intr    = &vsc82xx_config_intr,
 262         .driver         = { .owner = THIS_MODULE,},
 263 }, {
 264         .phy_id         = PHY_ID_VSC8574,
 265         .name           = "Vitesse VSC8574",
 266         .phy_id_mask    = 0x000ffff0,
 267         .features       = PHY_GBIT_FEATURES,
 268         .flags          = PHY_HAS_INTERRUPT,
 269         .config_init    = &vsc824x_config_init,
 270         .config_aneg    = &vsc82x4_config_aneg,
 271         .read_status    = &genphy_read_status,
 272         .ack_interrupt  = &vsc824x_ack_interrupt,
 273         .config_intr    = &vsc82xx_config_intr,
 274         .driver         = { .owner = THIS_MODULE,},
 275 }, {
 276         .phy_id         = PHY_ID_VSC8641,
 277         .name           = "Vitesse VSC8641",
 278         .phy_id_mask    = 0x000ffff0,
 279         .features       = PHY_GBIT_FEATURES,
 280         .flags          = PHY_HAS_INTERRUPT,
 281         .config_init    = &vsc824x_config_init,
 282         .config_aneg    = &vsc82x4_config_aneg,
 283         .read_status    = &genphy_read_status,
 284         .ack_interrupt  = &vsc824x_ack_interrupt,
 285         .config_intr    = &vsc82xx_config_intr,
 286         .driver         = { .owner = THIS_MODULE,},
 287 }, {
 288         .phy_id         = PHY_ID_VSC8662,
 289         .name           = "Vitesse VSC8662",
 290         .phy_id_mask    = 0x000ffff0,
 291         .features       = PHY_GBIT_FEATURES,
 292         .flags          = PHY_HAS_INTERRUPT,
 293         .config_init    = &vsc824x_config_init,
 294         .config_aneg    = &vsc82x4_config_aneg,
 295         .read_status    = &genphy_read_status,
 296         .ack_interrupt  = &vsc824x_ack_interrupt,
 297         .config_intr    = &vsc82xx_config_intr,
 298         .driver         = { .owner = THIS_MODULE,},
 299 }, {
 300         /* Vitesse 8221 */
 301         .phy_id         = PHY_ID_VSC8221,
 302         .phy_id_mask    = 0x000ffff0,
 303         .name           = "Vitesse VSC8221",
 304         .features       = PHY_GBIT_FEATURES,
 305         .flags          = PHY_HAS_INTERRUPT,
 306         .config_init    = &vsc8221_config_init,
 307         .config_aneg    = &genphy_config_aneg,
 308         .read_status    = &genphy_read_status,
 309         .ack_interrupt  = &vsc824x_ack_interrupt,
 310         .config_intr    = &vsc82xx_config_intr,
 311         .driver         = { .owner = THIS_MODULE,},
 312 }, {
 313         /* Vitesse 8211 */
 314         .phy_id         = PHY_ID_VSC8211,
 315         .phy_id_mask    = 0x000ffff0,
 316         .name           = "Vitesse VSC8211",
 317         .features       = PHY_GBIT_FEATURES,
 318         .flags          = PHY_HAS_INTERRUPT,
 319         .config_init    = &vsc8221_config_init,
 320         .config_aneg    = &genphy_config_aneg,
 321         .read_status    = &genphy_read_status,
 322         .ack_interrupt  = &vsc824x_ack_interrupt,
 323         .config_intr    = &vsc82xx_config_intr,
 324         .driver         = { .owner = THIS_MODULE,},
 325 } };
 326
 327 module_phy_driver(vsc82xx_driver);
 328
 329 static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
 330         { PHY_ID_VSC8234, 0x000ffff0 },
 331         { PHY_ID_VSC8244, 0x000fffc0 },
 332         { PHY_ID_VSC8514, 0x000ffff0 },
 333         { PHY_ID_VSC8574, 0x000ffff0 },
 334         { PHY_ID_VSC8641, 0x000ffff0 },
 335         { PHY_ID_VSC8662, 0x000ffff0 },
 336         { PHY_ID_VSC8221, 0x000ffff0 },
 337         { PHY_ID_VSC8211, 0x000ffff0 },
 338         { }
 339 };
 340
 341 MODULE_DEVICE_TABLE(mdio, vitesse_tbl);