drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46
  47 #ifdef RTL8169_DEBUG
  48 #define assert(expr) \
  49         if (!(expr)) {                                  \
  50                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  51                 #expr,__FILE__,__func__,__LINE__);              \
  52         }
  53 #define dprintk(fmt, args...) \
  54         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  55 #else
  56 #define assert(expr) do {} while (0)
  57 #define dprintk(fmt, args...)   do {} while (0)
  58 #endif /* RTL8169_DEBUG */
  59
  60 #define R8169_MSG_DEFAULT \
  61         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  62
  63 #define TX_BUFFS_AVAIL(tp) \
  64         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  65
  66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  68 static const int multicast_filter_limit = 32;
  69
  70 /* MAC address length */
  71 #define MAC_ADDR_LEN    6
  72
  73 #define MAX_READ_REQUEST_SHIFT  12
  74 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  76 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  77
  78 #define R8169_REGS_SIZE         256
  79 #define R8169_NAPI_WEIGHT       64
  80 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  81 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  82 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  83 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  84 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  85
  86 #define RTL8169_TX_TIMEOUT      (6*HZ)
  87 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  88
  89 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  90 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  91 #define RTL_EEPROM_SIG_ADDR     0x0000
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_VER_34,
 136         RTL_GIGA_MAC_NONE   = 0xff,
 137 };
 138
 139 enum rtl_tx_desc_version {
 140         RTL_TD_0        = 0,
 141         RTL_TD_1        = 1,
 142 };
 143
 144 #define _R(NAME,TD,FW) \
 145         { .name = NAME, .txd_version = TD, .fw_name = FW }
 146
 147 static const struct {
 148         const char *name;
 149         enum rtl_tx_desc_version txd_version;
 150         const char *fw_name;
 151 } rtl_chip_infos[] = {
 152         /* PCI devices. */
 153         [RTL_GIGA_MAC_VER_01] =
 154                 _R("RTL8169",           RTL_TD_0, NULL),
 155         [RTL_GIGA_MAC_VER_02] =
 156                 _R("RTL8169s",          RTL_TD_0, NULL),
 157         [RTL_GIGA_MAC_VER_03] =
 158                 _R("RTL8110s",          RTL_TD_0, NULL),
 159         [RTL_GIGA_MAC_VER_04] =
 160                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 161         [RTL_GIGA_MAC_VER_05] =
 162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 163         [RTL_GIGA_MAC_VER_06] =
 164                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 165         /* PCI-E devices. */
 166         [RTL_GIGA_MAC_VER_07] =
 167                 _R("RTL8102e",          RTL_TD_1, NULL),
 168         [RTL_GIGA_MAC_VER_08] =
 169                 _R("RTL8102e",          RTL_TD_1, NULL),
 170         [RTL_GIGA_MAC_VER_09] =
 171                 _R("RTL8102e",          RTL_TD_1, NULL),
 172         [RTL_GIGA_MAC_VER_10] =
 173                 _R("RTL8101e",          RTL_TD_0, NULL),
 174         [RTL_GIGA_MAC_VER_11] =
 175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 176         [RTL_GIGA_MAC_VER_12] =
 177                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 178         [RTL_GIGA_MAC_VER_13] =
 179                 _R("RTL8101e",          RTL_TD_0, NULL),
 180         [RTL_GIGA_MAC_VER_14] =
 181                 _R("RTL8100e",          RTL_TD_0, NULL),
 182         [RTL_GIGA_MAC_VER_15] =
 183                 _R("RTL8100e",          RTL_TD_0, NULL),
 184         [RTL_GIGA_MAC_VER_16] =
 185                 _R("RTL8101e",          RTL_TD_0, NULL),
 186         [RTL_GIGA_MAC_VER_17] =
 187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 188         [RTL_GIGA_MAC_VER_18] =
 189                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 190         [RTL_GIGA_MAC_VER_19] =
 191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 192         [RTL_GIGA_MAC_VER_20] =
 193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 194         [RTL_GIGA_MAC_VER_21] =
 195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 196         [RTL_GIGA_MAC_VER_22] =
 197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 198         [RTL_GIGA_MAC_VER_23] =
 199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 200         [RTL_GIGA_MAC_VER_24] =
 201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 202         [RTL_GIGA_MAC_VER_25] =
 203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 204         [RTL_GIGA_MAC_VER_26] =
 205                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 206         [RTL_GIGA_MAC_VER_27] =
 207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 208         [RTL_GIGA_MAC_VER_28] =
 209                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 210         [RTL_GIGA_MAC_VER_29] =
 211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 212         [RTL_GIGA_MAC_VER_30] =
 213                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 214         [RTL_GIGA_MAC_VER_31] =
 215                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 216         [RTL_GIGA_MAC_VER_32] =
 217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 218         [RTL_GIGA_MAC_VER_33] =
 219                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2),
 220         [RTL_GIGA_MAC_VER_34] =
 221                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
 222 };
 223 #undef _R
 224
 225 enum cfg_version {
 226         RTL_CFG_0 = 0x00,
 227         RTL_CFG_1,
 228         RTL_CFG_2
 229 };
 230
 231 static void rtl_hw_start_8169(struct net_device *);
 232 static void rtl_hw_start_8168(struct net_device *);
 233 static void rtl_hw_start_8101(struct net_device *);
 234
 235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 238         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 239         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 240         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 241         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 242         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 243         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 244         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 245         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 246                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 247         { 0x0001,                               0x8168,
 248                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 249         {0,},
 250 };
 251
 252 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 253
 254 static int rx_buf_sz = 16383;
 255 static int use_dac;
 256 static struct {
 257         u32 msg_enable;
 258 } debug = { -1 };
 259
 260 enum rtl_registers {
 261         MAC0            = 0,    /* Ethernet hardware address. */
 262         MAC4            = 4,
 263         MAR0            = 8,    /* Multicast filter. */
 264         CounterAddrLow          = 0x10,
 265         CounterAddrHigh         = 0x14,
 266         TxDescStartAddrLow      = 0x20,
 267         TxDescStartAddrHigh     = 0x24,
 268         TxHDescStartAddrLow     = 0x28,
 269         TxHDescStartAddrHigh    = 0x2c,
 270         FLASH           = 0x30,
 271         ERSR            = 0x36,
 272         ChipCmd         = 0x37,
 273         TxPoll          = 0x38,
 274         IntrMask        = 0x3c,
 275         IntrStatus      = 0x3e,
 276
 277         TxConfig        = 0x40,
 278 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 279 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 280
 281         RxConfig        = 0x44,
 282 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 283 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 284 #define RXCFG_FIFO_SHIFT                13
 285                                         /* No threshold before first PCI xfer */
 286 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 287 #define RXCFG_DMA_SHIFT                 8
 288                                         /* Unlimited maximum PCI burst. */
 289 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 290
 291         RxMissed        = 0x4c,
 292         Cfg9346         = 0x50,
 293         Config0         = 0x51,
 294         Config1         = 0x52,
 295         Config2         = 0x53,
 296         Config3         = 0x54,
 297         Config4         = 0x55,
 298         Config5         = 0x56,
 299         MultiIntr       = 0x5c,
 300         PHYAR           = 0x60,
 301         PHYstatus       = 0x6c,
 302         RxMaxSize       = 0xda,
 303         CPlusCmd        = 0xe0,
 304         IntrMitigate    = 0xe2,
 305         RxDescAddrLow   = 0xe4,
 306         RxDescAddrHigh  = 0xe8,
 307         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 308
 309 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 310
 311         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 312
 313 #define TxPacketMax     (8064 >> 7)
 314
 315         FuncEvent       = 0xf0,
 316         FuncEventMask   = 0xf4,
 317         FuncPresetState = 0xf8,
 318         FuncForceEvent  = 0xfc,
 319 };
 320
 321 enum rtl8110_registers {
 322         TBICSR                  = 0x64,
 323         TBI_ANAR                = 0x68,
 324         TBI_LPAR                = 0x6a,
 325 };
 326
 327 enum rtl8168_8101_registers {
 328         CSIDR                   = 0x64,
 329         CSIAR                   = 0x68,
 330 #define CSIAR_FLAG                      0x80000000
 331 #define CSIAR_WRITE_CMD                 0x80000000
 332 #define CSIAR_BYTE_ENABLE               0x0f
 333 #define CSIAR_BYTE_ENABLE_SHIFT         12
 334 #define CSIAR_ADDR_MASK                 0x0fff
 335         PMCH                    = 0x6f,
 336         EPHYAR                  = 0x80,
 337 #define EPHYAR_FLAG                     0x80000000
 338 #define EPHYAR_WRITE_CMD                0x80000000
 339 #define EPHYAR_REG_MASK                 0x1f
 340 #define EPHYAR_REG_SHIFT                16
 341 #define EPHYAR_DATA_MASK                0xffff
 342         DLLPR                   = 0xd0,
 343 #define PFM_EN                          (1 << 6)
 344         DBG_REG                 = 0xd1,
 345 #define FIX_NAK_1                       (1 << 4)
 346 #define FIX_NAK_2                       (1 << 3)
 347         TWSI                    = 0xd2,
 348         MCU                     = 0xd3,
 349 #define NOW_IS_OOB                      (1 << 7)
 350 #define EN_NDP                          (1 << 3)
 351 #define EN_OOB_RESET                    (1 << 2)
 352         EFUSEAR                 = 0xdc,
 353 #define EFUSEAR_FLAG                    0x80000000
 354 #define EFUSEAR_WRITE_CMD               0x80000000
 355 #define EFUSEAR_READ_CMD                0x00000000
 356 #define EFUSEAR_REG_MASK                0x03ff
 357 #define EFUSEAR_REG_SHIFT               8
 358 #define EFUSEAR_DATA_MASK               0xff
 359 };
 360
 361 enum rtl8168_registers {
 362         LED_FREQ                = 0x1a,
 363         EEE_LED                 = 0x1b,
 364         ERIDR                   = 0x70,
 365         ERIAR                   = 0x74,
 366 #define ERIAR_FLAG                      0x80000000
 367 #define ERIAR_WRITE_CMD                 0x80000000
 368 #define ERIAR_READ_CMD                  0x00000000
 369 #define ERIAR_ADDR_BYTE_ALIGN           4
 370 #define ERIAR_TYPE_SHIFT                16
 371 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 372 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 373 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 374 #define ERIAR_MASK_SHIFT                12
 375 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 376 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 377 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 378         EPHY_RXER_NUM           = 0x7c,
 379         OCPDR                   = 0xb0, /* OCP GPHY access */
 380 #define OCPDR_WRITE_CMD                 0x80000000
 381 #define OCPDR_READ_CMD                  0x00000000
 382 #define OCPDR_REG_MASK                  0x7f
 383 #define OCPDR_GPHY_REG_SHIFT            16
 384 #define OCPDR_DATA_MASK                 0xffff
 385         OCPAR                   = 0xb4,
 386 #define OCPAR_FLAG                      0x80000000
 387 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 388 #define OCPAR_GPHY_READ_CMD             0x0000f060
 389         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 390         MISC                    = 0xf0, /* 8168e only. */
 391 #define TXPLA_RST                       (1 << 29)
 392 #define PWM_EN                          (1 << 22)
 393 };
 394
 395 enum rtl_register_content {
 396         /* InterruptStatusBits */
 397         SYSErr          = 0x8000,
 398         PCSTimeout      = 0x4000,
 399         SWInt           = 0x0100,
 400         TxDescUnavail   = 0x0080,
 401         RxFIFOOver      = 0x0040,
 402         LinkChg         = 0x0020,
 403         RxOverflow      = 0x0010,
 404         TxErr           = 0x0008,
 405         TxOK            = 0x0004,
 406         RxErr           = 0x0002,
 407         RxOK            = 0x0001,
 408
 409         /* RxStatusDesc */
 410         RxFOVF  = (1 << 23),
 411         RxRWT   = (1 << 22),
 412         RxRES   = (1 << 21),
 413         RxRUNT  = (1 << 20),
 414         RxCRC   = (1 << 19),
 415
 416         /* ChipCmdBits */
 417         StopReq         = 0x80,
 418         CmdReset        = 0x10,
 419         CmdRxEnb        = 0x08,
 420         CmdTxEnb        = 0x04,
 421         RxBufEmpty      = 0x01,
 422
 423         /* TXPoll register p.5 */
 424         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 425         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 426         FSWInt          = 0x01,         /* Forced software interrupt */
 427
 428         /* Cfg9346Bits */
 429         Cfg9346_Lock    = 0x00,
 430         Cfg9346_Unlock  = 0xc0,
 431
 432         /* rx_mode_bits */
 433         AcceptErr       = 0x20,
 434         AcceptRunt      = 0x10,
 435         AcceptBroadcast = 0x08,
 436         AcceptMulticast = 0x04,
 437         AcceptMyPhys    = 0x02,
 438         AcceptAllPhys   = 0x01,
 439 #define RX_CONFIG_ACCEPT_MASK           0x3f
 440
 441         /* TxConfigBits */
 442         TxInterFrameGapShift = 24,
 443         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 444
 445         /* Config1 register p.24 */
 446         LEDS1           = (1 << 7),
 447         LEDS0           = (1 << 6),
 448         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 449         Speed_down      = (1 << 4),
 450         MEMMAP          = (1 << 3),
 451         IOMAP           = (1 << 2),
 452         VPD             = (1 << 1),
 453         PMEnable        = (1 << 0),     /* Power Management Enable */
 454
 455         /* Config2 register p. 25 */
 456         PCI_Clock_66MHz = 0x01,
 457         PCI_Clock_33MHz = 0x00,
 458
 459         /* Config3 register p.25 */
 460         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 461         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config5 register p.27 */
 465         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 466         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 467         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 468         Spi_en          = (1 << 3),
 469         LanWake         = (1 << 1),     /* LanWake enable/disable */
 470         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 471
 472         /* TBICSR p.28 */
 473         TBIReset        = 0x80000000,
 474         TBILoopback     = 0x40000000,
 475         TBINwEnable     = 0x20000000,
 476         TBINwRestart    = 0x10000000,
 477         TBILinkOk       = 0x02000000,
 478         TBINwComplete   = 0x01000000,
 479
 480         /* CPlusCmd p.31 */
 481         EnableBist      = (1 << 15),    // 8168 8101
 482         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 483         Normal_mode     = (1 << 13),    // unused
 484         Force_half_dup  = (1 << 12),    // 8168 8101
 485         Force_rxflow_en = (1 << 11),    // 8168 8101
 486         Force_txflow_en = (1 << 10),    // 8168 8101
 487         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 488         ASF             = (1 << 8),     // 8168 8101
 489         PktCntrDisable  = (1 << 7),     // 8168 8101
 490         Mac_dbgo_sel    = 0x001c,       // 8168
 491         RxVlan          = (1 << 6),
 492         RxChkSum        = (1 << 5),
 493         PCIDAC          = (1 << 4),
 494         PCIMulRW        = (1 << 3),
 495         INTT_0          = 0x0000,       // 8168
 496         INTT_1          = 0x0001,       // 8168
 497         INTT_2          = 0x0002,       // 8168
 498         INTT_3          = 0x0003,       // 8168
 499
 500         /* rtl8169_PHYstatus */
 501         TBI_Enable      = 0x80,
 502         TxFlowCtrl      = 0x40,
 503         RxFlowCtrl      = 0x20,
 504         _1000bpsF       = 0x10,
 505         _100bps         = 0x08,
 506         _10bps          = 0x04,
 507         LinkStatus      = 0x02,
 508         FullDup         = 0x01,
 509
 510         /* _TBICSRBit */
 511         TBILinkOK       = 0x02000000,
 512
 513         /* DumpCounterCommand */
 514         CounterDump     = 0x8,
 515 };
 516
 517 enum rtl_desc_bit {
 518         /* First doubleword. */
 519         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 520         RingEnd         = (1 << 30), /* End of descriptor ring */
 521         FirstFrag       = (1 << 29), /* First segment of a packet */
 522         LastFrag        = (1 << 28), /* Final segment of a packet */
 523 };
 524
 525 /* Generic case. */
 526 enum rtl_tx_desc_bit {
 527         /* First doubleword. */
 528         TD_LSO          = (1 << 27),            /* Large Send Offload */
 529 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 530
 531         /* Second doubleword. */
 532         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 533 };
 534
 535 /* 8169, 8168b and 810x except 8102e. */
 536 enum rtl_tx_desc_bit_0 {
 537         /* First doubleword. */
 538 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 539         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 540         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 541         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 542 };
 543
 544 /* 8102e, 8168c and beyond. */
 545 enum rtl_tx_desc_bit_1 {
 546         /* Second doubleword. */
 547 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 548         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 549         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 550         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 551 };
 552
 553 static const struct rtl_tx_desc_info {
 554         struct {
 555                 u32 udp;
 556                 u32 tcp;
 557         } checksum;
 558         u16 mss_shift;
 559         u16 opts_offset;
 560 } tx_desc_info [] = {
 561         [RTL_TD_0] = {
 562                 .checksum = {
 563                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 564                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 565                 },
 566                 .mss_shift      = TD0_MSS_SHIFT,
 567                 .opts_offset    = 0
 568         },
 569         [RTL_TD_1] = {
 570                 .checksum = {
 571                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 572                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 573                 },
 574                 .mss_shift      = TD1_MSS_SHIFT,
 575                 .opts_offset    = 1
 576         }
 577 };
 578
 579 enum rtl_rx_desc_bit {
 580         /* Rx private */
 581         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 582         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 583
 584 #define RxProtoUDP      (PID1)
 585 #define RxProtoTCP      (PID0)
 586 #define RxProtoIP       (PID1 | PID0)
 587 #define RxProtoMask     RxProtoIP
 588
 589         IPFail          = (1 << 16), /* IP checksum failed */
 590         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 591         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 592         RxVlanTag       = (1 << 16), /* VLAN tag available */
 593 };
 594
 595 #define RsvdMask        0x3fffc000
 596
 597 struct TxDesc {
 598         __le32 opts1;
 599         __le32 opts2;
 600         __le64 addr;
 601 };
 602
 603 struct RxDesc {
 604         __le32 opts1;
 605         __le32 opts2;
 606         __le64 addr;
 607 };
 608
 609 struct ring_info {
 610         struct sk_buff  *skb;
 611         u32             len;
 612         u8              __pad[sizeof(void *) - sizeof(u32)];
 613 };
 614
 615 enum features {
 616         RTL_FEATURE_WOL         = (1 << 0),
 617         RTL_FEATURE_MSI         = (1 << 1),
 618         RTL_FEATURE_GMII        = (1 << 2),
 619 };
 620
 621 struct rtl8169_counters {
 622         __le64  tx_packets;
 623         __le64  rx_packets;
 624         __le64  tx_errors;
 625         __le32  rx_errors;
 626         __le16  rx_missed;
 627         __le16  align_errors;
 628         __le32  tx_one_collision;
 629         __le32  tx_multi_collision;
 630         __le64  rx_unicast;
 631         __le64  rx_broadcast;
 632         __le32  rx_multicast;
 633         __le16  tx_aborted;
 634         __le16  tx_underun;
 635 };
 636
 637 struct rtl8169_private {
 638         void __iomem *mmio_addr;        /* memory map physical address */
 639         struct pci_dev *pci_dev;
 640         struct net_device *dev;
 641         struct napi_struct napi;
 642         spinlock_t lock;
 643         u32 msg_enable;
 644         u16 txd_version;
 645         u16 mac_version;
 646         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 647         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 648         u32 dirty_rx;
 649         u32 dirty_tx;
 650         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 651         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 652         dma_addr_t TxPhyAddr;
 653         dma_addr_t RxPhyAddr;
 654         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 655         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 656         struct timer_list timer;
 657         u16 cp_cmd;
 658         u16 intr_event;
 659         u16 napi_event;
 660         u16 intr_mask;
 661
 662         struct mdio_ops {
 663                 void (*write)(void __iomem *, int, int);
 664                 int (*read)(void __iomem *, int);
 665         } mdio_ops;
 666
 667         struct pll_power_ops {
 668                 void (*down)(struct rtl8169_private *);
 669                 void (*up)(struct rtl8169_private *);
 670         } pll_power_ops;
 671
 672         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 673         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 674         void (*phy_reset_enable)(struct rtl8169_private *tp);
 675         void (*hw_start)(struct net_device *);
 676         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 677         unsigned int (*link_ok)(void __iomem *);
 678         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 679         struct delayed_work task;
 680         unsigned features;
 681
 682         struct mii_if_info mii;
 683         struct rtl8169_counters counters;
 684         u32 saved_wolopts;
 685
 686         struct rtl_fw {
 687                 const struct firmware *fw;
 688
 689 #define RTL_VER_SIZE            32
 690
 691                 char version[RTL_VER_SIZE];
 692
 693                 struct rtl_fw_phy_action {
 694                         __le32 *code;
 695                         size_t size;
 696                 } phy_action;
 697         } *rtl_fw;
 698 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 699 };
 700
 701 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 702 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 703 module_param(use_dac, int, 0);
 704 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 705 module_param_named(debug, debug.msg_enable, int, 0);
 706 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 707 MODULE_LICENSE("GPL");
 708 MODULE_VERSION(RTL8169_VERSION);
 709 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 710 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 711 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 712 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 713 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 714 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 715
 716 static int rtl8169_open(struct net_device *dev);
 717 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 718                                       struct net_device *dev);
 719 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 720 static int rtl8169_init_ring(struct net_device *dev);
 721 static void rtl_hw_start(struct net_device *dev);
 722 static int rtl8169_close(struct net_device *dev);
 723 static void rtl_set_rx_mode(struct net_device *dev);
 724 static void rtl8169_tx_timeout(struct net_device *dev);
 725 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 726 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 727                                 void __iomem *, u32 budget);
 728 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 729 static void rtl8169_down(struct net_device *dev);
 730 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 731 static int rtl8169_poll(struct napi_struct *napi, int budget);
 732
 733 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 734 {
 735         void __iomem *ioaddr = tp->mmio_addr;
 736         int i;
 737
 738         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 739         for (i = 0; i < 20; i++) {
 740                 udelay(100);
 741                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 742                         break;
 743         }
 744         return RTL_R32(OCPDR);
 745 }
 746
 747 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 748 {
 749         void __iomem *ioaddr = tp->mmio_addr;
 750         int i;
 751
 752         RTL_W32(OCPDR, data);
 753         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 754         for (i = 0; i < 20; i++) {
 755                 udelay(100);
 756                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 757                         break;
 758         }
 759 }
 760
 761 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 762 {
 763         void __iomem *ioaddr = tp->mmio_addr;
 764         int i;
 765
 766         RTL_W8(ERIDR, cmd);
 767         RTL_W32(ERIAR, 0x800010e8);
 768         msleep(2);
 769         for (i = 0; i < 5; i++) {
 770                 udelay(100);
 771                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 772                         break;
 773         }
 774
 775         ocp_write(tp, 0x1, 0x30, 0x00000001);
 776 }
 777
 778 #define OOB_CMD_RESET           0x00
 779 #define OOB_CMD_DRIVER_START    0x05
 780 #define OOB_CMD_DRIVER_STOP     0x06
 781
 782 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 783 {
 784         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 785 }
 786
 787 static void rtl8168_driver_start(struct rtl8169_private *tp)
 788 {
 789         u16 reg;
 790         int i;
 791
 792         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 793
 794         reg = rtl8168_get_ocp_reg(tp);
 795
 796         for (i = 0; i < 10; i++) {
 797                 msleep(10);
 798                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 799                         break;
 800         }
 801 }
 802
 803 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 804 {
 805         u16 reg;
 806         int i;
 807
 808         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 809
 810         reg = rtl8168_get_ocp_reg(tp);
 811
 812         for (i = 0; i < 10; i++) {
 813                 msleep(10);
 814                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 815                         break;
 816         }
 817 }
 818
 819 static int r8168dp_check_dash(struct rtl8169_private *tp)
 820 {
 821         u16 reg = rtl8168_get_ocp_reg(tp);
 822
 823         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 824 }
 825
 826 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 827 {
 828         int i;
 829
 830         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 831
 832         for (i = 20; i > 0; i--) {
 833                 /*
 834                  * Check if the RTL8169 has completed writing to the specified
 835                  * MII register.
 836                  */
 837                 if (!(RTL_R32(PHYAR) & 0x80000000))
 838                         break;
 839                 udelay(25);
 840         }
 841         /*
 842          * According to hardware specs a 20us delay is required after write
 843          * complete indication, but before sending next command.
 844          */
 845         udelay(20);
 846 }
 847
 848 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 849 {
 850         int i, value = -1;
 851
 852         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 853
 854         for (i = 20; i > 0; i--) {
 855                 /*
 856                  * Check if the RTL8169 has completed retrieving data from
 857                  * the specified MII register.
 858                  */
 859                 if (RTL_R32(PHYAR) & 0x80000000) {
 860                         value = RTL_R32(PHYAR) & 0xffff;
 861                         break;
 862                 }
 863                 udelay(25);
 864         }
 865         /*
 866          * According to hardware specs a 20us delay is required after read
 867          * complete indication, but before sending next command.
 868          */
 869         udelay(20);
 870
 871         return value;
 872 }
 873
 874 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 875 {
 876         int i;
 877
 878         RTL_W32(OCPDR, data |
 879                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 880         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 881         RTL_W32(EPHY_RXER_NUM, 0);
 882
 883         for (i = 0; i < 100; i++) {
 884                 mdelay(1);
 885                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 886                         break;
 887         }
 888 }
 889
 890 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 891 {
 892         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 893                 (value & OCPDR_DATA_MASK));
 894 }
 895
 896 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 897 {
 898         int i;
 899
 900         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 901
 902         mdelay(1);
 903         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 904         RTL_W32(EPHY_RXER_NUM, 0);
 905
 906         for (i = 0; i < 100; i++) {
 907                 mdelay(1);
 908                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 909                         break;
 910         }
 911
 912         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 913 }
 914
 915 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 916
 917 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 918 {
 919         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 920 }
 921
 922 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 923 {
 924         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 925 }
 926
 927 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 928 {
 929         r8168dp_2_mdio_start(ioaddr);
 930
 931         r8169_mdio_write(ioaddr, reg_addr, value);
 932
 933         r8168dp_2_mdio_stop(ioaddr);
 934 }
 935
 936 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 937 {
 938         int value;
 939
 940         r8168dp_2_mdio_start(ioaddr);
 941
 942         value = r8169_mdio_read(ioaddr, reg_addr);
 943
 944         r8168dp_2_mdio_stop(ioaddr);
 945
 946         return value;
 947 }
 948
 949 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 950 {
 951         tp->mdio_ops.write(tp->mmio_addr, location, val);
 952 }
 953
 954 static int rtl_readphy(struct rtl8169_private *tp, int location)
 955 {
 956         return tp->mdio_ops.read(tp->mmio_addr, location);
 957 }
 958
 959 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 960 {
 961         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 962 }
 963
 964 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 965 {
 966         int val;
 967
 968         val = rtl_readphy(tp, reg_addr);
 969         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 970 }
 971
 972 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 973                            int val)
 974 {
 975         struct rtl8169_private *tp = netdev_priv(dev);
 976
 977         rtl_writephy(tp, location, val);
 978 }
 979
 980 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 981 {
 982         struct rtl8169_private *tp = netdev_priv(dev);
 983
 984         return rtl_readphy(tp, location);
 985 }
 986
 987 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 988 {
 989         unsigned int i;
 990
 991         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 992                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 993
 994         for (i = 0; i < 100; i++) {
 995                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 996                         break;
 997                 udelay(10);
 998         }
 999 }
1000
1001 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1002 {
1003         u16 value = 0xffff;
1004         unsigned int i;
1005
1006         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1007
1008         for (i = 0; i < 100; i++) {
1009                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1010                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1011                         break;
1012                 }
1013                 udelay(10);
1014         }
1015
1016         return value;
1017 }
1018
1019 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1020 {
1021         unsigned int i;
1022
1023         RTL_W32(CSIDR, value);
1024         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1025                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1026
1027         for (i = 0; i < 100; i++) {
1028                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1029                         break;
1030                 udelay(10);
1031         }
1032 }
1033
1034 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1035 {
1036         u32 value = ~0x00;
1037         unsigned int i;
1038
1039         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1040                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1041
1042         for (i = 0; i < 100; i++) {
1043                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1044                         value = RTL_R32(CSIDR);
1045                         break;
1046                 }
1047                 udelay(10);
1048         }
1049
1050         return value;
1051 }
1052
1053 static
1054 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1055 {
1056         unsigned int i;
1057
1058         BUG_ON((addr & 3) || (mask == 0));
1059         RTL_W32(ERIDR, val);
1060         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1061
1062         for (i = 0; i < 100; i++) {
1063                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1064                         break;
1065                 udelay(100);
1066         }
1067 }
1068
1069 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1070 {
1071         u32 value = ~0x00;
1072         unsigned int i;
1073
1074         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1075
1076         for (i = 0; i < 100; i++) {
1077                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1078                         value = RTL_R32(ERIDR);
1079                         break;
1080                 }
1081                 udelay(100);
1082         }
1083
1084         return value;
1085 }
1086
1087 static void
1088 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1089 {
1090         u32 val;
1091
1092         val = rtl_eri_read(ioaddr, addr, type);
1093         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1094 }
1095
1096 struct exgmac_reg {
1097         u16 addr;
1098         u16 mask;
1099         u32 val;
1100 };
1101
1102 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1103                                    const struct exgmac_reg *r, int len)
1104 {
1105         while (len-- > 0) {
1106                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1107                 r++;
1108         }
1109 }
1110
1111 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1112 {
1113         u8 value = 0xff;
1114         unsigned int i;
1115
1116         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1117
1118         for (i = 0; i < 300; i++) {
1119                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1120                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1121                         break;
1122                 }
1123                 udelay(100);
1124         }
1125
1126         return value;
1127 }
1128
1129 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1130 {
1131         RTL_W16(IntrMask, 0x0000);
1132
1133         RTL_W16(IntrStatus, 0xffff);
1134 }
1135
1136 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1137 {
1138         void __iomem *ioaddr = tp->mmio_addr;
1139
1140         return RTL_R32(TBICSR) & TBIReset;
1141 }
1142
1143 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1144 {
1145         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1146 }
1147
1148 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1149 {
1150         return RTL_R32(TBICSR) & TBILinkOk;
1151 }
1152
1153 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1154 {
1155         return RTL_R8(PHYstatus) & LinkStatus;
1156 }
1157
1158 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1159 {
1160         void __iomem *ioaddr = tp->mmio_addr;
1161
1162         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1163 }
1164
1165 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1166 {
1167         unsigned int val;
1168
1169         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1170         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1171 }
1172
1173 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1174 {
1175         void __iomem *ioaddr = tp->mmio_addr;
1176         struct net_device *dev = tp->dev;
1177
1178         if (!netif_running(dev))
1179                 return;
1180
1181         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1182                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1183                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1184                                       0x00000011, ERIAR_EXGMAC);
1185                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1186                                       0x00000005, ERIAR_EXGMAC);
1187                 } else if (RTL_R8(PHYstatus) & _100bps) {
1188                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1189                                       0x0000001f, ERIAR_EXGMAC);
1190                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1191                                       0x00000005, ERIAR_EXGMAC);
1192                 } else {
1193                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1194                                       0x0000001f, ERIAR_EXGMAC);
1195                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1196                                       0x0000003f, ERIAR_EXGMAC);
1197                 }
1198                 /* Reset packet filter */
1199                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1200                              ERIAR_EXGMAC);
1201                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1202                              ERIAR_EXGMAC);
1203         }
1204 }
1205
1206 static void __rtl8169_check_link_status(struct net_device *dev,
1207                                         struct rtl8169_private *tp,
1208                                         void __iomem *ioaddr, bool pm)
1209 {
1210         unsigned long flags;
1211
1212         spin_lock_irqsave(&tp->lock, flags);
1213         if (tp->link_ok(ioaddr)) {
1214                 rtl_link_chg_patch(tp);
1215                 /* This is to cancel a scheduled suspend if there's one. */
1216                 if (pm)
1217                         pm_request_resume(&tp->pci_dev->dev);
1218                 netif_carrier_on(dev);
1219                 if (net_ratelimit())
1220                         netif_info(tp, ifup, dev, "link up\n");
1221         } else {
1222                 netif_carrier_off(dev);
1223                 netif_info(tp, ifdown, dev, "link down\n");
1224                 if (pm)
1225                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1226         }
1227         spin_unlock_irqrestore(&tp->lock, flags);
1228 }
1229
1230 static void rtl8169_check_link_status(struct net_device *dev,
1231                                       struct rtl8169_private *tp,
1232                                       void __iomem *ioaddr)
1233 {
1234         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1235 }
1236
1237 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1238
1239 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1240 {
1241         void __iomem *ioaddr = tp->mmio_addr;
1242         u8 options;
1243         u32 wolopts = 0;
1244
1245         options = RTL_R8(Config1);
1246         if (!(options & PMEnable))
1247                 return 0;
1248
1249         options = RTL_R8(Config3);
1250         if (options & LinkUp)
1251                 wolopts |= WAKE_PHY;
1252         if (options & MagicPacket)
1253                 wolopts |= WAKE_MAGIC;
1254
1255         options = RTL_R8(Config5);
1256         if (options & UWF)
1257                 wolopts |= WAKE_UCAST;
1258         if (options & BWF)
1259                 wolopts |= WAKE_BCAST;
1260         if (options & MWF)
1261                 wolopts |= WAKE_MCAST;
1262
1263         return wolopts;
1264 }
1265
1266 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1267 {
1268         struct rtl8169_private *tp = netdev_priv(dev);
1269
1270         spin_lock_irq(&tp->lock);
1271
1272         wol->supported = WAKE_ANY;
1273         wol->wolopts = __rtl8169_get_wol(tp);
1274
1275         spin_unlock_irq(&tp->lock);
1276 }
1277
1278 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1279 {
1280         void __iomem *ioaddr = tp->mmio_addr;
1281         unsigned int i;
1282         static const struct {
1283                 u32 opt;
1284                 u16 reg;
1285                 u8  mask;
1286         } cfg[] = {
1287                 { WAKE_ANY,   Config1, PMEnable },
1288                 { WAKE_PHY,   Config3, LinkUp },
1289                 { WAKE_MAGIC, Config3, MagicPacket },
1290                 { WAKE_UCAST, Config5, UWF },
1291                 { WAKE_BCAST, Config5, BWF },
1292                 { WAKE_MCAST, Config5, MWF },
1293                 { WAKE_ANY,   Config5, LanWake }
1294         };
1295
1296         RTL_W8(Cfg9346, Cfg9346_Unlock);
1297
1298         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1299                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1300                 if (wolopts & cfg[i].opt)
1301                         options |= cfg[i].mask;
1302                 RTL_W8(cfg[i].reg, options);
1303         }
1304
1305         RTL_W8(Cfg9346, Cfg9346_Lock);
1306 }
1307
1308 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1309 {
1310         struct rtl8169_private *tp = netdev_priv(dev);
1311
1312         spin_lock_irq(&tp->lock);
1313
1314         if (wol->wolopts)
1315                 tp->features |= RTL_FEATURE_WOL;
1316         else
1317                 tp->features &= ~RTL_FEATURE_WOL;
1318         __rtl8169_set_wol(tp, wol->wolopts);
1319         spin_unlock_irq(&tp->lock);
1320
1321         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1322
1323         return 0;
1324 }
1325
1326 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1327 {
1328         return rtl_chip_infos[tp->mac_version].fw_name;
1329 }
1330
1331 static void rtl8169_get_drvinfo(struct net_device *dev,
1332                                 struct ethtool_drvinfo *info)
1333 {
1334         struct rtl8169_private *tp = netdev_priv(dev);
1335         struct rtl_fw *rtl_fw = tp->rtl_fw;
1336
1337         strcpy(info->driver, MODULENAME);
1338         strcpy(info->version, RTL8169_VERSION);
1339         strcpy(info->bus_info, pci_name(tp->pci_dev));
1340         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1341         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1342                rtl_fw->version);
1343 }
1344
1345 static int rtl8169_get_regs_len(struct net_device *dev)
1346 {
1347         return R8169_REGS_SIZE;
1348 }
1349
1350 static int rtl8169_set_speed_tbi(struct net_device *dev,
1351                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1352 {
1353         struct rtl8169_private *tp = netdev_priv(dev);
1354         void __iomem *ioaddr = tp->mmio_addr;
1355         int ret = 0;
1356         u32 reg;
1357
1358         reg = RTL_R32(TBICSR);
1359         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1360             (duplex == DUPLEX_FULL)) {
1361                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1362         } else if (autoneg == AUTONEG_ENABLE)
1363                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1364         else {
1365                 netif_warn(tp, link, dev,
1366                            "incorrect speed setting refused in TBI mode\n");
1367                 ret = -EOPNOTSUPP;
1368         }
1369
1370         return ret;
1371 }
1372
1373 static int rtl8169_set_speed_xmii(struct net_device *dev,
1374                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1375 {
1376         struct rtl8169_private *tp = netdev_priv(dev);
1377         int giga_ctrl, bmcr;
1378         int rc = -EINVAL;
1379
1380         rtl_writephy(tp, 0x1f, 0x0000);
1381
1382         if (autoneg == AUTONEG_ENABLE) {
1383                 int auto_nego;
1384
1385                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1386                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1387                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1388
1389                 if (adv & ADVERTISED_10baseT_Half)
1390                         auto_nego |= ADVERTISE_10HALF;
1391                 if (adv & ADVERTISED_10baseT_Full)
1392                         auto_nego |= ADVERTISE_10FULL;
1393                 if (adv & ADVERTISED_100baseT_Half)
1394                         auto_nego |= ADVERTISE_100HALF;
1395                 if (adv & ADVERTISED_100baseT_Full)
1396                         auto_nego |= ADVERTISE_100FULL;
1397
1398                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1399
1400                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1401                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1402
1403                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1404                 if (tp->mii.supports_gmii) {
1405                         if (adv & ADVERTISED_1000baseT_Half)
1406                                 giga_ctrl |= ADVERTISE_1000HALF;
1407                         if (adv & ADVERTISED_1000baseT_Full)
1408                                 giga_ctrl |= ADVERTISE_1000FULL;
1409                 } else if (adv & (ADVERTISED_1000baseT_Half |
1410                                   ADVERTISED_1000baseT_Full)) {
1411                         netif_info(tp, link, dev,
1412                                    "PHY does not support 1000Mbps\n");
1413                         goto out;
1414                 }
1415
1416                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1417
1418                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1419                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1420         } else {
1421                 giga_ctrl = 0;
1422
1423                 if (speed == SPEED_10)
1424                         bmcr = 0;
1425                 else if (speed == SPEED_100)
1426                         bmcr = BMCR_SPEED100;
1427                 else
1428                         goto out;
1429
1430                 if (duplex == DUPLEX_FULL)
1431                         bmcr |= BMCR_FULLDPLX;
1432         }
1433
1434         rtl_writephy(tp, MII_BMCR, bmcr);
1435
1436         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1437             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1438                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1439                         rtl_writephy(tp, 0x17, 0x2138);
1440                         rtl_writephy(tp, 0x0e, 0x0260);
1441                 } else {
1442                         rtl_writephy(tp, 0x17, 0x2108);
1443                         rtl_writephy(tp, 0x0e, 0x0000);
1444                 }
1445         }
1446
1447         rc = 0;
1448 out:
1449         return rc;
1450 }
1451
1452 static int rtl8169_set_speed(struct net_device *dev,
1453                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1454 {
1455         struct rtl8169_private *tp = netdev_priv(dev);
1456         int ret;
1457
1458         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1459         if (ret < 0)
1460                 goto out;
1461
1462         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1463             (advertising & ADVERTISED_1000baseT_Full)) {
1464                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1465         }
1466 out:
1467         return ret;
1468 }
1469
1470 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1471 {
1472         struct rtl8169_private *tp = netdev_priv(dev);
1473         unsigned long flags;
1474         int ret;
1475
1476         del_timer_sync(&tp->timer);
1477
1478         spin_lock_irqsave(&tp->lock, flags);
1479         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1480                                 cmd->duplex, cmd->advertising);
1481         spin_unlock_irqrestore(&tp->lock, flags);
1482
1483         return ret;
1484 }
1485
1486 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1487 {
1488         if (dev->mtu > TD_MSS_MAX)
1489                 features &= ~NETIF_F_ALL_TSO;
1490
1491         return features;
1492 }
1493
1494 static int rtl8169_set_features(struct net_device *dev, u32 features)
1495 {
1496         struct rtl8169_private *tp = netdev_priv(dev);
1497         void __iomem *ioaddr = tp->mmio_addr;
1498         unsigned long flags;
1499
1500         spin_lock_irqsave(&tp->lock, flags);
1501
1502         if (features & NETIF_F_RXCSUM)
1503                 tp->cp_cmd |= RxChkSum;
1504         else
1505                 tp->cp_cmd &= ~RxChkSum;
1506
1507         if (dev->features & NETIF_F_HW_VLAN_RX)
1508                 tp->cp_cmd |= RxVlan;
1509         else
1510                 tp->cp_cmd &= ~RxVlan;
1511
1512         RTL_W16(CPlusCmd, tp->cp_cmd);
1513         RTL_R16(CPlusCmd);
1514
1515         spin_unlock_irqrestore(&tp->lock, flags);
1516
1517         return 0;
1518 }
1519
1520 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1521                                       struct sk_buff *skb)
1522 {
1523         return (vlan_tx_tag_present(skb)) ?
1524                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1525 }
1526
1527 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1528 {
1529         u32 opts2 = le32_to_cpu(desc->opts2);
1530
1531         if (opts2 & RxVlanTag)
1532                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1533
1534         desc->opts2 = 0;
1535 }
1536
1537 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1538 {
1539         struct rtl8169_private *tp = netdev_priv(dev);
1540         void __iomem *ioaddr = tp->mmio_addr;
1541         u32 status;
1542
1543         cmd->supported =
1544                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1545         cmd->port = PORT_FIBRE;
1546         cmd->transceiver = XCVR_INTERNAL;
1547
1548         status = RTL_R32(TBICSR);
1549         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1550         cmd->autoneg = !!(status & TBINwEnable);
1551
1552         ethtool_cmd_speed_set(cmd, SPEED_1000);
1553         cmd->duplex = DUPLEX_FULL; /* Always set */
1554
1555         return 0;
1556 }
1557
1558 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1559 {
1560         struct rtl8169_private *tp = netdev_priv(dev);
1561
1562         return mii_ethtool_gset(&tp->mii, cmd);
1563 }
1564
1565 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1566 {
1567         struct rtl8169_private *tp = netdev_priv(dev);
1568         unsigned long flags;
1569         int rc;
1570
1571         spin_lock_irqsave(&tp->lock, flags);
1572
1573         rc = tp->get_settings(dev, cmd);
1574
1575         spin_unlock_irqrestore(&tp->lock, flags);
1576         return rc;
1577 }
1578
1579 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1580                              void *p)
1581 {
1582         struct rtl8169_private *tp = netdev_priv(dev);
1583         unsigned long flags;
1584
1585         if (regs->len > R8169_REGS_SIZE)
1586                 regs->len = R8169_REGS_SIZE;
1587
1588         spin_lock_irqsave(&tp->lock, flags);
1589         memcpy_fromio(p, tp->mmio_addr, regs->len);
1590         spin_unlock_irqrestore(&tp->lock, flags);
1591 }
1592
1593 static u32 rtl8169_get_msglevel(struct net_device *dev)
1594 {
1595         struct rtl8169_private *tp = netdev_priv(dev);
1596
1597         return tp->msg_enable;
1598 }
1599
1600 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1601 {
1602         struct rtl8169_private *tp = netdev_priv(dev);
1603
1604         tp->msg_enable = value;
1605 }
1606
1607 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1608         "tx_packets",
1609         "rx_packets",
1610         "tx_errors",
1611         "rx_errors",
1612         "rx_missed",
1613         "align_errors",
1614         "tx_single_collisions",
1615         "tx_multi_collisions",
1616         "unicast",
1617         "broadcast",
1618         "multicast",
1619         "tx_aborted",
1620         "tx_underrun",
1621 };
1622
1623 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1624 {
1625         switch (sset) {
1626         case ETH_SS_STATS:
1627                 return ARRAY_SIZE(rtl8169_gstrings);
1628         default:
1629                 return -EOPNOTSUPP;
1630         }
1631 }
1632
1633 static void rtl8169_update_counters(struct net_device *dev)
1634 {
1635         struct rtl8169_private *tp = netdev_priv(dev);
1636         void __iomem *ioaddr = tp->mmio_addr;
1637         struct device *d = &tp->pci_dev->dev;
1638         struct rtl8169_counters *counters;
1639         dma_addr_t paddr;
1640         u32 cmd;
1641         int wait = 1000;
1642
1643         /*
1644          * Some chips are unable to dump tally counters when the receiver
1645          * is disabled.
1646          */
1647         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1648                 return;
1649
1650         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1651         if (!counters)
1652                 return;
1653
1654         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1655         cmd = (u64)paddr & DMA_BIT_MASK(32);
1656         RTL_W32(CounterAddrLow, cmd);
1657         RTL_W32(CounterAddrLow, cmd | CounterDump);
1658
1659         while (wait--) {
1660                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1661                         memcpy(&tp->counters, counters, sizeof(*counters));
1662                         break;
1663                 }
1664                 udelay(10);
1665         }
1666
1667         RTL_W32(CounterAddrLow, 0);
1668         RTL_W32(CounterAddrHigh, 0);
1669
1670         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1671 }
1672
1673 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1674                                       struct ethtool_stats *stats, u64 *data)
1675 {
1676         struct rtl8169_private *tp = netdev_priv(dev);
1677
1678         ASSERT_RTNL();
1679
1680         rtl8169_update_counters(dev);
1681
1682         data[0] = le64_to_cpu(tp->counters.tx_packets);
1683         data[1] = le64_to_cpu(tp->counters.rx_packets);
1684         data[2] = le64_to_cpu(tp->counters.tx_errors);
1685         data[3] = le32_to_cpu(tp->counters.rx_errors);
1686         data[4] = le16_to_cpu(tp->counters.rx_missed);
1687         data[5] = le16_to_cpu(tp->counters.align_errors);
1688         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1689         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1690         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1691         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1692         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1693         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1694         data[12] = le16_to_cpu(tp->counters.tx_underun);
1695 }
1696
1697 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1698 {
1699         switch(stringset) {
1700         case ETH_SS_STATS:
1701                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1702                 break;
1703         }
1704 }
1705
1706 static const struct ethtool_ops rtl8169_ethtool_ops = {
1707         .get_drvinfo            = rtl8169_get_drvinfo,
1708         .get_regs_len           = rtl8169_get_regs_len,
1709         .get_link               = ethtool_op_get_link,
1710         .get_settings           = rtl8169_get_settings,
1711         .set_settings           = rtl8169_set_settings,
1712         .get_msglevel           = rtl8169_get_msglevel,
1713         .set_msglevel           = rtl8169_set_msglevel,
1714         .get_regs               = rtl8169_get_regs,
1715         .get_wol                = rtl8169_get_wol,
1716         .set_wol                = rtl8169_set_wol,
1717         .get_strings            = rtl8169_get_strings,
1718         .get_sset_count         = rtl8169_get_sset_count,
1719         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1720 };
1721
1722 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1723                                     struct net_device *dev, u8 default_version)
1724 {
1725         void __iomem *ioaddr = tp->mmio_addr;
1726         /*
1727          * The driver currently handles the 8168Bf and the 8168Be identically
1728          * but they can be identified more specifically through the test below
1729          * if needed:
1730          *
1731          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1732          *
1733          * Same thing for the 8101Eb and the 8101Ec:
1734          *
1735          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1736          */
1737         static const struct rtl_mac_info {
1738                 u32 mask;
1739                 u32 val;
1740                 int mac_version;
1741         } mac_info[] = {
1742                 /* 8168E family. */
1743                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1744                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1745                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1746                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1747
1748                 /* 8168D family. */
1749                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1750                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1751                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1752
1753                 /* 8168DP family. */
1754                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1755                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1756                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1757
1758                 /* 8168C family. */
1759                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1760                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1761                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1762                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1763                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1764                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1765                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1766                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1767                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1768
1769                 /* 8168B family. */
1770                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1771                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1772                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1773                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1774
1775                 /* 8101 family. */
1776                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1777                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1778                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1779                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1780                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1781                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1782                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1783                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1784                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1785                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1786                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1787                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1788                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1789                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1790                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1791                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1792                 /* FIXME: where did these entries come from ? -- FR */
1793                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1794                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1795
1796                 /* 8110 family. */
1797                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1798                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1799                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1800                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1801                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1802                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1803
1804                 /* Catch-all */
1805                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1806         };
1807         const struct rtl_mac_info *p = mac_info;
1808         u32 reg;
1809
1810         reg = RTL_R32(TxConfig);
1811         while ((reg & p->mask) != p->val)
1812                 p++;
1813         tp->mac_version = p->mac_version;
1814
1815         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1816                 netif_notice(tp, probe, dev,
1817                              "unknown MAC, using family default\n");
1818                 tp->mac_version = default_version;
1819         }
1820 }
1821
1822 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1823 {
1824         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1825 }
1826
1827 struct phy_reg {
1828         u16 reg;
1829         u16 val;
1830 };
1831
1832 static void rtl_writephy_batch(struct rtl8169_private *tp,
1833                                const struct phy_reg *regs, int len)
1834 {
1835         while (len-- > 0) {
1836                 rtl_writephy(tp, regs->reg, regs->val);
1837                 regs++;
1838         }
1839 }
1840
1841 #define PHY_READ                0x00000000
1842 #define PHY_DATA_OR             0x10000000
1843 #define PHY_DATA_AND            0x20000000
1844 #define PHY_BJMPN               0x30000000
1845 #define PHY_READ_EFUSE          0x40000000
1846 #define PHY_READ_MAC_BYTE       0x50000000
1847 #define PHY_WRITE_MAC_BYTE      0x60000000
1848 #define PHY_CLEAR_READCOUNT     0x70000000
1849 #define PHY_WRITE               0x80000000
1850 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1851 #define PHY_COMP_EQ_SKIPN       0xa0000000
1852 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1853 #define PHY_WRITE_PREVIOUS      0xc0000000
1854 #define PHY_SKIPN               0xd0000000
1855 #define PHY_DELAY_MS            0xe0000000
1856 #define PHY_WRITE_ERI_WORD      0xf0000000
1857
1858 struct fw_info {
1859         u32     magic;
1860         char    version[RTL_VER_SIZE];
1861         __le32  fw_start;
1862         __le32  fw_len;
1863         u8      chksum;
1864 } __packed;
1865
1866 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1867
1868 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1869 {
1870         const struct firmware *fw = rtl_fw->fw;
1871         struct fw_info *fw_info = (struct fw_info *)fw->data;
1872         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1873         char *version = rtl_fw->version;
1874         bool rc = false;
1875
1876         if (fw->size < FW_OPCODE_SIZE)
1877                 goto out;
1878
1879         if (!fw_info->magic) {
1880                 size_t i, size, start;
1881                 u8 checksum = 0;
1882
1883                 if (fw->size < sizeof(*fw_info))
1884                         goto out;
1885
1886                 for (i = 0; i < fw->size; i++)
1887                         checksum += fw->data[i];
1888                 if (checksum != 0)
1889                         goto out;
1890
1891                 start = le32_to_cpu(fw_info->fw_start);
1892                 if (start > fw->size)
1893                         goto out;
1894
1895                 size = le32_to_cpu(fw_info->fw_len);
1896                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1897                         goto out;
1898
1899                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1900
1901                 pa->code = (__le32 *)(fw->data + start);
1902                 pa->size = size;
1903         } else {
1904                 if (fw->size % FW_OPCODE_SIZE)
1905                         goto out;
1906
1907                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1908
1909                 pa->code = (__le32 *)fw->data;
1910                 pa->size = fw->size / FW_OPCODE_SIZE;
1911         }
1912         version[RTL_VER_SIZE - 1] = 0;
1913
1914         rc = true;
1915 out:
1916         return rc;
1917 }
1918
1919 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1920                            struct rtl_fw_phy_action *pa)
1921 {
1922         bool rc = false;
1923         size_t index;
1924
1925         for (index = 0; index < pa->size; index++) {
1926                 u32 action = le32_to_cpu(pa->code[index]);
1927                 u32 regno = (action & 0x0fff0000) >> 16;
1928
1929                 switch(action & 0xf0000000) {
1930                 case PHY_READ:
1931                 case PHY_DATA_OR:
1932                 case PHY_DATA_AND:
1933                 case PHY_READ_EFUSE:
1934                 case PHY_CLEAR_READCOUNT:
1935                 case PHY_WRITE:
1936                 case PHY_WRITE_PREVIOUS:
1937                 case PHY_DELAY_MS:
1938                         break;
1939
1940                 case PHY_BJMPN:
1941                         if (regno > index) {
1942                                 netif_err(tp, ifup, tp->dev,
1943                                           "Out of range of firmware\n");
1944                                 goto out;
1945                         }
1946                         break;
1947                 case PHY_READCOUNT_EQ_SKIP:
1948                         if (index + 2 >= pa->size) {
1949                                 netif_err(tp, ifup, tp->dev,
1950                                           "Out of range of firmware\n");
1951                                 goto out;
1952                         }
1953                         break;
1954                 case PHY_COMP_EQ_SKIPN:
1955                 case PHY_COMP_NEQ_SKIPN:
1956                 case PHY_SKIPN:
1957                         if (index + 1 + regno >= pa->size) {
1958                                 netif_err(tp, ifup, tp->dev,
1959                                           "Out of range of firmware\n");
1960                                 goto out;
1961                         }
1962                         break;
1963
1964                 case PHY_READ_MAC_BYTE:
1965                 case PHY_WRITE_MAC_BYTE:
1966                 case PHY_WRITE_ERI_WORD:
1967                 default:
1968                         netif_err(tp, ifup, tp->dev,
1969                                   "Invalid action 0x%08x\n", action);
1970                         goto out;
1971                 }
1972         }
1973         rc = true;
1974 out:
1975         return rc;
1976 }
1977
1978 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1979 {
1980         struct net_device *dev = tp->dev;
1981         int rc = -EINVAL;
1982
1983         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1984                 netif_err(tp, ifup, dev, "invalid firwmare\n");
1985                 goto out;
1986         }
1987
1988         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1989                 rc = 0;
1990 out:
1991         return rc;
1992 }
1993
1994 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1995 {
1996         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1997         u32 predata, count;
1998         size_t index;
1999
2000         predata = count = 0;
2001
2002         for (index = 0; index < pa->size; ) {
2003                 u32 action = le32_to_cpu(pa->code[index]);
2004                 u32 data = action & 0x0000ffff;
2005                 u32 regno = (action & 0x0fff0000) >> 16;
2006
2007                 if (!action)
2008                         break;
2009
2010                 switch(action & 0xf0000000) {
2011                 case PHY_READ:
2012                         predata = rtl_readphy(tp, regno);
2013                         count++;
2014                         index++;
2015                         break;
2016                 case PHY_DATA_OR:
2017                         predata |= data;
2018                         index++;
2019                         break;
2020                 case PHY_DATA_AND:
2021                         predata &= data;
2022                         index++;
2023                         break;
2024                 case PHY_BJMPN:
2025                         index -= regno;
2026                         break;
2027                 case PHY_READ_EFUSE:
2028                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2029                         index++;
2030                         break;
2031                 case PHY_CLEAR_READCOUNT:
2032                         count = 0;
2033                         index++;
2034                         break;
2035                 case PHY_WRITE:
2036                         rtl_writephy(tp, regno, data);
2037                         index++;
2038                         break;
2039                 case PHY_READCOUNT_EQ_SKIP:
2040                         index += (count == data) ? 2 : 1;
2041                         break;
2042                 case PHY_COMP_EQ_SKIPN:
2043                         if (predata == data)
2044                                 index += regno;
2045                         index++;
2046                         break;
2047                 case PHY_COMP_NEQ_SKIPN:
2048                         if (predata != data)
2049                                 index += regno;
2050                         index++;
2051                         break;
2052                 case PHY_WRITE_PREVIOUS:
2053                         rtl_writephy(tp, regno, predata);
2054                         index++;
2055                         break;
2056                 case PHY_SKIPN:
2057                         index += regno + 1;
2058                         break;
2059                 case PHY_DELAY_MS:
2060                         mdelay(data);
2061                         index++;
2062                         break;
2063
2064                 case PHY_READ_MAC_BYTE:
2065                 case PHY_WRITE_MAC_BYTE:
2066                 case PHY_WRITE_ERI_WORD:
2067                 default:
2068                         BUG();
2069                 }
2070         }
2071 }
2072
2073 static void rtl_release_firmware(struct rtl8169_private *tp)
2074 {
2075         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2076                 release_firmware(tp->rtl_fw->fw);
2077                 kfree(tp->rtl_fw);
2078         }
2079         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2080 }
2081
2082 static void rtl_apply_firmware(struct rtl8169_private *tp)
2083 {
2084         struct rtl_fw *rtl_fw = tp->rtl_fw;
2085
2086         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2087         if (!IS_ERR_OR_NULL(rtl_fw))
2088                 rtl_phy_write_fw(tp, rtl_fw);
2089 }
2090
2091 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2092 {
2093         if (rtl_readphy(tp, reg) != val)
2094                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2095         else
2096                 rtl_apply_firmware(tp);
2097 }
2098
2099 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2100 {
2101         static const struct phy_reg phy_reg_init[] = {
2102                 { 0x1f, 0x0001 },
2103                 { 0x06, 0x006e },
2104                 { 0x08, 0x0708 },
2105                 { 0x15, 0x4000 },
2106                 { 0x18, 0x65c7 },
2107
2108                 { 0x1f, 0x0001 },
2109                 { 0x03, 0x00a1 },
2110                 { 0x02, 0x0008 },
2111                 { 0x01, 0x0120 },
2112                 { 0x00, 0x1000 },
2113                 { 0x04, 0x0800 },
2114                 { 0x04, 0x0000 },
2115
2116                 { 0x03, 0xff41 },
2117                 { 0x02, 0xdf60 },
2118                 { 0x01, 0x0140 },
2119                 { 0x00, 0x0077 },
2120                 { 0x04, 0x7800 },
2121                 { 0x04, 0x7000 },
2122
2123                 { 0x03, 0x802f },
2124                 { 0x02, 0x4f02 },
2125                 { 0x01, 0x0409 },
2126                 { 0x00, 0xf0f9 },
2127                 { 0x04, 0x9800 },
2128                 { 0x04, 0x9000 },
2129
2130                 { 0x03, 0xdf01 },
2131                 { 0x02, 0xdf20 },
2132                 { 0x01, 0xff95 },
2133                 { 0x00, 0xba00 },
2134                 { 0x04, 0xa800 },
2135                 { 0x04, 0xa000 },
2136
2137                 { 0x03, 0xff41 },
2138                 { 0x02, 0xdf20 },
2139                 { 0x01, 0x0140 },
2140                 { 0x00, 0x00bb },
2141                 { 0x04, 0xb800 },
2142                 { 0x04, 0xb000 },
2143
2144                 { 0x03, 0xdf41 },
2145                 { 0x02, 0xdc60 },
2146                 { 0x01, 0x6340 },
2147                 { 0x00, 0x007d },
2148                 { 0x04, 0xd800 },
2149                 { 0x04, 0xd000 },
2150
2151                 { 0x03, 0xdf01 },
2152                 { 0x02, 0xdf20 },
2153                 { 0x01, 0x100a },
2154                 { 0x00, 0xa0ff },
2155                 { 0x04, 0xf800 },
2156                 { 0x04, 0xf000 },
2157
2158                 { 0x1f, 0x0000 },
2159                 { 0x0b, 0x0000 },
2160                 { 0x00, 0x9200 }
2161         };
2162
2163         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2164 }
2165
2166 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2167 {
2168         static const struct phy_reg phy_reg_init[] = {
2169                 { 0x1f, 0x0002 },
2170                 { 0x01, 0x90d0 },
2171                 { 0x1f, 0x0000 }
2172         };
2173
2174         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2175 }
2176
2177 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2178 {
2179         struct pci_dev *pdev = tp->pci_dev;
2180
2181         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2182             (pdev->subsystem_device != 0xe000))
2183                 return;
2184
2185         rtl_writephy(tp, 0x1f, 0x0001);
2186         rtl_writephy(tp, 0x10, 0xf01b);
2187         rtl_writephy(tp, 0x1f, 0x0000);
2188 }
2189
2190 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2191 {
2192         static const struct phy_reg phy_reg_init[] = {
2193                 { 0x1f, 0x0001 },
2194                 { 0x04, 0x0000 },
2195                 { 0x03, 0x00a1 },
2196                 { 0x02, 0x0008 },
2197                 { 0x01, 0x0120 },
2198                 { 0x00, 0x1000 },
2199                 { 0x04, 0x0800 },
2200                 { 0x04, 0x9000 },
2201                 { 0x03, 0x802f },
2202                 { 0x02, 0x4f02 },
2203                 { 0x01, 0x0409 },
2204                 { 0x00, 0xf099 },
2205                 { 0x04, 0x9800 },
2206                 { 0x04, 0xa000 },
2207                 { 0x03, 0xdf01 },
2208                 { 0x02, 0xdf20 },
2209                 { 0x01, 0xff95 },
2210                 { 0x00, 0xba00 },
2211                 { 0x04, 0xa800 },
2212                 { 0x04, 0xf000 },
2213                 { 0x03, 0xdf01 },
2214                 { 0x02, 0xdf20 },
2215                 { 0x01, 0x101a },
2216                 { 0x00, 0xa0ff },
2217                 { 0x04, 0xf800 },
2218                 { 0x04, 0x0000 },
2219                 { 0x1f, 0x0000 },
2220
2221                 { 0x1f, 0x0001 },
2222                 { 0x10, 0xf41b },
2223                 { 0x14, 0xfb54 },
2224                 { 0x18, 0xf5c7 },
2225                 { 0x1f, 0x0000 },
2226
2227                 { 0x1f, 0x0001 },
2228                 { 0x17, 0x0cc0 },
2229                 { 0x1f, 0x0000 }
2230         };
2231
2232         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2233
2234         rtl8169scd_hw_phy_config_quirk(tp);
2235 }
2236
2237 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2238 {
2239         static const struct phy_reg phy_reg_init[] = {
2240                 { 0x1f, 0x0001 },
2241                 { 0x04, 0x0000 },
2242                 { 0x03, 0x00a1 },
2243                 { 0x02, 0x0008 },
2244                 { 0x01, 0x0120 },
2245                 { 0x00, 0x1000 },
2246                 { 0x04, 0x0800 },
2247                 { 0x04, 0x9000 },
2248                 { 0x03, 0x802f },
2249                 { 0x02, 0x4f02 },
2250                 { 0x01, 0x0409 },
2251                 { 0x00, 0xf099 },
2252                 { 0x04, 0x9800 },
2253                 { 0x04, 0xa000 },
2254                 { 0x03, 0xdf01 },
2255                 { 0x02, 0xdf20 },
2256                 { 0x01, 0xff95 },
2257                 { 0x00, 0xba00 },
2258                 { 0x04, 0xa800 },
2259                 { 0x04, 0xf000 },
2260                 { 0x03, 0xdf01 },
2261                 { 0x02, 0xdf20 },
2262                 { 0x01, 0x101a },
2263                 { 0x00, 0xa0ff },
2264                 { 0x04, 0xf800 },
2265                 { 0x04, 0x0000 },
2266                 { 0x1f, 0x0000 },
2267
2268                 { 0x1f, 0x0001 },
2269                 { 0x0b, 0x8480 },
2270                 { 0x1f, 0x0000 },
2271
2272                 { 0x1f, 0x0001 },
2273                 { 0x18, 0x67c7 },
2274                 { 0x04, 0x2000 },
2275                 { 0x03, 0x002f },
2276                 { 0x02, 0x4360 },
2277                 { 0x01, 0x0109 },
2278                 { 0x00, 0x3022 },
2279                 { 0x04, 0x2800 },
2280                 { 0x1f, 0x0000 },
2281
2282                 { 0x1f, 0x0001 },
2283                 { 0x17, 0x0cc0 },
2284                 { 0x1f, 0x0000 }
2285         };
2286
2287         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2288 }
2289
2290 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2291 {
2292         static const struct phy_reg phy_reg_init[] = {
2293                 { 0x10, 0xf41b },
2294                 { 0x1f, 0x0000 }
2295         };
2296
2297         rtl_writephy(tp, 0x1f, 0x0001);
2298         rtl_patchphy(tp, 0x16, 1 << 0);
2299
2300         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2301 }
2302
2303 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2304 {
2305         static const struct phy_reg phy_reg_init[] = {
2306                 { 0x1f, 0x0001 },
2307                 { 0x10, 0xf41b },
2308                 { 0x1f, 0x0000 }
2309         };
2310
2311         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2312 }
2313
2314 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2315 {
2316         static const struct phy_reg phy_reg_init[] = {
2317                 { 0x1f, 0x0000 },
2318                 { 0x1d, 0x0f00 },
2319                 { 0x1f, 0x0002 },
2320                 { 0x0c, 0x1ec8 },
2321                 { 0x1f, 0x0000 }
2322         };
2323
2324         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2325 }
2326
2327 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2328 {
2329         static const struct phy_reg phy_reg_init[] = {
2330                 { 0x1f, 0x0001 },
2331                 { 0x1d, 0x3d98 },
2332                 { 0x1f, 0x0000 }
2333         };
2334
2335         rtl_writephy(tp, 0x1f, 0x0000);
2336         rtl_patchphy(tp, 0x14, 1 << 5);
2337         rtl_patchphy(tp, 0x0d, 1 << 5);
2338
2339         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2340 }
2341
2342 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2343 {
2344         static const struct phy_reg phy_reg_init[] = {
2345                 { 0x1f, 0x0001 },
2346                 { 0x12, 0x2300 },
2347                 { 0x1f, 0x0002 },
2348                 { 0x00, 0x88d4 },
2349                 { 0x01, 0x82b1 },
2350                 { 0x03, 0x7002 },
2351                 { 0x08, 0x9e30 },
2352                 { 0x09, 0x01f0 },
2353                 { 0x0a, 0x5500 },
2354                 { 0x0c, 0x00c8 },
2355                 { 0x1f, 0x0003 },
2356                 { 0x12, 0xc096 },
2357                 { 0x16, 0x000a },
2358                 { 0x1f, 0x0000 },
2359                 { 0x1f, 0x0000 },
2360                 { 0x09, 0x2000 },
2361                 { 0x09, 0x0000 }
2362         };
2363
2364         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2365
2366         rtl_patchphy(tp, 0x14, 1 << 5);
2367         rtl_patchphy(tp, 0x0d, 1 << 5);
2368         rtl_writephy(tp, 0x1f, 0x0000);
2369 }
2370
2371 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2372 {
2373         static const struct phy_reg phy_reg_init[] = {
2374                 { 0x1f, 0x0001 },
2375                 { 0x12, 0x2300 },
2376                 { 0x03, 0x802f },
2377                 { 0x02, 0x4f02 },
2378                 { 0x01, 0x0409 },
2379                 { 0x00, 0xf099 },
2380                 { 0x04, 0x9800 },
2381                 { 0x04, 0x9000 },
2382                 { 0x1d, 0x3d98 },
2383                 { 0x1f, 0x0002 },
2384                 { 0x0c, 0x7eb8 },
2385                 { 0x06, 0x0761 },
2386                 { 0x1f, 0x0003 },
2387                 { 0x16, 0x0f0a },
2388                 { 0x1f, 0x0000 }
2389         };
2390
2391         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2392
2393         rtl_patchphy(tp, 0x16, 1 << 0);
2394         rtl_patchphy(tp, 0x14, 1 << 5);
2395         rtl_patchphy(tp, 0x0d, 1 << 5);
2396         rtl_writephy(tp, 0x1f, 0x0000);
2397 }
2398
2399 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2400 {
2401         static const struct phy_reg phy_reg_init[] = {
2402                 { 0x1f, 0x0001 },
2403                 { 0x12, 0x2300 },
2404                 { 0x1d, 0x3d98 },
2405                 { 0x1f, 0x0002 },
2406                 { 0x0c, 0x7eb8 },
2407                 { 0x06, 0x5461 },
2408                 { 0x1f, 0x0003 },
2409                 { 0x16, 0x0f0a },
2410                 { 0x1f, 0x0000 }
2411         };
2412
2413         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2414
2415         rtl_patchphy(tp, 0x16, 1 << 0);
2416         rtl_patchphy(tp, 0x14, 1 << 5);
2417         rtl_patchphy(tp, 0x0d, 1 << 5);
2418         rtl_writephy(tp, 0x1f, 0x0000);
2419 }
2420
2421 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2422 {
2423         rtl8168c_3_hw_phy_config(tp);
2424 }
2425
2426 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2427 {
2428         static const struct phy_reg phy_reg_init_0[] = {
2429                 /* Channel Estimation */
2430                 { 0x1f, 0x0001 },
2431                 { 0x06, 0x4064 },
2432                 { 0x07, 0x2863 },
2433                 { 0x08, 0x059c },
2434                 { 0x09, 0x26b4 },
2435                 { 0x0a, 0x6a19 },
2436                 { 0x0b, 0xdcc8 },
2437                 { 0x10, 0xf06d },
2438                 { 0x14, 0x7f68 },
2439                 { 0x18, 0x7fd9 },
2440                 { 0x1c, 0xf0ff },
2441                 { 0x1d, 0x3d9c },
2442                 { 0x1f, 0x0003 },
2443                 { 0x12, 0xf49f },
2444                 { 0x13, 0x070b },
2445                 { 0x1a, 0x05ad },
2446                 { 0x14, 0x94c0 },
2447
2448                 /*
2449                  * Tx Error Issue
2450                  * Enhance line driver power
2451                  */
2452                 { 0x1f, 0x0002 },
2453                 { 0x06, 0x5561 },
2454                 { 0x1f, 0x0005 },
2455                 { 0x05, 0x8332 },
2456                 { 0x06, 0x5561 },
2457
2458                 /*
2459                  * Can not link to 1Gbps with bad cable
2460                  * Decrease SNR threshold form 21.07dB to 19.04dB
2461                  */
2462                 { 0x1f, 0x0001 },
2463                 { 0x17, 0x0cc0 },
2464
2465                 { 0x1f, 0x0000 },
2466                 { 0x0d, 0xf880 }
2467         };
2468         void __iomem *ioaddr = tp->mmio_addr;
2469
2470         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2471
2472         /*
2473          * Rx Error Issue
2474          * Fine Tune Switching regulator parameter
2475          */
2476         rtl_writephy(tp, 0x1f, 0x0002);
2477         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2478         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2479
2480         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2481                 static const struct phy_reg phy_reg_init[] = {
2482                         { 0x1f, 0x0002 },
2483                         { 0x05, 0x669a },
2484                         { 0x1f, 0x0005 },
2485                         { 0x05, 0x8330 },
2486                         { 0x06, 0x669a },
2487                         { 0x1f, 0x0002 }
2488                 };
2489                 int val;
2490
2491                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2492
2493                 val = rtl_readphy(tp, 0x0d);
2494
2495                 if ((val & 0x00ff) != 0x006c) {
2496                         static const u32 set[] = {
2497                                 0x0065, 0x0066, 0x0067, 0x0068,
2498                                 0x0069, 0x006a, 0x006b, 0x006c
2499                         };
2500                         int i;
2501
2502                         rtl_writephy(tp, 0x1f, 0x0002);
2503
2504                         val &= 0xff00;
2505                         for (i = 0; i < ARRAY_SIZE(set); i++)
2506                                 rtl_writephy(tp, 0x0d, val | set[i]);
2507                 }
2508         } else {
2509                 static const struct phy_reg phy_reg_init[] = {
2510                         { 0x1f, 0x0002 },
2511                         { 0x05, 0x6662 },
2512                         { 0x1f, 0x0005 },
2513                         { 0x05, 0x8330 },
2514                         { 0x06, 0x6662 }
2515                 };
2516
2517                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2518         }
2519
2520         /* RSET couple improve */
2521         rtl_writephy(tp, 0x1f, 0x0002);
2522         rtl_patchphy(tp, 0x0d, 0x0300);
2523         rtl_patchphy(tp, 0x0f, 0x0010);
2524
2525         /* Fine tune PLL performance */
2526         rtl_writephy(tp, 0x1f, 0x0002);
2527         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2528         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2529
2530         rtl_writephy(tp, 0x1f, 0x0005);
2531         rtl_writephy(tp, 0x05, 0x001b);
2532
2533         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2534
2535         rtl_writephy(tp, 0x1f, 0x0000);
2536 }
2537
2538 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2539 {
2540         static const struct phy_reg phy_reg_init_0[] = {
2541                 /* Channel Estimation */
2542                 { 0x1f, 0x0001 },
2543                 { 0x06, 0x4064 },
2544                 { 0x07, 0x2863 },
2545                 { 0x08, 0x059c },
2546                 { 0x09, 0x26b4 },
2547                 { 0x0a, 0x6a19 },
2548                 { 0x0b, 0xdcc8 },
2549                 { 0x10, 0xf06d },
2550                 { 0x14, 0x7f68 },
2551                 { 0x18, 0x7fd9 },
2552                 { 0x1c, 0xf0ff },
2553                 { 0x1d, 0x3d9c },
2554                 { 0x1f, 0x0003 },
2555                 { 0x12, 0xf49f },
2556                 { 0x13, 0x070b },
2557                 { 0x1a, 0x05ad },
2558                 { 0x14, 0x94c0 },
2559
2560                 /*
2561                  * Tx Error Issue
2562                  * Enhance line driver power
2563                  */
2564                 { 0x1f, 0x0002 },
2565                 { 0x06, 0x5561 },
2566                 { 0x1f, 0x0005 },
2567                 { 0x05, 0x8332 },
2568                 { 0x06, 0x5561 },
2569
2570                 /*
2571                  * Can not link to 1Gbps with bad cable
2572                  * Decrease SNR threshold form 21.07dB to 19.04dB
2573                  */
2574                 { 0x1f, 0x0001 },
2575                 { 0x17, 0x0cc0 },
2576
2577                 { 0x1f, 0x0000 },
2578                 { 0x0d, 0xf880 }
2579         };
2580         void __iomem *ioaddr = tp->mmio_addr;
2581
2582         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2583
2584         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2585                 static const struct phy_reg phy_reg_init[] = {
2586                         { 0x1f, 0x0002 },
2587                         { 0x05, 0x669a },
2588                         { 0x1f, 0x0005 },
2589                         { 0x05, 0x8330 },
2590                         { 0x06, 0x669a },
2591
2592                         { 0x1f, 0x0002 }
2593                 };
2594                 int val;
2595
2596                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2597
2598                 val = rtl_readphy(tp, 0x0d);
2599                 if ((val & 0x00ff) != 0x006c) {
2600                         static const u32 set[] = {
2601                                 0x0065, 0x0066, 0x0067, 0x0068,
2602                                 0x0069, 0x006a, 0x006b, 0x006c
2603                         };
2604                         int i;
2605
2606                         rtl_writephy(tp, 0x1f, 0x0002);
2607
2608                         val &= 0xff00;
2609                         for (i = 0; i < ARRAY_SIZE(set); i++)
2610                                 rtl_writephy(tp, 0x0d, val | set[i]);
2611                 }
2612         } else {
2613                 static const struct phy_reg phy_reg_init[] = {
2614                         { 0x1f, 0x0002 },
2615                         { 0x05, 0x2642 },
2616                         { 0x1f, 0x0005 },
2617                         { 0x05, 0x8330 },
2618                         { 0x06, 0x2642 }
2619                 };
2620
2621                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2622         }
2623
2624         /* Fine tune PLL performance */
2625         rtl_writephy(tp, 0x1f, 0x0002);
2626         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2627         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2628
2629         /* Switching regulator Slew rate */
2630         rtl_writephy(tp, 0x1f, 0x0002);
2631         rtl_patchphy(tp, 0x0f, 0x0017);
2632
2633         rtl_writephy(tp, 0x1f, 0x0005);
2634         rtl_writephy(tp, 0x05, 0x001b);
2635
2636         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2637
2638         rtl_writephy(tp, 0x1f, 0x0000);
2639 }
2640
2641 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2642 {
2643         static const struct phy_reg phy_reg_init[] = {
2644                 { 0x1f, 0x0002 },
2645                 { 0x10, 0x0008 },
2646                 { 0x0d, 0x006c },
2647
2648                 { 0x1f, 0x0000 },
2649                 { 0x0d, 0xf880 },
2650
2651                 { 0x1f, 0x0001 },
2652                 { 0x17, 0x0cc0 },
2653
2654                 { 0x1f, 0x0001 },
2655                 { 0x0b, 0xa4d8 },
2656                 { 0x09, 0x281c },
2657                 { 0x07, 0x2883 },
2658                 { 0x0a, 0x6b35 },
2659                 { 0x1d, 0x3da4 },
2660                 { 0x1c, 0xeffd },
2661                 { 0x14, 0x7f52 },
2662                 { 0x18, 0x7fc6 },
2663                 { 0x08, 0x0601 },
2664                 { 0x06, 0x4063 },
2665                 { 0x10, 0xf074 },
2666                 { 0x1f, 0x0003 },
2667                 { 0x13, 0x0789 },
2668                 { 0x12, 0xf4bd },
2669                 { 0x1a, 0x04fd },
2670                 { 0x14, 0x84b0 },
2671                 { 0x1f, 0x0000 },
2672                 { 0x00, 0x9200 },
2673
2674                 { 0x1f, 0x0005 },
2675                 { 0x01, 0x0340 },
2676                 { 0x1f, 0x0001 },
2677                 { 0x04, 0x4000 },
2678                 { 0x03, 0x1d21 },
2679                 { 0x02, 0x0c32 },
2680                 { 0x01, 0x0200 },
2681                 { 0x00, 0x5554 },
2682                 { 0x04, 0x4800 },
2683                 { 0x04, 0x4000 },
2684                 { 0x04, 0xf000 },
2685                 { 0x03, 0xdf01 },
2686                 { 0x02, 0xdf20 },
2687                 { 0x01, 0x101a },
2688                 { 0x00, 0xa0ff },
2689                 { 0x04, 0xf800 },
2690                 { 0x04, 0xf000 },
2691                 { 0x1f, 0x0000 },
2692
2693                 { 0x1f, 0x0007 },
2694                 { 0x1e, 0x0023 },
2695                 { 0x16, 0x0000 },
2696                 { 0x1f, 0x0000 }
2697         };
2698
2699         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2700 }
2701
2702 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2703 {
2704         static const struct phy_reg phy_reg_init[] = {
2705                 { 0x1f, 0x0001 },
2706                 { 0x17, 0x0cc0 },
2707
2708                 { 0x1f, 0x0007 },
2709                 { 0x1e, 0x002d },
2710                 { 0x18, 0x0040 },
2711                 { 0x1f, 0x0000 }
2712         };
2713
2714         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2715         rtl_patchphy(tp, 0x0d, 1 << 5);
2716 }
2717
2718 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2719 {
2720         static const struct phy_reg phy_reg_init[] = {
2721                 /* Enable Delay cap */
2722                 { 0x1f, 0x0005 },
2723                 { 0x05, 0x8b80 },
2724                 { 0x06, 0xc896 },
2725                 { 0x1f, 0x0000 },
2726
2727                 /* Channel estimation fine tune */
2728                 { 0x1f, 0x0001 },
2729                 { 0x0b, 0x6c20 },
2730                 { 0x07, 0x2872 },
2731                 { 0x1c, 0xefff },
2732                 { 0x1f, 0x0003 },
2733                 { 0x14, 0x6420 },
2734                 { 0x1f, 0x0000 },
2735
2736                 /* Update PFM & 10M TX idle timer */
2737                 { 0x1f, 0x0007 },
2738                 { 0x1e, 0x002f },
2739                 { 0x15, 0x1919 },
2740                 { 0x1f, 0x0000 },
2741
2742                 { 0x1f, 0x0007 },
2743                 { 0x1e, 0x00ac },
2744                 { 0x18, 0x0006 },
2745                 { 0x1f, 0x0000 }
2746         };
2747
2748         rtl_apply_firmware(tp);
2749
2750         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2751
2752         /* DCO enable for 10M IDLE Power */
2753         rtl_writephy(tp, 0x1f, 0x0007);
2754         rtl_writephy(tp, 0x1e, 0x0023);
2755         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2756         rtl_writephy(tp, 0x1f, 0x0000);
2757
2758         /* For impedance matching */
2759         rtl_writephy(tp, 0x1f, 0x0002);
2760         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2761         rtl_writephy(tp, 0x1f, 0x0000);
2762
2763         /* PHY auto speed down */
2764         rtl_writephy(tp, 0x1f, 0x0007);
2765         rtl_writephy(tp, 0x1e, 0x002d);
2766         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2767         rtl_writephy(tp, 0x1f, 0x0000);
2768         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2769
2770         rtl_writephy(tp, 0x1f, 0x0005);
2771         rtl_writephy(tp, 0x05, 0x8b86);
2772         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2773         rtl_writephy(tp, 0x1f, 0x0000);
2774
2775         rtl_writephy(tp, 0x1f, 0x0005);
2776         rtl_writephy(tp, 0x05, 0x8b85);
2777         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2778         rtl_writephy(tp, 0x1f, 0x0007);
2779         rtl_writephy(tp, 0x1e, 0x0020);
2780         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2781         rtl_writephy(tp, 0x1f, 0x0006);
2782         rtl_writephy(tp, 0x00, 0x5a00);
2783         rtl_writephy(tp, 0x1f, 0x0000);
2784         rtl_writephy(tp, 0x0d, 0x0007);
2785         rtl_writephy(tp, 0x0e, 0x003c);
2786         rtl_writephy(tp, 0x0d, 0x4007);
2787         rtl_writephy(tp, 0x0e, 0x0000);
2788         rtl_writephy(tp, 0x0d, 0x0000);
2789 }
2790
2791 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2792 {
2793         static const struct phy_reg phy_reg_init[] = {
2794                 /* Enable Delay cap */
2795                 { 0x1f, 0x0004 },
2796                 { 0x1f, 0x0007 },
2797                 { 0x1e, 0x00ac },
2798                 { 0x18, 0x0006 },
2799                 { 0x1f, 0x0002 },
2800                 { 0x1f, 0x0000 },
2801                 { 0x1f, 0x0000 },
2802
2803                 /* Channel estimation fine tune */
2804                 { 0x1f, 0x0003 },
2805                 { 0x09, 0xa20f },
2806                 { 0x1f, 0x0000 },
2807                 { 0x1f, 0x0000 },
2808
2809                 /* Green Setting */
2810                 { 0x1f, 0x0005 },
2811                 { 0x05, 0x8b5b },
2812                 { 0x06, 0x9222 },
2813                 { 0x05, 0x8b6d },
2814                 { 0x06, 0x8000 },
2815                 { 0x05, 0x8b76 },
2816                 { 0x06, 0x8000 },
2817                 { 0x1f, 0x0000 }
2818         };
2819
2820         rtl_apply_firmware(tp);
2821
2822         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2823
2824         /* For 4-corner performance improve */
2825         rtl_writephy(tp, 0x1f, 0x0005);
2826         rtl_writephy(tp, 0x05, 0x8b80);
2827         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2828         rtl_writephy(tp, 0x1f, 0x0000);
2829
2830         /* PHY auto speed down */
2831         rtl_writephy(tp, 0x1f, 0x0004);
2832         rtl_writephy(tp, 0x1f, 0x0007);
2833         rtl_writephy(tp, 0x1e, 0x002d);
2834         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2835         rtl_writephy(tp, 0x1f, 0x0002);
2836         rtl_writephy(tp, 0x1f, 0x0000);
2837         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2838
2839         /* improve 10M EEE waveform */
2840         rtl_writephy(tp, 0x1f, 0x0005);
2841         rtl_writephy(tp, 0x05, 0x8b86);
2842         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2843         rtl_writephy(tp, 0x1f, 0x0000);
2844
2845         /* Improve 2-pair detection performance */
2846         rtl_writephy(tp, 0x1f, 0x0005);
2847         rtl_writephy(tp, 0x05, 0x8b85);
2848         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2849         rtl_writephy(tp, 0x1f, 0x0000);
2850
2851         /* EEE setting */
2852         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2853                      ERIAR_EXGMAC);
2854         rtl_writephy(tp, 0x1f, 0x0005);
2855         rtl_writephy(tp, 0x05, 0x8b85);
2856         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2857         rtl_writephy(tp, 0x1f, 0x0004);
2858         rtl_writephy(tp, 0x1f, 0x0007);
2859         rtl_writephy(tp, 0x1e, 0x0020);
2860         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2861         rtl_writephy(tp, 0x1f, 0x0002);
2862         rtl_writephy(tp, 0x1f, 0x0000);
2863         rtl_writephy(tp, 0x0d, 0x0007);
2864         rtl_writephy(tp, 0x0e, 0x003c);
2865         rtl_writephy(tp, 0x0d, 0x4007);
2866         rtl_writephy(tp, 0x0e, 0x0000);
2867         rtl_writephy(tp, 0x0d, 0x0000);
2868
2869         /* Green feature */
2870         rtl_writephy(tp, 0x1f, 0x0003);
2871         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2872         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2873         rtl_writephy(tp, 0x1f, 0x0000);
2874 }
2875
2876 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2877 {
2878         static const struct phy_reg phy_reg_init[] = {
2879                 { 0x1f, 0x0003 },
2880                 { 0x08, 0x441d },
2881                 { 0x01, 0x9100 },
2882                 { 0x1f, 0x0000 }
2883         };
2884
2885         rtl_writephy(tp, 0x1f, 0x0000);
2886         rtl_patchphy(tp, 0x11, 1 << 12);
2887         rtl_patchphy(tp, 0x19, 1 << 13);
2888         rtl_patchphy(tp, 0x10, 1 << 15);
2889
2890         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2891 }
2892
2893 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2894 {
2895         static const struct phy_reg phy_reg_init[] = {
2896                 { 0x1f, 0x0005 },
2897                 { 0x1a, 0x0000 },
2898                 { 0x1f, 0x0000 },
2899
2900                 { 0x1f, 0x0004 },
2901                 { 0x1c, 0x0000 },
2902                 { 0x1f, 0x0000 },
2903
2904                 { 0x1f, 0x0001 },
2905                 { 0x15, 0x7701 },
2906                 { 0x1f, 0x0000 }
2907         };
2908
2909         /* Disable ALDPS before ram code */
2910         rtl_writephy(tp, 0x1f, 0x0000);
2911         rtl_writephy(tp, 0x18, 0x0310);
2912         msleep(100);
2913
2914         rtl_apply_firmware(tp);
2915
2916         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2917 }
2918
2919 static void rtl_hw_phy_config(struct net_device *dev)
2920 {
2921         struct rtl8169_private *tp = netdev_priv(dev);
2922
2923         rtl8169_print_mac_version(tp);
2924
2925         switch (tp->mac_version) {
2926         case RTL_GIGA_MAC_VER_01:
2927                 break;
2928         case RTL_GIGA_MAC_VER_02:
2929         case RTL_GIGA_MAC_VER_03:
2930                 rtl8169s_hw_phy_config(tp);
2931                 break;
2932         case RTL_GIGA_MAC_VER_04:
2933                 rtl8169sb_hw_phy_config(tp);
2934                 break;
2935         case RTL_GIGA_MAC_VER_05:
2936                 rtl8169scd_hw_phy_config(tp);
2937                 break;
2938         case RTL_GIGA_MAC_VER_06:
2939                 rtl8169sce_hw_phy_config(tp);
2940                 break;
2941         case RTL_GIGA_MAC_VER_07:
2942         case RTL_GIGA_MAC_VER_08:
2943         case RTL_GIGA_MAC_VER_09:
2944                 rtl8102e_hw_phy_config(tp);
2945                 break;
2946         case RTL_GIGA_MAC_VER_11:
2947                 rtl8168bb_hw_phy_config(tp);
2948                 break;
2949         case RTL_GIGA_MAC_VER_12:
2950                 rtl8168bef_hw_phy_config(tp);
2951                 break;
2952         case RTL_GIGA_MAC_VER_17:
2953                 rtl8168bef_hw_phy_config(tp);
2954                 break;
2955         case RTL_GIGA_MAC_VER_18:
2956                 rtl8168cp_1_hw_phy_config(tp);
2957                 break;
2958         case RTL_GIGA_MAC_VER_19:
2959                 rtl8168c_1_hw_phy_config(tp);
2960                 break;
2961         case RTL_GIGA_MAC_VER_20:
2962                 rtl8168c_2_hw_phy_config(tp);
2963                 break;
2964         case RTL_GIGA_MAC_VER_21:
2965                 rtl8168c_3_hw_phy_config(tp);
2966                 break;
2967         case RTL_GIGA_MAC_VER_22:
2968                 rtl8168c_4_hw_phy_config(tp);
2969                 break;
2970         case RTL_GIGA_MAC_VER_23:
2971         case RTL_GIGA_MAC_VER_24:
2972                 rtl8168cp_2_hw_phy_config(tp);
2973                 break;
2974         case RTL_GIGA_MAC_VER_25:
2975                 rtl8168d_1_hw_phy_config(tp);
2976                 break;
2977         case RTL_GIGA_MAC_VER_26:
2978                 rtl8168d_2_hw_phy_config(tp);
2979                 break;
2980         case RTL_GIGA_MAC_VER_27:
2981                 rtl8168d_3_hw_phy_config(tp);
2982                 break;
2983         case RTL_GIGA_MAC_VER_28:
2984                 rtl8168d_4_hw_phy_config(tp);
2985                 break;
2986         case RTL_GIGA_MAC_VER_29:
2987         case RTL_GIGA_MAC_VER_30:
2988                 rtl8105e_hw_phy_config(tp);
2989                 break;
2990         case RTL_GIGA_MAC_VER_31:
2991                 /* None. */
2992                 break;
2993         case RTL_GIGA_MAC_VER_32:
2994         case RTL_GIGA_MAC_VER_33:
2995                 rtl8168e_1_hw_phy_config(tp);
2996                 break;
2997         case RTL_GIGA_MAC_VER_34:
2998                 rtl8168e_2_hw_phy_config(tp);
2999                 break;
3000
3001         default:
3002                 break;
3003         }
3004 }
3005
3006 static void rtl8169_phy_timer(unsigned long __opaque)
3007 {
3008         struct net_device *dev = (struct net_device *)__opaque;
3009         struct rtl8169_private *tp = netdev_priv(dev);
3010         struct timer_list *timer = &tp->timer;
3011         void __iomem *ioaddr = tp->mmio_addr;
3012         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3013
3014         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3015
3016         spin_lock_irq(&tp->lock);
3017
3018         if (tp->phy_reset_pending(tp)) {
3019                 /*
3020                  * A busy loop could burn quite a few cycles on nowadays CPU.
3021                  * Let's delay the execution of the timer for a few ticks.
3022                  */
3023                 timeout = HZ/10;
3024                 goto out_mod_timer;
3025         }
3026
3027         if (tp->link_ok(ioaddr))
3028                 goto out_unlock;
3029
3030         netif_warn(tp, link, dev, "PHY reset until link up\n");
3031
3032         tp->phy_reset_enable(tp);
3033
3034 out_mod_timer:
3035         mod_timer(timer, jiffies + timeout);
3036 out_unlock:
3037         spin_unlock_irq(&tp->lock);
3038 }
3039
3040 #ifdef CONFIG_NET_POLL_CONTROLLER
3041 /*
3042  * Polling 'interrupt' - used by things like netconsole to send skbs
3043  * without having to re-enable interrupts. It's not called while
3044  * the interrupt routine is executing.
3045  */
3046 static void rtl8169_netpoll(struct net_device *dev)
3047 {
3048         struct rtl8169_private *tp = netdev_priv(dev);
3049         struct pci_dev *pdev = tp->pci_dev;
3050
3051         disable_irq(pdev->irq);
3052         rtl8169_interrupt(pdev->irq, dev);
3053         enable_irq(pdev->irq);
3054 }
3055 #endif
3056
3057 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3058                                   void __iomem *ioaddr)
3059 {
3060         iounmap(ioaddr);
3061         pci_release_regions(pdev);
3062         pci_clear_mwi(pdev);
3063         pci_disable_device(pdev);
3064         free_netdev(dev);
3065 }
3066
3067 static void rtl8169_phy_reset(struct net_device *dev,
3068                               struct rtl8169_private *tp)
3069 {
3070         unsigned int i;
3071
3072         tp->phy_reset_enable(tp);
3073         for (i = 0; i < 100; i++) {
3074                 if (!tp->phy_reset_pending(tp))
3075                         return;
3076                 msleep(1);
3077         }
3078         netif_err(tp, link, dev, "PHY reset failed\n");
3079 }
3080
3081 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3082 {
3083         void __iomem *ioaddr = tp->mmio_addr;
3084
3085         rtl_hw_phy_config(dev);
3086
3087         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3088                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3089                 RTL_W8(0x82, 0x01);
3090         }
3091
3092         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3093
3094         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3095                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3096
3097         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3098                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3099                 RTL_W8(0x82, 0x01);
3100                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3101                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3102         }
3103
3104         rtl8169_phy_reset(dev, tp);
3105
3106         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3107                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3108                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3109                           (tp->mii.supports_gmii ?
3110                            ADVERTISED_1000baseT_Half |
3111                            ADVERTISED_1000baseT_Full : 0));
3112
3113         if (RTL_R8(PHYstatus) & TBI_Enable)
3114                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3115 }
3116
3117 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3118 {
3119         void __iomem *ioaddr = tp->mmio_addr;
3120         u32 high;
3121         u32 low;
3122
3123         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3124         high = addr[4] | (addr[5] << 8);
3125
3126         spin_lock_irq(&tp->lock);
3127
3128         RTL_W8(Cfg9346, Cfg9346_Unlock);
3129
3130         RTL_W32(MAC4, high);
3131         RTL_R32(MAC4);
3132
3133         RTL_W32(MAC0, low);
3134         RTL_R32(MAC0);
3135
3136         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3137                 const struct exgmac_reg e[] = {
3138                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3139                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3140                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3141                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3142                                                                 low  >> 16 },
3143                 };
3144
3145                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3146         }
3147
3148         RTL_W8(Cfg9346, Cfg9346_Lock);
3149
3150         spin_unlock_irq(&tp->lock);
3151 }
3152
3153 static int rtl_set_mac_address(struct net_device *dev, void *p)
3154 {
3155         struct rtl8169_private *tp = netdev_priv(dev);
3156         struct sockaddr *addr = p;
3157
3158         if (!is_valid_ether_addr(addr->sa_data))
3159                 return -EADDRNOTAVAIL;
3160
3161         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3162
3163         rtl_rar_set(tp, dev->dev_addr);
3164
3165         return 0;
3166 }
3167
3168 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3169 {
3170         struct rtl8169_private *tp = netdev_priv(dev);
3171         struct mii_ioctl_data *data = if_mii(ifr);
3172
3173         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3174 }
3175
3176 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3177                           struct mii_ioctl_data *data, int cmd)
3178 {
3179         switch (cmd) {
3180         case SIOCGMIIPHY:
3181                 data->phy_id = 32; /* Internal PHY */
3182                 return 0;
3183
3184         case SIOCGMIIREG:
3185                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3186                 return 0;
3187
3188         case SIOCSMIIREG:
3189                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3190                 return 0;
3191         }
3192         return -EOPNOTSUPP;
3193 }
3194
3195 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3196 {
3197         return -EOPNOTSUPP;
3198 }
3199
3200 static const struct rtl_cfg_info {
3201         void (*hw_start)(struct net_device *);
3202         unsigned int region;
3203         unsigned int align;
3204         u16 intr_event;
3205         u16 napi_event;
3206         unsigned features;
3207         u8 default_ver;
3208 } rtl_cfg_infos [] = {
3209         [RTL_CFG_0] = {
3210                 .hw_start       = rtl_hw_start_8169,
3211                 .region         = 1,
3212                 .align          = 0,
3213                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3214                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3215                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3216                 .features       = RTL_FEATURE_GMII,
3217                 .default_ver    = RTL_GIGA_MAC_VER_01,
3218         },
3219         [RTL_CFG_1] = {
3220                 .hw_start       = rtl_hw_start_8168,
3221                 .region         = 2,
3222                 .align          = 8,
3223                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3224                                   TxErr | TxOK | RxOK | RxErr,
3225                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3226                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3227                 .default_ver    = RTL_GIGA_MAC_VER_11,
3228         },
3229         [RTL_CFG_2] = {
3230                 .hw_start       = rtl_hw_start_8101,
3231                 .region         = 2,
3232                 .align          = 8,
3233                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3234                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3235                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3236                 .features       = RTL_FEATURE_MSI,
3237                 .default_ver    = RTL_GIGA_MAC_VER_13,
3238         }
3239 };
3240
3241 /* Cfg9346_Unlock assumed. */
3242 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3243                             const struct rtl_cfg_info *cfg)
3244 {
3245         unsigned msi = 0;
3246         u8 cfg2;
3247
3248         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3249         if (cfg->features & RTL_FEATURE_MSI) {
3250                 if (pci_enable_msi(pdev)) {
3251                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3252                 } else {
3253                         cfg2 |= MSIEnable;
3254                         msi = RTL_FEATURE_MSI;
3255                 }
3256         }
3257         RTL_W8(Config2, cfg2);
3258         return msi;
3259 }
3260
3261 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3262 {
3263         if (tp->features & RTL_FEATURE_MSI) {
3264                 pci_disable_msi(pdev);
3265                 tp->features &= ~RTL_FEATURE_MSI;
3266         }
3267 }
3268
3269 static const struct net_device_ops rtl8169_netdev_ops = {
3270         .ndo_open               = rtl8169_open,
3271         .ndo_stop               = rtl8169_close,
3272         .ndo_get_stats          = rtl8169_get_stats,
3273         .ndo_start_xmit         = rtl8169_start_xmit,
3274         .ndo_tx_timeout         = rtl8169_tx_timeout,
3275         .ndo_validate_addr      = eth_validate_addr,
3276         .ndo_change_mtu         = rtl8169_change_mtu,
3277         .ndo_fix_features       = rtl8169_fix_features,
3278         .ndo_set_features       = rtl8169_set_features,
3279         .ndo_set_mac_address    = rtl_set_mac_address,
3280         .ndo_do_ioctl           = rtl8169_ioctl,
3281         .ndo_set_multicast_list = rtl_set_rx_mode,
3282 #ifdef CONFIG_NET_POLL_CONTROLLER
3283         .ndo_poll_controller    = rtl8169_netpoll,
3284 #endif
3285
3286 };
3287
3288 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3289 {
3290         struct mdio_ops *ops = &tp->mdio_ops;
3291
3292         switch (tp->mac_version) {
3293         case RTL_GIGA_MAC_VER_27:
3294                 ops->write      = r8168dp_1_mdio_write;
3295                 ops->read       = r8168dp_1_mdio_read;
3296                 break;
3297         case RTL_GIGA_MAC_VER_28:
3298         case RTL_GIGA_MAC_VER_31:
3299                 ops->write      = r8168dp_2_mdio_write;
3300                 ops->read       = r8168dp_2_mdio_read;
3301                 break;
3302         default:
3303                 ops->write      = r8169_mdio_write;
3304                 ops->read       = r8169_mdio_read;
3305                 break;
3306         }
3307 }
3308
3309 static void r810x_phy_power_down(struct rtl8169_private *tp)
3310 {
3311         rtl_writephy(tp, 0x1f, 0x0000);
3312         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3313 }
3314
3315 static void r810x_phy_power_up(struct rtl8169_private *tp)
3316 {
3317         rtl_writephy(tp, 0x1f, 0x0000);
3318         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3319 }
3320
3321 static void r810x_pll_power_down(struct rtl8169_private *tp)
3322 {
3323         void __iomem *ioaddr = tp->mmio_addr;
3324
3325         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3326                 rtl_writephy(tp, 0x1f, 0x0000);
3327                 rtl_writephy(tp, MII_BMCR, 0x0000);
3328
3329                 if (tp->mac_version == RTL_GIGA_MAC_VER_29 ||
3330                     tp->mac_version == RTL_GIGA_MAC_VER_30)
3331                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3332                                 AcceptMulticast | AcceptMyPhys);
3333                 return;
3334         }
3335
3336         r810x_phy_power_down(tp);
3337 }
3338
3339 static void r810x_pll_power_up(struct rtl8169_private *tp)
3340 {
3341         r810x_phy_power_up(tp);
3342 }
3343
3344 static void r8168_phy_power_up(struct rtl8169_private *tp)
3345 {
3346         rtl_writephy(tp, 0x1f, 0x0000);
3347         switch (tp->mac_version) {
3348         case RTL_GIGA_MAC_VER_11:
3349         case RTL_GIGA_MAC_VER_12:
3350         case RTL_GIGA_MAC_VER_17:
3351         case RTL_GIGA_MAC_VER_18:
3352         case RTL_GIGA_MAC_VER_19:
3353         case RTL_GIGA_MAC_VER_20:
3354         case RTL_GIGA_MAC_VER_21:
3355         case RTL_GIGA_MAC_VER_22:
3356         case RTL_GIGA_MAC_VER_23:
3357         case RTL_GIGA_MAC_VER_24:
3358         case RTL_GIGA_MAC_VER_25:
3359         case RTL_GIGA_MAC_VER_26:
3360         case RTL_GIGA_MAC_VER_27:
3361         case RTL_GIGA_MAC_VER_28:
3362         case RTL_GIGA_MAC_VER_31:
3363                 rtl_writephy(tp, 0x0e, 0x0000);
3364                 break;
3365         default:
3366                 break;
3367         }
3368         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3369 }
3370
3371 static void r8168_phy_power_down(struct rtl8169_private *tp)
3372 {
3373         rtl_writephy(tp, 0x1f, 0x0000);
3374         switch (tp->mac_version) {
3375         case RTL_GIGA_MAC_VER_32:
3376         case RTL_GIGA_MAC_VER_33:
3377                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3378                 break;
3379
3380         case RTL_GIGA_MAC_VER_11:
3381         case RTL_GIGA_MAC_VER_12:
3382         case RTL_GIGA_MAC_VER_17:
3383         case RTL_GIGA_MAC_VER_18:
3384         case RTL_GIGA_MAC_VER_19:
3385         case RTL_GIGA_MAC_VER_20:
3386         case RTL_GIGA_MAC_VER_21:
3387         case RTL_GIGA_MAC_VER_22:
3388         case RTL_GIGA_MAC_VER_23:
3389         case RTL_GIGA_MAC_VER_24:
3390         case RTL_GIGA_MAC_VER_25:
3391         case RTL_GIGA_MAC_VER_26:
3392         case RTL_GIGA_MAC_VER_27:
3393         case RTL_GIGA_MAC_VER_28:
3394         case RTL_GIGA_MAC_VER_31:
3395                 rtl_writephy(tp, 0x0e, 0x0200);
3396         default:
3397                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3398                 break;
3399         }
3400 }
3401
3402 static void r8168_pll_power_down(struct rtl8169_private *tp)
3403 {
3404         void __iomem *ioaddr = tp->mmio_addr;
3405
3406         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3407              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3408              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3409             r8168dp_check_dash(tp)) {
3410                 return;
3411         }
3412
3413         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3414              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3415             (RTL_R16(CPlusCmd) & ASF)) {
3416                 return;
3417         }
3418
3419         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3420             tp->mac_version == RTL_GIGA_MAC_VER_33)
3421                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3422
3423         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3424                 rtl_writephy(tp, 0x1f, 0x0000);
3425                 rtl_writephy(tp, MII_BMCR, 0x0000);
3426
3427                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3428                     tp->mac_version == RTL_GIGA_MAC_VER_33 ||
3429                     tp->mac_version == RTL_GIGA_MAC_VER_34)
3430                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3431                                 AcceptMulticast | AcceptMyPhys);
3432                 return;
3433         }
3434
3435         r8168_phy_power_down(tp);
3436
3437         switch (tp->mac_version) {
3438         case RTL_GIGA_MAC_VER_25:
3439         case RTL_GIGA_MAC_VER_26:
3440         case RTL_GIGA_MAC_VER_27:
3441         case RTL_GIGA_MAC_VER_28:
3442         case RTL_GIGA_MAC_VER_31:
3443         case RTL_GIGA_MAC_VER_32:
3444         case RTL_GIGA_MAC_VER_33:
3445                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3446                 break;
3447         }
3448 }
3449
3450 static void r8168_pll_power_up(struct rtl8169_private *tp)
3451 {
3452         void __iomem *ioaddr = tp->mmio_addr;
3453
3454         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3455              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3456              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3457             r8168dp_check_dash(tp)) {
3458                 return;
3459         }
3460
3461         switch (tp->mac_version) {
3462         case RTL_GIGA_MAC_VER_25:
3463         case RTL_GIGA_MAC_VER_26:
3464         case RTL_GIGA_MAC_VER_27:
3465         case RTL_GIGA_MAC_VER_28:
3466         case RTL_GIGA_MAC_VER_31:
3467         case RTL_GIGA_MAC_VER_32:
3468         case RTL_GIGA_MAC_VER_33:
3469                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3470                 break;
3471         }
3472
3473         r8168_phy_power_up(tp);
3474 }
3475
3476 static void rtl_pll_power_op(struct rtl8169_private *tp,
3477                              void (*op)(struct rtl8169_private *))
3478 {
3479         if (op)
3480                 op(tp);
3481 }
3482
3483 static void rtl_pll_power_down(struct rtl8169_private *tp)
3484 {
3485         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3486 }
3487
3488 static void rtl_pll_power_up(struct rtl8169_private *tp)
3489 {
3490         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3491 }
3492
3493 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3494 {
3495         struct pll_power_ops *ops = &tp->pll_power_ops;
3496
3497         switch (tp->mac_version) {
3498         case RTL_GIGA_MAC_VER_07:
3499         case RTL_GIGA_MAC_VER_08:
3500         case RTL_GIGA_MAC_VER_09:
3501         case RTL_GIGA_MAC_VER_10:
3502         case RTL_GIGA_MAC_VER_16:
3503         case RTL_GIGA_MAC_VER_29:
3504         case RTL_GIGA_MAC_VER_30:
3505                 ops->down       = r810x_pll_power_down;
3506                 ops->up         = r810x_pll_power_up;
3507                 break;
3508
3509         case RTL_GIGA_MAC_VER_11:
3510         case RTL_GIGA_MAC_VER_12:
3511         case RTL_GIGA_MAC_VER_17:
3512         case RTL_GIGA_MAC_VER_18:
3513         case RTL_GIGA_MAC_VER_19:
3514         case RTL_GIGA_MAC_VER_20:
3515         case RTL_GIGA_MAC_VER_21:
3516         case RTL_GIGA_MAC_VER_22:
3517         case RTL_GIGA_MAC_VER_23:
3518         case RTL_GIGA_MAC_VER_24:
3519         case RTL_GIGA_MAC_VER_25:
3520         case RTL_GIGA_MAC_VER_26:
3521         case RTL_GIGA_MAC_VER_27:
3522         case RTL_GIGA_MAC_VER_28:
3523         case RTL_GIGA_MAC_VER_31:
3524         case RTL_GIGA_MAC_VER_32:
3525         case RTL_GIGA_MAC_VER_33:
3526         case RTL_GIGA_MAC_VER_34:
3527                 ops->down       = r8168_pll_power_down;
3528                 ops->up         = r8168_pll_power_up;
3529                 break;
3530
3531         default:
3532                 ops->down       = NULL;
3533                 ops->up         = NULL;
3534                 break;
3535         }
3536 }
3537
3538 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3539 {
3540         void __iomem *ioaddr = tp->mmio_addr;
3541
3542         switch (tp->mac_version) {
3543         case RTL_GIGA_MAC_VER_01:
3544         case RTL_GIGA_MAC_VER_02:
3545         case RTL_GIGA_MAC_VER_03:
3546         case RTL_GIGA_MAC_VER_04:
3547         case RTL_GIGA_MAC_VER_05:
3548         case RTL_GIGA_MAC_VER_06:
3549         case RTL_GIGA_MAC_VER_10:
3550         case RTL_GIGA_MAC_VER_11:
3551         case RTL_GIGA_MAC_VER_12:
3552         case RTL_GIGA_MAC_VER_13:
3553         case RTL_GIGA_MAC_VER_14:
3554         case RTL_GIGA_MAC_VER_15:
3555         case RTL_GIGA_MAC_VER_16:
3556         case RTL_GIGA_MAC_VER_17:
3557                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3558                 break;
3559         case RTL_GIGA_MAC_VER_18:
3560         case RTL_GIGA_MAC_VER_19:
3561         case RTL_GIGA_MAC_VER_20:
3562         case RTL_GIGA_MAC_VER_21:
3563         case RTL_GIGA_MAC_VER_22:
3564         case RTL_GIGA_MAC_VER_23:
3565         case RTL_GIGA_MAC_VER_24:
3566                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3567                 break;
3568         default:
3569                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3570                 break;
3571         }
3572 }
3573
3574 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3575 {
3576         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3577 }
3578
3579 static void rtl_hw_reset(struct rtl8169_private *tp)
3580 {
3581         void __iomem *ioaddr = tp->mmio_addr;
3582         int i;
3583
3584         /* Soft reset the chip. */
3585         RTL_W8(ChipCmd, CmdReset);
3586
3587         /* Check that the chip has finished the reset. */
3588         for (i = 0; i < 100; i++) {
3589                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3590                         break;
3591                 udelay(100);
3592         }
3593
3594         rtl8169_init_ring_indexes(tp);
3595 }
3596
3597 static int __devinit
3598 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3599 {
3600         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3601         const unsigned int region = cfg->region;
3602         struct rtl8169_private *tp;
3603         struct mii_if_info *mii;
3604         struct net_device *dev;
3605         void __iomem *ioaddr;
3606         int chipset, i;
3607         int rc;
3608
3609         if (netif_msg_drv(&debug)) {
3610                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3611                        MODULENAME, RTL8169_VERSION);
3612         }
3613
3614         dev = alloc_etherdev(sizeof (*tp));
3615         if (!dev) {
3616                 if (netif_msg_drv(&debug))
3617                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3618                 rc = -ENOMEM;
3619                 goto out;
3620         }
3621
3622         SET_NETDEV_DEV(dev, &pdev->dev);
3623         dev->netdev_ops = &rtl8169_netdev_ops;
3624         tp = netdev_priv(dev);
3625         tp->dev = dev;
3626         tp->pci_dev = pdev;
3627         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3628
3629         mii = &tp->mii;
3630         mii->dev = dev;
3631         mii->mdio_read = rtl_mdio_read;
3632         mii->mdio_write = rtl_mdio_write;
3633         mii->phy_id_mask = 0x1f;
3634         mii->reg_num_mask = 0x1f;
3635         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3636
3637         /* disable ASPM completely as that cause random device stop working
3638          * problems as well as full system hangs for some PCIe devices users */
3639         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3640                                      PCIE_LINK_STATE_CLKPM);
3641
3642         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3643         rc = pci_enable_device(pdev);
3644         if (rc < 0) {
3645                 netif_err(tp, probe, dev, "enable failure\n");
3646                 goto err_out_free_dev_1;
3647         }
3648
3649         if (pci_set_mwi(pdev) < 0)
3650                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3651
3652         /* make sure PCI base addr 1 is MMIO */
3653         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3654                 netif_err(tp, probe, dev,
3655                           "region #%d not an MMIO resource, aborting\n",
3656                           region);
3657                 rc = -ENODEV;
3658                 goto err_out_mwi_2;
3659         }
3660
3661         /* check for weird/broken PCI region reporting */
3662         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3663                 netif_err(tp, probe, dev,
3664                           "Invalid PCI region size(s), aborting\n");
3665                 rc = -ENODEV;
3666                 goto err_out_mwi_2;
3667         }
3668
3669         rc = pci_request_regions(pdev, MODULENAME);
3670         if (rc < 0) {
3671                 netif_err(tp, probe, dev, "could not request regions\n");
3672                 goto err_out_mwi_2;
3673         }
3674
3675         tp->cp_cmd = RxChkSum;
3676
3677         if ((sizeof(dma_addr_t) > 4) &&
3678             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3679                 tp->cp_cmd |= PCIDAC;
3680                 dev->features |= NETIF_F_HIGHDMA;
3681         } else {
3682                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3683                 if (rc < 0) {
3684                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3685                         goto err_out_free_res_3;
3686                 }
3687         }
3688
3689         /* ioremap MMIO region */
3690         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3691         if (!ioaddr) {
3692                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3693                 rc = -EIO;
3694                 goto err_out_free_res_3;
3695         }
3696         tp->mmio_addr = ioaddr;
3697
3698         if (!pci_is_pcie(pdev))
3699                 netif_info(tp, probe, dev, "not PCI Express\n");
3700
3701         /* Identify chip attached to board */
3702         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3703
3704         rtl_init_rxcfg(tp);
3705
3706         RTL_W16(IntrMask, 0x0000);
3707
3708         rtl_hw_reset(tp);
3709
3710         RTL_W16(IntrStatus, 0xffff);
3711
3712         pci_set_master(pdev);
3713
3714         /*
3715          * Pretend we are using VLANs; This bypasses a nasty bug where
3716          * Interrupts stop flowing on high load on 8110SCd controllers.
3717          */
3718         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3719                 tp->cp_cmd |= RxVlan;
3720
3721         rtl_init_mdio_ops(tp);
3722         rtl_init_pll_power_ops(tp);
3723
3724         rtl8169_print_mac_version(tp);
3725
3726         chipset = tp->mac_version;
3727         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3728
3729         RTL_W8(Cfg9346, Cfg9346_Unlock);
3730         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3731         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3732         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3733                 tp->features |= RTL_FEATURE_WOL;
3734         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3735                 tp->features |= RTL_FEATURE_WOL;
3736         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3737         RTL_W8(Cfg9346, Cfg9346_Lock);
3738
3739         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3740             (RTL_R8(PHYstatus) & TBI_Enable)) {
3741                 tp->set_speed = rtl8169_set_speed_tbi;
3742                 tp->get_settings = rtl8169_gset_tbi;
3743                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3744                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3745                 tp->link_ok = rtl8169_tbi_link_ok;
3746                 tp->do_ioctl = rtl_tbi_ioctl;
3747         } else {
3748                 tp->set_speed = rtl8169_set_speed_xmii;
3749                 tp->get_settings = rtl8169_gset_xmii;
3750                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3751                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3752                 tp->link_ok = rtl8169_xmii_link_ok;
3753                 tp->do_ioctl = rtl_xmii_ioctl;
3754         }
3755
3756         spin_lock_init(&tp->lock);
3757
3758         /* Get MAC address */
3759         for (i = 0; i < MAC_ADDR_LEN; i++)
3760                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3761         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3762
3763         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3764         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3765         dev->irq = pdev->irq;
3766         dev->base_addr = (unsigned long) ioaddr;
3767
3768         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3769
3770         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3771          * properly for all devices */
3772         dev->features |= NETIF_F_RXCSUM |
3773                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3774
3775         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3776                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3777         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3778                 NETIF_F_HIGHDMA;
3779
3780         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3781                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3782                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3783
3784         tp->intr_mask = 0xffff;
3785         tp->hw_start = cfg->hw_start;
3786         tp->intr_event = cfg->intr_event;
3787         tp->napi_event = cfg->napi_event;
3788
3789         init_timer(&tp->timer);
3790         tp->timer.data = (unsigned long) dev;
3791         tp->timer.function = rtl8169_phy_timer;
3792
3793         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3794
3795         rc = register_netdev(dev);
3796         if (rc < 0)
3797                 goto err_out_msi_4;
3798
3799         pci_set_drvdata(pdev, dev);
3800
3801         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3802                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3803                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3804
3805         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3806             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3807             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3808                 rtl8168_driver_start(tp);
3809         }
3810
3811         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3812
3813         if (pci_dev_run_wake(pdev))
3814                 pm_runtime_put_noidle(&pdev->dev);
3815
3816         netif_carrier_off(dev);
3817
3818 out:
3819         return rc;
3820
3821 err_out_msi_4:
3822         rtl_disable_msi(pdev, tp);
3823         iounmap(ioaddr);
3824 err_out_free_res_3:
3825         pci_release_regions(pdev);
3826 err_out_mwi_2:
3827         pci_clear_mwi(pdev);
3828         pci_disable_device(pdev);
3829 err_out_free_dev_1:
3830         free_netdev(dev);
3831         goto out;
3832 }
3833
3834 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3835 {
3836         struct net_device *dev = pci_get_drvdata(pdev);
3837         struct rtl8169_private *tp = netdev_priv(dev);
3838
3839         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3840             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3841             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3842                 rtl8168_driver_stop(tp);
3843         }
3844
3845         cancel_delayed_work_sync(&tp->task);
3846
3847         unregister_netdev(dev);
3848
3849         rtl_release_firmware(tp);
3850
3851         if (pci_dev_run_wake(pdev))
3852                 pm_runtime_get_noresume(&pdev->dev);
3853
3854         /* restore original MAC address */
3855         rtl_rar_set(tp, dev->perm_addr);
3856
3857         rtl_disable_msi(pdev, tp);
3858         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3859         pci_set_drvdata(pdev, NULL);
3860 }
3861
3862 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3863 {
3864         struct rtl_fw *rtl_fw;
3865         const char *name;
3866         int rc = -ENOMEM;
3867
3868         name = rtl_lookup_firmware_name(tp);
3869         if (!name)
3870                 goto out_no_firmware;
3871
3872         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3873         if (!rtl_fw)
3874                 goto err_warn;
3875
3876         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3877         if (rc < 0)
3878                 goto err_free;
3879
3880         rc = rtl_check_firmware(tp, rtl_fw);
3881         if (rc < 0)
3882                 goto err_release_firmware;
3883
3884         tp->rtl_fw = rtl_fw;
3885 out:
3886         return;
3887
3888 err_release_firmware:
3889         release_firmware(rtl_fw->fw);
3890 err_free:
3891         kfree(rtl_fw);
3892 err_warn:
3893         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3894                    name, rc);
3895 out_no_firmware:
3896         tp->rtl_fw = NULL;
3897         goto out;
3898 }
3899
3900 static void rtl_request_firmware(struct rtl8169_private *tp)
3901 {
3902         if (IS_ERR(tp->rtl_fw))
3903                 rtl_request_uncached_firmware(tp);
3904 }
3905
3906 static int rtl8169_open(struct net_device *dev)
3907 {
3908         struct rtl8169_private *tp = netdev_priv(dev);
3909         void __iomem *ioaddr = tp->mmio_addr;
3910         struct pci_dev *pdev = tp->pci_dev;
3911         int retval = -ENOMEM;
3912
3913         pm_runtime_get_sync(&pdev->dev);
3914
3915         /*
3916          * Rx and Tx desscriptors needs 256 bytes alignment.
3917          * dma_alloc_coherent provides more.
3918          */
3919         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3920                                              &tp->TxPhyAddr, GFP_KERNEL);
3921         if (!tp->TxDescArray)
3922                 goto err_pm_runtime_put;
3923
3924         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3925                                              &tp->RxPhyAddr, GFP_KERNEL);
3926         if (!tp->RxDescArray)
3927                 goto err_free_tx_0;
3928
3929         retval = rtl8169_init_ring(dev);
3930         if (retval < 0)
3931                 goto err_free_rx_1;
3932
3933         INIT_DELAYED_WORK(&tp->task, NULL);
3934
3935         smp_mb();
3936
3937         rtl_request_firmware(tp);
3938
3939         retval = request_irq(dev->irq, rtl8169_interrupt,
3940                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3941                              dev->name, dev);
3942         if (retval < 0)
3943                 goto err_release_fw_2;
3944
3945         napi_enable(&tp->napi);
3946
3947         rtl8169_init_phy(dev, tp);
3948
3949         rtl8169_set_features(dev, dev->features);
3950
3951         rtl_pll_power_up(tp);
3952
3953         rtl_hw_start(dev);
3954
3955         tp->saved_wolopts = 0;
3956         pm_runtime_put_noidle(&pdev->dev);
3957
3958         rtl8169_check_link_status(dev, tp, ioaddr);
3959 out:
3960         return retval;
3961
3962 err_release_fw_2:
3963         rtl_release_firmware(tp);
3964         rtl8169_rx_clear(tp);
3965 err_free_rx_1:
3966         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3967                           tp->RxPhyAddr);
3968         tp->RxDescArray = NULL;
3969 err_free_tx_0:
3970         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3971                           tp->TxPhyAddr);
3972         tp->TxDescArray = NULL;
3973 err_pm_runtime_put:
3974         pm_runtime_put_noidle(&pdev->dev);
3975         goto out;
3976 }
3977
3978 static void rtl_rx_close(struct rtl8169_private *tp)
3979 {
3980         void __iomem *ioaddr = tp->mmio_addr;
3981
3982         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3983 }
3984
3985 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3986 {
3987         void __iomem *ioaddr = tp->mmio_addr;
3988
3989         /* Disable interrupts */
3990         rtl8169_irq_mask_and_ack(ioaddr);
3991
3992         rtl_rx_close(tp);
3993
3994         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3995             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3996             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3997                 while (RTL_R8(TxPoll) & NPQ)
3998                         udelay(20);
3999         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
4000                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4001                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4002                         udelay(100);
4003         } else {
4004                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4005                 udelay(100);
4006         }
4007
4008         rtl_hw_reset(tp);
4009 }
4010
4011 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4012 {
4013         void __iomem *ioaddr = tp->mmio_addr;
4014
4015         /* Set DMA burst size and Interframe Gap Time */
4016         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4017                 (InterFrameGap << TxInterFrameGapShift));
4018 }
4019
4020 static void rtl_hw_start(struct net_device *dev)
4021 {
4022         struct rtl8169_private *tp = netdev_priv(dev);
4023
4024         tp->hw_start(dev);
4025
4026         netif_start_queue(dev);
4027 }
4028
4029 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4030                                          void __iomem *ioaddr)
4031 {
4032         /*
4033          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4034          * register to be written before TxDescAddrLow to work.
4035          * Switching from MMIO to I/O access fixes the issue as well.
4036          */
4037         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4038         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4039         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4040         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4041 }
4042
4043 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4044 {
4045         u16 cmd;
4046
4047         cmd = RTL_R16(CPlusCmd);
4048         RTL_W16(CPlusCmd, cmd);
4049         return cmd;
4050 }
4051
4052 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4053 {
4054         /* Low hurts. Let's disable the filtering. */
4055         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4056 }
4057
4058 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4059 {
4060         static const struct rtl_cfg2_info {
4061                 u32 mac_version;
4062                 u32 clk;
4063                 u32 val;
4064         } cfg2_info [] = {
4065                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4066                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4067                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4068                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4069         };
4070         const struct rtl_cfg2_info *p = cfg2_info;
4071         unsigned int i;
4072         u32 clk;
4073
4074         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4075         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4076                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4077                         RTL_W32(0x7c, p->val);
4078                         break;
4079                 }
4080         }
4081 }
4082
4083 static void rtl_hw_start_8169(struct net_device *dev)
4084 {
4085         struct rtl8169_private *tp = netdev_priv(dev);
4086         void __iomem *ioaddr = tp->mmio_addr;
4087         struct pci_dev *pdev = tp->pci_dev;
4088
4089         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4090                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4091                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4092         }
4093
4094         RTL_W8(Cfg9346, Cfg9346_Unlock);
4095         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4096             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4097             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4098             tp->mac_version == RTL_GIGA_MAC_VER_04)
4099                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4100
4101         rtl_init_rxcfg(tp);
4102
4103         RTL_W8(EarlyTxThres, NoEarlyTx);
4104
4105         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4106
4107         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4108             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4109             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4110             tp->mac_version == RTL_GIGA_MAC_VER_04)
4111                 rtl_set_rx_tx_config_registers(tp);
4112
4113         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4114
4115         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4116             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4117                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4118                         "Bit-3 and bit-14 MUST be 1\n");
4119                 tp->cp_cmd |= (1 << 14);
4120         }
4121
4122         RTL_W16(CPlusCmd, tp->cp_cmd);
4123
4124         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4125
4126         /*
4127          * Undocumented corner. Supposedly:
4128          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4129          */
4130         RTL_W16(IntrMitigate, 0x0000);
4131
4132         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4133
4134         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4135             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4136             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4137             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4138                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4139                 rtl_set_rx_tx_config_registers(tp);
4140         }
4141
4142         RTL_W8(Cfg9346, Cfg9346_Lock);
4143
4144         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4145         RTL_R8(IntrMask);
4146
4147         RTL_W32(RxMissed, 0);
4148
4149         rtl_set_rx_mode(dev);
4150
4151         /* no early-rx interrupts */
4152         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4153
4154         /* Enable all known interrupts by setting the interrupt mask. */
4155         RTL_W16(IntrMask, tp->intr_event);
4156 }
4157
4158 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
4159 {
4160         int cap = pci_pcie_cap(pdev);
4161
4162         if (cap) {
4163                 u16 ctl;
4164
4165                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4166                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4167                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4168         }
4169 }
4170
4171 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4172 {
4173         u32 csi;
4174
4175         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4176         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4177 }
4178
4179 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4180 {
4181         rtl_csi_access_enable(ioaddr, 0x17000000);
4182 }
4183
4184 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4185 {
4186         rtl_csi_access_enable(ioaddr, 0x27000000);
4187 }
4188
4189 struct ephy_info {
4190         unsigned int offset;
4191         u16 mask;
4192         u16 bits;
4193 };
4194
4195 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4196 {
4197         u16 w;
4198
4199         while (len-- > 0) {
4200                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4201                 rtl_ephy_write(ioaddr, e->offset, w);
4202                 e++;
4203         }
4204 }
4205
4206 static void rtl_disable_clock_request(struct pci_dev *pdev)
4207 {
4208         int cap = pci_pcie_cap(pdev);
4209
4210         if (cap) {
4211                 u16 ctl;
4212
4213                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4214                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4215                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4216         }
4217 }
4218
4219 static void rtl_enable_clock_request(struct pci_dev *pdev)
4220 {
4221         int cap = pci_pcie_cap(pdev);
4222
4223         if (cap) {
4224                 u16 ctl;
4225
4226                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4227                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4228                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4229         }
4230 }
4231
4232 #define R8168_CPCMD_QUIRK_MASK (\
4233         EnableBist | \
4234         Mac_dbgo_oe | \
4235         Force_half_dup | \
4236         Force_rxflow_en | \
4237         Force_txflow_en | \
4238         Cxpl_dbg_sel | \
4239         ASF | \
4240         PktCntrDisable | \
4241         Mac_dbgo_sel)
4242
4243 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4244 {
4245         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4246
4247         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4248
4249         rtl_tx_performance_tweak(pdev,
4250                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4251 }
4252
4253 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4254 {
4255         rtl_hw_start_8168bb(ioaddr, pdev);
4256
4257         RTL_W8(MaxTxPacketSize, TxPacketMax);
4258
4259         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4260 }
4261
4262 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4263 {
4264         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4265
4266         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4267
4268         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4269
4270         rtl_disable_clock_request(pdev);
4271
4272         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4273 }
4274
4275 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4276 {
4277         static const struct ephy_info e_info_8168cp[] = {
4278                 { 0x01, 0,      0x0001 },
4279                 { 0x02, 0x0800, 0x1000 },
4280                 { 0x03, 0,      0x0042 },
4281                 { 0x06, 0x0080, 0x0000 },
4282                 { 0x07, 0,      0x2000 }
4283         };
4284
4285         rtl_csi_access_enable_2(ioaddr);
4286
4287         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4288
4289         __rtl_hw_start_8168cp(ioaddr, pdev);
4290 }
4291
4292 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4293 {
4294         rtl_csi_access_enable_2(ioaddr);
4295
4296         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4297
4298         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4299
4300         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4301 }
4302
4303 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4304 {
4305         rtl_csi_access_enable_2(ioaddr);
4306
4307         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4308
4309         /* Magic. */
4310         RTL_W8(DBG_REG, 0x20);
4311
4312         RTL_W8(MaxTxPacketSize, TxPacketMax);
4313
4314         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4315
4316         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4317 }
4318
4319 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4320 {
4321         static const struct ephy_info e_info_8168c_1[] = {
4322                 { 0x02, 0x0800, 0x1000 },
4323                 { 0x03, 0,      0x0002 },
4324                 { 0x06, 0x0080, 0x0000 }
4325         };
4326
4327         rtl_csi_access_enable_2(ioaddr);
4328
4329         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4330
4331         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4332
4333         __rtl_hw_start_8168cp(ioaddr, pdev);
4334 }
4335
4336 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4337 {
4338         static const struct ephy_info e_info_8168c_2[] = {
4339                 { 0x01, 0,      0x0001 },
4340                 { 0x03, 0x0400, 0x0220 }
4341         };
4342
4343         rtl_csi_access_enable_2(ioaddr);
4344
4345         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4346
4347         __rtl_hw_start_8168cp(ioaddr, pdev);
4348 }
4349
4350 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4351 {
4352         rtl_hw_start_8168c_2(ioaddr, pdev);
4353 }
4354
4355 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4356 {
4357         rtl_csi_access_enable_2(ioaddr);
4358
4359         __rtl_hw_start_8168cp(ioaddr, pdev);
4360 }
4361
4362 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4363 {
4364         rtl_csi_access_enable_2(ioaddr);
4365
4366         rtl_disable_clock_request(pdev);
4367
4368         RTL_W8(MaxTxPacketSize, TxPacketMax);
4369
4370         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4371
4372         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4373 }
4374
4375 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4376 {
4377         rtl_csi_access_enable_1(ioaddr);
4378
4379         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4380
4381         RTL_W8(MaxTxPacketSize, TxPacketMax);
4382
4383         rtl_disable_clock_request(pdev);
4384 }
4385
4386 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4387 {
4388         static const struct ephy_info e_info_8168d_4[] = {
4389                 { 0x0b, ~0,     0x48 },
4390                 { 0x19, 0x20,   0x50 },
4391                 { 0x0c, ~0,     0x20 }
4392         };
4393         int i;
4394
4395         rtl_csi_access_enable_1(ioaddr);
4396
4397         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4398
4399         RTL_W8(MaxTxPacketSize, TxPacketMax);
4400
4401         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4402                 const struct ephy_info *e = e_info_8168d_4 + i;
4403                 u16 w;
4404
4405                 w = rtl_ephy_read(ioaddr, e->offset);
4406                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4407         }
4408
4409         rtl_enable_clock_request(pdev);
4410 }
4411
4412 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4413 {
4414         static const struct ephy_info e_info_8168e_1[] = {
4415                 { 0x00, 0x0200, 0x0100 },
4416                 { 0x00, 0x0000, 0x0004 },
4417                 { 0x06, 0x0002, 0x0001 },
4418                 { 0x06, 0x0000, 0x0030 },
4419                 { 0x07, 0x0000, 0x2000 },
4420                 { 0x00, 0x0000, 0x0020 },
4421                 { 0x03, 0x5800, 0x2000 },
4422                 { 0x03, 0x0000, 0x0001 },
4423                 { 0x01, 0x0800, 0x1000 },
4424                 { 0x07, 0x0000, 0x4000 },
4425                 { 0x1e, 0x0000, 0x2000 },
4426                 { 0x19, 0xffff, 0xfe6c },
4427                 { 0x0a, 0x0000, 0x0040 }
4428         };
4429
4430         rtl_csi_access_enable_2(ioaddr);
4431
4432         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4433
4434         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4435
4436         RTL_W8(MaxTxPacketSize, TxPacketMax);
4437
4438         rtl_disable_clock_request(pdev);
4439
4440         /* Reset tx FIFO pointer */
4441         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4442         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4443
4444         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4445 }
4446
4447 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4448 {
4449         static const struct ephy_info e_info_8168e_2[] = {
4450                 { 0x09, 0x0000, 0x0080 },
4451                 { 0x19, 0x0000, 0x0224 }
4452         };
4453
4454         rtl_csi_access_enable_1(ioaddr);
4455
4456         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4457
4458         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4459
4460         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4461         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4462         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4463         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4464         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4465         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4466         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4467         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4468                      ERIAR_EXGMAC);
4469
4470         RTL_W8(MaxTxPacketSize, 0x27);
4471
4472         rtl_disable_clock_request(pdev);
4473
4474         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4475         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4476
4477         /* Adjust EEE LED frequency */
4478         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4479
4480         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4481         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4482         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4483 }
4484
4485 static void rtl_hw_start_8168(struct net_device *dev)
4486 {
4487         struct rtl8169_private *tp = netdev_priv(dev);
4488         void __iomem *ioaddr = tp->mmio_addr;
4489         struct pci_dev *pdev = tp->pci_dev;
4490
4491         RTL_W8(Cfg9346, Cfg9346_Unlock);
4492
4493         RTL_W8(MaxTxPacketSize, TxPacketMax);
4494
4495         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4496
4497         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4498
4499         RTL_W16(CPlusCmd, tp->cp_cmd);
4500
4501         RTL_W16(IntrMitigate, 0x5151);
4502
4503         /* Work around for RxFIFO overflow. */
4504         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4505             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4506                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4507                 tp->intr_event &= ~RxOverflow;
4508         }
4509
4510         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4511
4512         rtl_set_rx_mode(dev);
4513
4514         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4515                 (InterFrameGap << TxInterFrameGapShift));
4516
4517         RTL_R8(IntrMask);
4518
4519         switch (tp->mac_version) {
4520         case RTL_GIGA_MAC_VER_11:
4521                 rtl_hw_start_8168bb(ioaddr, pdev);
4522                 break;
4523
4524         case RTL_GIGA_MAC_VER_12:
4525         case RTL_GIGA_MAC_VER_17:
4526                 rtl_hw_start_8168bef(ioaddr, pdev);
4527                 break;
4528
4529         case RTL_GIGA_MAC_VER_18:
4530                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4531                 break;
4532
4533         case RTL_GIGA_MAC_VER_19:
4534                 rtl_hw_start_8168c_1(ioaddr, pdev);
4535                 break;
4536
4537         case RTL_GIGA_MAC_VER_20:
4538                 rtl_hw_start_8168c_2(ioaddr, pdev);
4539                 break;
4540
4541         case RTL_GIGA_MAC_VER_21:
4542                 rtl_hw_start_8168c_3(ioaddr, pdev);
4543                 break;
4544
4545         case RTL_GIGA_MAC_VER_22:
4546                 rtl_hw_start_8168c_4(ioaddr, pdev);
4547                 break;
4548
4549         case RTL_GIGA_MAC_VER_23:
4550                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4551                 break;
4552
4553         case RTL_GIGA_MAC_VER_24:
4554                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4555                 break;
4556
4557         case RTL_GIGA_MAC_VER_25:
4558         case RTL_GIGA_MAC_VER_26:
4559         case RTL_GIGA_MAC_VER_27:
4560                 rtl_hw_start_8168d(ioaddr, pdev);
4561                 break;
4562
4563         case RTL_GIGA_MAC_VER_28:
4564                 rtl_hw_start_8168d_4(ioaddr, pdev);
4565                 break;
4566
4567         case RTL_GIGA_MAC_VER_31:
4568                 rtl_hw_start_8168dp(ioaddr, pdev);
4569                 break;
4570
4571         case RTL_GIGA_MAC_VER_32:
4572         case RTL_GIGA_MAC_VER_33:
4573                 rtl_hw_start_8168e_1(ioaddr, pdev);
4574                 break;
4575         case RTL_GIGA_MAC_VER_34:
4576                 rtl_hw_start_8168e_2(ioaddr, pdev);
4577                 break;
4578
4579         default:
4580                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4581                         dev->name, tp->mac_version);
4582                 break;
4583         }
4584
4585         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4586
4587         RTL_W8(Cfg9346, Cfg9346_Lock);
4588
4589         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4590
4591         RTL_W16(IntrMask, tp->intr_event);
4592 }
4593
4594 #define R810X_CPCMD_QUIRK_MASK (\
4595         EnableBist | \
4596         Mac_dbgo_oe | \
4597         Force_half_dup | \
4598         Force_rxflow_en | \
4599         Force_txflow_en | \
4600         Cxpl_dbg_sel | \
4601         ASF | \
4602         PktCntrDisable | \
4603         Mac_dbgo_sel)
4604
4605 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4606 {
4607         static const struct ephy_info e_info_8102e_1[] = {
4608                 { 0x01, 0, 0x6e65 },
4609                 { 0x02, 0, 0x091f },
4610                 { 0x03, 0, 0xc2f9 },
4611                 { 0x06, 0, 0xafb5 },
4612                 { 0x07, 0, 0x0e00 },
4613                 { 0x19, 0, 0xec80 },
4614                 { 0x01, 0, 0x2e65 },
4615                 { 0x01, 0, 0x6e65 }
4616         };
4617         u8 cfg1;
4618
4619         rtl_csi_access_enable_2(ioaddr);
4620
4621         RTL_W8(DBG_REG, FIX_NAK_1);
4622
4623         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4624
4625         RTL_W8(Config1,
4626                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4627         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4628
4629         cfg1 = RTL_R8(Config1);
4630         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4631                 RTL_W8(Config1, cfg1 & ~LEDS0);
4632
4633         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4634 }
4635
4636 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4637 {
4638         rtl_csi_access_enable_2(ioaddr);
4639
4640         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4641
4642         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4643         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4644 }
4645
4646 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4647 {
4648         rtl_hw_start_8102e_2(ioaddr, pdev);
4649
4650         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4651 }
4652
4653 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4654 {
4655         static const struct ephy_info e_info_8105e_1[] = {
4656                 { 0x07, 0, 0x4000 },
4657                 { 0x19, 0, 0x0200 },
4658                 { 0x19, 0, 0x0020 },
4659                 { 0x1e, 0, 0x2000 },
4660                 { 0x03, 0, 0x0001 },
4661                 { 0x19, 0, 0x0100 },
4662                 { 0x19, 0, 0x0004 },
4663                 { 0x0a, 0, 0x0020 }
4664         };
4665
4666         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4667         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4668
4669         /* Disable Early Tally Counter */
4670         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4671
4672         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4673         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4674
4675         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4676 }
4677
4678 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4679 {
4680         rtl_hw_start_8105e_1(ioaddr, pdev);
4681         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4682 }
4683
4684 static void rtl_hw_start_8101(struct net_device *dev)
4685 {
4686         struct rtl8169_private *tp = netdev_priv(dev);
4687         void __iomem *ioaddr = tp->mmio_addr;
4688         struct pci_dev *pdev = tp->pci_dev;
4689
4690         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4691             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4692                 int cap = pci_pcie_cap(pdev);
4693
4694                 if (cap) {
4695                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4696                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4697                 }
4698         }
4699
4700         RTL_W8(Cfg9346, Cfg9346_Unlock);
4701
4702         switch (tp->mac_version) {
4703         case RTL_GIGA_MAC_VER_07:
4704                 rtl_hw_start_8102e_1(ioaddr, pdev);
4705                 break;
4706
4707         case RTL_GIGA_MAC_VER_08:
4708                 rtl_hw_start_8102e_3(ioaddr, pdev);
4709                 break;
4710
4711         case RTL_GIGA_MAC_VER_09:
4712                 rtl_hw_start_8102e_2(ioaddr, pdev);
4713                 break;
4714
4715         case RTL_GIGA_MAC_VER_29:
4716                 rtl_hw_start_8105e_1(ioaddr, pdev);
4717                 break;
4718         case RTL_GIGA_MAC_VER_30:
4719                 rtl_hw_start_8105e_2(ioaddr, pdev);
4720                 break;
4721         }
4722
4723         RTL_W8(Cfg9346, Cfg9346_Lock);
4724
4725         RTL_W8(MaxTxPacketSize, TxPacketMax);
4726
4727         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4728
4729         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4730         RTL_W16(CPlusCmd, tp->cp_cmd);
4731
4732         RTL_W16(IntrMitigate, 0x0000);
4733
4734         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4735
4736         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4737         rtl_set_rx_tx_config_registers(tp);
4738
4739         RTL_R8(IntrMask);
4740
4741         rtl_set_rx_mode(dev);
4742
4743         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4744
4745         RTL_W16(IntrMask, tp->intr_event);
4746 }
4747
4748 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4749 {
4750         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4751                 return -EINVAL;
4752
4753         dev->mtu = new_mtu;
4754         netdev_update_features(dev);
4755
4756         return 0;
4757 }
4758
4759 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4760 {
4761         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4762         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4763 }
4764
4765 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4766                                      void **data_buff, struct RxDesc *desc)
4767 {
4768         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4769                          DMA_FROM_DEVICE);
4770
4771         kfree(*data_buff);
4772         *data_buff = NULL;
4773         rtl8169_make_unusable_by_asic(desc);
4774 }
4775
4776 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4777 {
4778         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4779
4780         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4781 }
4782
4783 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4784                                        u32 rx_buf_sz)
4785 {
4786         desc->addr = cpu_to_le64(mapping);
4787         wmb();
4788         rtl8169_mark_to_asic(desc, rx_buf_sz);
4789 }
4790
4791 static inline void *rtl8169_align(void *data)
4792 {
4793         return (void *)ALIGN((long)data, 16);
4794 }
4795
4796 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4797                                              struct RxDesc *desc)
4798 {
4799         void *data;
4800         dma_addr_t mapping;
4801         struct device *d = &tp->pci_dev->dev;
4802         struct net_device *dev = tp->dev;
4803         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4804
4805         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4806         if (!data)
4807                 return NULL;
4808
4809         if (rtl8169_align(data) != data) {
4810                 kfree(data);
4811                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4812                 if (!data)
4813                         return NULL;
4814         }
4815
4816         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4817                                  DMA_FROM_DEVICE);
4818         if (unlikely(dma_mapping_error(d, mapping))) {
4819                 if (net_ratelimit())
4820                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4821                 goto err_out;
4822         }
4823
4824         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4825         return data;
4826
4827 err_out:
4828         kfree(data);
4829         return NULL;
4830 }
4831
4832 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4833 {
4834         unsigned int i;
4835
4836         for (i = 0; i < NUM_RX_DESC; i++) {
4837                 if (tp->Rx_databuff[i]) {
4838                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4839                                             tp->RxDescArray + i);
4840                 }
4841         }
4842 }
4843
4844 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4845 {
4846         desc->opts1 |= cpu_to_le32(RingEnd);
4847 }
4848
4849 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4850 {
4851         unsigned int i;
4852
4853         for (i = 0; i < NUM_RX_DESC; i++) {
4854                 void *data;
4855
4856                 if (tp->Rx_databuff[i])
4857                         continue;
4858
4859                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4860                 if (!data) {
4861                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4862                         goto err_out;
4863                 }
4864                 tp->Rx_databuff[i] = data;
4865         }
4866
4867         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4868         return 0;
4869
4870 err_out:
4871         rtl8169_rx_clear(tp);
4872         return -ENOMEM;
4873 }
4874
4875 static int rtl8169_init_ring(struct net_device *dev)
4876 {
4877         struct rtl8169_private *tp = netdev_priv(dev);
4878
4879         rtl8169_init_ring_indexes(tp);
4880
4881         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4882         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4883
4884         return rtl8169_rx_fill(tp);
4885 }
4886
4887 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4888                                  struct TxDesc *desc)
4889 {
4890         unsigned int len = tx_skb->len;
4891
4892         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4893
4894         desc->opts1 = 0x00;
4895         desc->opts2 = 0x00;
4896         desc->addr = 0x00;
4897         tx_skb->len = 0;
4898 }
4899
4900 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4901                                    unsigned int n)
4902 {
4903         unsigned int i;
4904
4905         for (i = 0; i < n; i++) {
4906                 unsigned int entry = (start + i) % NUM_TX_DESC;
4907                 struct ring_info *tx_skb = tp->tx_skb + entry;
4908                 unsigned int len = tx_skb->len;
4909
4910                 if (len) {
4911                         struct sk_buff *skb = tx_skb->skb;
4912
4913                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4914                                              tp->TxDescArray + entry);
4915                         if (skb) {
4916                                 tp->dev->stats.tx_dropped++;
4917                                 dev_kfree_skb(skb);
4918                                 tx_skb->skb = NULL;
4919                         }
4920                 }
4921         }
4922 }
4923
4924 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4925 {
4926         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4927         tp->cur_tx = tp->dirty_tx = 0;
4928 }
4929
4930 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4931 {
4932         struct rtl8169_private *tp = netdev_priv(dev);
4933
4934         PREPARE_DELAYED_WORK(&tp->task, task);
4935         schedule_delayed_work(&tp->task, 4);
4936 }
4937
4938 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4939 {
4940         struct rtl8169_private *tp = netdev_priv(dev);
4941         void __iomem *ioaddr = tp->mmio_addr;
4942
4943         synchronize_irq(dev->irq);
4944
4945         /* Wait for any pending NAPI task to complete */
4946         napi_disable(&tp->napi);
4947
4948         rtl8169_irq_mask_and_ack(ioaddr);
4949
4950         tp->intr_mask = 0xffff;
4951         RTL_W16(IntrMask, tp->intr_event);
4952         napi_enable(&tp->napi);
4953 }
4954
4955 static void rtl8169_reinit_task(struct work_struct *work)
4956 {
4957         struct rtl8169_private *tp =
4958                 container_of(work, struct rtl8169_private, task.work);
4959         struct net_device *dev = tp->dev;
4960         int ret;
4961
4962         rtnl_lock();
4963
4964         if (!netif_running(dev))
4965                 goto out_unlock;
4966
4967         rtl8169_wait_for_quiescence(dev);
4968         rtl8169_close(dev);
4969
4970         ret = rtl8169_open(dev);
4971         if (unlikely(ret < 0)) {
4972                 if (net_ratelimit())
4973                         netif_err(tp, drv, dev,
4974                                   "reinit failure (status = %d). Rescheduling\n",
4975                                   ret);
4976                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4977         }
4978
4979 out_unlock:
4980         rtnl_unlock();
4981 }
4982
4983 static void rtl8169_reset_task(struct work_struct *work)
4984 {
4985         struct rtl8169_private *tp =
4986                 container_of(work, struct rtl8169_private, task.work);
4987         struct net_device *dev = tp->dev;
4988         int i;
4989
4990         rtnl_lock();
4991
4992         if (!netif_running(dev))
4993                 goto out_unlock;
4994
4995         rtl8169_wait_for_quiescence(dev);
4996
4997         for (i = 0; i < NUM_RX_DESC; i++)
4998                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4999
5000         rtl8169_tx_clear(tp);
5001
5002         rtl8169_hw_reset(tp);
5003         rtl_hw_start(dev);
5004         netif_wake_queue(dev);
5005         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5006
5007 out_unlock:
5008         rtnl_unlock();
5009 }
5010
5011 static void rtl8169_tx_timeout(struct net_device *dev)
5012 {
5013         struct rtl8169_private *tp = netdev_priv(dev);
5014
5015         rtl8169_hw_reset(tp);
5016
5017         /* Let's wait a bit while any (async) irq lands on */
5018         rtl8169_schedule_work(dev, rtl8169_reset_task);
5019 }
5020
5021 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5022                               u32 *opts)
5023 {
5024         struct skb_shared_info *info = skb_shinfo(skb);
5025         unsigned int cur_frag, entry;
5026         struct TxDesc * uninitialized_var(txd);
5027         struct device *d = &tp->pci_dev->dev;
5028
5029         entry = tp->cur_tx;
5030         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5031                 skb_frag_t *frag = info->frags + cur_frag;
5032                 dma_addr_t mapping;
5033                 u32 status, len;
5034                 void *addr;
5035
5036                 entry = (entry + 1) % NUM_TX_DESC;
5037
5038                 txd = tp->TxDescArray + entry;
5039                 len = frag->size;
5040                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
5041                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5042                 if (unlikely(dma_mapping_error(d, mapping))) {
5043                         if (net_ratelimit())
5044                                 netif_err(tp, drv, tp->dev,
5045                                           "Failed to map TX fragments DMA!\n");
5046                         goto err_out;
5047                 }
5048
5049                 /* Anti gcc 2.95.3 bugware (sic) */
5050                 status = opts[0] | len |
5051                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5052
5053                 txd->opts1 = cpu_to_le32(status);
5054                 txd->opts2 = cpu_to_le32(opts[1]);
5055                 txd->addr = cpu_to_le64(mapping);
5056
5057                 tp->tx_skb[entry].len = len;
5058         }
5059
5060         if (cur_frag) {
5061                 tp->tx_skb[entry].skb = skb;
5062                 txd->opts1 |= cpu_to_le32(LastFrag);
5063         }
5064
5065         return cur_frag;
5066
5067 err_out:
5068         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5069         return -EIO;
5070 }
5071
5072 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5073                                     struct sk_buff *skb, u32 *opts)
5074 {
5075         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5076         u32 mss = skb_shinfo(skb)->gso_size;
5077         int offset = info->opts_offset;
5078
5079         if (mss) {
5080                 opts[0] |= TD_LSO;
5081                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5082         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5083                 const struct iphdr *ip = ip_hdr(skb);
5084
5085                 if (ip->protocol == IPPROTO_TCP)
5086                         opts[offset] |= info->checksum.tcp;
5087                 else if (ip->protocol == IPPROTO_UDP)
5088                         opts[offset] |= info->checksum.udp;
5089                 else
5090                         WARN_ON_ONCE(1);
5091         }
5092 }
5093
5094 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5095                                       struct net_device *dev)
5096 {
5097         struct rtl8169_private *tp = netdev_priv(dev);
5098         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5099         struct TxDesc *txd = tp->TxDescArray + entry;
5100         void __iomem *ioaddr = tp->mmio_addr;
5101         struct device *d = &tp->pci_dev->dev;
5102         dma_addr_t mapping;
5103         u32 status, len;
5104         u32 opts[2];
5105         int frags;
5106
5107         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5108                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5109                 goto err_stop_0;
5110         }
5111
5112         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5113                 goto err_stop_0;
5114
5115         len = skb_headlen(skb);
5116         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5117         if (unlikely(dma_mapping_error(d, mapping))) {
5118                 if (net_ratelimit())
5119                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5120                 goto err_dma_0;
5121         }
5122
5123         tp->tx_skb[entry].len = len;
5124         txd->addr = cpu_to_le64(mapping);
5125
5126         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5127         opts[0] = DescOwn;
5128
5129         rtl8169_tso_csum(tp, skb, opts);
5130
5131         frags = rtl8169_xmit_frags(tp, skb, opts);
5132         if (frags < 0)
5133                 goto err_dma_1;
5134         else if (frags)
5135                 opts[0] |= FirstFrag;
5136         else {
5137                 opts[0] |= FirstFrag | LastFrag;
5138                 tp->tx_skb[entry].skb = skb;
5139         }
5140
5141         txd->opts2 = cpu_to_le32(opts[1]);
5142
5143         wmb();
5144
5145         /* Anti gcc 2.95.3 bugware (sic) */
5146         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5147         txd->opts1 = cpu_to_le32(status);
5148
5149         tp->cur_tx += frags + 1;
5150
5151         wmb();
5152
5153         RTL_W8(TxPoll, NPQ);
5154
5155         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5156                 netif_stop_queue(dev);
5157                 smp_rmb();
5158                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5159                         netif_wake_queue(dev);
5160         }
5161
5162         return NETDEV_TX_OK;
5163
5164 err_dma_1:
5165         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5166 err_dma_0:
5167         dev_kfree_skb(skb);
5168         dev->stats.tx_dropped++;
5169         return NETDEV_TX_OK;
5170
5171 err_stop_0:
5172         netif_stop_queue(dev);
5173         dev->stats.tx_dropped++;
5174         return NETDEV_TX_BUSY;
5175 }
5176
5177 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5178 {
5179         struct rtl8169_private *tp = netdev_priv(dev);
5180         struct pci_dev *pdev = tp->pci_dev;
5181         u16 pci_status, pci_cmd;
5182
5183         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5184         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5185
5186         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5187                   pci_cmd, pci_status);
5188
5189         /*
5190          * The recovery sequence below admits a very elaborated explanation:
5191          * - it seems to work;
5192          * - I did not see what else could be done;
5193          * - it makes iop3xx happy.
5194          *
5195          * Feel free to adjust to your needs.
5196          */
5197         if (pdev->broken_parity_status)
5198                 pci_cmd &= ~PCI_COMMAND_PARITY;
5199         else
5200                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5201
5202         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5203
5204         pci_write_config_word(pdev, PCI_STATUS,
5205                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5206                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5207                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5208
5209         /* The infamous DAC f*ckup only happens at boot time */
5210         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5211                 void __iomem *ioaddr = tp->mmio_addr;
5212
5213                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5214                 tp->cp_cmd &= ~PCIDAC;
5215                 RTL_W16(CPlusCmd, tp->cp_cmd);
5216                 dev->features &= ~NETIF_F_HIGHDMA;
5217         }
5218
5219         rtl8169_hw_reset(tp);
5220
5221         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5222 }
5223
5224 static void rtl8169_tx_interrupt(struct net_device *dev,
5225                                  struct rtl8169_private *tp,
5226                                  void __iomem *ioaddr)
5227 {
5228         unsigned int dirty_tx, tx_left;
5229
5230         dirty_tx = tp->dirty_tx;
5231         smp_rmb();
5232         tx_left = tp->cur_tx - dirty_tx;
5233
5234         while (tx_left > 0) {
5235                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5236                 struct ring_info *tx_skb = tp->tx_skb + entry;
5237                 u32 status;
5238
5239                 rmb();
5240                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5241                 if (status & DescOwn)
5242                         break;
5243
5244                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5245                                      tp->TxDescArray + entry);
5246                 if (status & LastFrag) {
5247                         dev->stats.tx_packets++;
5248                         dev->stats.tx_bytes += tx_skb->skb->len;
5249                         dev_kfree_skb(tx_skb->skb);
5250                         tx_skb->skb = NULL;
5251                 }
5252                 dirty_tx++;
5253                 tx_left--;
5254         }
5255
5256         if (tp->dirty_tx != dirty_tx) {
5257                 tp->dirty_tx = dirty_tx;
5258                 smp_wmb();
5259                 if (netif_queue_stopped(dev) &&
5260                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5261                         netif_wake_queue(dev);
5262                 }
5263                 /*
5264                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5265                  * too close. Let's kick an extra TxPoll request when a burst
5266                  * of start_xmit activity is detected (if it is not detected,
5267                  * it is slow enough). -- FR
5268                  */
5269                 smp_rmb();
5270                 if (tp->cur_tx != dirty_tx)
5271                         RTL_W8(TxPoll, NPQ);
5272         }
5273 }
5274
5275 static inline int rtl8169_fragmented_frame(u32 status)
5276 {
5277         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5278 }
5279
5280 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5281 {
5282         u32 status = opts1 & RxProtoMask;
5283
5284         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5285             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5286                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5287         else
5288                 skb_checksum_none_assert(skb);
5289 }
5290
5291 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5292                                            struct rtl8169_private *tp,
5293                                            int pkt_size,
5294                                            dma_addr_t addr)
5295 {
5296         struct sk_buff *skb;
5297         struct device *d = &tp->pci_dev->dev;
5298
5299         data = rtl8169_align(data);
5300         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5301         prefetch(data);
5302         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5303         if (skb)
5304                 memcpy(skb->data, data, pkt_size);
5305         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5306
5307         return skb;
5308 }
5309
5310 static int rtl8169_rx_interrupt(struct net_device *dev,
5311                                 struct rtl8169_private *tp,
5312                                 void __iomem *ioaddr, u32 budget)
5313 {
5314         unsigned int cur_rx, rx_left;
5315         unsigned int count;
5316
5317         cur_rx = tp->cur_rx;
5318         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5319         rx_left = min(rx_left, budget);
5320
5321         for (; rx_left > 0; rx_left--, cur_rx++) {
5322                 unsigned int entry = cur_rx % NUM_RX_DESC;
5323                 struct RxDesc *desc = tp->RxDescArray + entry;
5324                 u32 status;
5325
5326                 rmb();
5327                 status = le32_to_cpu(desc->opts1);
5328
5329                 if (status & DescOwn)
5330                         break;
5331                 if (unlikely(status & RxRES)) {
5332                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5333                                    status);
5334                         dev->stats.rx_errors++;
5335                         if (status & (RxRWT | RxRUNT))
5336                                 dev->stats.rx_length_errors++;
5337                         if (status & RxCRC)
5338                                 dev->stats.rx_crc_errors++;
5339                         if (status & RxFOVF) {
5340                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5341                                 dev->stats.rx_fifo_errors++;
5342                         }
5343                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5344                 } else {
5345                         struct sk_buff *skb;
5346                         dma_addr_t addr = le64_to_cpu(desc->addr);
5347                         int pkt_size = (status & 0x00001FFF) - 4;
5348
5349                         /*
5350                          * The driver does not support incoming fragmented
5351                          * frames. They are seen as a symptom of over-mtu
5352                          * sized frames.
5353                          */
5354                         if (unlikely(rtl8169_fragmented_frame(status))) {
5355                                 dev->stats.rx_dropped++;
5356                                 dev->stats.rx_length_errors++;
5357                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5358                                 continue;
5359                         }
5360
5361                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5362                                                   tp, pkt_size, addr);
5363                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5364                         if (!skb) {
5365                                 dev->stats.rx_dropped++;
5366                                 continue;
5367                         }
5368
5369                         rtl8169_rx_csum(skb, status);
5370                         skb_put(skb, pkt_size);
5371                         skb->protocol = eth_type_trans(skb, dev);
5372
5373                         rtl8169_rx_vlan_tag(desc, skb);
5374
5375                         napi_gro_receive(&tp->napi, skb);
5376
5377                         dev->stats.rx_bytes += pkt_size;
5378                         dev->stats.rx_packets++;
5379                 }
5380
5381                 /* Work around for AMD plateform. */
5382                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5383                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5384                         desc->opts2 = 0;
5385                         cur_rx++;
5386                 }
5387         }
5388
5389         count = cur_rx - tp->cur_rx;
5390         tp->cur_rx = cur_rx;
5391
5392         tp->dirty_rx += count;
5393
5394         return count;
5395 }
5396
5397 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5398 {
5399         struct net_device *dev = dev_instance;
5400         struct rtl8169_private *tp = netdev_priv(dev);
5401         void __iomem *ioaddr = tp->mmio_addr;
5402         int handled = 0;
5403         int status;
5404
5405         /* loop handling interrupts until we have no new ones or
5406          * we hit a invalid/hotplug case.
5407          */
5408         status = RTL_R16(IntrStatus);
5409         while (status && status != 0xffff) {
5410                 handled = 1;
5411
5412                 /* Handle all of the error cases first. These will reset
5413                  * the chip, so just exit the loop.
5414                  */
5415                 if (unlikely(!netif_running(dev))) {
5416                         rtl8169_hw_reset(tp);
5417                         break;
5418                 }
5419
5420                 if (unlikely(status & RxFIFOOver)) {
5421                         switch (tp->mac_version) {
5422                         /* Work around for rx fifo overflow */
5423                         case RTL_GIGA_MAC_VER_11:
5424                         case RTL_GIGA_MAC_VER_22:
5425                         case RTL_GIGA_MAC_VER_26:
5426                                 netif_stop_queue(dev);
5427                                 rtl8169_tx_timeout(dev);
5428                                 goto done;
5429                         /* Testers needed. */
5430                         case RTL_GIGA_MAC_VER_17:
5431                         case RTL_GIGA_MAC_VER_19:
5432                         case RTL_GIGA_MAC_VER_20:
5433                         case RTL_GIGA_MAC_VER_21:
5434                         case RTL_GIGA_MAC_VER_23:
5435                         case RTL_GIGA_MAC_VER_24:
5436                         case RTL_GIGA_MAC_VER_27:
5437                         case RTL_GIGA_MAC_VER_28:
5438                         case RTL_GIGA_MAC_VER_31:
5439                         /* Experimental science. Pktgen proof. */
5440                         case RTL_GIGA_MAC_VER_12:
5441                         case RTL_GIGA_MAC_VER_25:
5442                                 if (status == RxFIFOOver)
5443                                         goto done;
5444                                 break;
5445                         default:
5446                                 break;
5447                         }
5448                 }
5449
5450                 if (unlikely(status & SYSErr)) {
5451                         rtl8169_pcierr_interrupt(dev);
5452                         break;
5453                 }
5454
5455                 if (status & LinkChg)
5456                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5457
5458                 /* We need to see the lastest version of tp->intr_mask to
5459                  * avoid ignoring an MSI interrupt and having to wait for
5460                  * another event which may never come.
5461                  */
5462                 smp_rmb();
5463                 if (status & tp->intr_mask & tp->napi_event) {
5464                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5465                         tp->intr_mask = ~tp->napi_event;
5466
5467                         if (likely(napi_schedule_prep(&tp->napi)))
5468                                 __napi_schedule(&tp->napi);
5469                         else
5470                                 netif_info(tp, intr, dev,
5471                                            "interrupt %04x in poll\n", status);
5472                 }
5473
5474                 /* We only get a new MSI interrupt when all active irq
5475                  * sources on the chip have been acknowledged. So, ack
5476                  * everything we've seen and check if new sources have become
5477                  * active to avoid blocking all interrupts from the chip.
5478                  */
5479                 RTL_W16(IntrStatus,
5480                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5481                 status = RTL_R16(IntrStatus);
5482         }
5483 done:
5484         return IRQ_RETVAL(handled);
5485 }
5486
5487 static int rtl8169_poll(struct napi_struct *napi, int budget)
5488 {
5489         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5490         struct net_device *dev = tp->dev;
5491         void __iomem *ioaddr = tp->mmio_addr;
5492         int work_done;
5493
5494         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5495         rtl8169_tx_interrupt(dev, tp, ioaddr);
5496
5497         if (work_done < budget) {
5498                 napi_complete(napi);
5499
5500                 /* We need for force the visibility of tp->intr_mask
5501                  * for other CPUs, as we can loose an MSI interrupt
5502                  * and potentially wait for a retransmit timeout if we don't.
5503                  * The posted write to IntrMask is safe, as it will
5504                  * eventually make it to the chip and we won't loose anything
5505                  * until it does.
5506                  */
5507                 tp->intr_mask = 0xffff;
5508                 wmb();
5509                 RTL_W16(IntrMask, tp->intr_event);
5510         }
5511
5512         return work_done;
5513 }
5514
5515 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5516 {
5517         struct rtl8169_private *tp = netdev_priv(dev);
5518
5519         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5520                 return;
5521
5522         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5523         RTL_W32(RxMissed, 0);
5524 }
5525
5526 static void rtl8169_down(struct net_device *dev)
5527 {
5528         struct rtl8169_private *tp = netdev_priv(dev);
5529         void __iomem *ioaddr = tp->mmio_addr;
5530
5531         del_timer_sync(&tp->timer);
5532
5533         netif_stop_queue(dev);
5534
5535         napi_disable(&tp->napi);
5536
5537         spin_lock_irq(&tp->lock);
5538
5539         rtl8169_hw_reset(tp);
5540         /*
5541          * At this point device interrupts can not be enabled in any function,
5542          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5543          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5544          */
5545         rtl8169_rx_missed(dev, ioaddr);
5546
5547         spin_unlock_irq(&tp->lock);
5548
5549         synchronize_irq(dev->irq);
5550
5551         /* Give a racing hard_start_xmit a few cycles to complete. */
5552         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5553
5554         rtl8169_tx_clear(tp);
5555
5556         rtl8169_rx_clear(tp);
5557
5558         rtl_pll_power_down(tp);
5559 }
5560
5561 static int rtl8169_close(struct net_device *dev)
5562 {
5563         struct rtl8169_private *tp = netdev_priv(dev);
5564         struct pci_dev *pdev = tp->pci_dev;
5565
5566         pm_runtime_get_sync(&pdev->dev);
5567
5568         /* Update counters before going down */
5569         rtl8169_update_counters(dev);
5570
5571         rtl8169_down(dev);
5572
5573         free_irq(dev->irq, dev);
5574
5575         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5576                           tp->RxPhyAddr);
5577         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5578                           tp->TxPhyAddr);
5579         tp->TxDescArray = NULL;
5580         tp->RxDescArray = NULL;
5581
5582         pm_runtime_put_sync(&pdev->dev);
5583
5584         return 0;
5585 }
5586
5587 static void rtl_set_rx_mode(struct net_device *dev)
5588 {
5589         struct rtl8169_private *tp = netdev_priv(dev);
5590         void __iomem *ioaddr = tp->mmio_addr;
5591         unsigned long flags;
5592         u32 mc_filter[2];       /* Multicast hash filter */
5593         int rx_mode;
5594         u32 tmp = 0;
5595
5596         if (dev->flags & IFF_PROMISC) {
5597                 /* Unconditionally log net taps. */
5598                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5599                 rx_mode =
5600                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5601                     AcceptAllPhys;
5602                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5603         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5604                    (dev->flags & IFF_ALLMULTI)) {
5605                 /* Too many to filter perfectly -- accept all multicasts. */
5606                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5607                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5608         } else {
5609                 struct netdev_hw_addr *ha;
5610
5611                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5612                 mc_filter[1] = mc_filter[0] = 0;
5613                 netdev_for_each_mc_addr(ha, dev) {
5614                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5615                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5616                         rx_mode |= AcceptMulticast;
5617                 }
5618         }
5619
5620         spin_lock_irqsave(&tp->lock, flags);
5621
5622         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5623
5624         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5625                 u32 data = mc_filter[0];
5626
5627                 mc_filter[0] = swab32(mc_filter[1]);
5628                 mc_filter[1] = swab32(data);
5629         }
5630
5631         RTL_W32(MAR0 + 4, mc_filter[1]);
5632         RTL_W32(MAR0 + 0, mc_filter[0]);
5633
5634         RTL_W32(RxConfig, tmp);
5635
5636         spin_unlock_irqrestore(&tp->lock, flags);
5637 }
5638
5639 /**
5640  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5641  *  @dev: The Ethernet Device to get statistics for
5642  *
5643  *  Get TX/RX statistics for rtl8169
5644  */
5645 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5646 {
5647         struct rtl8169_private *tp = netdev_priv(dev);
5648         void __iomem *ioaddr = tp->mmio_addr;
5649         unsigned long flags;
5650
5651         if (netif_running(dev)) {
5652                 spin_lock_irqsave(&tp->lock, flags);
5653                 rtl8169_rx_missed(dev, ioaddr);
5654                 spin_unlock_irqrestore(&tp->lock, flags);
5655         }
5656
5657         return &dev->stats;
5658 }
5659
5660 static void rtl8169_net_suspend(struct net_device *dev)
5661 {
5662         struct rtl8169_private *tp = netdev_priv(dev);
5663
5664         if (!netif_running(dev))
5665                 return;
5666
5667         rtl_pll_power_down(tp);
5668
5669         netif_device_detach(dev);
5670         netif_stop_queue(dev);
5671 }
5672
5673 #ifdef CONFIG_PM
5674
5675 static int rtl8169_suspend(struct device *device)
5676 {
5677         struct pci_dev *pdev = to_pci_dev(device);
5678         struct net_device *dev = pci_get_drvdata(pdev);
5679
5680         rtl8169_net_suspend(dev);
5681
5682         return 0;
5683 }
5684
5685 static void __rtl8169_resume(struct net_device *dev)
5686 {
5687         struct rtl8169_private *tp = netdev_priv(dev);
5688
5689         netif_device_attach(dev);
5690
5691         rtl_pll_power_up(tp);
5692
5693         rtl8169_schedule_work(dev, rtl8169_reset_task);
5694 }
5695
5696 static int rtl8169_resume(struct device *device)
5697 {
5698         struct pci_dev *pdev = to_pci_dev(device);
5699         struct net_device *dev = pci_get_drvdata(pdev);
5700         struct rtl8169_private *tp = netdev_priv(dev);
5701
5702         rtl8169_init_phy(dev, tp);
5703
5704         if (netif_running(dev))
5705                 __rtl8169_resume(dev);
5706
5707         return 0;
5708 }
5709
5710 static int rtl8169_runtime_suspend(struct device *device)
5711 {
5712         struct pci_dev *pdev = to_pci_dev(device);
5713         struct net_device *dev = pci_get_drvdata(pdev);
5714         struct rtl8169_private *tp = netdev_priv(dev);
5715
5716         if (!tp->TxDescArray)
5717                 return 0;
5718
5719         spin_lock_irq(&tp->lock);
5720         tp->saved_wolopts = __rtl8169_get_wol(tp);
5721         __rtl8169_set_wol(tp, WAKE_ANY);
5722         spin_unlock_irq(&tp->lock);
5723
5724         rtl8169_net_suspend(dev);
5725
5726         return 0;
5727 }
5728
5729 static int rtl8169_runtime_resume(struct device *device)
5730 {
5731         struct pci_dev *pdev = to_pci_dev(device);
5732         struct net_device *dev = pci_get_drvdata(pdev);
5733         struct rtl8169_private *tp = netdev_priv(dev);
5734
5735         if (!tp->TxDescArray)
5736                 return 0;
5737
5738         spin_lock_irq(&tp->lock);
5739         __rtl8169_set_wol(tp, tp->saved_wolopts);
5740         tp->saved_wolopts = 0;
5741         spin_unlock_irq(&tp->lock);
5742
5743         rtl8169_init_phy(dev, tp);
5744
5745         __rtl8169_resume(dev);
5746
5747         return 0;
5748 }
5749
5750 static int rtl8169_runtime_idle(struct device *device)
5751 {
5752         struct pci_dev *pdev = to_pci_dev(device);
5753         struct net_device *dev = pci_get_drvdata(pdev);
5754         struct rtl8169_private *tp = netdev_priv(dev);
5755
5756         return tp->TxDescArray ? -EBUSY : 0;
5757 }
5758
5759 static const struct dev_pm_ops rtl8169_pm_ops = {
5760         .suspend                = rtl8169_suspend,
5761         .resume                 = rtl8169_resume,
5762         .freeze                 = rtl8169_suspend,
5763         .thaw                   = rtl8169_resume,
5764         .poweroff               = rtl8169_suspend,
5765         .restore                = rtl8169_resume,
5766         .runtime_suspend        = rtl8169_runtime_suspend,
5767         .runtime_resume         = rtl8169_runtime_resume,
5768         .runtime_idle           = rtl8169_runtime_idle,
5769 };
5770
5771 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5772
5773 #else /* !CONFIG_PM */
5774
5775 #define RTL8169_PM_OPS  NULL
5776
5777 #endif /* !CONFIG_PM */
5778
5779 static void rtl_shutdown(struct pci_dev *pdev)
5780 {
5781         struct net_device *dev = pci_get_drvdata(pdev);
5782         struct rtl8169_private *tp = netdev_priv(dev);
5783         void __iomem *ioaddr = tp->mmio_addr;
5784
5785         rtl8169_net_suspend(dev);
5786
5787         /* Restore original MAC address */
5788         rtl_rar_set(tp, dev->perm_addr);
5789
5790         spin_lock_irq(&tp->lock);
5791
5792         rtl8169_hw_reset(tp);
5793
5794         spin_unlock_irq(&tp->lock);
5795
5796         if (system_state == SYSTEM_POWER_OFF) {
5797                 /* WoL fails with 8168b when the receiver is disabled. */
5798                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5799                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5800                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5801                     (tp->features & RTL_FEATURE_WOL)) {
5802                         pci_clear_master(pdev);
5803
5804                         RTL_W8(ChipCmd, CmdRxEnb);
5805                         /* PCI commit */
5806                         RTL_R8(ChipCmd);
5807                 }
5808
5809                 pci_wake_from_d3(pdev, true);
5810                 pci_set_power_state(pdev, PCI_D3hot);
5811         }
5812 }
5813
5814 static struct pci_driver rtl8169_pci_driver = {
5815         .name           = MODULENAME,
5816         .id_table       = rtl8169_pci_tbl,
5817         .probe          = rtl8169_init_one,
5818         .remove         = __devexit_p(rtl8169_remove_one),
5819         .shutdown       = rtl_shutdown,
5820         .driver.pm      = RTL8169_PM_OPS,
5821 };
5822
5823 static int __init rtl8169_init_module(void)
5824 {
5825         return pci_register_driver(&rtl8169_pci_driver);
5826 }
5827
5828 static void __exit rtl8169_cleanup_module(void)
5829 {
5830         pci_unregister_driver(&rtl8169_pci_driver);
5831 }
5832
5833 module_init(rtl8169_init_module);
5834 module_exit(rtl8169_cleanup_module);