2 * Copyright (c) 2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_phy.h"
19 #include "ar9003_eeprom.h"
21 #define COMP_HDR_LEN 4
22 #define COMP_CKSUM_LEN 2
24 #define AR_CH0_TOP (0x00016288)
25 #define AR_CH0_TOP_XPABIASLVL (0x300)
26 #define AR_CH0_TOP_XPABIASLVL_S (8)
28 #define AR_CH0_THERM (0x00016290)
29 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
30 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
31 #define AR_CH0_THERM_XPASHORT2GND 0x4
32 #define AR_CH0_THERM_XPASHORT2GND_S 2
34 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
35 #define AR_SWITCH_TABLE_COM_ALL_S (0)
37 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
38 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
40 #define AR_SWITCH_TABLE_ALL (0xfff)
41 #define AR_SWITCH_TABLE_ALL_S (0)
43 #define LE16(x) __constant_cpu_to_le16(x)
44 #define LE32(x) __constant_cpu_to_le32(x)
46 /* Local defines to distinguish between extension and control CTL's */
47 #define EXT_ADDITIVE (0x8000)
48 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
49 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
50 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
51 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
52 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
53 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
54 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
55 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
57 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
58 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
60 static int ar9003_hw_power_interpolate(int32_t x,
61 int32_t *px, int32_t *py, u_int16_t np);
62 static const struct ar9300_eeprom ar9300_default = {
65 .macAddr = {1, 2, 3, 4, 5, 6},
66 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
67 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
69 .regDmn = { LE16(0), LE16(0x1f) },
70 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
72 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
76 .blueToothOptions = 0,
78 .deviceType = 5, /* takes lower byte in eeprom location */
79 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
80 .params_for_tuning_caps = {0, 0},
81 .featureEnable = 0x0c,
83 * bit0 - enable tx temp comp - disabled
84 * bit1 - enable tx volt comp - disabled
85 * bit2 - enable fastClock - enabled
86 * bit3 - enable doubling - enabled
87 * bit4 - enable internal regulator - disabled
88 * bit5 - enable pa predistortion - disabled
90 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
91 .eepromWriteEnableGpio = 3,
94 .rxBandSelectGpio = 0xff,
99 /* ar9300_modal_eep_header 2g */
100 /* 4 idle,t1,t2,b(4 bits per setting) */
101 .antCtrlCommon = LE32(0x110),
102 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
103 .antCtrlCommon2 = LE32(0x22222),
106 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
107 * rx1, rx12, b (2 bits each)
109 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
112 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
113 * for ar9280 (0xa20c/b20c 5:0)
115 .xatten1DB = {0, 0, 0},
118 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
119 * for ar9280 (0xa20c/b20c 16:12
121 .xatten1Margin = {0, 0, 0},
126 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
127 * channels in usual fbin coding format
129 .spurChans = {0, 0, 0, 0, 0},
132 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
133 * if the register is per chain
135 .noiseFloorThreshCh = {-1, 0, 0},
136 .ob = {1, 1, 1},/* 3 chain */
137 .db_stage2 = {1, 1, 1}, /* 3 chain */
138 .db_stage3 = {0, 0, 0},
139 .db_stage4 = {0, 0, 0},
141 .txFrameToDataStart = 0x0e,
142 .txFrameToPaOn = 0x0e,
143 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
145 .switchSettling = 0x2c,
146 .adcDesiredSize = -30,
149 .txFrameToXpaOn = 0xe,
151 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
152 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
158 .ant_div_control = 0,
159 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
166 /* ar9300_cal_data_per_freq_op_loop 2g */
168 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
169 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
170 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
172 .calTarget_freqbin_Cck = {
176 .calTarget_freqbin_2G = {
181 .calTarget_freqbin_2GHT20 = {
186 .calTarget_freqbin_2GHT40 = {
191 .calTargetPowerCck = {
192 /* 1L-5L,5S,11L,11S */
193 { {36, 36, 36, 36} },
194 { {36, 36, 36, 36} },
196 .calTargetPower2G = {
198 { {32, 32, 28, 24} },
199 { {32, 32, 28, 24} },
200 { {32, 32, 28, 24} },
202 .calTargetPower2GHT20 = {
203 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
204 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
205 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
207 .calTargetPower2GHT40 = {
208 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
209 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
210 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
213 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
214 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
244 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
245 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
246 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
247 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
251 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
252 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
253 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
258 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
259 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
265 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
266 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
267 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
268 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
272 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
273 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
274 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
278 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
279 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
280 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
285 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
286 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
287 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
292 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
293 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
294 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
295 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
299 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
300 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
301 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
303 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
304 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
305 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
307 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
308 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
309 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
311 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
312 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
313 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
316 /* 4 idle,t1,t2,b (4 bits per setting) */
317 .antCtrlCommon = LE32(0x110),
318 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
319 .antCtrlCommon2 = LE32(0x22222),
320 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
322 LE16(0x000), LE16(0x000), LE16(0x000),
324 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
325 .xatten1DB = {0, 0, 0},
328 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
329 * for merlin (0xa20c/b20c 16:12
331 .xatten1Margin = {0, 0, 0},
334 /* spurChans spur channels in usual fbin coding format */
335 .spurChans = {0, 0, 0, 0, 0},
336 /* noiseFloorThreshCh Check if the register is per chain */
337 .noiseFloorThreshCh = {-1, 0, 0},
338 .ob = {3, 3, 3}, /* 3 chain */
339 .db_stage2 = {3, 3, 3}, /* 3 chain */
340 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
341 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
343 .txFrameToDataStart = 0x0e,
344 .txFrameToPaOn = 0x0e,
345 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
347 .switchSettling = 0x2d,
348 .adcDesiredSize = -30,
351 .txFrameToXpaOn = 0xe,
353 .papdRateMaskHt20 = LE32(0x0c80c080),
354 .papdRateMaskHt40 = LE32(0x0080c080),
356 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
362 .xatten1DBLow = {0, 0, 0},
363 .xatten1MarginLow = {0, 0, 0},
364 .xatten1DBHigh = {0, 0, 0},
365 .xatten1MarginHigh = {0, 0, 0}
410 .calTarget_freqbin_5G = {
420 .calTarget_freqbin_5GHT20 = {
430 .calTarget_freqbin_5GHT40 = {
440 .calTargetPower5G = {
442 { {20, 20, 20, 10} },
443 { {20, 20, 20, 10} },
444 { {20, 20, 20, 10} },
445 { {20, 20, 20, 10} },
446 { {20, 20, 20, 10} },
447 { {20, 20, 20, 10} },
448 { {20, 20, 20, 10} },
449 { {20, 20, 20, 10} },
451 .calTargetPower5GHT20 = {
453 * 0_8_16,1-3_9-11_17-19,
454 * 4,5,6,7,12,13,14,15,20,21,22,23
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
465 .calTargetPower5GHT40 = {
467 * 0_8_16,1-3_9-11_17-19,
468 * 4,5,6,7,12,13,14,15,20,21,22,23
470 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
472 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
473 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
474 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
475 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
476 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
477 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
480 0x10, 0x16, 0x18, 0x40, 0x46,
481 0x48, 0x30, 0x36, 0x38
485 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
486 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
487 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
488 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
489 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
490 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
491 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
492 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
495 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
496 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
497 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
498 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
499 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
500 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
501 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
502 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
506 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
507 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
508 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
509 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
510 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
511 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
512 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
513 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
517 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
518 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
519 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
520 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
521 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
522 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
523 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
524 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
528 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
529 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
530 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
531 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
532 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
533 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
534 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
535 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
539 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
540 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
541 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
542 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
543 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
544 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
545 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
546 /* Data[5].ctlEdges[7].bChannel */ 0xFF
550 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
551 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
552 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
553 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
554 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
555 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
556 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
557 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
561 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
562 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
563 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
564 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
565 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
566 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
567 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
568 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
572 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
573 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
574 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
575 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
576 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
577 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
578 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
579 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
585 {60, 1}, {60, 1}, {60, 1}, {60, 1},
586 {60, 1}, {60, 1}, {60, 1}, {60, 0},
591 {60, 1}, {60, 1}, {60, 1}, {60, 1},
592 {60, 1}, {60, 1}, {60, 1}, {60, 0},
597 {60, 0}, {60, 1}, {60, 0}, {60, 1},
598 {60, 1}, {60, 1}, {60, 1}, {60, 1},
603 {60, 0}, {60, 1}, {60, 1}, {60, 0},
604 {60, 1}, {60, 0}, {60, 0}, {60, 0},
609 {60, 1}, {60, 1}, {60, 1}, {60, 0},
610 {60, 0}, {60, 0}, {60, 0}, {60, 0},
615 {60, 1}, {60, 1}, {60, 1}, {60, 1},
616 {60, 1}, {60, 0}, {60, 0}, {60, 0},
621 {60, 1}, {60, 1}, {60, 1}, {60, 1},
622 {60, 1}, {60, 1}, {60, 1}, {60, 1},
627 {60, 1}, {60, 1}, {60, 0}, {60, 1},
628 {60, 1}, {60, 1}, {60, 1}, {60, 0},
633 {60, 1}, {60, 0}, {60, 1}, {60, 1},
634 {60, 1}, {60, 1}, {60, 0}, {60, 1},
640 static const struct ar9300_eeprom ar9300_x113 = {
642 .templateVersion = 6,
643 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
644 .custData = {"x113-023-f0000"},
646 .regDmn = { LE16(0), LE16(0x1f) },
647 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
649 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
653 .blueToothOptions = 0,
655 .deviceType = 5, /* takes lower byte in eeprom location */
656 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
657 .params_for_tuning_caps = {0, 0},
658 .featureEnable = 0x0d,
660 * bit0 - enable tx temp comp - disabled
661 * bit1 - enable tx volt comp - disabled
662 * bit2 - enable fastClock - enabled
663 * bit3 - enable doubling - enabled
664 * bit4 - enable internal regulator - disabled
665 * bit5 - enable pa predistortion - disabled
667 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
668 .eepromWriteEnableGpio = 6,
669 .wlanDisableGpio = 0,
671 .rxBandSelectGpio = 0xff,
676 /* ar9300_modal_eep_header 2g */
677 /* 4 idle,t1,t2,b(4 bits per setting) */
678 .antCtrlCommon = LE32(0x110),
679 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
680 .antCtrlCommon2 = LE32(0x44444),
683 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
684 * rx1, rx12, b (2 bits each)
686 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
689 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
690 * for ar9280 (0xa20c/b20c 5:0)
692 .xatten1DB = {0, 0, 0},
695 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
696 * for ar9280 (0xa20c/b20c 16:12
698 .xatten1Margin = {0, 0, 0},
703 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
704 * channels in usual fbin coding format
706 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
709 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
710 * if the register is per chain
712 .noiseFloorThreshCh = {-1, 0, 0},
713 .ob = {1, 1, 1},/* 3 chain */
714 .db_stage2 = {1, 1, 1}, /* 3 chain */
715 .db_stage3 = {0, 0, 0},
716 .db_stage4 = {0, 0, 0},
718 .txFrameToDataStart = 0x0e,
719 .txFrameToPaOn = 0x0e,
720 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
722 .switchSettling = 0x2c,
723 .adcDesiredSize = -30,
726 .txFrameToXpaOn = 0xe,
728 .papdRateMaskHt20 = LE32(0x0c80c080),
729 .papdRateMaskHt40 = LE32(0x0080c080),
731 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
735 .ant_div_control = 0,
736 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
743 /* ar9300_cal_data_per_freq_op_loop 2g */
745 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
746 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
747 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
749 .calTarget_freqbin_Cck = {
753 .calTarget_freqbin_2G = {
758 .calTarget_freqbin_2GHT20 = {
763 .calTarget_freqbin_2GHT40 = {
768 .calTargetPowerCck = {
769 /* 1L-5L,5S,11L,11S */
770 { {34, 34, 34, 34} },
771 { {34, 34, 34, 34} },
773 .calTargetPower2G = {
775 { {34, 34, 32, 32} },
776 { {34, 34, 32, 32} },
777 { {34, 34, 32, 32} },
779 .calTargetPower2GHT20 = {
780 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
781 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
782 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
784 .calTargetPower2GHT40 = {
785 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
786 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
787 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
790 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
791 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
821 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
822 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
823 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
824 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
828 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
829 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
830 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
835 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
836 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
842 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
843 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
844 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
845 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
849 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
850 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
851 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
855 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
856 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
857 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
862 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
863 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
864 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
869 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
870 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
871 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
872 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
876 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
877 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
878 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
880 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
881 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
882 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
884 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
885 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
886 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
888 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
889 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
890 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
893 /* 4 idle,t1,t2,b (4 bits per setting) */
894 .antCtrlCommon = LE32(0x220),
895 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
896 .antCtrlCommon2 = LE32(0x11111),
897 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
899 LE16(0x150), LE16(0x150), LE16(0x150),
901 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
902 .xatten1DB = {0, 0, 0},
905 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
906 * for merlin (0xa20c/b20c 16:12
908 .xatten1Margin = {0, 0, 0},
911 /* spurChans spur channels in usual fbin coding format */
912 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
913 /* noiseFloorThreshCh Check if the register is per chain */
914 .noiseFloorThreshCh = {-1, 0, 0},
915 .ob = {3, 3, 3}, /* 3 chain */
916 .db_stage2 = {3, 3, 3}, /* 3 chain */
917 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
918 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
920 .txFrameToDataStart = 0x0e,
921 .txFrameToPaOn = 0x0e,
922 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
924 .switchSettling = 0x2d,
925 .adcDesiredSize = -30,
928 .txFrameToXpaOn = 0xe,
930 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
931 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
933 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
938 .tempSlopeHigh = 105,
939 .xatten1DBLow = {0, 0, 0},
940 .xatten1MarginLow = {0, 0, 0},
941 .xatten1DBHigh = {0, 0, 0},
942 .xatten1MarginHigh = {0, 0, 0}
987 .calTarget_freqbin_5G = {
997 .calTarget_freqbin_5GHT20 = {
1007 .calTarget_freqbin_5GHT40 = {
1017 .calTargetPower5G = {
1019 { {42, 40, 40, 34} },
1020 { {42, 40, 40, 34} },
1021 { {42, 40, 40, 34} },
1022 { {42, 40, 40, 34} },
1023 { {42, 40, 40, 34} },
1024 { {42, 40, 40, 34} },
1025 { {42, 40, 40, 34} },
1026 { {42, 40, 40, 34} },
1028 .calTargetPower5GHT20 = {
1030 * 0_8_16,1-3_9-11_17-19,
1031 * 4,5,6,7,12,13,14,15,20,21,22,23
1033 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1034 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1035 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1036 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1037 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1038 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1039 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1040 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1042 .calTargetPower5GHT40 = {
1044 * 0_8_16,1-3_9-11_17-19,
1045 * 4,5,6,7,12,13,14,15,20,21,22,23
1047 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1048 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1049 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1050 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1051 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1052 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1053 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1054 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1057 0x10, 0x16, 0x18, 0x40, 0x46,
1058 0x48, 0x30, 0x36, 0x38
1062 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1063 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1064 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1065 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1066 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1067 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1068 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1069 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1072 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1073 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1074 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1075 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1076 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1077 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1078 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1079 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1083 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1084 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1085 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1086 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1087 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1088 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1089 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1090 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1094 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1095 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1096 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1097 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1098 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1099 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1100 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1101 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1105 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1106 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1107 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1108 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1109 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1110 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1111 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1112 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1116 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1117 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1118 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1119 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1120 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1121 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1122 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1123 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1127 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1128 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1129 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1130 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1131 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1132 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1133 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1134 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1138 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1139 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1140 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1141 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1142 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1143 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1144 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1145 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1149 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1150 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1151 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1152 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1153 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1154 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1155 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1156 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1159 .ctlPowerData_5G = {
1162 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1163 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1168 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1169 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1174 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1175 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1180 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1181 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1186 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1187 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1192 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1193 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1198 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1199 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1204 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1205 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1210 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1211 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1218 static const struct ar9300_eeprom ar9300_h112 = {
1220 .templateVersion = 3,
1221 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1222 .custData = {"h112-241-f0000"},
1224 .regDmn = { LE16(0), LE16(0x1f) },
1225 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1227 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1231 .blueToothOptions = 0,
1233 .deviceType = 5, /* takes lower byte in eeprom location */
1234 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1235 .params_for_tuning_caps = {0, 0},
1236 .featureEnable = 0x0d,
1238 * bit0 - enable tx temp comp - disabled
1239 * bit1 - enable tx volt comp - disabled
1240 * bit2 - enable fastClock - enabled
1241 * bit3 - enable doubling - enabled
1242 * bit4 - enable internal regulator - disabled
1243 * bit5 - enable pa predistortion - disabled
1245 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1246 .eepromWriteEnableGpio = 6,
1247 .wlanDisableGpio = 0,
1249 .rxBandSelectGpio = 0xff,
1254 /* ar9300_modal_eep_header 2g */
1255 /* 4 idle,t1,t2,b(4 bits per setting) */
1256 .antCtrlCommon = LE32(0x110),
1257 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1258 .antCtrlCommon2 = LE32(0x44444),
1261 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1262 * rx1, rx12, b (2 bits each)
1264 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1267 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1268 * for ar9280 (0xa20c/b20c 5:0)
1270 .xatten1DB = {0, 0, 0},
1273 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1274 * for ar9280 (0xa20c/b20c 16:12
1276 .xatten1Margin = {0, 0, 0},
1281 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1282 * channels in usual fbin coding format
1284 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1287 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1288 * if the register is per chain
1290 .noiseFloorThreshCh = {-1, 0, 0},
1291 .ob = {1, 1, 1},/* 3 chain */
1292 .db_stage2 = {1, 1, 1}, /* 3 chain */
1293 .db_stage3 = {0, 0, 0},
1294 .db_stage4 = {0, 0, 0},
1296 .txFrameToDataStart = 0x0e,
1297 .txFrameToPaOn = 0x0e,
1298 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1300 .switchSettling = 0x2c,
1301 .adcDesiredSize = -30,
1304 .txFrameToXpaOn = 0xe,
1306 .papdRateMaskHt20 = LE32(0x80c080),
1307 .papdRateMaskHt40 = LE32(0x80c080),
1309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1313 .ant_div_control = 0,
1314 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1321 /* ar9300_cal_data_per_freq_op_loop 2g */
1323 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1324 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1325 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1327 .calTarget_freqbin_Cck = {
1331 .calTarget_freqbin_2G = {
1336 .calTarget_freqbin_2GHT20 = {
1341 .calTarget_freqbin_2GHT40 = {
1346 .calTargetPowerCck = {
1347 /* 1L-5L,5S,11L,11S */
1348 { {34, 34, 34, 34} },
1349 { {34, 34, 34, 34} },
1351 .calTargetPower2G = {
1353 { {34, 34, 32, 32} },
1354 { {34, 34, 32, 32} },
1355 { {34, 34, 32, 32} },
1357 .calTargetPower2GHT20 = {
1358 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1359 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1360 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1362 .calTargetPower2GHT40 = {
1363 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1364 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1365 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1368 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1369 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1399 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1400 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1401 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1402 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1406 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1413 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1420 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1427 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1428 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1429 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1433 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1434 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1435 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1440 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1441 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1442 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1447 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1448 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1449 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1450 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1453 .ctlPowerData_2G = {
1454 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1455 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1456 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
1458 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
1459 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1460 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1462 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
1463 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1464 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1466 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1467 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1468 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1471 /* 4 idle,t1,t2,b (4 bits per setting) */
1472 .antCtrlCommon = LE32(0x220),
1473 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1474 .antCtrlCommon2 = LE32(0x44444),
1475 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1477 LE16(0x150), LE16(0x150), LE16(0x150),
1479 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1480 .xatten1DB = {0, 0, 0},
1483 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1484 * for merlin (0xa20c/b20c 16:12
1486 .xatten1Margin = {0, 0, 0},
1489 /* spurChans spur channels in usual fbin coding format */
1490 .spurChans = {0, 0, 0, 0, 0},
1491 /* noiseFloorThreshCh Check if the register is per chain */
1492 .noiseFloorThreshCh = {-1, 0, 0},
1493 .ob = {3, 3, 3}, /* 3 chain */
1494 .db_stage2 = {3, 3, 3}, /* 3 chain */
1495 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1496 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1498 .txFrameToDataStart = 0x0e,
1499 .txFrameToPaOn = 0x0e,
1500 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1502 .switchSettling = 0x2d,
1503 .adcDesiredSize = -30,
1506 .txFrameToXpaOn = 0xe,
1508 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1509 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1516 .tempSlopeHigh = 50,
1517 .xatten1DBLow = {0, 0, 0},
1518 .xatten1MarginLow = {0, 0, 0},
1519 .xatten1DBHigh = {0, 0, 0},
1520 .xatten1MarginHigh = {0, 0, 0}
1565 .calTarget_freqbin_5G = {
1575 .calTarget_freqbin_5GHT20 = {
1585 .calTarget_freqbin_5GHT40 = {
1595 .calTargetPower5G = {
1597 { {30, 30, 28, 24} },
1598 { {30, 30, 28, 24} },
1599 { {30, 30, 28, 24} },
1600 { {30, 30, 28, 24} },
1601 { {30, 30, 28, 24} },
1602 { {30, 30, 28, 24} },
1603 { {30, 30, 28, 24} },
1604 { {30, 30, 28, 24} },
1606 .calTargetPower5GHT20 = {
1608 * 0_8_16,1-3_9-11_17-19,
1609 * 4,5,6,7,12,13,14,15,20,21,22,23
1611 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1612 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1613 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1614 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1615 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1616 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1617 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1618 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1620 .calTargetPower5GHT40 = {
1622 * 0_8_16,1-3_9-11_17-19,
1623 * 4,5,6,7,12,13,14,15,20,21,22,23
1625 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1626 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1627 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1628 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1629 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1630 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1631 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1632 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1635 0x10, 0x16, 0x18, 0x40, 0x46,
1636 0x48, 0x30, 0x36, 0x38
1640 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1641 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1642 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1643 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1644 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1645 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1646 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1647 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1650 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1651 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1652 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1653 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1654 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1655 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1656 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1657 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1661 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1662 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1663 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1664 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1665 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1666 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1667 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1668 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1672 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1673 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1674 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1675 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1676 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1677 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1678 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1679 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1683 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1684 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1685 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1686 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1687 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1688 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1689 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1690 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1694 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1695 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1696 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1697 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1698 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1699 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1700 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1701 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1705 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1706 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1707 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1708 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1709 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1710 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1711 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1712 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1716 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1717 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1718 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1719 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1720 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1721 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1722 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1723 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1727 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1728 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1729 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1730 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1731 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1732 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1733 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1734 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1737 .ctlPowerData_5G = {
1740 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1741 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1746 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1747 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1752 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1753 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1758 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1759 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1764 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1765 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1770 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1771 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1776 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1777 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1782 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1783 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1788 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1789 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1796 static const struct ar9300_eeprom ar9300_x112 = {
1798 .templateVersion = 5,
1799 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1800 .custData = {"x112-041-f0000"},
1802 .regDmn = { LE16(0), LE16(0x1f) },
1803 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1805 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1809 .blueToothOptions = 0,
1811 .deviceType = 5, /* takes lower byte in eeprom location */
1812 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1813 .params_for_tuning_caps = {0, 0},
1814 .featureEnable = 0x0d,
1816 * bit0 - enable tx temp comp - disabled
1817 * bit1 - enable tx volt comp - disabled
1818 * bit2 - enable fastclock - enabled
1819 * bit3 - enable doubling - enabled
1820 * bit4 - enable internal regulator - disabled
1821 * bit5 - enable pa predistortion - disabled
1823 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1824 .eepromWriteEnableGpio = 6,
1825 .wlanDisableGpio = 0,
1827 .rxBandSelectGpio = 0xff,
1832 /* ar9300_modal_eep_header 2g */
1833 /* 4 idle,t1,t2,b(4 bits per setting) */
1834 .antCtrlCommon = LE32(0x110),
1835 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1836 .antCtrlCommon2 = LE32(0x22222),
1839 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1840 * rx1, rx12, b (2 bits each)
1842 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1845 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1846 * for ar9280 (0xa20c/b20c 5:0)
1848 .xatten1DB = {0x1b, 0x1b, 0x1b},
1851 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1852 * for ar9280 (0xa20c/b20c 16:12
1854 .xatten1Margin = {0x15, 0x15, 0x15},
1859 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1860 * channels in usual fbin coding format
1862 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1865 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1866 * if the register is per chain
1868 .noiseFloorThreshCh = {-1, 0, 0},
1869 .ob = {1, 1, 1},/* 3 chain */
1870 .db_stage2 = {1, 1, 1}, /* 3 chain */
1871 .db_stage3 = {0, 0, 0},
1872 .db_stage4 = {0, 0, 0},
1874 .txFrameToDataStart = 0x0e,
1875 .txFrameToPaOn = 0x0e,
1876 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1878 .switchSettling = 0x2c,
1879 .adcDesiredSize = -30,
1882 .txFrameToXpaOn = 0xe,
1884 .papdRateMaskHt20 = LE32(0x0c80c080),
1885 .papdRateMaskHt40 = LE32(0x0080c080),
1887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1891 .ant_div_control = 0,
1892 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1899 /* ar9300_cal_data_per_freq_op_loop 2g */
1901 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1902 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1903 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1905 .calTarget_freqbin_Cck = {
1909 .calTarget_freqbin_2G = {
1914 .calTarget_freqbin_2GHT20 = {
1919 .calTarget_freqbin_2GHT40 = {
1924 .calTargetPowerCck = {
1925 /* 1L-5L,5S,11L,11s */
1926 { {38, 38, 38, 38} },
1927 { {38, 38, 38, 38} },
1929 .calTargetPower2G = {
1931 { {38, 38, 36, 34} },
1932 { {38, 38, 36, 34} },
1933 { {38, 38, 34, 32} },
1935 .calTargetPower2GHT20 = {
1936 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1937 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1938 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1940 .calTargetPower2GHT40 = {
1941 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1942 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1943 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1946 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1947 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1977 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1978 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1979 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1980 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1984 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1985 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1986 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1991 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1998 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1999 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2000 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2001 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2005 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2006 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2007 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2011 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2012 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2013 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2018 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2019 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2020 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2025 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2026 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2027 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2028 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2031 .ctlPowerData_2G = {
2032 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2033 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2034 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2036 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2037 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2038 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2040 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2041 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2042 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2044 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2045 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2046 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2049 /* 4 idle,t1,t2,b (4 bits per setting) */
2050 .antCtrlCommon = LE32(0x110),
2051 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2052 .antCtrlCommon2 = LE32(0x22222),
2053 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2055 LE16(0x0), LE16(0x0), LE16(0x0),
2057 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2058 .xatten1DB = {0x13, 0x19, 0x17},
2061 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2062 * for merlin (0xa20c/b20c 16:12
2064 .xatten1Margin = {0x19, 0x19, 0x19},
2067 /* spurChans spur channels in usual fbin coding format */
2068 .spurChans = {0, 0, 0, 0, 0},
2069 /* noiseFloorThreshch check if the register is per chain */
2070 .noiseFloorThreshCh = {-1, 0, 0},
2071 .ob = {3, 3, 3}, /* 3 chain */
2072 .db_stage2 = {3, 3, 3}, /* 3 chain */
2073 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2074 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2076 .txFrameToDataStart = 0x0e,
2077 .txFrameToPaOn = 0x0e,
2078 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2080 .switchSettling = 0x2d,
2081 .adcDesiredSize = -30,
2084 .txFrameToXpaOn = 0xe,
2086 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2087 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2089 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2094 .tempSlopeHigh = 105,
2095 .xatten1DBLow = {0x10, 0x14, 0x10},
2096 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2097 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2098 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2143 .calTarget_freqbin_5G = {
2153 .calTarget_freqbin_5GHT20 = {
2163 .calTarget_freqbin_5GHT40 = {
2173 .calTargetPower5G = {
2175 { {32, 32, 28, 26} },
2176 { {32, 32, 28, 26} },
2177 { {32, 32, 28, 26} },
2178 { {32, 32, 26, 24} },
2179 { {32, 32, 26, 24} },
2180 { {32, 32, 24, 22} },
2181 { {30, 30, 24, 22} },
2182 { {30, 30, 24, 22} },
2184 .calTargetPower5GHT20 = {
2186 * 0_8_16,1-3_9-11_17-19,
2187 * 4,5,6,7,12,13,14,15,20,21,22,23
2189 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2190 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2191 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2192 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2193 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2194 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2195 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2196 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2198 .calTargetPower5GHT40 = {
2200 * 0_8_16,1-3_9-11_17-19,
2201 * 4,5,6,7,12,13,14,15,20,21,22,23
2203 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2204 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2205 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2206 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2207 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2208 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2209 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2210 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2213 0x10, 0x16, 0x18, 0x40, 0x46,
2214 0x48, 0x30, 0x36, 0x38
2218 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2219 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2220 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2221 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2222 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2223 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2224 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2225 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2228 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2231 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2232 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2233 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2234 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2235 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2239 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2241 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2242 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2243 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2244 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2245 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2246 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2250 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2253 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2254 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2256 /* Data[3].ctledges[6].bchannel */ 0xFF,
2257 /* Data[3].ctledges[7].bchannel */ 0xFF,
2261 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2264 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2265 /* Data[4].ctledges[4].bchannel */ 0xFF,
2266 /* Data[4].ctledges[5].bchannel */ 0xFF,
2267 /* Data[4].ctledges[6].bchannel */ 0xFF,
2268 /* Data[4].ctledges[7].bchannel */ 0xFF,
2272 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2274 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2275 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2277 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278 /* Data[5].ctledges[6].bchannel */ 0xFF,
2279 /* Data[5].ctledges[7].bchannel */ 0xFF
2283 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2284 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2285 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2286 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2287 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2288 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2289 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2290 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2294 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2295 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2296 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2297 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2298 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2299 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2300 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2301 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2305 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2306 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2307 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2308 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2309 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2310 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2311 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2312 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2315 .ctlPowerData_5G = {
2318 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2319 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2324 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2325 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2330 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2331 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2336 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2337 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2342 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2343 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2348 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2349 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2354 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2355 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2360 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2361 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2366 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2367 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2373 static const struct ar9300_eeprom ar9300_h116 = {
2375 .templateVersion = 4,
2376 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2377 .custData = {"h116-041-f0000"},
2379 .regDmn = { LE16(0), LE16(0x1f) },
2380 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2382 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
2386 .blueToothOptions = 0,
2388 .deviceType = 5, /* takes lower byte in eeprom location */
2389 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2390 .params_for_tuning_caps = {0, 0},
2391 .featureEnable = 0x0d,
2393 * bit0 - enable tx temp comp - disabled
2394 * bit1 - enable tx volt comp - disabled
2395 * bit2 - enable fastClock - enabled
2396 * bit3 - enable doubling - enabled
2397 * bit4 - enable internal regulator - disabled
2398 * bit5 - enable pa predistortion - disabled
2400 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2401 .eepromWriteEnableGpio = 6,
2402 .wlanDisableGpio = 0,
2404 .rxBandSelectGpio = 0xff,
2409 /* ar9300_modal_eep_header 2g */
2410 /* 4 idle,t1,t2,b(4 bits per setting) */
2411 .antCtrlCommon = LE32(0x110),
2412 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2413 .antCtrlCommon2 = LE32(0x44444),
2416 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2417 * rx1, rx12, b (2 bits each)
2419 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2422 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2423 * for ar9280 (0xa20c/b20c 5:0)
2425 .xatten1DB = {0x1f, 0x1f, 0x1f},
2428 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2429 * for ar9280 (0xa20c/b20c 16:12
2431 .xatten1Margin = {0x12, 0x12, 0x12},
2436 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2437 * channels in usual fbin coding format
2439 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2442 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2443 * if the register is per chain
2445 .noiseFloorThreshCh = {-1, 0, 0},
2446 .ob = {1, 1, 1},/* 3 chain */
2447 .db_stage2 = {1, 1, 1}, /* 3 chain */
2448 .db_stage3 = {0, 0, 0},
2449 .db_stage4 = {0, 0, 0},
2451 .txFrameToDataStart = 0x0e,
2452 .txFrameToPaOn = 0x0e,
2453 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2455 .switchSettling = 0x2c,
2456 .adcDesiredSize = -30,
2459 .txFrameToXpaOn = 0xe,
2461 .papdRateMaskHt20 = LE32(0x0c80C080),
2462 .papdRateMaskHt40 = LE32(0x0080C080),
2464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468 .ant_div_control = 0,
2469 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2476 /* ar9300_cal_data_per_freq_op_loop 2g */
2478 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2479 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2480 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2482 .calTarget_freqbin_Cck = {
2486 .calTarget_freqbin_2G = {
2491 .calTarget_freqbin_2GHT20 = {
2496 .calTarget_freqbin_2GHT40 = {
2501 .calTargetPowerCck = {
2502 /* 1L-5L,5S,11L,11S */
2503 { {34, 34, 34, 34} },
2504 { {34, 34, 34, 34} },
2506 .calTargetPower2G = {
2508 { {34, 34, 32, 32} },
2509 { {34, 34, 32, 32} },
2510 { {34, 34, 32, 32} },
2512 .calTargetPower2GHT20 = {
2513 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2514 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2515 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2517 .calTargetPower2GHT40 = {
2518 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2519 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2520 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2523 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2524 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2554 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2555 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2556 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2557 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2561 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2568 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2575 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2576 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2577 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2578 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2582 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2583 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2584 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2588 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2589 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2590 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2595 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2596 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2597 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2602 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2603 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2604 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2605 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2608 .ctlPowerData_2G = {
2609 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2610 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2611 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2613 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2614 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2615 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2617 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2618 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2619 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2621 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2622 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2623 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2626 /* 4 idle,t1,t2,b (4 bits per setting) */
2627 .antCtrlCommon = LE32(0x220),
2628 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2629 .antCtrlCommon2 = LE32(0x44444),
2630 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2632 LE16(0x150), LE16(0x150), LE16(0x150),
2634 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2635 .xatten1DB = {0x19, 0x19, 0x19},
2638 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2639 * for merlin (0xa20c/b20c 16:12
2641 .xatten1Margin = {0x14, 0x14, 0x14},
2644 /* spurChans spur channels in usual fbin coding format */
2645 .spurChans = {0, 0, 0, 0, 0},
2646 /* noiseFloorThreshCh Check if the register is per chain */
2647 .noiseFloorThreshCh = {-1, 0, 0},
2648 .ob = {3, 3, 3}, /* 3 chain */
2649 .db_stage2 = {3, 3, 3}, /* 3 chain */
2650 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2651 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2653 .txFrameToDataStart = 0x0e,
2654 .txFrameToPaOn = 0x0e,
2655 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2657 .switchSettling = 0x2d,
2658 .adcDesiredSize = -30,
2661 .txFrameToXpaOn = 0xe,
2663 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2664 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2671 .tempSlopeHigh = 50,
2672 .xatten1DBLow = {0, 0, 0},
2673 .xatten1MarginLow = {0, 0, 0},
2674 .xatten1DBHigh = {0, 0, 0},
2675 .xatten1MarginHigh = {0, 0, 0}
2720 .calTarget_freqbin_5G = {
2730 .calTarget_freqbin_5GHT20 = {
2740 .calTarget_freqbin_5GHT40 = {
2750 .calTargetPower5G = {
2752 { {30, 30, 28, 24} },
2753 { {30, 30, 28, 24} },
2754 { {30, 30, 28, 24} },
2755 { {30, 30, 28, 24} },
2756 { {30, 30, 28, 24} },
2757 { {30, 30, 28, 24} },
2758 { {30, 30, 28, 24} },
2759 { {30, 30, 28, 24} },
2761 .calTargetPower5GHT20 = {
2763 * 0_8_16,1-3_9-11_17-19,
2764 * 4,5,6,7,12,13,14,15,20,21,22,23
2766 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2767 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2768 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2769 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2770 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2771 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2772 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2773 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2775 .calTargetPower5GHT40 = {
2777 * 0_8_16,1-3_9-11_17-19,
2778 * 4,5,6,7,12,13,14,15,20,21,22,23
2780 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2781 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2782 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2783 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2784 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2785 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2786 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2787 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2790 0x10, 0x16, 0x18, 0x40, 0x46,
2791 0x48, 0x30, 0x36, 0x38
2795 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2796 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2797 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2798 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2799 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2800 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2801 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2802 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2805 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2806 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2807 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2808 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2809 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2810 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2811 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2812 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2816 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2817 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2818 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2819 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2820 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2821 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2822 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2823 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2827 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2828 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2829 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2830 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2831 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2832 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2833 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2834 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2838 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2839 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2840 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2841 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2842 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2843 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2844 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2845 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2849 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2850 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2851 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2852 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2853 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2854 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2855 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2856 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2860 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2861 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2862 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2863 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2864 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2865 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2866 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2867 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2871 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2872 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2873 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2874 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2875 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2876 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2877 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2878 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2882 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2883 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2884 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2885 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2886 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2887 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2888 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2889 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2892 .ctlPowerData_5G = {
2895 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2896 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2901 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2902 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2907 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2908 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2913 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2914 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2919 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2920 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2925 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2926 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2931 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2932 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2937 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2938 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2943 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2944 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2951 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2959 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2961 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2964 for (it = 0; it < N_LOOP; it++)
2965 if (ar9300_eep_templates[it]->templateVersion == id)
2966 return ar9300_eep_templates[it];
2972 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2974 if (fbin == AR9300_BCHAN_UNUSED)
2977 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2980 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2985 static int interpolate(int x, int xa, int xb, int ya, int yb)
2987 int bf, factor, plus;
2989 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2992 return ya + factor + plus;
2995 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2996 enum eeprom_param param)
2998 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2999 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3003 return eep->macAddr[0] << 8 | eep->macAddr[1];
3005 return eep->macAddr[2] << 8 | eep->macAddr[3];
3007 return eep->macAddr[4] << 8 | eep->macAddr[5];
3009 return le16_to_cpu(pBase->regDmn[0]);
3011 return le16_to_cpu(pBase->regDmn[1]);
3013 return pBase->deviceCap;
3015 return pBase->opCapFlags.opFlags;
3017 return pBase->rfSilent;
3019 return (pBase->txrxMask >> 4) & 0xf;
3021 return pBase->txrxMask & 0xf;
3022 case EEP_DRIVE_STRENGTH:
3023 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3024 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3025 case EEP_INTERNAL_REGULATOR:
3026 /* Bit 4 is internal regulator flag */
3027 return (pBase->featureEnable & 0x10) >> 4;
3029 return le32_to_cpu(pBase->swreg);
3031 return !!(pBase->featureEnable & BIT(5));
3032 case EEP_CHAIN_MASK_REDUCE:
3033 return (pBase->miscConfiguration >> 0x3) & 0x1;
3039 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3044 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3047 *buffer = (val >> (8 * (address % 2))) & 0xff;
3051 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3056 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3059 buffer[0] = val >> 8;
3060 buffer[1] = val & 0xff;
3065 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3068 struct ath_common *common = ath9k_hw_common(ah);
3071 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3072 ath_print(common, ATH_DBG_EEPROM,
3073 "eeprom address not in range\n");
3078 * Since we're reading the bytes in reverse order from a little-endian
3079 * word stream, an even address means we only use the lower half of
3080 * the 16-bit word at that address
3082 if (address % 2 == 0) {
3083 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3089 for (i = 0; i < count / 2; i++) {
3090 if (!ar9300_eeprom_read_word(common, address, buffer))
3098 if (!ar9300_eeprom_read_byte(common, address, buffer))
3104 ath_print(common, ATH_DBG_EEPROM,
3105 "unable to read eeprom region at offset %d\n", address);
3109 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3111 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3113 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3114 AR9300_OTP_STATUS_VALID, 1000))
3117 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3121 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3127 for (i = 0; i < count; i++) {
3128 int offset = 8 * ((address - i) % 4);
3129 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3132 buffer[i] = (data >> offset) & 0xff;
3139 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3140 int *length, int *major, int *minor)
3142 unsigned long value[4];
3148 *code = ((value[0] >> 5) & 0x0007);
3149 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3150 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3151 *major = (value[2] & 0x000f);
3152 *minor = (value[3] & 0x00ff);
3155 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3157 int it, checksum = 0;
3159 for (it = 0; it < dsize; it++) {
3160 checksum += data[it];
3167 static bool ar9300_uncompress_block(struct ath_hw *ah,
3177 struct ath_common *common = ath9k_hw_common(ah);
3181 for (it = 0; it < size; it += (length+2)) {
3185 length = block[it+1];
3188 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3189 ath_print(common, ATH_DBG_EEPROM,
3190 "Restore at %d: spot=%d "
3191 "offset=%d length=%d\n",
3192 it, spot, offset, length);
3193 memcpy(&mptr[spot], &block[it+2], length);
3195 } else if (length > 0) {
3196 ath_print(common, ATH_DBG_EEPROM,
3197 "Bad restore at %d: spot=%d "
3198 "offset=%d length=%d\n",
3199 it, spot, offset, length);
3206 static int ar9300_compress_decision(struct ath_hw *ah,
3211 u8 *word, int length, int mdata_size)
3213 struct ath_common *common = ath9k_hw_common(ah);
3215 const struct ar9300_eeprom *eep = NULL;
3219 if (length != mdata_size) {
3220 ath_print(common, ATH_DBG_EEPROM,
3221 "EEPROM structure size mismatch"
3222 "memory=%d eeprom=%d\n", mdata_size, length);
3225 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3226 ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
3227 " uncompressed, length %d\n", it, length);
3229 case _CompressBlock:
3230 if (reference == 0) {
3233 eep = ar9003_eeprom_struct_find_by_id(reference);
3235 ath_print(common, ATH_DBG_EEPROM,
3236 "cant find reference eeprom"
3237 "struct %d\n", reference);
3240 memcpy(mptr, eep, mdata_size);
3242 ath_print(common, ATH_DBG_EEPROM,
3243 "restore eeprom %d: block, reference %d,"
3244 " length %d\n", it, reference, length);
3245 ar9300_uncompress_block(ah, mptr, mdata_size,
3246 (u8 *) (word + COMP_HDR_LEN), length);
3249 ath_print(common, ATH_DBG_EEPROM, "unknown compression"
3250 " code %d\n", code);
3256 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3259 static bool ar9300_check_header(void *data)
3262 return !(*word == 0 || *word == ~0);
3265 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3270 if (!read(ah, base_addr, header, 4))
3273 return ar9300_check_header(header);
3276 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3279 struct ath_common *common = ath9k_hw_common(ah);
3280 u16 *data = (u16 *) mptr;
3283 for (i = 0; i < mdata_size / 2; i++, data++)
3284 ath9k_hw_nvram_read(common, i, data);
3289 * Read the configuration data from the eeprom.
3290 * The data can be put in any specified memory buffer.
3292 * Returns -1 on error.
3293 * Returns address of next memory location on success.
3295 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3296 u8 *mptr, int mdata_size)
3303 int reference, length, major, minor;
3306 u16 checksum, mchecksum;
3307 struct ath_common *common = ath9k_hw_common(ah);
3308 eeprom_read_op read;
3310 if (ath9k_hw_use_flash(ah))
3311 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3313 word = kzalloc(2048, GFP_KERNEL);
3317 memcpy(mptr, &ar9300_default, mdata_size);
3319 read = ar9300_read_eeprom;
3320 cptr = AR9300_BASE_ADDR;
3321 ath_print(common, ATH_DBG_EEPROM,
3322 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3323 if (ar9300_check_eeprom_header(ah, read, cptr))
3326 cptr = AR9300_BASE_ADDR_512;
3327 ath_print(common, ATH_DBG_EEPROM,
3328 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3329 if (ar9300_check_eeprom_header(ah, read, cptr))
3332 read = ar9300_read_otp;
3333 cptr = AR9300_BASE_ADDR;
3334 ath_print(common, ATH_DBG_EEPROM,
3335 "Trying OTP accesss at Address 0x%04x\n", cptr);
3336 if (ar9300_check_eeprom_header(ah, read, cptr))
3339 cptr = AR9300_BASE_ADDR_512;
3340 ath_print(common, ATH_DBG_EEPROM,
3341 "Trying OTP accesss at Address 0x%04x\n", cptr);
3342 if (ar9300_check_eeprom_header(ah, read, cptr))
3348 ath_print(common, ATH_DBG_EEPROM, "Found valid EEPROM data");
3350 for (it = 0; it < MSTATE; it++) {
3351 if (!read(ah, cptr, word, COMP_HDR_LEN))
3354 if (!ar9300_check_header(word))
3357 ar9300_comp_hdr_unpack(word, &code, &reference,
3358 &length, &major, &minor);
3359 ath_print(common, ATH_DBG_EEPROM,
3360 "Found block at %x: code=%d ref=%d"
3361 "length=%d major=%d minor=%d\n", cptr, code,
3362 reference, length, major, minor);
3363 if (length >= 1024) {
3364 ath_print(common, ATH_DBG_EEPROM,
3365 "Skipping bad header\n");
3366 cptr -= COMP_HDR_LEN;
3371 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3372 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3373 mchecksum = word[COMP_HDR_LEN + osize] |
3374 (word[COMP_HDR_LEN + osize + 1] << 8);
3375 ath_print(common, ATH_DBG_EEPROM,
3376 "checksum %x %x\n", checksum, mchecksum);
3377 if (checksum == mchecksum) {
3378 ar9300_compress_decision(ah, it, code, reference, mptr,
3379 word, length, mdata_size);
3381 ath_print(common, ATH_DBG_EEPROM,
3382 "skipping block with bad checksum\n");
3384 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3396 * Restore the configuration structure by reading the eeprom.
3397 * This function destroys any existing in-memory structure
3400 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3402 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3404 if (ar9300_eeprom_restore_internal(ah, mptr,
3405 sizeof(struct ar9300_eeprom)) < 0)
3411 /* XXX: review hardware docs */
3412 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3414 return ah->eeprom.ar9300_eep.eepromVersion;
3417 /* XXX: could be read from the eepromVersion, not sure yet */
3418 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3423 static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
3424 enum ath9k_hal_freq_band freq_band)
3429 static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
3430 struct ath9k_channel *chan)
3435 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3437 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3440 return eep->modalHeader2G.xpaBiasLvl;
3442 return eep->modalHeader5G.xpaBiasLvl;
3445 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3447 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3448 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3449 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
3450 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
3453 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3455 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3459 val = eep->modalHeader2G.antCtrlCommon;
3461 val = eep->modalHeader5G.antCtrlCommon;
3462 return le32_to_cpu(val);
3465 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3467 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3471 val = eep->modalHeader2G.antCtrlCommon2;
3473 val = eep->modalHeader5G.antCtrlCommon2;
3474 return le32_to_cpu(val);
3477 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3481 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3484 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3486 val = eep->modalHeader2G.antCtrlChain[chain];
3488 val = eep->modalHeader5G.antCtrlChain[chain];
3491 return le16_to_cpu(val);
3494 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3496 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3497 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3499 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3500 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3502 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3503 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3505 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3506 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
3508 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3509 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
3512 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3517 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3519 if (!drive_strength)
3522 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3530 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3532 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3543 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3545 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3550 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3553 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3554 struct ath9k_channel *chan)
3558 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3560 if (chain >= 0 && chain < 3) {
3561 if (IS_CHAN_2GHZ(chan))
3562 return eep->modalHeader2G.xatten1DB[chain];
3563 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3564 t[0] = eep->base_ext2.xatten1DBLow[chain];
3566 t[1] = eep->modalHeader5G.xatten1DB[chain];
3568 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3570 value = ar9003_hw_power_interpolate((s32) chan->channel,
3574 return eep->modalHeader5G.xatten1DB[chain];
3581 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3582 struct ath9k_channel *chan)
3586 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3588 if (chain >= 0 && chain < 3) {
3589 if (IS_CHAN_2GHZ(chan))
3590 return eep->modalHeader2G.xatten1Margin[chain];
3591 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3592 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3594 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3596 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3598 value = ar9003_hw_power_interpolate((s32) chan->channel,
3602 return eep->modalHeader5G.xatten1Margin[chain];
3608 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3612 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3613 AR_PHY_EXT_ATTEN_CTL_1,
3614 AR_PHY_EXT_ATTEN_CTL_2,
3617 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3618 for (i = 0; i < 3; i++) {
3619 value = ar9003_hw_atten_chain_get(ah, i, chan);
3620 REG_RMW_FIELD(ah, ext_atten_reg[i],
3621 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3623 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3624 REG_RMW_FIELD(ah, ext_atten_reg[i],
3625 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
3629 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3631 int internal_regulator =
3632 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3634 if (internal_regulator) {
3635 /* Internal regulator is ON. Write swreg register. */
3636 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3637 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3638 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3639 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3640 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3641 /* Set REG_CONTROL1.SWREG_PROGRAM */
3642 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3644 AR_RTC_REG_CONTROL1) |
3645 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3647 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3650 AR_RTC_FORCE_SWREG_PRD));
3654 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3655 struct ath9k_channel *chan)
3657 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3658 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3659 ar9003_hw_drive_strength_apply(ah);
3660 ar9003_hw_atten_apply(ah, chan);
3661 ar9003_hw_internal_regulator_apply(ah);
3664 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3665 struct ath9k_channel *chan)
3670 * Returns the interpolated y value corresponding to the specified x value
3671 * from the np ordered pairs of data (px,py).
3672 * The pairs do not have to be in any order.
3673 * If the specified x value is less than any of the px,
3674 * the returned y value is equal to the py for the lowest px.
3675 * If the specified x value is greater than any of the px,
3676 * the returned y value is equal to the py for the highest px.
3678 static int ar9003_hw_power_interpolate(int32_t x,
3679 int32_t *px, int32_t *py, u_int16_t np)
3682 int lx = 0, ly = 0, lhave = 0;
3683 int hx = 0, hy = 0, hhave = 0;
3690 /* identify best lower and higher x calibration measurement */
3691 for (ip = 0; ip < np; ip++) {
3694 /* this measurement is higher than our desired x */
3696 if (!hhave || dx > (x - hx)) {
3697 /* new best higher x measurement */
3703 /* this measurement is lower than our desired x */
3705 if (!lhave || dx < (x - lx)) {
3706 /* new best lower x measurement */
3714 /* the low x is good */
3716 /* so is the high x */
3718 /* they're the same, so just pick one */
3721 else /* interpolate */
3722 y = interpolate(x, lx, hx, ly, hy);
3723 } else /* only low is good, use it */
3725 } else if (hhave) /* only high is good, use it */
3727 else /* nothing is good,this should never happen unless np=0, ???? */
3732 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3733 u16 rateIndex, u16 freq, bool is2GHz)
3736 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3737 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3738 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3739 struct cal_tgt_pow_legacy *pEepromTargetPwr;
3743 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3744 pEepromTargetPwr = eep->calTargetPower2G;
3745 pFreqBin = eep->calTarget_freqbin_2G;
3747 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3748 pEepromTargetPwr = eep->calTargetPower5G;
3749 pFreqBin = eep->calTarget_freqbin_5G;
3753 * create array of channels and targetpower from
3754 * targetpower piers stored on eeprom
3756 for (i = 0; i < numPiers; i++) {
3757 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3758 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3761 /* interpolate to get target power for given frequency */
3762 return (u8) ar9003_hw_power_interpolate((s32) freq,
3764 targetPowerArray, numPiers);
3767 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3769 u16 freq, bool is2GHz)
3772 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3773 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3774 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3775 struct cal_tgt_pow_ht *pEepromTargetPwr;
3779 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3780 pEepromTargetPwr = eep->calTargetPower2GHT20;
3781 pFreqBin = eep->calTarget_freqbin_2GHT20;
3783 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3784 pEepromTargetPwr = eep->calTargetPower5GHT20;
3785 pFreqBin = eep->calTarget_freqbin_5GHT20;
3789 * create array of channels and targetpower
3790 * from targetpower piers stored on eeprom
3792 for (i = 0; i < numPiers; i++) {
3793 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3794 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3797 /* interpolate to get target power for given frequency */
3798 return (u8) ar9003_hw_power_interpolate((s32) freq,
3800 targetPowerArray, numPiers);
3803 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3805 u16 freq, bool is2GHz)
3808 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3809 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3810 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3811 struct cal_tgt_pow_ht *pEepromTargetPwr;
3815 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3816 pEepromTargetPwr = eep->calTargetPower2GHT40;
3817 pFreqBin = eep->calTarget_freqbin_2GHT40;
3819 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3820 pEepromTargetPwr = eep->calTargetPower5GHT40;
3821 pFreqBin = eep->calTarget_freqbin_5GHT40;
3825 * create array of channels and targetpower from
3826 * targetpower piers stored on eeprom
3828 for (i = 0; i < numPiers; i++) {
3829 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3830 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3833 /* interpolate to get target power for given frequency */
3834 return (u8) ar9003_hw_power_interpolate((s32) freq,
3836 targetPowerArray, numPiers);
3839 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3840 u16 rateIndex, u16 freq)
3842 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3843 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3844 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3845 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3846 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3847 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3850 * create array of channels and targetpower from
3851 * targetpower piers stored on eeprom
3853 for (i = 0; i < numPiers; i++) {
3854 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3855 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3858 /* interpolate to get target power for given frequency */
3859 return (u8) ar9003_hw_power_interpolate((s32) freq,
3861 targetPowerArray, numPiers);
3864 /* Set tx power registers to array of values passed in */
3865 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
3867 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
3868 /* make sure forced gain is not set */
3869 REG_WRITE(ah, 0xa458, 0);
3871 /* Write the OFDM power per rate set */
3873 /* 6 (LSB), 9, 12, 18 (MSB) */
3874 REG_WRITE(ah, 0xa3c0,
3875 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
3876 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
3877 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
3878 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3880 /* 24 (LSB), 36, 48, 54 (MSB) */
3881 REG_WRITE(ah, 0xa3c4,
3882 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
3883 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
3884 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
3885 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3887 /* Write the CCK power per rate set */
3889 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3890 REG_WRITE(ah, 0xa3c8,
3891 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
3892 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
3893 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
3894 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
3896 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3897 REG_WRITE(ah, 0xa3cc,
3898 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
3899 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
3900 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
3901 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
3904 /* Write the HT20 power per rate set */
3906 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3907 REG_WRITE(ah, 0xa3d0,
3908 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
3909 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
3910 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
3911 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
3914 /* 6 (LSB), 7, 12, 13 (MSB) */
3915 REG_WRITE(ah, 0xa3d4,
3916 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
3917 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
3918 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
3919 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
3922 /* 14 (LSB), 15, 20, 21 */
3923 REG_WRITE(ah, 0xa3e4,
3924 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
3925 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
3926 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
3927 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
3930 /* Mixed HT20 and HT40 rates */
3932 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3933 REG_WRITE(ah, 0xa3e8,
3934 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
3935 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
3936 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
3937 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
3941 * Write the HT40 power per rate set
3942 * correct PAR difference between HT40 and HT20/LEGACY
3943 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
3945 REG_WRITE(ah, 0xa3d8,
3946 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
3947 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
3948 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
3949 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
3952 /* 6 (LSB), 7, 12, 13 (MSB) */
3953 REG_WRITE(ah, 0xa3dc,
3954 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
3955 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
3956 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
3957 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
3960 /* 14 (LSB), 15, 20, 21 */
3961 REG_WRITE(ah, 0xa3ec,
3962 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
3963 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
3964 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
3965 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
3972 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
3973 u8 *targetPowerValT2)
3975 /* XXX: hard code for now, need to get from eeprom struct */
3976 u8 ht40PowerIncForPdadc = 0;
3977 bool is2GHz = false;
3979 struct ath_common *common = ath9k_hw_common(ah);
3984 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
3985 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
3987 targetPowerValT2[ALL_TARGET_LEGACY_36] =
3988 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
3990 targetPowerValT2[ALL_TARGET_LEGACY_48] =
3991 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
3993 targetPowerValT2[ALL_TARGET_LEGACY_54] =
3994 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
3996 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
3997 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
3999 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4000 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4001 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4002 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4003 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4004 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4005 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4006 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4008 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4009 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4011 targetPowerValT2[ALL_TARGET_HT20_4] =
4012 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4014 targetPowerValT2[ALL_TARGET_HT20_5] =
4015 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4017 targetPowerValT2[ALL_TARGET_HT20_6] =
4018 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4020 targetPowerValT2[ALL_TARGET_HT20_7] =
4021 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4023 targetPowerValT2[ALL_TARGET_HT20_12] =
4024 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4026 targetPowerValT2[ALL_TARGET_HT20_13] =
4027 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4029 targetPowerValT2[ALL_TARGET_HT20_14] =
4030 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4032 targetPowerValT2[ALL_TARGET_HT20_15] =
4033 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4035 targetPowerValT2[ALL_TARGET_HT20_20] =
4036 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4038 targetPowerValT2[ALL_TARGET_HT20_21] =
4039 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4041 targetPowerValT2[ALL_TARGET_HT20_22] =
4042 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4044 targetPowerValT2[ALL_TARGET_HT20_23] =
4045 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4047 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4048 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4049 is2GHz) + ht40PowerIncForPdadc;
4050 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4051 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4053 is2GHz) + ht40PowerIncForPdadc;
4054 targetPowerValT2[ALL_TARGET_HT40_4] =
4055 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4056 is2GHz) + ht40PowerIncForPdadc;
4057 targetPowerValT2[ALL_TARGET_HT40_5] =
4058 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4059 is2GHz) + ht40PowerIncForPdadc;
4060 targetPowerValT2[ALL_TARGET_HT40_6] =
4061 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4062 is2GHz) + ht40PowerIncForPdadc;
4063 targetPowerValT2[ALL_TARGET_HT40_7] =
4064 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4065 is2GHz) + ht40PowerIncForPdadc;
4066 targetPowerValT2[ALL_TARGET_HT40_12] =
4067 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4068 is2GHz) + ht40PowerIncForPdadc;
4069 targetPowerValT2[ALL_TARGET_HT40_13] =
4070 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4071 is2GHz) + ht40PowerIncForPdadc;
4072 targetPowerValT2[ALL_TARGET_HT40_14] =
4073 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4074 is2GHz) + ht40PowerIncForPdadc;
4075 targetPowerValT2[ALL_TARGET_HT40_15] =
4076 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4077 is2GHz) + ht40PowerIncForPdadc;
4078 targetPowerValT2[ALL_TARGET_HT40_20] =
4079 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4080 is2GHz) + ht40PowerIncForPdadc;
4081 targetPowerValT2[ALL_TARGET_HT40_21] =
4082 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4083 is2GHz) + ht40PowerIncForPdadc;
4084 targetPowerValT2[ALL_TARGET_HT40_22] =
4085 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4086 is2GHz) + ht40PowerIncForPdadc;
4087 targetPowerValT2[ALL_TARGET_HT40_23] =
4088 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4089 is2GHz) + ht40PowerIncForPdadc;
4091 while (i < ar9300RateSize) {
4092 ath_print(common, ATH_DBG_EEPROM,
4093 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4096 ath_print(common, ATH_DBG_EEPROM,
4097 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4100 ath_print(common, ATH_DBG_EEPROM,
4101 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4104 ath_print(common, ATH_DBG_EEPROM,
4105 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4110 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4116 int *ptemperature, int *pvoltage)
4119 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4121 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4122 struct ath_common *common = ath9k_hw_common(ah);
4124 if (ichain >= AR9300_MAX_CHAINS) {
4125 ath_print(common, ATH_DBG_EEPROM,
4126 "Invalid chain index, must be less than %d\n",
4131 if (mode) { /* 5GHz */
4132 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4133 ath_print(common, ATH_DBG_EEPROM,
4134 "Invalid 5GHz cal pier index, must "
4135 "be less than %d\n",
4136 AR9300_NUM_5G_CAL_PIERS);
4139 pCalPier = &(eep->calFreqPier5G[ipier]);
4140 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4143 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4144 ath_print(common, ATH_DBG_EEPROM,
4145 "Invalid 2GHz cal pier index, must "
4146 "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
4150 pCalPier = &(eep->calFreqPier2G[ipier]);
4151 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4155 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4156 *pcorrection = pCalPierStruct->refPower;
4157 *ptemperature = pCalPierStruct->tempMeas;
4158 *pvoltage = pCalPierStruct->voltMeas;
4163 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4166 int *voltage, int *temperature)
4169 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4172 REG_RMW(ah, AR_PHY_TPC_11_B0,
4173 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4174 AR_PHY_TPC_OLPC_GAIN_DELTA);
4175 REG_RMW(ah, AR_PHY_TPC_11_B1,
4176 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4177 AR_PHY_TPC_OLPC_GAIN_DELTA);
4178 REG_RMW(ah, AR_PHY_TPC_11_B2,
4179 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4180 AR_PHY_TPC_OLPC_GAIN_DELTA);
4182 /* enable open loop power control on chip */
4183 REG_RMW(ah, AR_PHY_TPC_6_B0,
4184 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4185 AR_PHY_TPC_6_ERROR_EST_MODE);
4186 REG_RMW(ah, AR_PHY_TPC_6_B1,
4187 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4188 AR_PHY_TPC_6_ERROR_EST_MODE);
4189 REG_RMW(ah, AR_PHY_TPC_6_B2,
4190 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4191 AR_PHY_TPC_6_ERROR_EST_MODE);
4194 * enable temperature compensation
4195 * Need to use register names
4197 if (frequency < 4000)
4198 tempSlope = eep->modalHeader2G.tempSlope;
4199 else if (eep->base_ext2.tempSlopeLow != 0) {
4200 t[0] = eep->base_ext2.tempSlopeLow;
4202 t[1] = eep->modalHeader5G.tempSlope;
4204 t[2] = eep->base_ext2.tempSlopeHigh;
4206 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4209 tempSlope = eep->modalHeader5G.tempSlope;
4211 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4212 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4218 /* Apply the recorded correction values. */
4219 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4221 int ichain, ipier, npier;
4223 int lfrequency[AR9300_MAX_CHAINS],
4224 lcorrection[AR9300_MAX_CHAINS],
4225 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4226 int hfrequency[AR9300_MAX_CHAINS],
4227 hcorrection[AR9300_MAX_CHAINS],
4228 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4230 int correction[AR9300_MAX_CHAINS],
4231 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4232 int pfrequency, pcorrection, ptemperature, pvoltage;
4233 struct ath_common *common = ath9k_hw_common(ah);
4235 mode = (frequency >= 4000);
4237 npier = AR9300_NUM_5G_CAL_PIERS;
4239 npier = AR9300_NUM_2G_CAL_PIERS;
4241 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4242 lfrequency[ichain] = 0;
4243 hfrequency[ichain] = 100000;
4245 /* identify best lower and higher frequency calibration measurement */
4246 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4247 for (ipier = 0; ipier < npier; ipier++) {
4248 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4249 &pfrequency, &pcorrection,
4250 &ptemperature, &pvoltage)) {
4251 fdiff = frequency - pfrequency;
4254 * this measurement is higher than
4255 * our desired frequency
4258 if (hfrequency[ichain] <= 0 ||
4259 hfrequency[ichain] >= 100000 ||
4261 (frequency - hfrequency[ichain])) {
4264 * frequency measurement
4266 hfrequency[ichain] = pfrequency;
4267 hcorrection[ichain] =
4269 htemperature[ichain] =
4271 hvoltage[ichain] = pvoltage;
4275 if (lfrequency[ichain] <= 0
4277 (frequency - lfrequency[ichain])) {
4280 * frequency measurement
4282 lfrequency[ichain] = pfrequency;
4283 lcorrection[ichain] =
4285 ltemperature[ichain] =
4287 lvoltage[ichain] = pvoltage;
4295 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4296 ath_print(common, ATH_DBG_EEPROM,
4297 "ch=%d f=%d low=%d %d h=%d %d\n",
4298 ichain, frequency, lfrequency[ichain],
4299 lcorrection[ichain], hfrequency[ichain],
4300 hcorrection[ichain]);
4301 /* they're the same, so just pick one */
4302 if (hfrequency[ichain] == lfrequency[ichain]) {
4303 correction[ichain] = lcorrection[ichain];
4304 voltage[ichain] = lvoltage[ichain];
4305 temperature[ichain] = ltemperature[ichain];
4307 /* the low frequency is good */
4308 else if (frequency - lfrequency[ichain] < 1000) {
4309 /* so is the high frequency, interpolate */
4310 if (hfrequency[ichain] - frequency < 1000) {
4312 correction[ichain] = interpolate(frequency,
4315 lcorrection[ichain],
4316 hcorrection[ichain]);
4318 temperature[ichain] = interpolate(frequency,
4321 ltemperature[ichain],
4322 htemperature[ichain]);
4324 voltage[ichain] = interpolate(frequency,
4330 /* only low is good, use it */
4332 correction[ichain] = lcorrection[ichain];
4333 temperature[ichain] = ltemperature[ichain];
4334 voltage[ichain] = lvoltage[ichain];
4337 /* only high is good, use it */
4338 else if (hfrequency[ichain] - frequency < 1000) {
4339 correction[ichain] = hcorrection[ichain];
4340 temperature[ichain] = htemperature[ichain];
4341 voltage[ichain] = hvoltage[ichain];
4342 } else { /* nothing is good, presume 0???? */
4343 correction[ichain] = 0;
4344 temperature[ichain] = 0;
4345 voltage[ichain] = 0;
4349 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4352 ath_print(common, ATH_DBG_EEPROM,
4353 "for frequency=%d, calibration correction = %d %d %d\n",
4354 frequency, correction[0], correction[1], correction[2]);
4359 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4364 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4365 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4368 return ctl_2g[idx].ctlEdges[edge].tPower;
4370 return ctl_5g[idx].ctlEdges[edge].tPower;
4373 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4379 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4380 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4382 u8 *ctl_freqbin = is2GHz ?
4383 &eep->ctl_freqbin_2G[idx][0] :
4384 &eep->ctl_freqbin_5G[idx][0];
4387 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4388 ctl_2g[idx].ctlEdges[edge - 1].flag)
4389 return ctl_2g[idx].ctlEdges[edge - 1].tPower;
4391 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4392 ctl_5g[idx].ctlEdges[edge - 1].flag)
4393 return ctl_5g[idx].ctlEdges[edge - 1].tPower;
4396 return AR9300_MAX_RATE_POWER;
4400 * Find the maximum conformance test limit for the given channel and CTL info
4402 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4403 u16 freq, int idx, bool is2GHz)
4405 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4406 u8 *ctl_freqbin = is2GHz ?
4407 &eep->ctl_freqbin_2G[idx][0] :
4408 &eep->ctl_freqbin_5G[idx][0];
4409 u16 num_edges = is2GHz ?
4410 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4413 /* Get the edge power */
4415 (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
4418 * If there's an exact channel match or an inband flag set
4419 * on the lower channel use the given rdEdgePower
4421 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4423 ar9003_hw_get_direct_edge_power(eep, idx,
4426 } else if ((edge > 0) &&
4427 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4430 ar9003_hw_get_indirect_edge_power(eep, idx,
4434 * Leave loop - no more affecting edges possible in
4435 * this monotonic increasing list
4440 return twiceMaxEdgePower;
4443 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4444 struct ath9k_channel *chan,
4445 u8 *pPwrArray, u16 cfgCtl,
4446 u8 twiceAntennaReduction,
4447 u8 twiceMaxRegulatoryPower,
4450 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4451 struct ath_common *common = ath9k_hw_common(ah);
4452 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4453 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4454 static const u16 tpScaleReductionTable[5] = {
4455 0, 3, 6, 9, AR9300_MAX_RATE_POWER
4458 int16_t twiceLargestAntenna;
4459 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4460 static const u16 ctlModesFor11a[] = {
4461 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4463 static const u16 ctlModesFor11g[] = {
4464 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4465 CTL_11G_EXT, CTL_2GHT40
4468 const u16 *pCtlMode;
4470 struct chan_centers centers;
4473 u16 twiceMinEdgePower;
4474 bool is2ghz = IS_CHAN_2GHZ(chan);
4476 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
4478 /* Compute TxPower reduction due to Antenna Gain */
4480 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4482 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4484 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4485 twiceLargestAntenna, 0);
4488 * scaledPower is the minimum of the user input power level
4489 * and the regulatory allowed power level
4491 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4493 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4494 maxRegAllowedPower -=
4495 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4498 scaledPower = min(powerLimit, maxRegAllowedPower);
4501 * Reduce scaled Power by number of chains active to get
4502 * to per chain tx power level
4504 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4508 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4511 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4515 scaledPower = max((u16)0, scaledPower);
4518 * Get target powers from EEPROM - our baseline for TX Power
4521 /* Setup for CTL modes */
4522 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4524 ARRAY_SIZE(ctlModesFor11g) -
4525 SUB_NUM_CTL_MODES_AT_2G_40;
4526 pCtlMode = ctlModesFor11g;
4527 if (IS_CHAN_HT40(chan))
4529 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4531 /* Setup for CTL modes */
4532 /* CTL_11A, CTL_5GHT20 */
4533 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4534 SUB_NUM_CTL_MODES_AT_5G_40;
4535 pCtlMode = ctlModesFor11a;
4536 if (IS_CHAN_HT40(chan))
4538 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4542 * For MIMO, need to apply regulatory caps individually across
4543 * dynamically running modes: CCK, OFDM, HT20, HT40
4545 * The outer loop walks through each possible applicable runtime mode.
4546 * The inner loop walks through each ctlIndex entry in EEPROM.
4547 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4549 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4550 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4551 (pCtlMode[ctlMode] == CTL_2GHT40);
4553 freq = centers.synth_center;
4554 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4555 freq = centers.ext_center;
4557 freq = centers.ctl_center;
4559 ath_print(common, ATH_DBG_REGULATORY,
4560 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4561 "EXT_ADDITIVE %d\n",
4562 ctlMode, numCtlModes, isHt40CtlMode,
4563 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4565 /* walk through each CTL index stored in EEPROM */
4567 ctlIndex = pEepData->ctlIndex_2G;
4568 ctlNum = AR9300_NUM_CTLS_2G;
4570 ctlIndex = pEepData->ctlIndex_5G;
4571 ctlNum = AR9300_NUM_CTLS_5G;
4574 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4575 ath_print(common, ATH_DBG_REGULATORY,
4576 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4577 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4579 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4583 * compare test group from regulatory
4584 * channel list with test mode from pCtlMode
4587 if ((((cfgCtl & ~CTL_MODE_M) |
4588 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4590 (((cfgCtl & ~CTL_MODE_M) |
4591 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4592 ((ctlIndex[i] & CTL_MODE_M) |
4595 ar9003_hw_get_max_edge_power(pEepData,
4599 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4601 * Find the minimum of all CTL
4602 * edge powers that apply to
4606 min(twiceMaxEdgePower,
4617 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4619 ath_print(common, ATH_DBG_REGULATORY,
4620 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
4621 "sP %d minCtlPwr %d\n",
4622 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4623 scaledPower, minCtlPower);
4625 /* Apply ctl mode to correct target power set */
4626 switch (pCtlMode[ctlMode]) {
4628 for (i = ALL_TARGET_LEGACY_1L_5L;
4629 i <= ALL_TARGET_LEGACY_11S; i++)
4631 (u8)min((u16)pPwrArray[i],
4636 for (i = ALL_TARGET_LEGACY_6_24;
4637 i <= ALL_TARGET_LEGACY_54; i++)
4639 (u8)min((u16)pPwrArray[i],
4644 for (i = ALL_TARGET_HT20_0_8_16;
4645 i <= ALL_TARGET_HT20_21; i++)
4647 (u8)min((u16)pPwrArray[i],
4649 pPwrArray[ALL_TARGET_HT20_22] =
4650 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4652 pPwrArray[ALL_TARGET_HT20_23] =
4653 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4658 for (i = ALL_TARGET_HT40_0_8_16;
4659 i <= ALL_TARGET_HT40_23; i++)
4661 (u8)min((u16)pPwrArray[i],
4667 } /* end ctl mode checking */
4670 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4671 struct ath9k_channel *chan, u16 cfgCtl,
4672 u8 twiceAntennaReduction,
4673 u8 twiceMaxRegulatoryPower,
4674 u8 powerLimit, bool test)
4676 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4677 struct ath_common *common = ath9k_hw_common(ah);
4678 u8 targetPowerValT2[ar9300RateSize];
4681 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4682 ar9003_hw_set_power_per_rate_table(ah, chan,
4683 targetPowerValT2, cfgCtl,
4684 twiceAntennaReduction,
4685 twiceMaxRegulatoryPower,
4688 regulatory->max_power_level = 0;
4689 for (i = 0; i < ar9300RateSize; i++) {
4690 if (targetPowerValT2[i] > regulatory->max_power_level)
4691 regulatory->max_power_level = targetPowerValT2[i];
4697 for (i = 0; i < ar9300RateSize; i++) {
4698 ath_print(common, ATH_DBG_EEPROM,
4699 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4701 ath_print(common, ATH_DBG_EEPROM,
4702 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4704 ath_print(common, ATH_DBG_EEPROM,
4705 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4707 ath_print(common, ATH_DBG_EEPROM,
4708 "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
4713 * This is the TX power we send back to driver core,
4714 * and it can use to pass to userspace to display our
4715 * currently configured TX power setting.
4717 * Since power is rate dependent, use one of the indices
4718 * from the AR9300_Rates enum to select an entry from
4719 * targetPowerValT2[] to report. Currently returns the
4720 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4721 * as CCK power is less interesting (?).
4723 i = ALL_TARGET_LEGACY_6_24; /* legacy */
4724 if (IS_CHAN_HT40(chan))
4725 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4726 else if (IS_CHAN_HT20(chan))
4727 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4729 ah->txpower_limit = targetPowerValT2[i];
4730 regulatory->max_power_level = targetPowerValT2[i];
4732 /* Write target power array to registers */
4733 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4734 ar9003_hw_calibration_apply(ah, chan->channel);
4737 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4743 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4745 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4747 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4750 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4752 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4754 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4757 const struct eeprom_ops eep_ar9300_ops = {
4758 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4759 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4760 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4761 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4762 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
4763 .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
4764 .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
4765 .set_board_values = ath9k_hw_ar9300_set_board_values,
4766 .set_addac = ath9k_hw_ar9300_set_addac,
4767 .set_txpower = ath9k_hw_ar9300_set_txpower,
4768 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel