drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20
  21 #define AR9300_OFDM_RATES       8
  22 #define AR9300_HT_SS_RATES      8
  23 #define AR9300_HT_DS_RATES      8
  24 #define AR9300_HT_TS_RATES      8
  25
  26 #define AR9300_11NA_OFDM_SHIFT          0
  27 #define AR9300_11NA_HT_SS_SHIFT         8
  28 #define AR9300_11NA_HT_DS_SHIFT         16
  29 #define AR9300_11NA_HT_TS_SHIFT         24
  30
  31 #define AR9300_11NG_OFDM_SHIFT          4
  32 #define AR9300_11NG_HT_SS_SHIFT         12
  33 #define AR9300_11NG_HT_DS_SHIFT         20
  34 #define AR9300_11NG_HT_TS_SHIFT         28
  35
  36 static const int firstep_table[] =
  37 /* level:  0   1   2   3   4   5   6   7   8  */
  38         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  39
  40 static const int cycpwrThr1_table[] =
  41 /* level:  0   1   2   3   4   5   6   7   8  */
  42         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  43
  44 /*
  45  * register values to turn OFDM weak signal detection OFF
  46  */
  47 static const int m1ThreshLow_off = 127;
  48 static const int m2ThreshLow_off = 127;
  49 static const int m1Thresh_off = 127;
  50 static const int m2Thresh_off = 127;
  51 static const int m2CountThr_off =  31;
  52 static const int m2CountThrLow_off =  63;
  53 static const int m1ThreshLowExt_off = 127;
  54 static const int m2ThreshLowExt_off = 127;
  55 static const int m1ThreshExt_off = 127;
  56 static const int m2ThreshExt_off = 127;
  57
  58 static const u8 ofdm2pwr[] = {
  59         ALL_TARGET_LEGACY_6_24,
  60         ALL_TARGET_LEGACY_6_24,
  61         ALL_TARGET_LEGACY_6_24,
  62         ALL_TARGET_LEGACY_6_24,
  63         ALL_TARGET_LEGACY_6_24,
  64         ALL_TARGET_LEGACY_36,
  65         ALL_TARGET_LEGACY_48,
  66         ALL_TARGET_LEGACY_54
  67 };
  68
  69 static const u8 mcs2pwr_ht20[] = {
  70         ALL_TARGET_HT20_0_8_16,
  71         ALL_TARGET_HT20_1_3_9_11_17_19,
  72         ALL_TARGET_HT20_1_3_9_11_17_19,
  73         ALL_TARGET_HT20_1_3_9_11_17_19,
  74         ALL_TARGET_HT20_4,
  75         ALL_TARGET_HT20_5,
  76         ALL_TARGET_HT20_6,
  77         ALL_TARGET_HT20_7,
  78         ALL_TARGET_HT20_0_8_16,
  79         ALL_TARGET_HT20_1_3_9_11_17_19,
  80         ALL_TARGET_HT20_1_3_9_11_17_19,
  81         ALL_TARGET_HT20_1_3_9_11_17_19,
  82         ALL_TARGET_HT20_12,
  83         ALL_TARGET_HT20_13,
  84         ALL_TARGET_HT20_14,
  85         ALL_TARGET_HT20_15,
  86         ALL_TARGET_HT20_0_8_16,
  87         ALL_TARGET_HT20_1_3_9_11_17_19,
  88         ALL_TARGET_HT20_1_3_9_11_17_19,
  89         ALL_TARGET_HT20_1_3_9_11_17_19,
  90         ALL_TARGET_HT20_20,
  91         ALL_TARGET_HT20_21,
  92         ALL_TARGET_HT20_22,
  93         ALL_TARGET_HT20_23
  94 };
  95
  96 static const u8 mcs2pwr_ht40[] = {
  97         ALL_TARGET_HT40_0_8_16,
  98         ALL_TARGET_HT40_1_3_9_11_17_19,
  99         ALL_TARGET_HT40_1_3_9_11_17_19,
 100         ALL_TARGET_HT40_1_3_9_11_17_19,
 101         ALL_TARGET_HT40_4,
 102         ALL_TARGET_HT40_5,
 103         ALL_TARGET_HT40_6,
 104         ALL_TARGET_HT40_7,
 105         ALL_TARGET_HT40_0_8_16,
 106         ALL_TARGET_HT40_1_3_9_11_17_19,
 107         ALL_TARGET_HT40_1_3_9_11_17_19,
 108         ALL_TARGET_HT40_1_3_9_11_17_19,
 109         ALL_TARGET_HT40_12,
 110         ALL_TARGET_HT40_13,
 111         ALL_TARGET_HT40_14,
 112         ALL_TARGET_HT40_15,
 113         ALL_TARGET_HT40_0_8_16,
 114         ALL_TARGET_HT40_1_3_9_11_17_19,
 115         ALL_TARGET_HT40_1_3_9_11_17_19,
 116         ALL_TARGET_HT40_1_3_9_11_17_19,
 117         ALL_TARGET_HT40_20,
 118         ALL_TARGET_HT40_21,
 119         ALL_TARGET_HT40_22,
 120         ALL_TARGET_HT40_23,
 121 };
 122
 123 /**
 124  * ar9003_hw_set_channel - set channel on single-chip device
 125  * @ah: atheros hardware structure
 126  * @chan:
 127  *
 128  * This is the function to change channel on single-chip devices, that is
 129  * for AR9300 family of chipsets.
 130  *
 131  * This function takes the channel value in MHz and sets
 132  * hardware channel value. Assumes writes have been enabled to analog bus.
 133  *
 134  * Actual Expression,
 135  *
 136  * For 2GHz channel,
 137  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
 138  * (freq_ref = 40MHz)
 139  *
 140  * For 5GHz channel,
 141  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
 142  * (freq_ref = 40MHz/(24>>amodeRefSel))
 143  *
 144  * For 5GHz channels which are 5MHz spaced,
 145  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
 146  * (freq_ref = 40MHz)
 147  */
 148 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 149 {
 150         u16 bMode, fracMode = 0, aModeRefSel = 0;
 151         u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
 152         struct chan_centers centers;
 153         int loadSynthChannel;
 154
 155         ath9k_hw_get_channel_centers(ah, chan, &centers);
 156         freq = centers.synth_center;
 157
 158         if (freq < 4800) {     /* 2 GHz, fractional mode */
 159                 if (AR_SREV_9330(ah)) {
 160                         if (ah->is_clk_25mhz)
 161                                 div = 75;
 162                         else
 163                                 div = 120;
 164
 165                         channelSel = (freq * 4) / div;
 166                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
 167                         channelSel = (channelSel << 17) | chan_frac;
 168                 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
 169                         /*
 170                          * freq_ref = 40 / (refdiva >> amoderefsel);
 171                          * where refdiva=1 and amoderefsel=0
 172                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
 173                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
 174                          */
 175                         channelSel = (freq * 4) / 120;
 176                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
 177                         channelSel = (channelSel << 17) | chan_frac;
 178                 } else if (AR_SREV_9340(ah)) {
 179                         if (ah->is_clk_25mhz) {
 180                                 channelSel = (freq * 2) / 75;
 181                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 182                                 channelSel = (channelSel << 17) | chan_frac;
 183                         } else {
 184                                 channelSel = CHANSEL_2G(freq) >> 1;
 185                         }
 186                 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
 187                            AR_SREV_9561(ah)) {
 188                         if (ah->is_clk_25mhz)
 189                                 div = 75;
 190                         else
 191                                 div = 120;
 192
 193                         channelSel = (freq * 4) / div;
 194                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
 195                         channelSel = (channelSel << 17) | chan_frac;
 196                 } else {
 197                         channelSel = CHANSEL_2G(freq);
 198                 }
 199                 /* Set to 2G mode */
 200                 bMode = 1;
 201         } else {
 202                 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) ||
 203                      AR_SREV_9531(ah) || AR_SREV_9561(ah)) &&
 204                     ah->is_clk_25mhz) {
 205                         channelSel = freq / 75;
 206                         chan_frac = ((freq % 75) * 0x20000) / 75;
 207                         channelSel = (channelSel << 17) | chan_frac;
 208                 } else {
 209                         channelSel = CHANSEL_5G(freq);
 210                         /* Doubler is ON, so, divide channelSel by 2. */
 211                         channelSel >>= 1;
 212                 }
 213                 /* Set to 5G mode */
 214                 bMode = 0;
 215         }
 216
 217         /* Enable fractional mode for all channels */
 218         fracMode = 1;
 219         aModeRefSel = 0;
 220         loadSynthChannel = 0;
 221
 222         reg32 = (bMode << 29);
 223         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 224
 225         /* Enable Long shift Select for Synthesizer */
 226         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 227                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 228
 229         /* Program Synth. setting */
 230         reg32 = (channelSel << 2) | (fracMode << 30) |
 231                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 232         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 233
 234         /* Toggle Load Synth channel bit */
 235         loadSynthChannel = 1;
 236         reg32 = (channelSel << 2) | (fracMode << 30) |
 237                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 238         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 239
 240         ah->curchan = chan;
 241
 242         return 0;
 243 }
 244
 245 /**
 246  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 247  * @ah: atheros hardware structure
 248  * @chan:
 249  *
 250  * For single-chip solutions. Converts to baseband spur frequency given the
 251  * input channel frequency and compute register settings below.
 252  *
 253  * Spur mitigation for MRC CCK
 254  */
 255 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 256                                             struct ath9k_channel *chan)
 257 {
 258         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 259         int cur_bb_spur, negative = 0, cck_spur_freq;
 260         int i;
 261         int range, max_spur_cnts, synth_freq;
 262         u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
 263
 264         /*
 265          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 266          * is out-of-band and can be ignored.
 267          */
 268
 269         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 270             AR_SREV_9550(ah) || AR_SREV_9561(ah)) {
 271                 if (spur_fbin_ptr[0] == 0) /* No spur */
 272                         return;
 273                 max_spur_cnts = 5;
 274                 if (IS_CHAN_HT40(chan)) {
 275                         range = 19;
 276                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 277                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 278                                 synth_freq = chan->channel + 10;
 279                         else
 280                                 synth_freq = chan->channel - 10;
 281                 } else {
 282                         range = 10;
 283                         synth_freq = chan->channel;
 284                 }
 285         } else {
 286                 range = AR_SREV_9462(ah) ? 5 : 10;
 287                 max_spur_cnts = 4;
 288                 synth_freq = chan->channel;
 289         }
 290
 291         for (i = 0; i < max_spur_cnts; i++) {
 292                 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
 293                         continue;
 294
 295                 negative = 0;
 296                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 297                     AR_SREV_9550(ah) || AR_SREV_9561(ah))
 298                         cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
 299                                                          IS_CHAN_2GHZ(chan));
 300                 else
 301                         cur_bb_spur = spur_freq[i];
 302
 303                 cur_bb_spur -= synth_freq;
 304                 if (cur_bb_spur < 0) {
 305                         negative = 1;
 306                         cur_bb_spur = -cur_bb_spur;
 307                 }
 308                 if (cur_bb_spur < range) {
 309                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 310
 311                         if (negative == 1)
 312                                 cck_spur_freq = -cck_spur_freq;
 313
 314                         cck_spur_freq = cck_spur_freq & 0xfffff;
 315
 316                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 317                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 318                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 319                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 320                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 321                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 322                                       0x2);
 323                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 324                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 325                                       0x1);
 326                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 327                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 328                                       cck_spur_freq);
 329
 330                         return;
 331                 }
 332         }
 333
 334         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 335                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 336         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 337                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 338         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 339                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 340 }
 341
 342 /* Clean all spur register fields */
 343 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 344 {
 345         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 346                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 347         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 348                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 349         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 350                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 351         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 352                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 353         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 354                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 355         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 356                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 357         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 358                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 359         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 360                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 361         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 362                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 363
 364         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 365                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 366         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 367                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 368         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 369                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 370         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 371                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 372         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 373                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 374         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 375                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 376         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 377                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 378         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 379                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 380         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 381                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 382         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 383                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 384 }
 385
 386 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 387                                 int freq_offset,
 388                                 int spur_freq_sd,
 389                                 int spur_delta_phase,
 390                                 int spur_subchannel_sd,
 391                                 int range,
 392                                 int synth_freq)
 393 {
 394         int mask_index = 0;
 395
 396         /* OFDM Spur mitigation */
 397         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 398                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 399         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 400                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 401         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 402                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 403         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 404                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 405         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 406                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 407
 408         if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
 409                 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 410                               AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 411
 412         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 413                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 414         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 415                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 416         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 417                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 418
 419         if (!AR_SREV_9340(ah) &&
 420             REG_READ_FIELD(ah, AR_PHY_MODE,
 421                            AR_PHY_MODE_DYNAMIC) == 0x1)
 422                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 423                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 424
 425         mask_index = (freq_offset << 4) / 5;
 426         if (mask_index < 0)
 427                 mask_index = mask_index - 1;
 428
 429         mask_index = mask_index & 0x7f;
 430
 431         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 432                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 433         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 434                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 435         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 436                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 437         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 438                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 439         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 440                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 441         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 442                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 443         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 444                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 445         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 446                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 447         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 448                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 449         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 450                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 451 }
 452
 453 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
 454                                      int freq_offset)
 455 {
 456         int mask_index = 0;
 457
 458         mask_index = (freq_offset << 4) / 5;
 459         if (mask_index < 0)
 460                 mask_index = mask_index - 1;
 461
 462         mask_index = mask_index & 0x7f;
 463
 464         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 465                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
 466                       mask_index);
 467
 468         /* A == B */
 469         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 470                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
 471                       mask_index);
 472
 473         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 474                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
 475                       mask_index);
 476         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 477                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
 478         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 479                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
 480
 481         /* A == B */
 482         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 483                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 484 }
 485
 486 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 487                                      struct ath9k_channel *chan,
 488                                      int freq_offset,
 489                                      int range,
 490                                      int synth_freq)
 491 {
 492         int spur_freq_sd = 0;
 493         int spur_subchannel_sd = 0;
 494         int spur_delta_phase = 0;
 495
 496         if (IS_CHAN_HT40(chan)) {
 497                 if (freq_offset < 0) {
 498                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 499                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 500                                 spur_subchannel_sd = 1;
 501                         else
 502                                 spur_subchannel_sd = 0;
 503
 504                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 505
 506                 } else {
 507                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 508                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 509                                 spur_subchannel_sd = 0;
 510                         else
 511                                 spur_subchannel_sd = 1;
 512
 513                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 514
 515                 }
 516
 517                 spur_delta_phase = (freq_offset << 17) / 5;
 518
 519         } else {
 520                 spur_subchannel_sd = 0;
 521                 spur_freq_sd = (freq_offset << 9) /11;
 522                 spur_delta_phase = (freq_offset << 18) / 5;
 523         }
 524
 525         spur_freq_sd = spur_freq_sd & 0x3ff;
 526         spur_delta_phase = spur_delta_phase & 0xfffff;
 527
 528         ar9003_hw_spur_ofdm(ah,
 529                             freq_offset,
 530                             spur_freq_sd,
 531                             spur_delta_phase,
 532                             spur_subchannel_sd,
 533                             range, synth_freq);
 534 }
 535
 536 /* Spur mitigation for OFDM */
 537 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 538                                          struct ath9k_channel *chan)
 539 {
 540         int synth_freq;
 541         int range = 10;
 542         int freq_offset = 0;
 543         int mode;
 544         u8* spurChansPtr;
 545         unsigned int i;
 546         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 547
 548         if (IS_CHAN_5GHZ(chan)) {
 549                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 550                 mode = 0;
 551         }
 552         else {
 553                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 554                 mode = 1;
 555         }
 556
 557         if (spurChansPtr[0] == 0)
 558                 return; /* No spur in the mode */
 559
 560         if (IS_CHAN_HT40(chan)) {
 561                 range = 19;
 562                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 563                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 564                         synth_freq = chan->channel - 10;
 565                 else
 566                         synth_freq = chan->channel + 10;
 567         } else {
 568                 range = 10;
 569                 synth_freq = chan->channel;
 570         }
 571
 572         ar9003_hw_spur_ofdm_clear(ah);
 573
 574         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 575                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
 576                 freq_offset -= synth_freq;
 577                 if (abs(freq_offset) < range) {
 578                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
 579                                                  range, synth_freq);
 580
 581                         if (AR_SREV_9565(ah) && (i < 4)) {
 582                                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
 583                                                                  mode);
 584                                 freq_offset -= synth_freq;
 585                                 if (abs(freq_offset) < range)
 586                                         ar9003_hw_spur_ofdm_9565(ah, freq_offset);
 587                         }
 588
 589                         break;
 590                 }
 591         }
 592 }
 593
 594 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 595                                     struct ath9k_channel *chan)
 596 {
 597         if (!AR_SREV_9565(ah))
 598                 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 599         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 600 }
 601
 602 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
 603                                              struct ath9k_channel *chan)
 604 {
 605         u32 pll;
 606
 607         pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
 608
 609         if (chan && IS_CHAN_HALF_RATE(chan))
 610                 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
 611         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 612                 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
 613
 614         pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
 615
 616         return pll;
 617 }
 618
 619 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 620                                          struct ath9k_channel *chan)
 621 {
 622         u32 pll;
 623
 624         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 625
 626         if (chan && IS_CHAN_HALF_RATE(chan))
 627                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 628         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 629                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 630
 631         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 632
 633         return pll;
 634 }
 635
 636 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 637                                        struct ath9k_channel *chan)
 638 {
 639         u32 phymode;
 640         u32 enableDacFifo = 0;
 641
 642         enableDacFifo =
 643                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 644
 645         /* Enable 11n HT, 20 MHz */
 646         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 647
 648         if (!AR_SREV_9561(ah))
 649                 phymode |= AR_PHY_GC_SINGLE_HT_LTF1;
 650
 651         /* Configure baseband for dynamic 20/40 operation */
 652         if (IS_CHAN_HT40(chan)) {
 653                 phymode |= AR_PHY_GC_DYN2040_EN;
 654                 /* Configure control (primary) channel at +-10MHz */
 655                 if (IS_CHAN_HT40PLUS(chan))
 656                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 657
 658         }
 659
 660         /* make sure we preserve INI settings */
 661         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 662         /* turn off Green Field detection for STA for now */
 663         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 664
 665         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 666
 667         /* Configure MAC for 20/40 operation */
 668         ath9k_hw_set11nmac2040(ah, chan);
 669
 670         /* global transmit timeout (25 TUs default)*/
 671         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 672         /* carrier sense timeout */
 673         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 674 }
 675
 676 static void ar9003_hw_init_bb(struct ath_hw *ah,
 677                               struct ath9k_channel *chan)
 678 {
 679         u32 synthDelay;
 680
 681         /*
 682          * Wait for the frequency synth to settle (synth goes on
 683          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 684          * Value is in 100ns increments.
 685          */
 686         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 687
 688         /* Activate the PHY (includes baseband activate + synthesizer on) */
 689         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 690         ath9k_hw_synth_delay(ah, chan, synthDelay);
 691 }
 692
 693 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 694 {
 695         if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
 696                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 697                             AR_PHY_SWAP_ALT_CHAIN);
 698
 699         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 700         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 701
 702         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 703                 tx = 3;
 704
 705         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 706 }
 707
 708 /*
 709  * Override INI values with chip specific configuration.
 710  */
 711 static void ar9003_hw_override_ini(struct ath_hw *ah)
 712 {
 713         u32 val;
 714
 715         /*
 716          * Set the RX_ABORT and RX_DIS and clear it only after
 717          * RXE is set for MAC. This prevents frames with
 718          * corrupted descriptor status.
 719          */
 720         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 721
 722         /*
 723          * For AR9280 and above, there is a new feature that allows
 724          * Multicast search based on both MAC Address and Key ID. By default,
 725          * this feature is enabled. But since the driver is not using this
 726          * feature, we switch it off; otherwise multicast search based on
 727          * MAC addr only will fail.
 728          */
 729         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 730         val |= AR_AGG_WEP_ENABLE_FIX |
 731                AR_AGG_WEP_ENABLE |
 732                AR_PCU_MISC_MODE2_CFP_IGNORE;
 733         REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
 734
 735         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 736                 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
 737                           AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
 738
 739                 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 740                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 741                         ah->enabled_cals |= TX_IQ_CAL;
 742                 else
 743                         ah->enabled_cals &= ~TX_IQ_CAL;
 744
 745         }
 746
 747         if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
 748                 ah->enabled_cals |= TX_CL_CAL;
 749         else
 750                 ah->enabled_cals &= ~TX_CL_CAL;
 751
 752         if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
 753             AR_SREV_9561(ah)) {
 754                 if (ah->is_clk_25mhz) {
 755                         REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
 756                         REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
 757                         REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
 758                 } else {
 759                         REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
 760                         REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
 761                         REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
 762                 }
 763                 udelay(100);
 764         }
 765 }
 766
 767 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 768                                struct ar5416IniArray *iniArr,
 769                                int column)
 770 {
 771         unsigned int i, regWrites = 0;
 772
 773         /* New INI format: Array may be undefined (pre, core, post arrays) */
 774         if (!iniArr->ia_array)
 775                 return;
 776
 777         /*
 778          * New INI format: Pre, core, and post arrays for a given subsystem
 779          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 780          * the array is non-modal and force the column to 1.
 781          */
 782         if (column >= iniArr->ia_columns)
 783                 column = 1;
 784
 785         for (i = 0; i < iniArr->ia_rows; i++) {
 786                 u32 reg = INI_RA(iniArr, i, 0);
 787                 u32 val = INI_RA(iniArr, i, column);
 788
 789                 REG_WRITE(ah, reg, val);
 790
 791                 DO_DELAY(regWrites);
 792         }
 793 }
 794
 795 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
 796                                             struct ath9k_channel *chan)
 797 {
 798         int ret;
 799
 800         if (IS_CHAN_2GHZ(chan)) {
 801                 if (IS_CHAN_HT40(chan))
 802                         return 7;
 803                 else
 804                         return 8;
 805         }
 806
 807         if (chan->channel <= 5350)
 808                 ret = 1;
 809         else if ((chan->channel > 5350) && (chan->channel <= 5600))
 810                 ret = 3;
 811         else
 812                 ret = 5;
 813
 814         if (IS_CHAN_HT40(chan))
 815                 ret++;
 816
 817         return ret;
 818 }
 819
 820 static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah,
 821                                             struct ath9k_channel *chan)
 822 {
 823         if (IS_CHAN_2GHZ(chan)) {
 824                 if (IS_CHAN_HT40(chan))
 825                         return 1;
 826                 else
 827                         return 2;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static void ar9003_doubler_fix(struct ath_hw *ah)
 834 {
 835         if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
 836                 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
 837                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 838                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 839                 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
 840                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 841                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 842                 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
 843                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 844                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 845
 846                 udelay(200);
 847
 848                 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
 849                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 850                 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
 851                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 852                 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
 853                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 854
 855                 udelay(1);
 856
 857                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
 858                               AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 859                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
 860                               AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 861                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
 862                               AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 863
 864                 udelay(200);
 865
 866                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
 867                               AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
 868
 869                 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
 870                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 871                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 872                 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
 873                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 874                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 875                 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
 876                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 877                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 878         }
 879 }
 880
 881 static int ar9003_hw_process_ini(struct ath_hw *ah,
 882                                  struct ath9k_channel *chan)
 883 {
 884         unsigned int regWrites = 0, i;
 885         u32 modesIndex;
 886
 887         if (IS_CHAN_5GHZ(chan))
 888                 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
 889         else
 890                 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
 891
 892         /*
 893          * SOC, MAC, BB, RADIO initvals.
 894          */
 895         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 896                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 897                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 898                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 899                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 900                 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
 901                         ar9003_hw_prog_ini(ah,
 902                                            &ah->ini_radio_post_sys2ant,
 903                                            modesIndex);
 904         }
 905
 906         ar9003_doubler_fix(ah);
 907
 908         /*
 909          * RXGAIN initvals.
 910          */
 911         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 912
 913         if (AR_SREV_9462_20_OR_LATER(ah)) {
 914                 /*
 915                  * CUS217 mix LNA mode.
 916                  */
 917                 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
 918                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
 919                                         1, regWrites);
 920                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 921                                         modesIndex, regWrites);
 922                 }
 923
 924                 /*
 925                  * 5G-XLNA
 926                  */
 927                 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
 928                     (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
 929                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 930                                         modesIndex, regWrites);
 931                 }
 932
 933                 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
 934                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 935                                         modesIndex, regWrites);
 936         }
 937
 938         if (AR_SREV_9550(ah) || AR_SREV_9561(ah))
 939                 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
 940                                 regWrites);
 941
 942         /*
 943          * TXGAIN initvals.
 944          */
 945         if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
 946                 int modes_txgain_index = 1;
 947
 948                 if (AR_SREV_9550(ah))
 949                         modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
 950
 951                 if (AR_SREV_9561(ah))
 952                         modes_txgain_index =
 953                                 ar9561_hw_get_modes_txgain_index(ah, chan);
 954
 955                 if (modes_txgain_index < 0)
 956                         return -EINVAL;
 957
 958                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
 959                                 regWrites);
 960         } else {
 961                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 962         }
 963
 964         /*
 965          * For 5GHz channels requiring Fast Clock, apply
 966          * different modal values.
 967          */
 968         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 969                 REG_WRITE_ARRAY(&ah->iniModesFastClock,
 970                                 modesIndex, regWrites);
 971
 972         /*
 973          * Clock frequency initvals.
 974          */
 975         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
 976
 977         /*
 978          * JAPAN regulatory.
 979          */
 980         if (chan->channel == 2484)
 981                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 982
 983         ah->modes_index = modesIndex;
 984         ar9003_hw_override_ini(ah);
 985         ar9003_hw_set_channel_regs(ah, chan);
 986         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 987         ath9k_hw_apply_txpower(ah, chan, false);
 988
 989         return 0;
 990 }
 991
 992 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 993                                  struct ath9k_channel *chan)
 994 {
 995         u32 rfMode = 0;
 996
 997         if (chan == NULL)
 998                 return;
 999
1000         if (IS_CHAN_2GHZ(chan))
1001                 rfMode |= AR_PHY_MODE_DYNAMIC;
1002         else
1003                 rfMode |= AR_PHY_MODE_OFDM;
1004
1005         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1006                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1007
1008         if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
1009                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
1010                               AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
1011
1012         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1013 }
1014
1015 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
1016 {
1017         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1018 }
1019
1020 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
1021                                       struct ath9k_channel *chan)
1022 {
1023         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1024         u32 clockMhzScaled = 0x64000000;
1025         struct chan_centers centers;
1026
1027         /*
1028          * half and quarter rate can divide the scaled clock by 2 or 4
1029          * scale for selected channel bandwidth
1030          */
1031         if (IS_CHAN_HALF_RATE(chan))
1032                 clockMhzScaled = clockMhzScaled >> 1;
1033         else if (IS_CHAN_QUARTER_RATE(chan))
1034                 clockMhzScaled = clockMhzScaled >> 2;
1035
1036         /*
1037          * ALGO -> coef = 1e8/fcarrier*fclock/40;
1038          * scaled coef to provide precision for this floating calculation
1039          */
1040         ath9k_hw_get_channel_centers(ah, chan, &centers);
1041         coef_scaled = clockMhzScaled / centers.synth_center;
1042
1043         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1044                                       &ds_coef_exp);
1045
1046         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1047                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1048         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1049                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1050
1051         /*
1052          * For Short GI,
1053          * scaled coeff is 9/10 that of normal coeff
1054          */
1055         coef_scaled = (9 * coef_scaled) / 10;
1056
1057         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1058                                       &ds_coef_exp);
1059
1060         /* for short gi */
1061         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1062                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
1063         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1064                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
1065 }
1066
1067 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
1068 {
1069         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1070         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1071                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1072 }
1073
1074 /*
1075  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1076  * Read the phy active delay register. Value is in 100ns increments.
1077  */
1078 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
1079 {
1080         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1081
1082         ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
1083
1084         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1085 }
1086
1087 static bool ar9003_hw_ani_control(struct ath_hw *ah,
1088                                   enum ath9k_ani_cmd cmd, int param)
1089 {
1090         struct ath_common *common = ath9k_hw_common(ah);
1091         struct ath9k_channel *chan = ah->curchan;
1092         struct ar5416AniState *aniState = &ah->ani;
1093         int m1ThreshLow, m2ThreshLow;
1094         int m1Thresh, m2Thresh;
1095         int m2CountThr, m2CountThrLow;
1096         int m1ThreshLowExt, m2ThreshLowExt;
1097         int m1ThreshExt, m2ThreshExt;
1098         s32 value, value2;
1099
1100         switch (cmd & ah->ani_function) {
1101         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1102                 /*
1103                  * on == 1 means ofdm weak signal detection is ON
1104                  * on == 1 is the default, for less noise immunity
1105                  *
1106                  * on == 0 means ofdm weak signal detection is OFF
1107                  * on == 0 means more noise imm
1108                  */
1109                 u32 on = param ? 1 : 0;
1110
1111                 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1112                         goto skip_ws_det;
1113
1114                 m1ThreshLow = on ?
1115                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1116                 m2ThreshLow = on ?
1117                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1118                 m1Thresh = on ?
1119                         aniState->iniDef.m1Thresh : m1Thresh_off;
1120                 m2Thresh = on ?
1121                         aniState->iniDef.m2Thresh : m2Thresh_off;
1122                 m2CountThr = on ?
1123                         aniState->iniDef.m2CountThr : m2CountThr_off;
1124                 m2CountThrLow = on ?
1125                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1126                 m1ThreshLowExt = on ?
1127                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1128                 m2ThreshLowExt = on ?
1129                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1130                 m1ThreshExt = on ?
1131                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1132                 m2ThreshExt = on ?
1133                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1134
1135                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1136                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1137                               m1ThreshLow);
1138                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1139                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1140                               m2ThreshLow);
1141                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1142                               AR_PHY_SFCORR_M1_THRESH,
1143                               m1Thresh);
1144                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1145                               AR_PHY_SFCORR_M2_THRESH,
1146                               m2Thresh);
1147                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1148                               AR_PHY_SFCORR_M2COUNT_THR,
1149                               m2CountThr);
1150                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1151                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1152                               m2CountThrLow);
1153                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1154                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1155                               m1ThreshLowExt);
1156                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1157                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1158                               m2ThreshLowExt);
1159                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1160                               AR_PHY_SFCORR_EXT_M1_THRESH,
1161                               m1ThreshExt);
1162                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1163                               AR_PHY_SFCORR_EXT_M2_THRESH,
1164                               m2ThreshExt);
1165 skip_ws_det:
1166                 if (on)
1167                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1168                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1169                 else
1170                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1171                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1172
1173                 if (on != aniState->ofdmWeakSigDetect) {
1174                         ath_dbg(common, ANI,
1175                                 "** ch %d: ofdm weak signal: %s=>%s\n",
1176                                 chan->channel,
1177                                 aniState->ofdmWeakSigDetect ?
1178                                 "on" : "off",
1179                                 on ? "on" : "off");
1180                         if (on)
1181                                 ah->stats.ast_ani_ofdmon++;
1182                         else
1183                                 ah->stats.ast_ani_ofdmoff++;
1184                         aniState->ofdmWeakSigDetect = on;
1185                 }
1186                 break;
1187         }
1188         case ATH9K_ANI_FIRSTEP_LEVEL:{
1189                 u32 level = param;
1190
1191                 if (level >= ARRAY_SIZE(firstep_table)) {
1192                         ath_dbg(common, ANI,
1193                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1194                                 level, ARRAY_SIZE(firstep_table));
1195                         return false;
1196                 }
1197
1198                 /*
1199                  * make register setting relative to default
1200                  * from INI file & cap value
1201                  */
1202                 value = firstep_table[level] -
1203                         firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1204                         aniState->iniDef.firstep;
1205                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1206                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1207                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1208                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1209                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1210                               AR_PHY_FIND_SIG_FIRSTEP,
1211                               value);
1212                 /*
1213                  * we need to set first step low register too
1214                  * make register setting relative to default
1215                  * from INI file & cap value
1216                  */
1217                 value2 = firstep_table[level] -
1218                          firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1219                          aniState->iniDef.firstepLow;
1220                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1221                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1222                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1223                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1224
1225                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1226                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1227
1228                 if (level != aniState->firstepLevel) {
1229                         ath_dbg(common, ANI,
1230                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1231                                 chan->channel,
1232                                 aniState->firstepLevel,
1233                                 level,
1234                                 ATH9K_ANI_FIRSTEP_LVL,
1235                                 value,
1236                                 aniState->iniDef.firstep);
1237                         ath_dbg(common, ANI,
1238                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1239                                 chan->channel,
1240                                 aniState->firstepLevel,
1241                                 level,
1242                                 ATH9K_ANI_FIRSTEP_LVL,
1243                                 value2,
1244                                 aniState->iniDef.firstepLow);
1245                         if (level > aniState->firstepLevel)
1246                                 ah->stats.ast_ani_stepup++;
1247                         else if (level < aniState->firstepLevel)
1248                                 ah->stats.ast_ani_stepdown++;
1249                         aniState->firstepLevel = level;
1250                 }
1251                 break;
1252         }
1253         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1254                 u32 level = param;
1255
1256                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1257                         ath_dbg(common, ANI,
1258                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1259                                 level, ARRAY_SIZE(cycpwrThr1_table));
1260                         return false;
1261                 }
1262                 /*
1263                  * make register setting relative to default
1264                  * from INI file & cap value
1265                  */
1266                 value = cycpwrThr1_table[level] -
1267                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1268                         aniState->iniDef.cycpwrThr1;
1269                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1270                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1271                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1272                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1273                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1274                               AR_PHY_TIMING5_CYCPWR_THR1,
1275                               value);
1276
1277                 /*
1278                  * set AR_PHY_EXT_CCA for extension channel
1279                  * make register setting relative to default
1280                  * from INI file & cap value
1281                  */
1282                 value2 = cycpwrThr1_table[level] -
1283                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1284                          aniState->iniDef.cycpwrThr1Ext;
1285                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1286                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1287                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1288                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1289                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1290                               AR_PHY_EXT_CYCPWR_THR1, value2);
1291
1292                 if (level != aniState->spurImmunityLevel) {
1293                         ath_dbg(common, ANI,
1294                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1295                                 chan->channel,
1296                                 aniState->spurImmunityLevel,
1297                                 level,
1298                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1299                                 value,
1300                                 aniState->iniDef.cycpwrThr1);
1301                         ath_dbg(common, ANI,
1302                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1303                                 chan->channel,
1304                                 aniState->spurImmunityLevel,
1305                                 level,
1306                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1307                                 value2,
1308                                 aniState->iniDef.cycpwrThr1Ext);
1309                         if (level > aniState->spurImmunityLevel)
1310                                 ah->stats.ast_ani_spurup++;
1311                         else if (level < aniState->spurImmunityLevel)
1312                                 ah->stats.ast_ani_spurdown++;
1313                         aniState->spurImmunityLevel = level;
1314                 }
1315                 break;
1316         }
1317         case ATH9K_ANI_MRC_CCK:{
1318                 /*
1319                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1320                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1321                  */
1322                 bool is_on = param ? 1 : 0;
1323
1324                 if (ah->caps.rx_chainmask == 1)
1325                         break;
1326
1327                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1328                               AR_PHY_MRC_CCK_ENABLE, is_on);
1329                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1330                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1331                 if (is_on != aniState->mrcCCK) {
1332                         ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1333                                 chan->channel,
1334                                 aniState->mrcCCK ? "on" : "off",
1335                                 is_on ? "on" : "off");
1336                 if (is_on)
1337                         ah->stats.ast_ani_ccklow++;
1338                 else
1339                         ah->stats.ast_ani_cckhigh++;
1340                 aniState->mrcCCK = is_on;
1341                 }
1342         break;
1343         }
1344         default:
1345                 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1346                 return false;
1347         }
1348
1349         ath_dbg(common, ANI,
1350                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1351                 aniState->spurImmunityLevel,
1352                 aniState->ofdmWeakSigDetect ? "on" : "off",
1353                 aniState->firstepLevel,
1354                 aniState->mrcCCK ? "on" : "off",
1355                 aniState->listenTime,
1356                 aniState->ofdmPhyErrCount,
1357                 aniState->cckPhyErrCount);
1358         return true;
1359 }
1360
1361 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1362                               int16_t nfarray[NUM_NF_READINGS])
1363 {
1364 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1365 #define AR_PHY_CH_MINCCA_PWR_S  20
1366 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1367 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1368
1369         int16_t nf;
1370         int i;
1371
1372         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1373                 if (ah->rxchainmask & BIT(i)) {
1374                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1375                                          AR_PHY_CH_MINCCA_PWR);
1376                         nfarray[i] = sign_extend32(nf, 8);
1377
1378                         if (IS_CHAN_HT40(ah->curchan)) {
1379                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1380
1381                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1382                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1383                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1384                         }
1385                 }
1386         }
1387 }
1388
1389 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1390 {
1391         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1392         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1393         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1394         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1395         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1396         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1397
1398         if (AR_SREV_9330(ah))
1399                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1400
1401         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1402                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1403                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1404                 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1405                 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1406         }
1407 }
1408
1409 /*
1410  * Initialize the ANI register values with default (ini) values.
1411  * This routine is called during a (full) hardware reset after
1412  * all the registers are initialised from the INI.
1413  */
1414 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1415 {
1416         struct ar5416AniState *aniState;
1417         struct ath_common *common = ath9k_hw_common(ah);
1418         struct ath9k_channel *chan = ah->curchan;
1419         struct ath9k_ani_default *iniDef;
1420         u32 val;
1421
1422         aniState = &ah->ani;
1423         iniDef = &aniState->iniDef;
1424
1425         ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1426                 ah->hw_version.macVersion,
1427                 ah->hw_version.macRev,
1428                 ah->opmode,
1429                 chan->channel);
1430
1431         val = REG_READ(ah, AR_PHY_SFCORR);
1432         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1433         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1434         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1435
1436         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1437         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1438         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1439         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1440
1441         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1442         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1443         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1444         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1445         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1446         iniDef->firstep = REG_READ_FIELD(ah,
1447                                          AR_PHY_FIND_SIG,
1448                                          AR_PHY_FIND_SIG_FIRSTEP);
1449         iniDef->firstepLow = REG_READ_FIELD(ah,
1450                                             AR_PHY_FIND_SIG_LOW,
1451                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1452         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1453                                             AR_PHY_TIMING5,
1454                                             AR_PHY_TIMING5_CYCPWR_THR1);
1455         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1456                                                AR_PHY_EXT_CCA,
1457                                                AR_PHY_EXT_CYCPWR_THR1);
1458
1459         /* these levels just got reset to defaults by the INI */
1460         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1461         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1462         aniState->ofdmWeakSigDetect = true;
1463         aniState->mrcCCK = true;
1464 }
1465
1466 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1467                                        struct ath_hw_radar_conf *conf)
1468 {
1469         unsigned int regWrites = 0;
1470         u32 radar_0 = 0, radar_1;
1471
1472         if (!conf) {
1473                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1474                 return;
1475         }
1476
1477         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1478         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1479         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1480         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1481         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1482         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1483
1484         radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1485         radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1486                      AR_PHY_RADAR_1_RELPWR_THRESH);
1487         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1488         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1489         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1490         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1491         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1492
1493         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1494         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1495         if (conf->ext_channel)
1496                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1497         else
1498                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1499
1500         if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1501                 REG_WRITE_ARRAY(&ah->ini_dfs,
1502                                 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1503         }
1504 }
1505
1506 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1507 {
1508         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1509
1510         conf->fir_power = -28;
1511         conf->radar_rssi = 0;
1512         conf->pulse_height = 10;
1513         conf->pulse_rssi = 15;
1514         conf->pulse_inband = 8;
1515         conf->pulse_maxlen = 255;
1516         conf->pulse_inband_step = 12;
1517         conf->radar_inband = 8;
1518 }
1519
1520 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1521                                            struct ath_hw_antcomb_conf *antconf)
1522 {
1523         u32 regval;
1524
1525         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1526         antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1527                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1528         antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1529                                  AR_PHY_ANT_DIV_ALT_LNACONF_S;
1530         antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1531                                   AR_PHY_ANT_FAST_DIV_BIAS_S;
1532
1533         if (AR_SREV_9330_11(ah)) {
1534                 antconf->lna1_lna2_switch_delta = -1;
1535                 antconf->lna1_lna2_delta = -9;
1536                 antconf->div_group = 1;
1537         } else if (AR_SREV_9485(ah)) {
1538                 antconf->lna1_lna2_switch_delta = -1;
1539                 antconf->lna1_lna2_delta = -9;
1540                 antconf->div_group = 2;
1541         } else if (AR_SREV_9565(ah)) {
1542                 antconf->lna1_lna2_switch_delta = 3;
1543                 antconf->lna1_lna2_delta = -9;
1544                 antconf->div_group = 3;
1545         } else {
1546                 antconf->lna1_lna2_switch_delta = -1;
1547                 antconf->lna1_lna2_delta = -3;
1548                 antconf->div_group = 0;
1549         }
1550 }
1551
1552 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1553                                    struct ath_hw_antcomb_conf *antconf)
1554 {
1555         u32 regval;
1556
1557         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1558         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1559                     AR_PHY_ANT_DIV_ALT_LNACONF |
1560                     AR_PHY_ANT_FAST_DIV_BIAS |
1561                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1562                     AR_PHY_ANT_DIV_ALT_GAINTB);
1563         regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1564                    & AR_PHY_ANT_DIV_MAIN_LNACONF);
1565         regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1566                    & AR_PHY_ANT_DIV_ALT_LNACONF);
1567         regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1568                    & AR_PHY_ANT_FAST_DIV_BIAS);
1569         regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1570                    & AR_PHY_ANT_DIV_MAIN_GAINTB);
1571         regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1572                    & AR_PHY_ANT_DIV_ALT_GAINTB);
1573
1574         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1575 }
1576
1577 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1578
1579 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1580 {
1581         struct ath9k_hw_capabilities *pCap = &ah->caps;
1582         u8 ant_div_ctl1;
1583         u32 regval;
1584
1585         if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1586                 return;
1587
1588         if (AR_SREV_9485(ah)) {
1589                 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1590                                                  IS_CHAN_2GHZ(ah->curchan));
1591                 if (enable) {
1592                         regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1593                         regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1594                 }
1595                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1596                               AR_SWITCH_TABLE_COM2_ALL, regval);
1597         }
1598
1599         ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1600
1601         /*
1602          * Set MAIN/ALT LNA conf.
1603          * Set MAIN/ALT gain_tb.
1604          */
1605         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1606         regval &= (~AR_ANT_DIV_CTRL_ALL);
1607         regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1608         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1609
1610         if (AR_SREV_9485_11_OR_LATER(ah)) {
1611                 /*
1612                  * Enable LNA diversity.
1613                  */
1614                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1615                 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1616                 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1617                 if (enable)
1618                         regval |= AR_ANT_DIV_ENABLE;
1619
1620                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1621
1622                 /*
1623                  * Enable fast antenna diversity.
1624                  */
1625                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1626                 regval &= ~AR_FAST_DIV_ENABLE;
1627                 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1628                 if (enable)
1629                         regval |= AR_FAST_DIV_ENABLE;
1630
1631                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1632
1633                 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1634                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1635                         regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1636                                      AR_PHY_ANT_DIV_ALT_LNACONF |
1637                                      AR_PHY_ANT_DIV_ALT_GAINTB |
1638                                      AR_PHY_ANT_DIV_MAIN_GAINTB));
1639                         /*
1640                          * Set MAIN to LNA1 and ALT to LNA2 at the
1641                          * beginning.
1642                          */
1643                         regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1644                                    AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1645                         regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1646                                    AR_PHY_ANT_DIV_ALT_LNACONF_S);
1647                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1648                 }
1649         } else if (AR_SREV_9565(ah)) {
1650                 if (enable) {
1651                         REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1652                                     AR_ANT_DIV_ENABLE);
1653                         REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1654                                     (1 << AR_PHY_ANT_SW_RX_PROT_S));
1655                         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1656                                     AR_FAST_DIV_ENABLE);
1657                         REG_SET_BIT(ah, AR_PHY_RESTART,
1658                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1659                         REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1660                                     AR_BTCOEX_WL_LNADIV_FORCE_ON);
1661                 } else {
1662                         REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1663                                     AR_ANT_DIV_ENABLE);
1664                         REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1665                                     (1 << AR_PHY_ANT_SW_RX_PROT_S));
1666                         REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1667                                     AR_FAST_DIV_ENABLE);
1668                         REG_CLR_BIT(ah, AR_PHY_RESTART,
1669                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1670                         REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1671                                     AR_BTCOEX_WL_LNADIV_FORCE_ON);
1672
1673                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1674                         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1675                                     AR_PHY_ANT_DIV_ALT_LNACONF |
1676                                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1677                                     AR_PHY_ANT_DIV_ALT_GAINTB);
1678                         regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1679                                    AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1680                         regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1681                                    AR_PHY_ANT_DIV_ALT_LNACONF_S);
1682                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1683                 }
1684         }
1685 }
1686
1687 #endif
1688
1689 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1690                                       struct ath9k_channel *chan,
1691                                       u8 *ini_reloaded)
1692 {
1693         unsigned int regWrites = 0;
1694         u32 modesIndex, txgain_index;
1695
1696         if (IS_CHAN_5GHZ(chan))
1697                 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1698         else
1699                 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1700
1701         txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1702
1703         if (modesIndex == ah->modes_index) {
1704                 *ini_reloaded = false;
1705                 goto set_rfmode;
1706         }
1707
1708         ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1709         ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1710         ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1711         ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1712
1713         if (AR_SREV_9462_20_OR_LATER(ah))
1714                 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1715                                    modesIndex);
1716
1717         REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
1718
1719         if (AR_SREV_9462_20_OR_LATER(ah)) {
1720                 /*
1721                  * CUS217 mix LNA mode.
1722                  */
1723                 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1724                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1725                                         1, regWrites);
1726                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1727                                         modesIndex, regWrites);
1728                 }
1729         }
1730
1731         /*
1732          * For 5GHz channels requiring Fast Clock, apply
1733          * different modal values.
1734          */
1735         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1736                 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1737
1738         if (AR_SREV_9565(ah))
1739                 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1740
1741         /*
1742          * JAPAN regulatory.
1743          */
1744         if (chan->channel == 2484)
1745                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1746
1747         ah->modes_index = modesIndex;
1748         *ini_reloaded = true;
1749
1750 set_rfmode:
1751         ar9003_hw_set_rfmode(ah, chan);
1752         return 0;
1753 }
1754
1755 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1756                                            struct ath_spec_scan *param)
1757 {
1758         u8 count;
1759
1760         if (!param->enabled) {
1761                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1762                             AR_PHY_SPECTRAL_SCAN_ENABLE);
1763                 return;
1764         }
1765
1766         REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1767         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1768
1769         /* on AR93xx and newer, count = 0 will make the the chip send
1770          * spectral samples endlessly. Check if this really was intended,
1771          * and fix otherwise.
1772          */
1773         count = param->count;
1774         if (param->endless)
1775                 count = 0;
1776         else if (param->count == 0)
1777                 count = 1;
1778
1779         if (param->short_repeat)
1780                 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1781                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1782         else
1783                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1784                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1785
1786         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1787                       AR_PHY_SPECTRAL_SCAN_COUNT, count);
1788         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1789                       AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1790         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1791                       AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1792
1793         return;
1794 }
1795
1796 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1797 {
1798         /* Activate spectral scan */
1799         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1800                     AR_PHY_SPECTRAL_SCAN_ACTIVE);
1801 }
1802
1803 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1804 {
1805         struct ath_common *common = ath9k_hw_common(ah);
1806
1807         /* Poll for spectral scan complete */
1808         if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1809                            AR_PHY_SPECTRAL_SCAN_ACTIVE,
1810                            0, AH_WAIT_TIMEOUT)) {
1811                 ath_err(common, "spectral scan wait failed\n");
1812                 return;
1813         }
1814 }
1815
1816 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1817 {
1818         REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1819         REG_SET_BIT(ah, 0x9864, 0x7f000);
1820         REG_SET_BIT(ah, 0x9924, 0x7f00fe);
1821         REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1822         REG_WRITE(ah, AR_CR, AR_CR_RXD);
1823         REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1824         REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1825         REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1826         REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1827         REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1828         REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1829 }
1830
1831 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1832 {
1833         REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1834         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1835 }
1836
1837 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1838 {
1839         static s16 p_pwr_array[ar9300RateSize] = { 0 };
1840         unsigned int i;
1841
1842         if (txpower <= MAX_RATE_POWER) {
1843                 for (i = 0; i < ar9300RateSize; i++)
1844                         p_pwr_array[i] = txpower;
1845         } else {
1846                 for (i = 0; i < ar9300RateSize; i++)
1847                         p_pwr_array[i] = MAX_RATE_POWER;
1848         }
1849
1850         REG_WRITE(ah, 0xa458, 0);
1851
1852         REG_WRITE(ah, 0xa3c0,
1853                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
1854                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
1855                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24],  8) |
1856                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24],  0));
1857         REG_WRITE(ah, 0xa3c4,
1858                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54],  24) |
1859                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48],  16) |
1860                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36],   8) |
1861                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1862         REG_WRITE(ah, 0xa3c8,
1863                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
1864                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
1865                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L],  0));
1866         REG_WRITE(ah, 0xa3cc,
1867                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S],   24) |
1868                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L],   16) |
1869                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S],     8) |
1870                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L],  0));
1871         REG_WRITE(ah, 0xa3d0,
1872                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5],  24) |
1873                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4],  16) |
1874                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
1875                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
1876         REG_WRITE(ah, 0xa3d4,
1877                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
1878                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
1879                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7],   8) |
1880                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6],   0));
1881         REG_WRITE(ah, 0xa3e4,
1882                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
1883                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
1884                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15],  8) |
1885                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14],  0));
1886         REG_WRITE(ah, 0xa3e8,
1887                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
1888                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
1889                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23],  8) |
1890                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22],  0));
1891         REG_WRITE(ah, 0xa3d8,
1892                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
1893                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
1894                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1895                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
1896         REG_WRITE(ah, 0xa3dc,
1897                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
1898                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
1899                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7],   8) |
1900                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6],   0));
1901         REG_WRITE(ah, 0xa3ec,
1902                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
1903                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
1904                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15],  8) |
1905                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14],  0));
1906 }
1907
1908 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
1909 {
1910         ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1911         ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1912         ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
1913                               rate_array[ALL_TARGET_LEGACY_5S]);
1914         ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
1915                               rate_array[ALL_TARGET_LEGACY_11S]);
1916 }
1917
1918 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
1919                                         int offset)
1920 {
1921         int i, j;
1922
1923         for (i = offset; i < offset + AR9300_OFDM_RATES; i++) {
1924                 /* OFDM rate to power table idx */
1925                 j = ofdm2pwr[i - offset];
1926                 ah->tx_power[i] = rate_array[j];
1927         }
1928 }
1929
1930 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
1931                                       int ss_offset, int ds_offset,
1932                                       int ts_offset, bool is_40)
1933 {
1934         int i, j, mcs_idx = 0;
1935         const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20;
1936
1937         for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) {
1938                 j = mcs2pwr[mcs_idx];
1939                 ah->tx_power[i] = rate_array[j];
1940                 mcs_idx++;
1941         }
1942
1943         for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) {
1944                 j = mcs2pwr[mcs_idx];
1945                 ah->tx_power[i] = rate_array[j];
1946                 mcs_idx++;
1947         }
1948
1949         for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) {
1950                 j = mcs2pwr[mcs_idx];
1951                 ah->tx_power[i] = rate_array[j];
1952                 mcs_idx++;
1953         }
1954 }
1955
1956 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
1957                                         int ds_offset, int ts_offset)
1958 {
1959         memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
1960                AR9300_HT_SS_RATES);
1961         memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
1962                AR9300_HT_DS_RATES);
1963         memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
1964                AR9300_HT_TS_RATES);
1965 }
1966
1967 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1968                                  struct ath9k_channel *chan)
1969 {
1970         if (IS_CHAN_5GHZ(chan)) {
1971                 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1972                                             AR9300_11NA_OFDM_SHIFT);
1973                 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1974                         ar9003_hw_init_txpower_ht(ah, rate_array,
1975                                                   AR9300_11NA_HT_SS_SHIFT,
1976                                                   AR9300_11NA_HT_DS_SHIFT,
1977                                                   AR9300_11NA_HT_TS_SHIFT,
1978                                                   IS_CHAN_HT40(chan));
1979                         ar9003_hw_init_txpower_stbc(ah,
1980                                                     AR9300_11NA_HT_SS_SHIFT,
1981                                                     AR9300_11NA_HT_DS_SHIFT,
1982                                                     AR9300_11NA_HT_TS_SHIFT);
1983                 }
1984         } else {
1985                 ar9003_hw_init_txpower_cck(ah, rate_array);
1986                 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1987                                             AR9300_11NG_OFDM_SHIFT);
1988                 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1989                         ar9003_hw_init_txpower_ht(ah, rate_array,
1990                                                   AR9300_11NG_HT_SS_SHIFT,
1991                                                   AR9300_11NG_HT_DS_SHIFT,
1992                                                   AR9300_11NG_HT_TS_SHIFT,
1993                                                   IS_CHAN_HT40(chan));
1994                         ar9003_hw_init_txpower_stbc(ah,
1995                                                     AR9300_11NG_HT_SS_SHIFT,
1996                                                     AR9300_11NG_HT_DS_SHIFT,
1997                                                     AR9300_11NG_HT_TS_SHIFT);
1998                 }
1999         }
2000 }
2001
2002 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
2003 {
2004         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
2005         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
2006         static const u32 ar9300_cca_regs[6] = {
2007                 AR_PHY_CCA_0,
2008                 AR_PHY_CCA_1,
2009                 AR_PHY_CCA_2,
2010                 AR_PHY_EXT_CCA,
2011                 AR_PHY_EXT_CCA_1,
2012                 AR_PHY_EXT_CCA_2,
2013         };
2014
2015         priv_ops->rf_set_freq = ar9003_hw_set_channel;
2016         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
2017
2018         if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
2019             AR_SREV_9561(ah))
2020                 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
2021         else
2022                 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
2023
2024         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
2025         priv_ops->init_bb = ar9003_hw_init_bb;
2026         priv_ops->process_ini = ar9003_hw_process_ini;
2027         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
2028         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
2029         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
2030         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
2031         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
2032         priv_ops->ani_control = ar9003_hw_ani_control;
2033         priv_ops->do_getnf = ar9003_hw_do_getnf;
2034         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
2035         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
2036         priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
2037
2038         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
2039         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
2040         ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
2041         ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
2042         ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
2043
2044 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2045         ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
2046 #endif
2047         ops->tx99_start = ar9003_hw_tx99_start;
2048         ops->tx99_stop = ar9003_hw_tx99_stop;
2049         ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
2050
2051         ar9003_hw_set_nf_limits(ah);
2052         ar9003_hw_set_radar_conf(ah);
2053         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
2054 }
2055
2056 /*
2057  * Baseband Watchdog signatures:
2058  *
2059  * 0x04000539: BB hang when operating in HT40 DFS Channel.
2060  *             Full chip reset is not required, but a recovery
2061  *             mechanism is needed.
2062  *
2063  * 0x1300000a: Related to CAC deafness.
2064  *             Chip reset is not required.
2065  *
2066  * 0x0400000a: Related to CAC deafness.
2067  *             Full chip reset is required.
2068  *
2069  * 0x04000b09: RX state machine gets into an illegal state
2070  *             when a packet with unsupported rate is received.
2071  *             Full chip reset is required and PHY_RESTART has
2072  *             to be disabled.
2073  *
2074  * 0x04000409: Packet stuck on receive.
2075  *             Full chip reset is required for all chips except AR9340.
2076  */
2077
2078 /*
2079  * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
2080  */
2081 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
2082 {
2083         u32 val;
2084
2085         switch(ah->bb_watchdog_last_status) {
2086         case 0x04000539:
2087                 val = REG_READ(ah, AR_PHY_RADAR_0);
2088                 val &= (~AR_PHY_RADAR_0_FIRPWR);
2089                 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
2090                 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2091                 udelay(1);
2092                 val = REG_READ(ah, AR_PHY_RADAR_0);
2093                 val &= ~AR_PHY_RADAR_0_FIRPWR;
2094                 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
2095                 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2096
2097                 return false;
2098         case 0x1300000a:
2099                 return false;
2100         case 0x0400000a:
2101         case 0x04000b09:
2102                 return true;
2103         case 0x04000409:
2104                 if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
2105                         return false;
2106                 else
2107                         return true;
2108         default:
2109                 /*
2110                  * For any other unknown signatures, do a
2111                  * full chip reset.
2112                  */
2113                 return true;
2114         }
2115 }
2116 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
2117
2118 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
2119 {
2120         struct ath_common *common = ath9k_hw_common(ah);
2121         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
2122         u32 val, idle_count;
2123
2124         if (!idle_tmo_ms) {
2125                 /* disable IRQ, disable chip-reset for BB panic */
2126                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2127                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
2128                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
2129                             AR_PHY_WATCHDOG_IRQ_ENABLE));
2130
2131                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
2132                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2133                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
2134                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2135                             AR_PHY_WATCHDOG_IDLE_ENABLE));
2136
2137                 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
2138                 return;
2139         }
2140
2141         /* enable IRQ, disable chip-reset for BB watchdog */
2142         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
2143         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2144                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
2145                   ~AR_PHY_WATCHDOG_RST_ENABLE);
2146
2147         /* bound limit to 10 secs */
2148         if (idle_tmo_ms > 10000)
2149                 idle_tmo_ms = 10000;
2150
2151         /*
2152          * The time unit for watchdog event is 2^15 44/88MHz cycles.
2153          *
2154          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
2155          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
2156          *
2157          * Given we use fast clock now in 5 GHz, these time units should
2158          * be common for both 2 GHz and 5 GHz.
2159          */
2160         idle_count = (100 * idle_tmo_ms) / 74;
2161         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
2162                 idle_count = (100 * idle_tmo_ms) / 37;
2163
2164         /*
2165          * enable watchdog in non-IDLE mode, disable in IDLE mode,
2166          * set idle time-out.
2167          */
2168         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2169                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2170                   AR_PHY_WATCHDOG_IDLE_MASK |
2171                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
2172
2173         ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
2174                 idle_tmo_ms);
2175 }
2176
2177 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
2178 {
2179         /*
2180          * we want to avoid printing in ISR context so we save the
2181          * watchdog status to be printed later in bottom half context.
2182          */
2183         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
2184
2185         /*
2186          * the watchdog timer should reset on status read but to be sure
2187          * sure we write 0 to the watchdog status bit.
2188          */
2189         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
2190                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
2191 }
2192
2193 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
2194 {
2195         struct ath_common *common = ath9k_hw_common(ah);
2196         u32 status;
2197
2198         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
2199                 return;
2200
2201         status = ah->bb_watchdog_last_status;
2202         ath_dbg(common, RESET,
2203                 "\n==== BB update: BB status=0x%08x ====\n", status);
2204         ath_dbg(common, RESET,
2205                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
2206                 MS(status, AR_PHY_WATCHDOG_INFO),
2207                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
2208                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
2209                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
2210                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
2211                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
2212                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
2213                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
2214                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
2215
2216         ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
2217                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
2218                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
2219         ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
2220                 REG_READ(ah, AR_PHY_GEN_CTRL));
2221
2222 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
2223         if (common->cc_survey.cycles)
2224                 ath_dbg(common, RESET,
2225                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
2226                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
2227
2228         ath_dbg(common, RESET, "==== BB update: done ====\n\n");
2229 }
2230 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
2231
2232 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
2233 {
2234         u8 result;
2235         u32 val;
2236
2237         /* While receiving unsupported rate frame rx state machine
2238          * gets into a state 0xb and if phy_restart happens in that
2239          * state, BB would go hang. If RXSM is in 0xb state after
2240          * first bb panic, ensure to disable the phy_restart.
2241          */
2242         result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
2243
2244         if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2245                 ah->bb_hang_rx_ofdm = true;
2246                 val = REG_READ(ah, AR_PHY_RESTART);
2247                 val &= ~AR_PHY_RESTART_ENA;
2248                 REG_WRITE(ah, AR_PHY_RESTART, val);
2249         }
2250 }
2251 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);