drivers/net/wireless/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <asm/unaligned.h>
  26
  27 #include <soc.h>
  28 #include <chipcommon.h>
  29 #include <brcmu_utils.h>
  30 #include <brcmu_wifi.h>
  31 #include <brcm_hw_ids.h>
  32
  33 #include "debug.h"
  34 #include "bus.h"
  35 #include "commonring.h"
  36 #include "msgbuf.h"
  37 #include "pcie.h"
  38 #include "firmware.h"
  39 #include "chip.h"
  40
  41
  42 enum brcmf_pcie_state {
  43         BRCMFMAC_PCIE_STATE_DOWN,
  44         BRCMFMAC_PCIE_STATE_UP
  45 };
  46
  47
  48 #define BRCMF_PCIE_43602_FW_NAME                "brcm/brcmfmac43602-pcie.bin"
  49 #define BRCMF_PCIE_43602_NVRAM_NAME             "brcm/brcmfmac43602-pcie.txt"
  50 #define BRCMF_PCIE_4350_FW_NAME                 "brcm/brcmfmac4350-pcie.bin"
  51 #define BRCMF_PCIE_4350_NVRAM_NAME              "brcm/brcmfmac4350-pcie.txt"
  52 #define BRCMF_PCIE_4356_FW_NAME                 "brcm/brcmfmac4356-pcie.bin"
  53 #define BRCMF_PCIE_4356_NVRAM_NAME              "brcm/brcmfmac4356-pcie.txt"
  54 #define BRCMF_PCIE_43570_FW_NAME                "brcm/brcmfmac43570-pcie.bin"
  55 #define BRCMF_PCIE_43570_NVRAM_NAME             "brcm/brcmfmac43570-pcie.txt"
  56 #define BRCMF_PCIE_4358_FW_NAME                 "brcm/brcmfmac4358-pcie.bin"
  57 #define BRCMF_PCIE_4358_NVRAM_NAME              "brcm/brcmfmac4358-pcie.txt"
  58 #define BRCMF_PCIE_4365_FW_NAME                 "brcm/brcmfmac4365b-pcie.bin"
  59 #define BRCMF_PCIE_4365_NVRAM_NAME              "brcm/brcmfmac4365b-pcie.txt"
  60 #define BRCMF_PCIE_4366_FW_NAME                 "brcm/brcmfmac4366b-pcie.bin"
  61 #define BRCMF_PCIE_4366_NVRAM_NAME              "brcm/brcmfmac4366b-pcie.txt"
  62 #define BRCMF_PCIE_4371_FW_NAME                 "brcm/brcmfmac4371-pcie.bin"
  63 #define BRCMF_PCIE_4371_NVRAM_NAME              "brcm/brcmfmac4371-pcie.txt"
  64
  65 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  66
  67 #define BRCMF_PCIE_TCM_MAP_SIZE                 (4096 * 1024)
  68 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  69
  70 /* backplane addres space accessed by BAR0 */
  71 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  72 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  73 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  74
  75 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  76 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  77
  78 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  79 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  80
  81 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  82 #define BRCMF_PCIE_REG_INTMASK                  0x94
  83 #define BRCMF_PCIE_REG_SBMBX                    0x98
  84
  85 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
  86
  87 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
  88 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
  89 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
  90 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
  91 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
  92 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
  93
  94 #define BRCMF_PCIE_GENREV1                      1
  95 #define BRCMF_PCIE_GENREV2                      2
  96
  97 #define BRCMF_PCIE2_INTA                        0x01
  98 #define BRCMF_PCIE2_INTB                        0x02
  99
 100 #define BRCMF_PCIE_INT_0                        0x01
 101 #define BRCMF_PCIE_INT_1                        0x02
 102 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 103                                                  BRCMF_PCIE_INT_1)
 104
 105 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 106 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 107 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 108 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 109 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 110 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 111 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 112 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 113 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 114 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 115
 116 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 117                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 118                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 119                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 120                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 121                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 122                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 123                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 124
 125 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 126 #define BRCMF_PCIE_MAX_SHARED_VERSION           5
 127 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 128 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 129 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 130
 131 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 132 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 133
 134 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 135 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 136 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 137 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 138 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 139 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 140 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 141 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 142 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 143 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 144 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 145
 146 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 147 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 148 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 149 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 150
 151 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 152 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 153 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 154 #define BRCMF_RING_MEM_SZ                       16
 155 #define BRCMF_RING_STATE_SZ                     8
 156
 157 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET  4
 158 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET  8
 159 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET  12
 160 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET  16
 161 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET   20
 162 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET   28
 163 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET   36
 164 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET   44
 165 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET     0
 166 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES        52
 167
 168 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 169
 170 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 171 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 172 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 173
 174 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 175 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 176
 177 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 178 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 179 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 180
 181 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 182 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 183 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 184 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 185
 186 #define BRCMF_PCIE_MBDATA_TIMEOUT               2000
 187
 188 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 189 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 190 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 191 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 192 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 193 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 194 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 195 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 196 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 197 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 198 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 199 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 200 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 201
 202
 203 MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
 204 MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
 205 MODULE_FIRMWARE(BRCMF_PCIE_4350_FW_NAME);
 206 MODULE_FIRMWARE(BRCMF_PCIE_4350_NVRAM_NAME);
 207 MODULE_FIRMWARE(BRCMF_PCIE_4356_FW_NAME);
 208 MODULE_FIRMWARE(BRCMF_PCIE_4356_NVRAM_NAME);
 209 MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
 210 MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
 211 MODULE_FIRMWARE(BRCMF_PCIE_4358_FW_NAME);
 212 MODULE_FIRMWARE(BRCMF_PCIE_4358_NVRAM_NAME);
 213 MODULE_FIRMWARE(BRCMF_PCIE_4365_FW_NAME);
 214 MODULE_FIRMWARE(BRCMF_PCIE_4365_NVRAM_NAME);
 215 MODULE_FIRMWARE(BRCMF_PCIE_4366_FW_NAME);
 216 MODULE_FIRMWARE(BRCMF_PCIE_4366_NVRAM_NAME);
 217 MODULE_FIRMWARE(BRCMF_PCIE_4371_FW_NAME);
 218 MODULE_FIRMWARE(BRCMF_PCIE_4371_NVRAM_NAME);
 219
 220
 221 struct brcmf_pcie_console {
 222         u32 base_addr;
 223         u32 buf_addr;
 224         u32 bufsize;
 225         u32 read_idx;
 226         u8 log_str[256];
 227         u8 log_idx;
 228 };
 229
 230 struct brcmf_pcie_shared_info {
 231         u32 tcm_base_address;
 232         u32 flags;
 233         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 234         struct brcmf_pcie_ringbuf *flowrings;
 235         u16 max_rxbufpost;
 236         u32 nrof_flowrings;
 237         u32 rx_dataoffset;
 238         u32 htod_mb_data_addr;
 239         u32 dtoh_mb_data_addr;
 240         u32 ring_info_addr;
 241         struct brcmf_pcie_console console;
 242         void *scratch;
 243         dma_addr_t scratch_dmahandle;
 244         void *ringupd;
 245         dma_addr_t ringupd_dmahandle;
 246 };
 247
 248 struct brcmf_pcie_core_info {
 249         u32 base;
 250         u32 wrapbase;
 251 };
 252
 253 struct brcmf_pciedev_info {
 254         enum brcmf_pcie_state state;
 255         bool in_irq;
 256         bool irq_requested;
 257         struct pci_dev *pdev;
 258         char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 259         char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 260         void __iomem *regs;
 261         void __iomem *tcm;
 262         u32 tcm_size;
 263         u32 ram_base;
 264         u32 ram_size;
 265         struct brcmf_chip *ci;
 266         u32 coreid;
 267         u32 generic_corerev;
 268         struct brcmf_pcie_shared_info shared;
 269         void (*ringbell)(struct brcmf_pciedev_info *devinfo);
 270         wait_queue_head_t mbdata_resp_wait;
 271         bool mbdata_completed;
 272         bool irq_allocated;
 273         bool wowl_enabled;
 274         u8 dma_idx_sz;
 275         void *idxbuf;
 276         u32 idxbuf_sz;
 277         dma_addr_t idxbuf_dmahandle;
 278         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 279         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 280                           u16 value);
 281 };
 282
 283 struct brcmf_pcie_ringbuf {
 284         struct brcmf_commonring commonring;
 285         dma_addr_t dma_handle;
 286         u32 w_idx_addr;
 287         u32 r_idx_addr;
 288         struct brcmf_pciedev_info *devinfo;
 289         u8 id;
 290 };
 291
 292
 293 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 294         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 295         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 296         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 297         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 298         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 299 };
 300
 301 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 302         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 303         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 304         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 305         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 306         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 307 };
 308
 309
 310 static u32
 311 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 312 {
 313         void __iomem *address = devinfo->regs + reg_offset;
 314
 315         return (ioread32(address));
 316 }
 317
 318
 319 static void
 320 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 321                        u32 value)
 322 {
 323         void __iomem *address = devinfo->regs + reg_offset;
 324
 325         iowrite32(value, address);
 326 }
 327
 328
 329 static u8
 330 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 331 {
 332         void __iomem *address = devinfo->tcm + mem_offset;
 333
 334         return (ioread8(address));
 335 }
 336
 337
 338 static u16
 339 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 340 {
 341         void __iomem *address = devinfo->tcm + mem_offset;
 342
 343         return (ioread16(address));
 344 }
 345
 346
 347 static void
 348 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 349                        u16 value)
 350 {
 351         void __iomem *address = devinfo->tcm + mem_offset;
 352
 353         iowrite16(value, address);
 354 }
 355
 356
 357 static u16
 358 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 359 {
 360         u16 *address = devinfo->idxbuf + mem_offset;
 361
 362         return (*(address));
 363 }
 364
 365
 366 static void
 367 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 368                      u16 value)
 369 {
 370         u16 *address = devinfo->idxbuf + mem_offset;
 371
 372         *(address) = value;
 373 }
 374
 375
 376 static u32
 377 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 378 {
 379         void __iomem *address = devinfo->tcm + mem_offset;
 380
 381         return (ioread32(address));
 382 }
 383
 384
 385 static void
 386 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 387                        u32 value)
 388 {
 389         void __iomem *address = devinfo->tcm + mem_offset;
 390
 391         iowrite32(value, address);
 392 }
 393
 394
 395 static u32
 396 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 397 {
 398         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 399
 400         return (ioread32(addr));
 401 }
 402
 403
 404 static void
 405 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 406                        u32 value)
 407 {
 408         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 409
 410         iowrite32(value, addr);
 411 }
 412
 413
 414 static void
 415 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 416                           void *srcaddr, u32 len)
 417 {
 418         void __iomem *address = devinfo->tcm + mem_offset;
 419         __le32 *src32;
 420         __le16 *src16;
 421         u8 *src8;
 422
 423         if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 424                 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 425                         src8 = (u8 *)srcaddr;
 426                         while (len) {
 427                                 iowrite8(*src8, address);
 428                                 address++;
 429                                 src8++;
 430                                 len--;
 431                         }
 432                 } else {
 433                         len = len / 2;
 434                         src16 = (__le16 *)srcaddr;
 435                         while (len) {
 436                                 iowrite16(le16_to_cpu(*src16), address);
 437                                 address += 2;
 438                                 src16++;
 439                                 len--;
 440                         }
 441                 }
 442         } else {
 443                 len = len / 4;
 444                 src32 = (__le32 *)srcaddr;
 445                 while (len) {
 446                         iowrite32(le32_to_cpu(*src32), address);
 447                         address += 4;
 448                         src32++;
 449                         len--;
 450                 }
 451         }
 452 }
 453
 454
 455 static void
 456 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 457                           void *dstaddr, u32 len)
 458 {
 459         void __iomem *address = devinfo->tcm + mem_offset;
 460         __le32 *dst32;
 461         __le16 *dst16;
 462         u8 *dst8;
 463
 464         if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 465                 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 466                         dst8 = (u8 *)dstaddr;
 467                         while (len) {
 468                                 *dst8 = ioread8(address);
 469                                 address++;
 470                                 dst8++;
 471                                 len--;
 472                         }
 473                 } else {
 474                         len = len / 2;
 475                         dst16 = (__le16 *)dstaddr;
 476                         while (len) {
 477                                 *dst16 = cpu_to_le16(ioread16(address));
 478                                 address += 2;
 479                                 dst16++;
 480                                 len--;
 481                         }
 482                 }
 483         } else {
 484                 len = len / 4;
 485                 dst32 = (__le32 *)dstaddr;
 486                 while (len) {
 487                         *dst32 = cpu_to_le32(ioread32(address));
 488                         address += 4;
 489                         dst32++;
 490                         len--;
 491                 }
 492         }
 493 }
 494
 495
 496 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 497                 CHIPCREGOFFS(reg), value)
 498
 499
 500 static void
 501 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 502 {
 503         const struct pci_dev *pdev = devinfo->pdev;
 504         struct brcmf_core *core;
 505         u32 bar0_win;
 506
 507         core = brcmf_chip_get_core(devinfo->ci, coreid);
 508         if (core) {
 509                 bar0_win = core->base;
 510                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 511                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 512                                           &bar0_win) == 0) {
 513                         if (bar0_win != core->base) {
 514                                 bar0_win = core->base;
 515                                 pci_write_config_dword(pdev,
 516                                                        BRCMF_PCIE_BAR0_WINDOW,
 517                                                        bar0_win);
 518                         }
 519                 }
 520         } else {
 521                 brcmf_err("Unsupported core selected %x\n", coreid);
 522         }
 523 }
 524
 525
 526 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 527 {
 528         struct brcmf_core *core;
 529         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 530                              BRCMF_PCIE_CFGREG_PM_CSR,
 531                              BRCMF_PCIE_CFGREG_MSI_CAP,
 532                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 533                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 534                              BRCMF_PCIE_CFGREG_MSI_DATA,
 535                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 536                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 537                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 538                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 539                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 540         u32 i;
 541         u32 val;
 542         u32 lsc;
 543
 544         if (!devinfo->ci)
 545                 return;
 546
 547         /* Disable ASPM */
 548         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 549         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 550                               &lsc);
 551         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 552         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 553                                val);
 554
 555         /* Watchdog reset */
 556         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 557         WRITECC32(devinfo, watchdog, 4);
 558         msleep(100);
 559
 560         /* Restore ASPM */
 561         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 562         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 563                                lsc);
 564
 565         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 566         if (core->rev <= 13) {
 567                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 568                         brcmf_pcie_write_reg32(devinfo,
 569                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 570                                                cfg_offset[i]);
 571                         val = brcmf_pcie_read_reg32(devinfo,
 572                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 573                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 574                                   cfg_offset[i], val);
 575                         brcmf_pcie_write_reg32(devinfo,
 576                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 577                                                val);
 578                 }
 579         }
 580 }
 581
 582
 583 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 584 {
 585         u32 config;
 586
 587         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 588         /* BAR1 window may not be sized properly */
 589         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 590         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 591         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 592         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 593
 594         device_wakeup_enable(&devinfo->pdev->dev);
 595 }
 596
 597
 598 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 599 {
 600         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 601                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 602                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 603                                        5);
 604                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 605                                        0);
 606                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 607                                        7);
 608                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 609                                        0);
 610         }
 611         return 0;
 612 }
 613
 614
 615 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 616                                           u32 resetintr)
 617 {
 618         struct brcmf_core *core;
 619
 620         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 621                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 622                 brcmf_chip_resetcore(core, 0, 0, 0);
 623         }
 624
 625         return !brcmf_chip_set_active(devinfo->ci, resetintr);
 626 }
 627
 628
 629 static int
 630 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 631 {
 632         struct brcmf_pcie_shared_info *shared;
 633         u32 addr;
 634         u32 cur_htod_mb_data;
 635         u32 i;
 636
 637         shared = &devinfo->shared;
 638         addr = shared->htod_mb_data_addr;
 639         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 640
 641         if (cur_htod_mb_data != 0)
 642                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 643                           cur_htod_mb_data);
 644
 645         i = 0;
 646         while (cur_htod_mb_data != 0) {
 647                 msleep(10);
 648                 i++;
 649                 if (i > 100)
 650                         return -EIO;
 651                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 652         }
 653
 654         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 655         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 656         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 657
 658         return 0;
 659 }
 660
 661
 662 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 663 {
 664         struct brcmf_pcie_shared_info *shared;
 665         u32 addr;
 666         u32 dtoh_mb_data;
 667
 668         shared = &devinfo->shared;
 669         addr = shared->dtoh_mb_data_addr;
 670         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 671
 672         if (!dtoh_mb_data)
 673                 return;
 674
 675         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 676
 677         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 678         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 679                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 680                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 681                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 682         }
 683         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 684                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 685         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 686                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 687                 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
 688                         devinfo->mbdata_completed = true;
 689                         wake_up(&devinfo->mbdata_resp_wait);
 690                 }
 691         }
 692 }
 693
 694
 695 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 696 {
 697         struct brcmf_pcie_shared_info *shared;
 698         struct brcmf_pcie_console *console;
 699         u32 addr;
 700
 701         shared = &devinfo->shared;
 702         console = &shared->console;
 703         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 704         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 705
 706         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 707         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 708         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 709         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 710
 711         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 712                   console->base_addr, console->buf_addr, console->bufsize);
 713 }
 714
 715
 716 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 717 {
 718         struct brcmf_pcie_console *console;
 719         u32 addr;
 720         u8 ch;
 721         u32 newidx;
 722
 723         if (!BRCMF_FWCON_ON())
 724                 return;
 725
 726         console = &devinfo->shared.console;
 727         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 728         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 729         while (newidx != console->read_idx) {
 730                 addr = console->buf_addr + console->read_idx;
 731                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 732                 console->read_idx++;
 733                 if (console->read_idx == console->bufsize)
 734                         console->read_idx = 0;
 735                 if (ch == '\r')
 736                         continue;
 737                 console->log_str[console->log_idx] = ch;
 738                 console->log_idx++;
 739                 if ((ch != '\n') &&
 740                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 741                         ch = '\n';
 742                         console->log_str[console->log_idx] = ch;
 743                         console->log_idx++;
 744                 }
 745                 if (ch == '\n') {
 746                         console->log_str[console->log_idx] = 0;
 747                         pr_debug("CONSOLE: %s", console->log_str);
 748                         console->log_idx = 0;
 749                 }
 750         }
 751 }
 752
 753
 754 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
 755 {
 756         u32 reg_value;
 757
 758         brcmf_dbg(PCIE, "RING !\n");
 759         reg_value = brcmf_pcie_read_reg32(devinfo,
 760                                           BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 761         reg_value |= BRCMF_PCIE2_INTB;
 762         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 763                                reg_value);
 764 }
 765
 766
 767 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
 768 {
 769         brcmf_dbg(PCIE, "RING !\n");
 770         /* Any arbitrary value will do, lets use 1 */
 771         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 772 }
 773
 774
 775 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 776 {
 777         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 778                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 779                                        0);
 780         else
 781                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 782                                        0);
 783 }
 784
 785
 786 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 787 {
 788         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 789                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 790                                        BRCMF_PCIE_INT_DEF);
 791         else
 792                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 793                                        BRCMF_PCIE_MB_INT_D2H_DB |
 794                                        BRCMF_PCIE_MB_INT_FN0_0 |
 795                                        BRCMF_PCIE_MB_INT_FN0_1);
 796 }
 797
 798
 799 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
 800 {
 801         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 802         u32 status;
 803
 804         status = 0;
 805         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 806         if (status) {
 807                 brcmf_pcie_intr_disable(devinfo);
 808                 brcmf_dbg(PCIE, "Enter\n");
 809                 return IRQ_WAKE_THREAD;
 810         }
 811         return IRQ_NONE;
 812 }
 813
 814
 815 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 816 {
 817         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 818
 819         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 820                 brcmf_pcie_intr_disable(devinfo);
 821                 brcmf_dbg(PCIE, "Enter\n");
 822                 return IRQ_WAKE_THREAD;
 823         }
 824         return IRQ_NONE;
 825 }
 826
 827
 828 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 829 {
 830         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 831         const struct pci_dev *pdev = devinfo->pdev;
 832         u32 status;
 833
 834         devinfo->in_irq = true;
 835         status = 0;
 836         pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 837         brcmf_dbg(PCIE, "Enter %x\n", status);
 838         if (status) {
 839                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 840                 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 841                         brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 842         }
 843         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 844                 brcmf_pcie_intr_enable(devinfo);
 845         devinfo->in_irq = false;
 846         return IRQ_HANDLED;
 847 }
 848
 849
 850 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 851 {
 852         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 853         u32 status;
 854
 855         devinfo->in_irq = true;
 856         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 857         brcmf_dbg(PCIE, "Enter %x\n", status);
 858         if (status) {
 859                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 860                                        status);
 861                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 862                               BRCMF_PCIE_MB_INT_FN0_1))
 863                         brcmf_pcie_handle_mb_data(devinfo);
 864                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 865                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 866                                 brcmf_proto_msgbuf_rx_trigger(
 867                                                         &devinfo->pdev->dev);
 868                 }
 869         }
 870         brcmf_pcie_bus_console_read(devinfo);
 871         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 872                 brcmf_pcie_intr_enable(devinfo);
 873         devinfo->in_irq = false;
 874         return IRQ_HANDLED;
 875 }
 876
 877
 878 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 879 {
 880         struct pci_dev *pdev;
 881
 882         pdev = devinfo->pdev;
 883
 884         brcmf_pcie_intr_disable(devinfo);
 885
 886         brcmf_dbg(PCIE, "Enter\n");
 887         /* is it a v1 or v2 implementation */
 888         devinfo->irq_requested = false;
 889         pci_enable_msi(pdev);
 890         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 891                 if (request_threaded_irq(pdev->irq,
 892                                          brcmf_pcie_quick_check_isr_v1,
 893                                          brcmf_pcie_isr_thread_v1,
 894                                          IRQF_SHARED, "brcmf_pcie_intr",
 895                                          devinfo)) {
 896                         pci_disable_msi(pdev);
 897                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 898                         return -EIO;
 899                 }
 900         } else {
 901                 if (request_threaded_irq(pdev->irq,
 902                                          brcmf_pcie_quick_check_isr_v2,
 903                                          brcmf_pcie_isr_thread_v2,
 904                                          IRQF_SHARED, "brcmf_pcie_intr",
 905                                          devinfo)) {
 906                         pci_disable_msi(pdev);
 907                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 908                         return -EIO;
 909                 }
 910         }
 911         devinfo->irq_requested = true;
 912         devinfo->irq_allocated = true;
 913         return 0;
 914 }
 915
 916
 917 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 918 {
 919         struct pci_dev *pdev;
 920         u32 status;
 921         u32 count;
 922
 923         if (!devinfo->irq_allocated)
 924                 return;
 925
 926         pdev = devinfo->pdev;
 927
 928         brcmf_pcie_intr_disable(devinfo);
 929         if (!devinfo->irq_requested)
 930                 return;
 931         devinfo->irq_requested = false;
 932         free_irq(pdev->irq, devinfo);
 933         pci_disable_msi(pdev);
 934
 935         msleep(50);
 936         count = 0;
 937         while ((devinfo->in_irq) && (count < 20)) {
 938                 msleep(50);
 939                 count++;
 940         }
 941         if (devinfo->in_irq)
 942                 brcmf_err("Still in IRQ (processing) !!!\n");
 943
 944         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 945                 status = 0;
 946                 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 947                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 948         } else {
 949                 status = brcmf_pcie_read_reg32(devinfo,
 950                                                BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 951                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 952                                        status);
 953         }
 954         devinfo->irq_allocated = false;
 955 }
 956
 957
 958 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 959 {
 960         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 961         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 962         struct brcmf_commonring *commonring = &ring->commonring;
 963
 964         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 965                 return -EIO;
 966
 967         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 968                   commonring->w_ptr, ring->id);
 969
 970         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 971
 972         return 0;
 973 }
 974
 975
 976 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 977 {
 978         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 979         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 980         struct brcmf_commonring *commonring = &ring->commonring;
 981
 982         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 983                 return -EIO;
 984
 985         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 986                   commonring->r_ptr, ring->id);
 987
 988         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 989
 990         return 0;
 991 }
 992
 993
 994 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 995 {
 996         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 997         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 998
 999         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1000                 return -EIO;
1001
1002         devinfo->ringbell(devinfo);
1003
1004         return 0;
1005 }
1006
1007
1008 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
1009 {
1010         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1011         struct brcmf_pciedev_info *devinfo = ring->devinfo;
1012         struct brcmf_commonring *commonring = &ring->commonring;
1013
1014         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1015                 return -EIO;
1016
1017         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
1018
1019         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1020                   commonring->w_ptr, ring->id);
1021
1022         return 0;
1023 }
1024
1025
1026 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1027 {
1028         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1029         struct brcmf_pciedev_info *devinfo = ring->devinfo;
1030         struct brcmf_commonring *commonring = &ring->commonring;
1031
1032         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1033                 return -EIO;
1034
1035         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1036
1037         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1038                   commonring->r_ptr, ring->id);
1039
1040         return 0;
1041 }
1042
1043
1044 static void *
1045 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1046                                      u32 size, u32 tcm_dma_phys_addr,
1047                                      dma_addr_t *dma_handle)
1048 {
1049         void *ring;
1050         u64 address;
1051
1052         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1053                                   GFP_KERNEL);
1054         if (!ring)
1055                 return NULL;
1056
1057         address = (u64)*dma_handle;
1058         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1059                                address & 0xffffffff);
1060         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1061
1062         memset(ring, 0, size);
1063
1064         return (ring);
1065 }
1066
1067
1068 static struct brcmf_pcie_ringbuf *
1069 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1070                               u32 tcm_ring_phys_addr)
1071 {
1072         void *dma_buf;
1073         dma_addr_t dma_handle;
1074         struct brcmf_pcie_ringbuf *ring;
1075         u32 size;
1076         u32 addr;
1077
1078         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
1079         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1080                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1081                         &dma_handle);
1082         if (!dma_buf)
1083                 return NULL;
1084
1085         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1086         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1087         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1088         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1089
1090         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1091         if (!ring) {
1092                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1093                                   dma_handle);
1094                 return NULL;
1095         }
1096         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1097                                 brcmf_ring_itemsize[ring_id], dma_buf);
1098         ring->dma_handle = dma_handle;
1099         ring->devinfo = devinfo;
1100         brcmf_commonring_register_cb(&ring->commonring,
1101                                      brcmf_pcie_ring_mb_ring_bell,
1102                                      brcmf_pcie_ring_mb_update_rptr,
1103                                      brcmf_pcie_ring_mb_update_wptr,
1104                                      brcmf_pcie_ring_mb_write_rptr,
1105                                      brcmf_pcie_ring_mb_write_wptr, ring);
1106
1107         return (ring);
1108 }
1109
1110
1111 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1112                                           struct brcmf_pcie_ringbuf *ring)
1113 {
1114         void *dma_buf;
1115         u32 size;
1116
1117         if (!ring)
1118                 return;
1119
1120         dma_buf = ring->commonring.buf_addr;
1121         if (dma_buf) {
1122                 size = ring->commonring.depth * ring->commonring.item_len;
1123                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1124         }
1125         kfree(ring);
1126 }
1127
1128
1129 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1130 {
1131         u32 i;
1132
1133         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1134                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1135                                               devinfo->shared.commonrings[i]);
1136                 devinfo->shared.commonrings[i] = NULL;
1137         }
1138         kfree(devinfo->shared.flowrings);
1139         devinfo->shared.flowrings = NULL;
1140         if (devinfo->idxbuf) {
1141                 dma_free_coherent(&devinfo->pdev->dev,
1142                                   devinfo->idxbuf_sz,
1143                                   devinfo->idxbuf,
1144                                   devinfo->idxbuf_dmahandle);
1145                 devinfo->idxbuf = NULL;
1146         }
1147 }
1148
1149
1150 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1151 {
1152         struct brcmf_pcie_ringbuf *ring;
1153         struct brcmf_pcie_ringbuf *rings;
1154         u32 ring_addr;
1155         u32 d2h_w_idx_ptr;
1156         u32 d2h_r_idx_ptr;
1157         u32 h2d_w_idx_ptr;
1158         u32 h2d_r_idx_ptr;
1159         u32 addr;
1160         u32 ring_mem_ptr;
1161         u32 i;
1162         u64 address;
1163         u32 bufsz;
1164         u16 max_sub_queues;
1165         u8 idx_offset;
1166
1167         ring_addr = devinfo->shared.ring_info_addr;
1168         brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1169         addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1170         max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1171
1172         if (devinfo->dma_idx_sz != 0) {
1173                 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
1174                         devinfo->dma_idx_sz * 2;
1175                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1176                                                      &devinfo->idxbuf_dmahandle,
1177                                                      GFP_KERNEL);
1178                 if (!devinfo->idxbuf)
1179                         devinfo->dma_idx_sz = 0;
1180         }
1181
1182         if (devinfo->dma_idx_sz == 0) {
1183                 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1184                 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1185                 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1186                 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1187                 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1188                 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1189                 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1190                 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1191                 idx_offset = sizeof(u32);
1192                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1193                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1194                 brcmf_dbg(PCIE, "Using TCM indices\n");
1195         } else {
1196                 memset(devinfo->idxbuf, 0, bufsz);
1197                 devinfo->idxbuf_sz = bufsz;
1198                 idx_offset = devinfo->dma_idx_sz;
1199                 devinfo->write_ptr = brcmf_pcie_write_idx;
1200                 devinfo->read_ptr = brcmf_pcie_read_idx;
1201
1202                 h2d_w_idx_ptr = 0;
1203                 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
1204                 address = (u64)devinfo->idxbuf_dmahandle;
1205                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1206                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1207
1208                 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
1209                 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
1210                 address += max_sub_queues * idx_offset;
1211                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1212                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1213
1214                 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
1215                 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
1216                 address += max_sub_queues * idx_offset;
1217                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1218                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1219
1220                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1221                                 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1222                 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
1223                 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1224                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1225                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1226                 brcmf_dbg(PCIE, "Using host memory indices\n");
1227         }
1228
1229         addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1230         ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1231
1232         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1233                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1234                 if (!ring)
1235                         goto fail;
1236                 ring->w_idx_addr = h2d_w_idx_ptr;
1237                 ring->r_idx_addr = h2d_r_idx_ptr;
1238                 ring->id = i;
1239                 devinfo->shared.commonrings[i] = ring;
1240
1241                 h2d_w_idx_ptr += idx_offset;
1242                 h2d_r_idx_ptr += idx_offset;
1243                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1244         }
1245
1246         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1247              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1248                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1249                 if (!ring)
1250                         goto fail;
1251                 ring->w_idx_addr = d2h_w_idx_ptr;
1252                 ring->r_idx_addr = d2h_r_idx_ptr;
1253                 ring->id = i;
1254                 devinfo->shared.commonrings[i] = ring;
1255
1256                 d2h_w_idx_ptr += idx_offset;
1257                 d2h_r_idx_ptr += idx_offset;
1258                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1259         }
1260
1261         devinfo->shared.nrof_flowrings =
1262                         max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1263         rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1264                         GFP_KERNEL);
1265         if (!rings)
1266                 goto fail;
1267
1268         brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1269                   devinfo->shared.nrof_flowrings);
1270
1271         for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1272                 ring = &rings[i];
1273                 ring->devinfo = devinfo;
1274                 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1275                 brcmf_commonring_register_cb(&ring->commonring,
1276                                              brcmf_pcie_ring_mb_ring_bell,
1277                                              brcmf_pcie_ring_mb_update_rptr,
1278                                              brcmf_pcie_ring_mb_update_wptr,
1279                                              brcmf_pcie_ring_mb_write_rptr,
1280                                              brcmf_pcie_ring_mb_write_wptr,
1281                                              ring);
1282                 ring->w_idx_addr = h2d_w_idx_ptr;
1283                 ring->r_idx_addr = h2d_r_idx_ptr;
1284                 h2d_w_idx_ptr += idx_offset;
1285                 h2d_r_idx_ptr += idx_offset;
1286         }
1287         devinfo->shared.flowrings = rings;
1288
1289         return 0;
1290
1291 fail:
1292         brcmf_err("Allocating ring buffers failed\n");
1293         brcmf_pcie_release_ringbuffers(devinfo);
1294         return -ENOMEM;
1295 }
1296
1297
1298 static void
1299 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1300 {
1301         if (devinfo->shared.scratch)
1302                 dma_free_coherent(&devinfo->pdev->dev,
1303                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1304                                   devinfo->shared.scratch,
1305                                   devinfo->shared.scratch_dmahandle);
1306         if (devinfo->shared.ringupd)
1307                 dma_free_coherent(&devinfo->pdev->dev,
1308                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1309                                   devinfo->shared.ringupd,
1310                                   devinfo->shared.ringupd_dmahandle);
1311 }
1312
1313 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1314 {
1315         u64 address;
1316         u32 addr;
1317
1318         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1319                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1320                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1321         if (!devinfo->shared.scratch)
1322                 goto fail;
1323
1324         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1325
1326         addr = devinfo->shared.tcm_base_address +
1327                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1328         address = (u64)devinfo->shared.scratch_dmahandle;
1329         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1330         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1331         addr = devinfo->shared.tcm_base_address +
1332                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1333         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1334
1335         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1336                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1337                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1338         if (!devinfo->shared.ringupd)
1339                 goto fail;
1340
1341         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1342
1343         addr = devinfo->shared.tcm_base_address +
1344                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1345         address = (u64)devinfo->shared.ringupd_dmahandle;
1346         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1347         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1348         addr = devinfo->shared.tcm_base_address +
1349                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1350         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1351         return 0;
1352
1353 fail:
1354         brcmf_err("Allocating scratch buffers failed\n");
1355         brcmf_pcie_release_scratchbuffers(devinfo);
1356         return -ENOMEM;
1357 }
1358
1359
1360 static void brcmf_pcie_down(struct device *dev)
1361 {
1362 }
1363
1364
1365 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1366 {
1367         return 0;
1368 }
1369
1370
1371 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1372                                 uint len)
1373 {
1374         return 0;
1375 }
1376
1377
1378 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1379                                 uint len)
1380 {
1381         return 0;
1382 }
1383
1384
1385 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1386 {
1387         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1388         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1389         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1390
1391         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1392         devinfo->wowl_enabled = enabled;
1393         if (enabled)
1394                 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1395         else
1396                 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1397 }
1398
1399
1400 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1401 {
1402         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1403         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1404         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1405
1406         return devinfo->ci->ramsize - devinfo->ci->srsize;
1407 }
1408
1409
1410 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1411 {
1412         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1413         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1414         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1415
1416         brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1417         brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1418         return 0;
1419 }
1420
1421
1422 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1423         .txdata = brcmf_pcie_tx,
1424         .stop = brcmf_pcie_down,
1425         .txctl = brcmf_pcie_tx_ctlpkt,
1426         .rxctl = brcmf_pcie_rx_ctlpkt,
1427         .wowl_config = brcmf_pcie_wowl_config,
1428         .get_ramsize = brcmf_pcie_get_ramsize,
1429         .get_memdump = brcmf_pcie_get_memdump,
1430 };
1431
1432
1433 static int
1434 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1435                                u32 sharedram_addr)
1436 {
1437         struct brcmf_pcie_shared_info *shared;
1438         u32 addr;
1439         u32 version;
1440
1441         shared = &devinfo->shared;
1442         shared->tcm_base_address = sharedram_addr;
1443
1444         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1445         version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1446         brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1447         if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1448             (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1449                 brcmf_err("Unsupported PCIE version %d\n", version);
1450                 return -EINVAL;
1451         }
1452
1453         /* check firmware support dma indicies */
1454         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1455                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1456                         devinfo->dma_idx_sz = sizeof(u16);
1457                 else
1458                         devinfo->dma_idx_sz = sizeof(u32);
1459         }
1460
1461         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1462         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1463         if (shared->max_rxbufpost == 0)
1464                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1465
1466         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1467         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1468
1469         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1470         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1471
1472         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1473         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1474
1475         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1476         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1477
1478         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1479                   shared->max_rxbufpost, shared->rx_dataoffset);
1480
1481         brcmf_pcie_bus_console_init(devinfo);
1482
1483         return 0;
1484 }
1485
1486
1487 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1488 {
1489         char *fw_name;
1490         char *nvram_name;
1491         uint fw_len, nv_len;
1492         char end;
1493
1494         brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1495                   devinfo->ci->chiprev);
1496
1497         switch (devinfo->ci->chip) {
1498         case BRCM_CC_43602_CHIP_ID:
1499                 fw_name = BRCMF_PCIE_43602_FW_NAME;
1500                 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1501                 break;
1502         case BRCM_CC_4350_CHIP_ID:
1503                 fw_name = BRCMF_PCIE_4350_FW_NAME;
1504                 nvram_name = BRCMF_PCIE_4350_NVRAM_NAME;
1505                 break;
1506         case BRCM_CC_4356_CHIP_ID:
1507                 fw_name = BRCMF_PCIE_4356_FW_NAME;
1508                 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1509                 break;
1510         case BRCM_CC_43567_CHIP_ID:
1511         case BRCM_CC_43569_CHIP_ID:
1512         case BRCM_CC_43570_CHIP_ID:
1513                 fw_name = BRCMF_PCIE_43570_FW_NAME;
1514                 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1515                 break;
1516         case BRCM_CC_4358_CHIP_ID:
1517                 fw_name = BRCMF_PCIE_4358_FW_NAME;
1518                 nvram_name = BRCMF_PCIE_4358_NVRAM_NAME;
1519                 break;
1520         case BRCM_CC_4365_CHIP_ID:
1521                 fw_name = BRCMF_PCIE_4365_FW_NAME;
1522                 nvram_name = BRCMF_PCIE_4365_NVRAM_NAME;
1523                 break;
1524         case BRCM_CC_4366_CHIP_ID:
1525                 fw_name = BRCMF_PCIE_4366_FW_NAME;
1526                 nvram_name = BRCMF_PCIE_4366_NVRAM_NAME;
1527                 break;
1528         case BRCM_CC_4371_CHIP_ID:
1529                 fw_name = BRCMF_PCIE_4371_FW_NAME;
1530                 nvram_name = BRCMF_PCIE_4371_NVRAM_NAME;
1531                 break;
1532         default:
1533                 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1534                 return -ENODEV;
1535         }
1536
1537         fw_len = sizeof(devinfo->fw_name) - 1;
1538         nv_len = sizeof(devinfo->nvram_name) - 1;
1539         /* check if firmware path is provided by module parameter */
1540         if (brcmf_firmware_path[0] != '\0') {
1541                 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1542                 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1543                 fw_len -= strlen(devinfo->fw_name);
1544                 nv_len -= strlen(devinfo->nvram_name);
1545
1546                 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1547                 if (end != '/') {
1548                         strncat(devinfo->fw_name, "/", fw_len);
1549                         strncat(devinfo->nvram_name, "/", nv_len);
1550                         fw_len--;
1551                         nv_len--;
1552                 }
1553         }
1554         strncat(devinfo->fw_name, fw_name, fw_len);
1555         strncat(devinfo->nvram_name, nvram_name, nv_len);
1556
1557         return 0;
1558 }
1559
1560
1561 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1562                                         const struct firmware *fw, void *nvram,
1563                                         u32 nvram_len)
1564 {
1565         u32 sharedram_addr;
1566         u32 sharedram_addr_written;
1567         u32 loop_counter;
1568         int err;
1569         u32 address;
1570         u32 resetintr;
1571
1572         devinfo->ringbell = brcmf_pcie_ringbell_v2;
1573         devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1574
1575         brcmf_dbg(PCIE, "Halt ARM.\n");
1576         err = brcmf_pcie_enter_download_state(devinfo);
1577         if (err)
1578                 return err;
1579
1580         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1581         brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1582                                   (void *)fw->data, fw->size);
1583
1584         resetintr = get_unaligned_le32(fw->data);
1585         release_firmware(fw);
1586
1587         /* reset last 4 bytes of RAM address. to be used for shared
1588          * area. This identifies when FW is running
1589          */
1590         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1591
1592         if (nvram) {
1593                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1594                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1595                           nvram_len;
1596                 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1597                 brcmf_fw_nvram_free(nvram);
1598         } else {
1599                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1600                           devinfo->nvram_name);
1601         }
1602
1603         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1604                                                        devinfo->ci->ramsize -
1605                                                        4);
1606         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1607         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1608         if (err)
1609                 return err;
1610
1611         brcmf_dbg(PCIE, "Wait for FW init\n");
1612         sharedram_addr = sharedram_addr_written;
1613         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1614         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1615                 msleep(50);
1616                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1617                                                        devinfo->ci->ramsize -
1618                                                        4);
1619                 loop_counter--;
1620         }
1621         if (sharedram_addr == sharedram_addr_written) {
1622                 brcmf_err("FW failed to initialize\n");
1623                 return -ENODEV;
1624         }
1625         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1626
1627         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1628 }
1629
1630
1631 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1632 {
1633         struct pci_dev *pdev;
1634         int err;
1635         phys_addr_t  bar0_addr, bar1_addr;
1636         ulong bar1_size;
1637
1638         pdev = devinfo->pdev;
1639
1640         err = pci_enable_device(pdev);
1641         if (err) {
1642                 brcmf_err("pci_enable_device failed err=%d\n", err);
1643                 return err;
1644         }
1645
1646         pci_set_master(pdev);
1647
1648         /* Bar-0 mapped address */
1649         bar0_addr = pci_resource_start(pdev, 0);
1650         /* Bar-1 mapped address */
1651         bar1_addr = pci_resource_start(pdev, 2);
1652         /* read Bar-1 mapped memory range */
1653         bar1_size = pci_resource_len(pdev, 2);
1654         if ((bar1_size == 0) || (bar1_addr == 0)) {
1655                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1656                           bar1_size, (unsigned long long)bar1_addr);
1657                 return -EINVAL;
1658         }
1659
1660         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1661         devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1662         devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1663
1664         if (!devinfo->regs || !devinfo->tcm) {
1665                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1666                           devinfo->tcm);
1667                 return -EINVAL;
1668         }
1669         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1670                   devinfo->regs, (unsigned long long)bar0_addr);
1671         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1672                   devinfo->tcm, (unsigned long long)bar1_addr);
1673
1674         return 0;
1675 }
1676
1677
1678 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1679 {
1680         if (devinfo->tcm)
1681                 iounmap(devinfo->tcm);
1682         if (devinfo->regs)
1683                 iounmap(devinfo->regs);
1684
1685         pci_disable_device(devinfo->pdev);
1686 }
1687
1688
1689 static int brcmf_pcie_attach_bus(struct device *dev)
1690 {
1691         int ret;
1692
1693         /* Attach to the common driver interface */
1694         ret = brcmf_attach(dev);
1695         if (ret) {
1696                 brcmf_err("brcmf_attach failed\n");
1697         } else {
1698                 ret = brcmf_bus_start(dev);
1699                 if (ret)
1700                         brcmf_err("dongle is not responding\n");
1701         }
1702
1703         return ret;
1704 }
1705
1706
1707 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1708 {
1709         u32 ret_addr;
1710
1711         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1712         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1713         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1714
1715         return ret_addr;
1716 }
1717
1718
1719 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1720 {
1721         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1722
1723         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1724         return brcmf_pcie_read_reg32(devinfo, addr);
1725 }
1726
1727
1728 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1729 {
1730         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1731
1732         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1733         brcmf_pcie_write_reg32(devinfo, addr, value);
1734 }
1735
1736
1737 static int brcmf_pcie_buscoreprep(void *ctx)
1738 {
1739         return brcmf_pcie_get_resource(ctx);
1740 }
1741
1742
1743 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1744 {
1745         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1746         u32 val;
1747
1748         devinfo->ci = chip;
1749         brcmf_pcie_reset_device(devinfo);
1750
1751         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1752         if (val != 0xffffffff)
1753                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1754                                        val);
1755
1756         return 0;
1757 }
1758
1759
1760 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1761                                         u32 rstvec)
1762 {
1763         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1764
1765         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1766 }
1767
1768
1769 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1770         .prepare = brcmf_pcie_buscoreprep,
1771         .reset = brcmf_pcie_buscore_reset,
1772         .activate = brcmf_pcie_buscore_activate,
1773         .read32 = brcmf_pcie_buscore_read32,
1774         .write32 = brcmf_pcie_buscore_write32,
1775 };
1776
1777 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1778                              void *nvram, u32 nvram_len)
1779 {
1780         struct brcmf_bus *bus = dev_get_drvdata(dev);
1781         struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1782         struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1783         struct brcmf_commonring **flowrings;
1784         int ret;
1785         u32 i;
1786
1787         brcmf_pcie_attach(devinfo);
1788
1789         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1790         if (ret)
1791                 goto fail;
1792
1793         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1794
1795         ret = brcmf_pcie_init_ringbuffers(devinfo);
1796         if (ret)
1797                 goto fail;
1798
1799         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1800         if (ret)
1801                 goto fail;
1802
1803         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1804         ret = brcmf_pcie_request_irq(devinfo);
1805         if (ret)
1806                 goto fail;
1807
1808         /* hook the commonrings in the bus structure. */
1809         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1810                 bus->msgbuf->commonrings[i] =
1811                                 &devinfo->shared.commonrings[i]->commonring;
1812
1813         flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
1814                             GFP_KERNEL);
1815         if (!flowrings)
1816                 goto fail;
1817
1818         for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1819                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1820         bus->msgbuf->flowrings = flowrings;
1821
1822         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1823         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1824         bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1825
1826         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1827
1828         brcmf_pcie_intr_enable(devinfo);
1829         if (brcmf_pcie_attach_bus(bus->dev) == 0)
1830                 return;
1831
1832         brcmf_pcie_bus_console_read(devinfo);
1833
1834 fail:
1835         device_release_driver(dev);
1836 }
1837
1838 static int
1839 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1840 {
1841         int ret;
1842         struct brcmf_pciedev_info *devinfo;
1843         struct brcmf_pciedev *pcie_bus_dev;
1844         struct brcmf_bus *bus;
1845         u16 domain_nr;
1846         u16 bus_nr;
1847
1848         domain_nr = pci_domain_nr(pdev->bus) + 1;
1849         bus_nr = pdev->bus->number;
1850         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1851                   domain_nr, bus_nr);
1852
1853         ret = -ENOMEM;
1854         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1855         if (devinfo == NULL)
1856                 return ret;
1857
1858         devinfo->pdev = pdev;
1859         pcie_bus_dev = NULL;
1860         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1861         if (IS_ERR(devinfo->ci)) {
1862                 ret = PTR_ERR(devinfo->ci);
1863                 devinfo->ci = NULL;
1864                 goto fail;
1865         }
1866
1867         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1868         if (pcie_bus_dev == NULL) {
1869                 ret = -ENOMEM;
1870                 goto fail;
1871         }
1872
1873         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1874         if (!bus) {
1875                 ret = -ENOMEM;
1876                 goto fail;
1877         }
1878         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1879         if (!bus->msgbuf) {
1880                 ret = -ENOMEM;
1881                 kfree(bus);
1882                 goto fail;
1883         }
1884
1885         /* hook it all together. */
1886         pcie_bus_dev->devinfo = devinfo;
1887         pcie_bus_dev->bus = bus;
1888         bus->dev = &pdev->dev;
1889         bus->bus_priv.pcie = pcie_bus_dev;
1890         bus->ops = &brcmf_pcie_bus_ops;
1891         bus->proto_type = BRCMF_PROTO_MSGBUF;
1892         bus->chip = devinfo->coreid;
1893         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1894         dev_set_drvdata(&pdev->dev, bus);
1895
1896         ret = brcmf_pcie_get_fwnames(devinfo);
1897         if (ret)
1898                 goto fail_bus;
1899
1900         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1901                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1902                                           devinfo->fw_name, devinfo->nvram_name,
1903                                           brcmf_pcie_setup, domain_nr, bus_nr);
1904         if (ret == 0)
1905                 return 0;
1906 fail_bus:
1907         kfree(bus->msgbuf);
1908         kfree(bus);
1909 fail:
1910         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1911         brcmf_pcie_release_resource(devinfo);
1912         if (devinfo->ci)
1913                 brcmf_chip_detach(devinfo->ci);
1914         kfree(pcie_bus_dev);
1915         kfree(devinfo);
1916         return ret;
1917 }
1918
1919
1920 static void
1921 brcmf_pcie_remove(struct pci_dev *pdev)
1922 {
1923         struct brcmf_pciedev_info *devinfo;
1924         struct brcmf_bus *bus;
1925
1926         brcmf_dbg(PCIE, "Enter\n");
1927
1928         bus = dev_get_drvdata(&pdev->dev);
1929         if (bus == NULL)
1930                 return;
1931
1932         devinfo = bus->bus_priv.pcie->devinfo;
1933
1934         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1935         if (devinfo->ci)
1936                 brcmf_pcie_intr_disable(devinfo);
1937
1938         brcmf_detach(&pdev->dev);
1939
1940         kfree(bus->bus_priv.pcie);
1941         kfree(bus->msgbuf->flowrings);
1942         kfree(bus->msgbuf);
1943         kfree(bus);
1944
1945         brcmf_pcie_release_irq(devinfo);
1946         brcmf_pcie_release_scratchbuffers(devinfo);
1947         brcmf_pcie_release_ringbuffers(devinfo);
1948         brcmf_pcie_reset_device(devinfo);
1949         brcmf_pcie_release_resource(devinfo);
1950
1951         if (devinfo->ci)
1952                 brcmf_chip_detach(devinfo->ci);
1953
1954         kfree(devinfo);
1955         dev_set_drvdata(&pdev->dev, NULL);
1956 }
1957
1958
1959 #ifdef CONFIG_PM
1960
1961
1962 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1963 {
1964         struct brcmf_pciedev_info *devinfo;
1965         struct brcmf_bus *bus;
1966         int err;
1967
1968         brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1969
1970         bus = dev_get_drvdata(&pdev->dev);
1971         devinfo = bus->bus_priv.pcie->devinfo;
1972
1973         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1974
1975         devinfo->mbdata_completed = false;
1976         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1977
1978         wait_event_timeout(devinfo->mbdata_resp_wait,
1979                            devinfo->mbdata_completed,
1980                            msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1981         if (!devinfo->mbdata_completed) {
1982                 brcmf_err("Timeout on response for entering D3 substate\n");
1983                 return -EIO;
1984         }
1985         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
1986
1987         err = pci_save_state(pdev);
1988         if (err)
1989                 brcmf_err("pci_save_state failed, err=%d\n", err);
1990         if ((err) || (!devinfo->wowl_enabled)) {
1991                 brcmf_chip_detach(devinfo->ci);
1992                 devinfo->ci = NULL;
1993                 brcmf_pcie_remove(pdev);
1994                 return 0;
1995         }
1996
1997         return pci_prepare_to_sleep(pdev);
1998 }
1999
2000 static int brcmf_pcie_resume(struct pci_dev *pdev)
2001 {
2002         struct brcmf_pciedev_info *devinfo;
2003         struct brcmf_bus *bus;
2004         int err;
2005
2006         bus = dev_get_drvdata(&pdev->dev);
2007         brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
2008
2009         err = pci_set_power_state(pdev, PCI_D0);
2010         if (err) {
2011                 brcmf_err("pci_set_power_state failed, err=%d\n", err);
2012                 goto cleanup;
2013         }
2014         pci_restore_state(pdev);
2015         pci_enable_wake(pdev, PCI_D3hot, false);
2016         pci_enable_wake(pdev, PCI_D3cold, false);
2017
2018         /* Check if device is still up and running, if so we are ready */
2019         if (bus) {
2020                 devinfo = bus->bus_priv.pcie->devinfo;
2021                 if (brcmf_pcie_read_reg32(devinfo,
2022                                           BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
2023                         if (brcmf_pcie_send_mb_data(devinfo,
2024                                                     BRCMF_H2D_HOST_D0_INFORM))
2025                                 goto cleanup;
2026                         brcmf_dbg(PCIE, "Hot resume, continue....\n");
2027                         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2028                         brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2029                         brcmf_pcie_intr_enable(devinfo);
2030                         return 0;
2031                 }
2032         }
2033
2034 cleanup:
2035         if (bus) {
2036                 devinfo = bus->bus_priv.pcie->devinfo;
2037                 brcmf_chip_detach(devinfo->ci);
2038                 devinfo->ci = NULL;
2039                 brcmf_pcie_remove(pdev);
2040         }
2041         err = brcmf_pcie_probe(pdev, NULL);
2042         if (err)
2043                 brcmf_err("probe after resume failed, err=%d\n", err);
2044
2045         return err;
2046 }
2047
2048
2049 #endif /* CONFIG_PM */
2050
2051
2052 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
2053         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
2054
2055 static struct pci_device_id brcmf_pcie_devid_table[] = {
2056         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
2057         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
2058         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
2059         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
2060         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
2061         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
2062         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
2063         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
2064         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
2065         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
2066         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
2067         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
2068         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
2069         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
2070         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
2071         BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
2072         { /* end: all zeroes */ }
2073 };
2074
2075
2076 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2077
2078
2079 static struct pci_driver brcmf_pciedrvr = {
2080         .node = {},
2081         .name = KBUILD_MODNAME,
2082         .id_table = brcmf_pcie_devid_table,
2083         .probe = brcmf_pcie_probe,
2084         .remove = brcmf_pcie_remove,
2085 #ifdef CONFIG_PM
2086         .suspend = brcmf_pcie_suspend,
2087         .resume = brcmf_pcie_resume
2088 #endif /* CONFIG_PM */
2089 };
2090
2091
2092 void brcmf_pcie_register(void)
2093 {
2094         int err;
2095
2096         brcmf_dbg(PCIE, "Enter\n");
2097         err = pci_register_driver(&brcmf_pciedrvr);
2098         if (err)
2099                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
2100 }
2101
2102
2103 void brcmf_pcie_exit(void)
2104 {
2105         brcmf_dbg(PCIE, "Enter\n");
2106         pci_unregister_driver(&brcmf_pciedrvr);
2107 }