drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
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  41  *    notice, this list of conditions and the following disclaimer.
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  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-trans-pcie-int.h"
  74 #include "iwl-csr.h"
  75 #include "iwl-prph.h"
  76 #include "iwl-eeprom.h"
  77 #include "iwl-agn-hw.h"
  78 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  79 #include "iwl-commands.h"
  80
  81 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
  82
  83 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)       \
  84         (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
  85         (~(1<<(trans_pcie)->cmd_queue)))
  86
  87 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  88 {
  89         struct iwl_trans_pcie *trans_pcie =
  90                 IWL_TRANS_GET_PCIE_TRANS(trans);
  91         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  92         struct device *dev = trans->dev;
  93
  94         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  95
  96         spin_lock_init(&rxq->lock);
  97
  98         if (WARN_ON(rxq->bd || rxq->rb_stts))
  99                 return -EINVAL;
 100
 101         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
 102         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 103                                       &rxq->bd_dma, GFP_KERNEL);
 104         if (!rxq->bd)
 105                 goto err_bd;
 106
 107         /*Allocate the driver's pointer to receive buffer status */
 108         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 109                                            &rxq->rb_stts_dma, GFP_KERNEL);
 110         if (!rxq->rb_stts)
 111                 goto err_rb_stts;
 112
 113         return 0;
 114
 115 err_rb_stts:
 116         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 117                         rxq->bd, rxq->bd_dma);
 118         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 119         rxq->bd = NULL;
 120 err_bd:
 121         return -ENOMEM;
 122 }
 123
 124 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 125 {
 126         struct iwl_trans_pcie *trans_pcie =
 127                 IWL_TRANS_GET_PCIE_TRANS(trans);
 128         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 129         int i;
 130
 131         /* Fill the rx_used queue with _all_ of the Rx buffers */
 132         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 133                 /* In the reset function, these buffers may have been allocated
 134                  * to an SKB, so we need to unmap and free potential storage */
 135                 if (rxq->pool[i].page != NULL) {
 136                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 137                                 PAGE_SIZE << trans_pcie->rx_page_order,
 138                                 DMA_FROM_DEVICE);
 139                         __free_pages(rxq->pool[i].page,
 140                                      trans_pcie->rx_page_order);
 141                         rxq->pool[i].page = NULL;
 142                 }
 143                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 144         }
 145 }
 146
 147 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 148                                  struct iwl_rx_queue *rxq)
 149 {
 150         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 151         u32 rb_size;
 152         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 153         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 154
 155         if (trans_pcie->rx_buf_size_8k)
 156                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 157         else
 158                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 159
 160         /* Stop Rx DMA */
 161         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 162
 163         /* Reset driver's Rx queue write index */
 164         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 165
 166         /* Tell device where to find RBD circular buffer in DRAM */
 167         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 168                            (u32)(rxq->bd_dma >> 8));
 169
 170         /* Tell device where in DRAM to update its Rx status */
 171         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 172                            rxq->rb_stts_dma >> 4);
 173
 174         /* Enable Rx DMA
 175          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 176          *      the credit mechanism in 5000 HW RX FIFO
 177          * Direct rx interrupts to hosts
 178          * Rx buffer size 4 or 8k
 179          * RB timeout 0x10
 180          * 256 RBDs
 181          */
 182         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 183                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 184                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 185                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 186                            rb_size|
 187                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 188                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 189
 190         /* Set interrupt coalescing timer to default (2048 usecs) */
 191         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 192 }
 193
 194 static int iwl_rx_init(struct iwl_trans *trans)
 195 {
 196         struct iwl_trans_pcie *trans_pcie =
 197                 IWL_TRANS_GET_PCIE_TRANS(trans);
 198         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 199
 200         int i, err;
 201         unsigned long flags;
 202
 203         if (!rxq->bd) {
 204                 err = iwl_trans_rx_alloc(trans);
 205                 if (err)
 206                         return err;
 207         }
 208
 209         spin_lock_irqsave(&rxq->lock, flags);
 210         INIT_LIST_HEAD(&rxq->rx_free);
 211         INIT_LIST_HEAD(&rxq->rx_used);
 212
 213         iwl_trans_rxq_free_rx_bufs(trans);
 214
 215         for (i = 0; i < RX_QUEUE_SIZE; i++)
 216                 rxq->queue[i] = NULL;
 217
 218         /* Set us so that we have processed and used all buffers, but have
 219          * not restocked the Rx queue with fresh buffers */
 220         rxq->read = rxq->write = 0;
 221         rxq->write_actual = 0;
 222         rxq->free_count = 0;
 223         spin_unlock_irqrestore(&rxq->lock, flags);
 224
 225         iwlagn_rx_replenish(trans);
 226
 227         iwl_trans_rx_hw_init(trans, rxq);
 228
 229         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 230         rxq->need_update = 1;
 231         iwl_rx_queue_update_write_ptr(trans, rxq);
 232         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 233
 234         return 0;
 235 }
 236
 237 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 238 {
 239         struct iwl_trans_pcie *trans_pcie =
 240                 IWL_TRANS_GET_PCIE_TRANS(trans);
 241         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 242
 243         unsigned long flags;
 244
 245         /*if rxq->bd is NULL, it means that nothing has been allocated,
 246          * exit now */
 247         if (!rxq->bd) {
 248                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 249                 return;
 250         }
 251
 252         spin_lock_irqsave(&rxq->lock, flags);
 253         iwl_trans_rxq_free_rx_bufs(trans);
 254         spin_unlock_irqrestore(&rxq->lock, flags);
 255
 256         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 257                           rxq->bd, rxq->bd_dma);
 258         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 259         rxq->bd = NULL;
 260
 261         if (rxq->rb_stts)
 262                 dma_free_coherent(trans->dev,
 263                                   sizeof(struct iwl_rb_status),
 264                                   rxq->rb_stts, rxq->rb_stts_dma);
 265         else
 266                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 267         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 268         rxq->rb_stts = NULL;
 269 }
 270
 271 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 272 {
 273
 274         /* stop Rx DMA */
 275         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 276         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 277                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 278 }
 279
 280 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 281                                     struct iwl_dma_ptr *ptr, size_t size)
 282 {
 283         if (WARN_ON(ptr->addr))
 284                 return -EINVAL;
 285
 286         ptr->addr = dma_alloc_coherent(trans->dev, size,
 287                                        &ptr->dma, GFP_KERNEL);
 288         if (!ptr->addr)
 289                 return -ENOMEM;
 290         ptr->size = size;
 291         return 0;
 292 }
 293
 294 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 295                                     struct iwl_dma_ptr *ptr)
 296 {
 297         if (unlikely(!ptr->addr))
 298                 return;
 299
 300         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 301         memset(ptr, 0, sizeof(*ptr));
 302 }
 303
 304 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
 305 {
 306         struct iwl_tx_queue *txq = (void *)data;
 307         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 308         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 309
 310         spin_lock(&txq->lock);
 311         /* check if triggered erroneously */
 312         if (txq->q.read_ptr == txq->q.write_ptr) {
 313                 spin_unlock(&txq->lock);
 314                 return;
 315         }
 316         spin_unlock(&txq->lock);
 317
 318
 319         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 320                 jiffies_to_msecs(trans_pcie->wd_timeout));
 321         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 322                 txq->q.read_ptr, txq->q.write_ptr);
 323         IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
 324                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq->q.id))
 325                                         & (TFD_QUEUE_SIZE_MAX - 1),
 326                 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq->q.id)));
 327
 328         iwl_op_mode_nic_error(trans->op_mode);
 329 }
 330
 331 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 332                                 struct iwl_tx_queue *txq, int slots_num,
 333                                 u32 txq_id)
 334 {
 335         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 336         int i;
 337         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 338
 339         if (WARN_ON(txq->entries || txq->tfds))
 340                 return -EINVAL;
 341
 342         setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
 343                     (unsigned long)txq);
 344         txq->trans_pcie = trans_pcie;
 345
 346         txq->q.n_window = slots_num;
 347
 348         txq->entries = kcalloc(slots_num,
 349                                sizeof(struct iwl_pcie_tx_queue_entry),
 350                                GFP_KERNEL);
 351
 352         if (!txq->entries)
 353                 goto error;
 354
 355         if (txq_id == trans_pcie->cmd_queue)
 356                 for (i = 0; i < slots_num; i++) {
 357                         txq->entries[i].cmd =
 358                                 kmalloc(sizeof(struct iwl_device_cmd),
 359                                         GFP_KERNEL);
 360                         if (!txq->entries[i].cmd)
 361                                 goto error;
 362                 }
 363
 364         /* Circular buffer of transmit frame descriptors (TFDs),
 365          * shared with device */
 366         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 367                                        &txq->q.dma_addr, GFP_KERNEL);
 368         if (!txq->tfds) {
 369                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 370                 goto error;
 371         }
 372         txq->q.id = txq_id;
 373
 374         return 0;
 375 error:
 376         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 377                 for (i = 0; i < slots_num; i++)
 378                         kfree(txq->entries[i].cmd);
 379         kfree(txq->entries);
 380         txq->entries = NULL;
 381
 382         return -ENOMEM;
 383
 384 }
 385
 386 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 387                               int slots_num, u32 txq_id)
 388 {
 389         int ret;
 390
 391         txq->need_update = 0;
 392
 393         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 394          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 395         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 396
 397         /* Initialize queue's high/low-water marks, and head/tail indexes */
 398         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 399                         txq_id);
 400         if (ret)
 401                 return ret;
 402
 403         spin_lock_init(&txq->lock);
 404
 405         /*
 406          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 407          * given Tx queue, and enable the DMA channel used for that queue.
 408          * Circular buffer (TFD queue in DRAM) physical base address */
 409         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 410                              txq->q.dma_addr >> 8);
 411
 412         return 0;
 413 }
 414
 415 /**
 416  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 417  */
 418 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 419 {
 420         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 421         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 422         struct iwl_queue *q = &txq->q;
 423         enum dma_data_direction dma_dir;
 424
 425         if (!q->n_bd)
 426                 return;
 427
 428         /* In the command queue, all the TBs are mapped as BIDI
 429          * so unmap them as such.
 430          */
 431         if (txq_id == trans_pcie->cmd_queue)
 432                 dma_dir = DMA_BIDIRECTIONAL;
 433         else
 434                 dma_dir = DMA_TO_DEVICE;
 435
 436         spin_lock_bh(&txq->lock);
 437         while (q->write_ptr != q->read_ptr) {
 438                 iwlagn_txq_free_tfd(trans, txq, dma_dir);
 439                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 440         }
 441         spin_unlock_bh(&txq->lock);
 442 }
 443
 444 /**
 445  * iwl_tx_queue_free - Deallocate DMA queue.
 446  * @txq: Transmit queue to deallocate.
 447  *
 448  * Empty queue by removing and destroying all BD's.
 449  * Free all buffers.
 450  * 0-fill, but do not free "txq" descriptor structure.
 451  */
 452 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 453 {
 454         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 455         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 456         struct device *dev = trans->dev;
 457         int i;
 458         if (WARN_ON(!txq))
 459                 return;
 460
 461         iwl_tx_queue_unmap(trans, txq_id);
 462
 463         /* De-alloc array of command/tx buffers */
 464
 465         if (txq_id == trans_pcie->cmd_queue)
 466                 for (i = 0; i < txq->q.n_window; i++)
 467                         kfree(txq->entries[i].cmd);
 468
 469         /* De-alloc circular buffer of TFDs */
 470         if (txq->q.n_bd) {
 471                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 472                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 473                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 474         }
 475
 476         kfree(txq->entries);
 477         txq->entries = NULL;
 478
 479         del_timer_sync(&txq->stuck_timer);
 480
 481         /* 0-fill queue descriptor structure */
 482         memset(txq, 0, sizeof(*txq));
 483 }
 484
 485 /**
 486  * iwl_trans_tx_free - Free TXQ Context
 487  *
 488  * Destroy all TX DMA queues and structures
 489  */
 490 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 491 {
 492         int txq_id;
 493         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 494
 495         /* Tx queues */
 496         if (trans_pcie->txq) {
 497                 for (txq_id = 0;
 498                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 499                         iwl_tx_queue_free(trans, txq_id);
 500         }
 501
 502         kfree(trans_pcie->txq);
 503         trans_pcie->txq = NULL;
 504
 505         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 506
 507         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 508 }
 509
 510 /**
 511  * iwl_trans_tx_alloc - allocate TX context
 512  * Allocate all Tx DMA structures and initialize them
 513  *
 514  * @param priv
 515  * @return error code
 516  */
 517 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 518 {
 519         int ret;
 520         int txq_id, slots_num;
 521         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 522
 523         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 524                         sizeof(struct iwlagn_scd_bc_tbl);
 525
 526         /*It is not allowed to alloc twice, so warn when this happens.
 527          * We cannot rely on the previous allocation, so free and fail */
 528         if (WARN_ON(trans_pcie->txq)) {
 529                 ret = -EINVAL;
 530                 goto error;
 531         }
 532
 533         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 534                                    scd_bc_tbls_size);
 535         if (ret) {
 536                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 537                 goto error;
 538         }
 539
 540         /* Alloc keep-warm buffer */
 541         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 542         if (ret) {
 543                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 544                 goto error;
 545         }
 546
 547         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 548                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 549         if (!trans_pcie->txq) {
 550                 IWL_ERR(trans, "Not enough memory for txq\n");
 551                 ret = ENOMEM;
 552                 goto error;
 553         }
 554
 555         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 556         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 557              txq_id++) {
 558                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 559                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 560                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 561                                           slots_num, txq_id);
 562                 if (ret) {
 563                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 564                         goto error;
 565                 }
 566         }
 567
 568         return 0;
 569
 570 error:
 571         iwl_trans_pcie_tx_free(trans);
 572
 573         return ret;
 574 }
 575 static int iwl_tx_init(struct iwl_trans *trans)
 576 {
 577         int ret;
 578         int txq_id, slots_num;
 579         unsigned long flags;
 580         bool alloc = false;
 581         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 582
 583         if (!trans_pcie->txq) {
 584                 ret = iwl_trans_tx_alloc(trans);
 585                 if (ret)
 586                         goto error;
 587                 alloc = true;
 588         }
 589
 590         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 591
 592         /* Turn off all Tx DMA fifos */
 593         iwl_write_prph(trans, SCD_TXFACT, 0);
 594
 595         /* Tell NIC where to find the "keep warm" buffer */
 596         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 597                            trans_pcie->kw.dma >> 4);
 598
 599         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 600
 601         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 602         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 603              txq_id++) {
 604                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 605                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 606                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 607                                          slots_num, txq_id);
 608                 if (ret) {
 609                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 610                         goto error;
 611                 }
 612         }
 613
 614         return 0;
 615 error:
 616         /*Upon error, free only if we allocated something */
 617         if (alloc)
 618                 iwl_trans_pcie_tx_free(trans);
 619         return ret;
 620 }
 621
 622 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 623 {
 624 /*
 625  * (for documentation purposes)
 626  * to set power to V_AUX, do:
 627
 628                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 629                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 630                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 631                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 632  */
 633
 634         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 635                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 636                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 637 }
 638
 639 /* PCI registers */
 640 #define PCI_CFG_RETRY_TIMEOUT   0x041
 641 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 642 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 643
 644 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 645 {
 646         int pos;
 647         u16 pci_lnk_ctl;
 648         struct iwl_trans_pcie *trans_pcie =
 649                 IWL_TRANS_GET_PCIE_TRANS(trans);
 650
 651         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 652
 653         pos = pci_pcie_cap(pci_dev);
 654         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 655         return pci_lnk_ctl;
 656 }
 657
 658 static void iwl_apm_config(struct iwl_trans *trans)
 659 {
 660         /*
 661          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 662          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 663          * If so (likely), disable L0S, so device moves directly L0->L1;
 664          *    costs negligible amount of power savings.
 665          * If not (unlikely), enable L0S, so there is at least some
 666          *    power savings, even without L1.
 667          */
 668         u16 lctl = iwl_pciexp_link_ctrl(trans);
 669
 670         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 671                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 672                 /* L1-ASPM enabled; disable(!) L0S */
 673                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 674                 dev_printk(KERN_INFO, trans->dev,
 675                            "L1 Enabled; Disabling L0S\n");
 676         } else {
 677                 /* L1-ASPM disabled; enable(!) L0S */
 678                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 679                 dev_printk(KERN_INFO, trans->dev,
 680                            "L1 Disabled; Enabling L0S\n");
 681         }
 682         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 683 }
 684
 685 /*
 686  * Start up NIC's basic functionality after it has been reset
 687  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 688  * NOTE:  This does not load uCode nor start the embedded processor
 689  */
 690 static int iwl_apm_init(struct iwl_trans *trans)
 691 {
 692         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 693         int ret = 0;
 694         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 695
 696         /*
 697          * Use "set_bit" below rather than "write", to preserve any hardware
 698          * bits already set by default after reset.
 699          */
 700
 701         /* Disable L0S exit timer (platform NMI Work/Around) */
 702         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 703                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 704
 705         /*
 706          * Disable L0s without affecting L1;
 707          *  don't wait for ICH L0s (ICH bug W/A)
 708          */
 709         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 710                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 711
 712         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 713         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 714
 715         /*
 716          * Enable HAP INTA (interrupt from management bus) to
 717          * wake device's PCI Express link L1a -> L0s
 718          */
 719         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 720                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 721
 722         iwl_apm_config(trans);
 723
 724         /* Configure analog phase-lock-loop before activating to D0A */
 725         if (trans->cfg->base_params->pll_cfg_val)
 726                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 727                             trans->cfg->base_params->pll_cfg_val);
 728
 729         /*
 730          * Set "initialization complete" bit to move adapter from
 731          * D0U* --> D0A* (powered-up active) state.
 732          */
 733         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 734
 735         /*
 736          * Wait for clock stabilization; once stabilized, access to
 737          * device-internal resources is supported, e.g. iwl_write_prph()
 738          * and accesses to uCode SRAM.
 739          */
 740         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 741                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 742                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 743         if (ret < 0) {
 744                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 745                 goto out;
 746         }
 747
 748         /*
 749          * Enable DMA clock and wait for it to stabilize.
 750          *
 751          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 752          * do not disable clocks.  This preserves any hardware bits already
 753          * set by default in "CLK_CTRL_REG" after reset.
 754          */
 755         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 756         udelay(20);
 757
 758         /* Disable L1-Active */
 759         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 760                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 761
 762         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 763
 764 out:
 765         return ret;
 766 }
 767
 768 static int iwl_apm_stop_master(struct iwl_trans *trans)
 769 {
 770         int ret = 0;
 771
 772         /* stop device's busmaster DMA activity */
 773         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 774
 775         ret = iwl_poll_bit(trans, CSR_RESET,
 776                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 777                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 778         if (ret)
 779                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 780
 781         IWL_DEBUG_INFO(trans, "stop master\n");
 782
 783         return ret;
 784 }
 785
 786 static void iwl_apm_stop(struct iwl_trans *trans)
 787 {
 788         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 789         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 790
 791         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 792
 793         /* Stop device's DMA activity */
 794         iwl_apm_stop_master(trans);
 795
 796         /* Reset the entire device */
 797         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 798
 799         udelay(10);
 800
 801         /*
 802          * Clear "initialization complete" bit to move adapter from
 803          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 804          */
 805         iwl_clear_bit(trans, CSR_GP_CNTRL,
 806                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 807 }
 808
 809 static int iwl_nic_init(struct iwl_trans *trans)
 810 {
 811         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 812         unsigned long flags;
 813
 814         /* nic_init */
 815         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 816         iwl_apm_init(trans);
 817
 818         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 819         iwl_write8(trans, CSR_INT_COALESCING,
 820                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 821
 822         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 823
 824         iwl_set_pwr_vmain(trans);
 825
 826         iwl_op_mode_nic_config(trans->op_mode);
 827
 828 #ifndef CONFIG_IWLWIFI_IDI
 829         /* Allocate the RX queue, or reset if it is already allocated */
 830         iwl_rx_init(trans);
 831 #endif
 832
 833         /* Allocate or reset and init all Tx and Command queues */
 834         if (iwl_tx_init(trans))
 835                 return -ENOMEM;
 836
 837         if (trans->cfg->base_params->shadow_reg_enable) {
 838                 /* enable shadow regs in HW */
 839                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 840                         0x800FFFFF);
 841         }
 842
 843         return 0;
 844 }
 845
 846 #define HW_READY_TIMEOUT (50)
 847
 848 /* Note: returns poll_bit return value, which is >= 0 if success */
 849 static int iwl_set_hw_ready(struct iwl_trans *trans)
 850 {
 851         int ret;
 852
 853         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 854                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 855
 856         /* See if we got it */
 857         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 858                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 859                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 860                                 HW_READY_TIMEOUT);
 861
 862         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 863         return ret;
 864 }
 865
 866 /* Note: returns standard 0/-ERROR code */
 867 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 868 {
 869         int ret;
 870
 871         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 872
 873         ret = iwl_set_hw_ready(trans);
 874         /* If the card is ready, exit 0 */
 875         if (ret >= 0)
 876                 return 0;
 877
 878         /* If HW is not ready, prepare the conditions to check again */
 879         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 880                         CSR_HW_IF_CONFIG_REG_PREPARE);
 881
 882         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 883                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 884                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 885
 886         if (ret < 0)
 887                 return ret;
 888
 889         /* HW should be ready by now, check again. */
 890         ret = iwl_set_hw_ready(trans);
 891         if (ret >= 0)
 892                 return 0;
 893         return ret;
 894 }
 895
 896 /*
 897  * ucode
 898  */
 899 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
 900                             const struct fw_desc *section)
 901 {
 902         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 903         dma_addr_t phy_addr = section->p_addr;
 904         u32 byte_cnt = section->len;
 905         u32 dst_addr = section->offset;
 906         int ret;
 907
 908         trans_pcie->ucode_write_complete = false;
 909
 910         iwl_write_direct32(trans,
 911                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 912                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 913
 914         iwl_write_direct32(trans,
 915                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 916
 917         iwl_write_direct32(trans,
 918                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 919                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 920
 921         iwl_write_direct32(trans,
 922                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 923                 (iwl_get_dma_hi_addr(phy_addr)
 924                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 925
 926         iwl_write_direct32(trans,
 927                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 928                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 929                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 930                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 931
 932         iwl_write_direct32(trans,
 933                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 934                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 935                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 936                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 937
 938         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 939                      section_num);
 940         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 941                                  trans_pcie->ucode_write_complete, 5 * HZ);
 942         if (!ret) {
 943                 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
 944                         section_num);
 945                 return -ETIMEDOUT;
 946         }
 947
 948         return 0;
 949 }
 950
 951 static int iwl_load_given_ucode(struct iwl_trans *trans,
 952                                 const struct fw_img *image)
 953 {
 954         int ret = 0;
 955                 int i;
 956
 957                 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 958                         if (!image->sec[i].p_addr)
 959                                 break;
 960
 961                         ret = iwl_load_section(trans, i, &image->sec[i]);
 962                         if (ret)
 963                                 return ret;
 964                 }
 965
 966         /* Remove all resets to allow NIC to operate */
 967         iwl_write32(trans, CSR_RESET, 0);
 968
 969         return 0;
 970 }
 971
 972 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 973                                    const struct fw_img *fw)
 974 {
 975         int ret;
 976         bool hw_rfkill;
 977
 978         /* This may fail if AMT took ownership of the device */
 979         if (iwl_prepare_card_hw(trans)) {
 980                 IWL_WARN(trans, "Exit HW not ready\n");
 981                 return -EIO;
 982         }
 983
 984         iwl_enable_rfkill_int(trans);
 985
 986         /* If platform's RF_KILL switch is NOT set to KILL */
 987         hw_rfkill = iwl_is_rfkill_set(trans);
 988         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 989         if (hw_rfkill)
 990                 return -ERFKILL;
 991
 992         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 993
 994         ret = iwl_nic_init(trans);
 995         if (ret) {
 996                 IWL_ERR(trans, "Unable to init nic\n");
 997                 return ret;
 998         }
 999
1000         /* make sure rfkill handshake bits are cleared */
1001         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1002         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1003                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1004
1005         /* clear (again), then enable host interrupts */
1006         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1007         iwl_enable_interrupts(trans);
1008
1009         /* really make sure rfkill handshake bits are cleared */
1010         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1011         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1012
1013         /* Load the given image to the HW */
1014         return iwl_load_given_ucode(trans, fw);
1015 }
1016
1017 /*
1018  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1019  * must be called under the irq lock and with MAC access
1020  */
1021 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1022 {
1023         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1024                 IWL_TRANS_GET_PCIE_TRANS(trans);
1025
1026         lockdep_assert_held(&trans_pcie->irq_lock);
1027
1028         iwl_write_prph(trans, SCD_TXFACT, mask);
1029 }
1030
1031 static void iwl_tx_start(struct iwl_trans *trans)
1032 {
1033         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1034         u32 a;
1035         unsigned long flags;
1036         int i, chan;
1037         u32 reg_val;
1038
1039         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1040
1041         trans_pcie->scd_base_addr =
1042                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1043         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1044         /* reset conext data memory */
1045         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1046                 a += 4)
1047                 iwl_write_targ_mem(trans, a, 0);
1048         /* reset tx status memory */
1049         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1050                 a += 4)
1051                 iwl_write_targ_mem(trans, a, 0);
1052         for (; a < trans_pcie->scd_base_addr +
1053                SCD_TRANS_TBL_OFFSET_QUEUE(
1054                                 trans->cfg->base_params->num_of_queues);
1055                a += 4)
1056                 iwl_write_targ_mem(trans, a, 0);
1057
1058         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1059                        trans_pcie->scd_bc_tbls.dma >> 10);
1060
1061         /* Enable DMA channel */
1062         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1063                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1064                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1065                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1066
1067         /* Update FH chicken bits */
1068         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1069         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1070                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1071
1072         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1073                 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1074         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1075
1076         /* initiate the queues */
1077         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1078                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1079                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1080                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1081                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1082                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1083                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1084                                 sizeof(u32),
1085                                 ((SCD_WIN_SIZE <<
1086                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1087                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1088                                 ((SCD_FRAME_LIMIT <<
1089                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1090                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1091         }
1092
1093         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1094                         IWL_MASK(0, trans->cfg->base_params->num_of_queues));
1095
1096         /* Activate all Tx DMA/FIFO channels */
1097         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1098
1099         iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0);
1100
1101         /* make sure all queue are not stopped/used */
1102         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1103         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1104
1105         for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
1106                 int fifo = trans_pcie->setup_q_to_fifo[i];
1107
1108                 set_bit(i, trans_pcie->queue_used);
1109
1110                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1111                                               fifo, true);
1112         }
1113
1114         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1115
1116         /* Enable L1-Active */
1117         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1118                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1119 }
1120
1121 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1122 {
1123         iwl_reset_ict(trans);
1124         iwl_tx_start(trans);
1125 }
1126
1127 /**
1128  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1129  */
1130 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1131 {
1132         int ch, txq_id, ret;
1133         unsigned long flags;
1134         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1135
1136         /* Turn off all Tx DMA fifos */
1137         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1138
1139         iwl_trans_txq_set_sched(trans, 0);
1140
1141         /* Stop each Tx DMA channel, and wait for it to be idle */
1142         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1143                 iwl_write_direct32(trans,
1144                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1145                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1146                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1147                                     1000);
1148                 if (ret < 0)
1149                         IWL_ERR(trans, "Failing on timeout while stopping"
1150                             " DMA channel %d [0x%08x]", ch,
1151                             iwl_read_direct32(trans,
1152                                               FH_TSSR_TX_STATUS_REG));
1153         }
1154         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1155
1156         if (!trans_pcie->txq) {
1157                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1158                 return 0;
1159         }
1160
1161         /* Unmap DMA from host system and free skb's */
1162         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1163              txq_id++)
1164                 iwl_tx_queue_unmap(trans, txq_id);
1165
1166         return 0;
1167 }
1168
1169 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1170 {
1171         unsigned long flags;
1172         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1173
1174         /* tell the device to stop sending interrupts */
1175         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1176         iwl_disable_interrupts(trans);
1177         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1178
1179         /* device going down, Stop using ICT table */
1180         iwl_disable_ict(trans);
1181
1182         /*
1183          * If a HW restart happens during firmware loading,
1184          * then the firmware loading might call this function
1185          * and later it might be called again due to the
1186          * restart. So don't process again if the device is
1187          * already dead.
1188          */
1189         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1190                 iwl_trans_tx_stop(trans);
1191 #ifndef CONFIG_IWLWIFI_IDI
1192                 iwl_trans_rx_stop(trans);
1193 #endif
1194                 /* Power-down device's busmaster DMA clocks */
1195                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1196                                APMG_CLK_VAL_DMA_CLK_RQT);
1197                 udelay(5);
1198         }
1199
1200         /* Make sure (redundant) we've released our request to stay awake */
1201         iwl_clear_bit(trans, CSR_GP_CNTRL,
1202                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1203
1204         /* Stop the device, and put it in low power state */
1205         iwl_apm_stop(trans);
1206
1207         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1208          * Clean again the interrupt here
1209          */
1210         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1211         iwl_disable_interrupts(trans);
1212         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1213
1214         iwl_enable_rfkill_int(trans);
1215
1216         /* wait to make sure we flush pending tasklet*/
1217         synchronize_irq(trans_pcie->irq);
1218         tasklet_kill(&trans_pcie->irq_tasklet);
1219
1220         cancel_work_sync(&trans_pcie->rx_replenish);
1221
1222         /* stop and reset the on-board processor */
1223         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1224
1225         /* clear all status bits */
1226         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1227         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1228         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1229         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1230 }
1231
1232 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1233 {
1234         /* let the ucode operate on its own */
1235         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1236                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1237
1238         iwl_disable_interrupts(trans);
1239         iwl_clear_bit(trans, CSR_GP_CNTRL,
1240                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1241 }
1242
1243 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1244                              struct iwl_device_cmd *dev_cmd, int txq_id)
1245 {
1246         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1247         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1248         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1249         struct iwl_cmd_meta *out_meta;
1250         struct iwl_tx_queue *txq;
1251         struct iwl_queue *q;
1252         dma_addr_t phys_addr = 0;
1253         dma_addr_t txcmd_phys;
1254         dma_addr_t scratch_phys;
1255         u16 len, firstlen, secondlen;
1256         u8 wait_write_ptr = 0;
1257         __le16 fc = hdr->frame_control;
1258         u8 hdr_len = ieee80211_hdrlen(fc);
1259         u16 __maybe_unused wifi_seq;
1260
1261         txq = &trans_pcie->txq[txq_id];
1262         q = &txq->q;
1263
1264         if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1265                 WARN_ON_ONCE(1);
1266                 return -EINVAL;
1267         }
1268
1269         spin_lock(&txq->lock);
1270
1271         /* Set up driver data for this TFD */
1272         txq->entries[q->write_ptr].skb = skb;
1273         txq->entries[q->write_ptr].cmd = dev_cmd;
1274
1275         dev_cmd->hdr.cmd = REPLY_TX;
1276         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1277                                 INDEX_TO_SEQ(q->write_ptr)));
1278
1279         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1280         out_meta = &txq->entries[q->write_ptr].meta;
1281
1282         /*
1283          * Use the first empty entry in this queue's command buffer array
1284          * to contain the Tx command and MAC header concatenated together
1285          * (payload data will be in another buffer).
1286          * Size of this varies, due to varying MAC header length.
1287          * If end is not dword aligned, we'll have 2 extra bytes at the end
1288          * of the MAC header (device reads on dword boundaries).
1289          * We'll tell device about this padding later.
1290          */
1291         len = sizeof(struct iwl_tx_cmd) +
1292                 sizeof(struct iwl_cmd_header) + hdr_len;
1293         firstlen = (len + 3) & ~3;
1294
1295         /* Tell NIC about any 2-byte padding after MAC header */
1296         if (firstlen != len)
1297                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1298
1299         /* Physical address of this Tx command's header (not MAC header!),
1300          * within command buffer array. */
1301         txcmd_phys = dma_map_single(trans->dev,
1302                                     &dev_cmd->hdr, firstlen,
1303                                     DMA_BIDIRECTIONAL);
1304         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1305                 goto out_err;
1306         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1307         dma_unmap_len_set(out_meta, len, firstlen);
1308
1309         if (!ieee80211_has_morefrags(fc)) {
1310                 txq->need_update = 1;
1311         } else {
1312                 wait_write_ptr = 1;
1313                 txq->need_update = 0;
1314         }
1315
1316         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1317          * if any (802.11 null frames have no payload). */
1318         secondlen = skb->len - hdr_len;
1319         if (secondlen > 0) {
1320                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1321                                            secondlen, DMA_TO_DEVICE);
1322                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1323                         dma_unmap_single(trans->dev,
1324                                          dma_unmap_addr(out_meta, mapping),
1325                                          dma_unmap_len(out_meta, len),
1326                                          DMA_BIDIRECTIONAL);
1327                         goto out_err;
1328                 }
1329         }
1330
1331         /* Attach buffers to TFD */
1332         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1333         if (secondlen > 0)
1334                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1335                                              secondlen, 0);
1336
1337         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1338                                 offsetof(struct iwl_tx_cmd, scratch);
1339
1340         /* take back ownership of DMA buffer to enable update */
1341         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1342                         DMA_BIDIRECTIONAL);
1343         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1344         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1345
1346         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1347                      le16_to_cpu(dev_cmd->hdr.sequence));
1348         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1349
1350         /* Set up entry for this TFD in Tx byte-count array */
1351         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1352
1353         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1354                         DMA_BIDIRECTIONAL);
1355
1356         trace_iwlwifi_dev_tx(trans->dev,
1357                              &txq->tfds[txq->q.write_ptr],
1358                              sizeof(struct iwl_tfd),
1359                              &dev_cmd->hdr, firstlen,
1360                              skb->data + hdr_len, secondlen);
1361
1362         /* start timer if queue currently empty */
1363         if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1364                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1365
1366         /* Tell device the write index *just past* this latest filled TFD */
1367         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1368         iwl_txq_update_write_ptr(trans, txq);
1369
1370         /*
1371          * At this point the frame is "transmitted" successfully
1372          * and we will get a TX status notification eventually,
1373          * regardless of the value of ret. "ret" only indicates
1374          * whether or not we should update the write pointer.
1375          */
1376         if (iwl_queue_space(q) < q->high_mark) {
1377                 if (wait_write_ptr) {
1378                         txq->need_update = 1;
1379                         iwl_txq_update_write_ptr(trans, txq);
1380                 } else {
1381                         iwl_stop_queue(trans, txq);
1382                 }
1383         }
1384         spin_unlock(&txq->lock);
1385         return 0;
1386  out_err:
1387         spin_unlock(&txq->lock);
1388         return -1;
1389 }
1390
1391 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1392 {
1393         struct iwl_trans_pcie *trans_pcie =
1394                 IWL_TRANS_GET_PCIE_TRANS(trans);
1395         int err;
1396         bool hw_rfkill;
1397
1398         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1399
1400         if (!trans_pcie->irq_requested) {
1401                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1402                         iwl_irq_tasklet, (unsigned long)trans);
1403
1404                 iwl_alloc_isr_ict(trans);
1405
1406                 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1407                         DRV_NAME, trans);
1408                 if (err) {
1409                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1410                                 trans_pcie->irq);
1411                         goto error;
1412                 }
1413
1414                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1415                 trans_pcie->irq_requested = true;
1416         }
1417
1418         err = iwl_prepare_card_hw(trans);
1419         if (err) {
1420                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1421                 goto err_free_irq;
1422         }
1423
1424         iwl_apm_init(trans);
1425
1426         /* From now on, the op_mode will be kept updated about RF kill state */
1427         iwl_enable_rfkill_int(trans);
1428
1429         hw_rfkill = iwl_is_rfkill_set(trans);
1430         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1431
1432         return err;
1433
1434 err_free_irq:
1435         free_irq(trans_pcie->irq, trans);
1436 error:
1437         iwl_free_isr_ict(trans);
1438         tasklet_kill(&trans_pcie->irq_tasklet);
1439         return err;
1440 }
1441
1442 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1443                                    bool op_mode_leaving)
1444 {
1445         bool hw_rfkill;
1446         unsigned long flags;
1447         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1448
1449         iwl_apm_stop(trans);
1450
1451         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1452         iwl_disable_interrupts(trans);
1453         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1454
1455         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1456
1457         if (!op_mode_leaving) {
1458                 /*
1459                  * Even if we stop the HW, we still want the RF kill
1460                  * interrupt
1461                  */
1462                 iwl_enable_rfkill_int(trans);
1463
1464                 /*
1465                  * Check again since the RF kill state may have changed while
1466                  * all the interrupts were disabled, in this case we couldn't
1467                  * receive the RF kill interrupt and update the state in the
1468                  * op_mode.
1469                  */
1470                 hw_rfkill = iwl_is_rfkill_set(trans);
1471                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1472         }
1473 }
1474
1475 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1476                                    struct sk_buff_head *skbs)
1477 {
1478         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1479         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1480         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1481         int tfd_num = ssn & (txq->q.n_bd - 1);
1482         int freed = 0;
1483
1484         spin_lock(&txq->lock);
1485
1486         if (txq->q.read_ptr != tfd_num) {
1487                 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1488                                    txq_id, txq->q.read_ptr, tfd_num, ssn);
1489                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1490                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1491                         iwl_wake_queue(trans, txq);
1492         }
1493
1494         spin_unlock(&txq->lock);
1495 }
1496
1497 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1498 {
1499         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1500 }
1501
1502 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1503 {
1504         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1505 }
1506
1507 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1508 {
1509         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1510 }
1511
1512 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1513                                      const struct iwl_trans_config *trans_cfg)
1514 {
1515         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1516
1517         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1518         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1519                 trans_pcie->n_no_reclaim_cmds = 0;
1520         else
1521                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1522         if (trans_pcie->n_no_reclaim_cmds)
1523                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1524                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1525
1526         trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo;
1527
1528         if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES))
1529                 trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES;
1530
1531         /* at least the command queue must be mapped */
1532         WARN_ON(!trans_pcie->n_q_to_fifo);
1533
1534         memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo,
1535                trans_pcie->n_q_to_fifo * sizeof(u8));
1536
1537         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1538         if (trans_pcie->rx_buf_size_8k)
1539                 trans_pcie->rx_page_order = get_order(8 * 1024);
1540         else
1541                 trans_pcie->rx_page_order = get_order(4 * 1024);
1542
1543         trans_pcie->wd_timeout =
1544                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1545
1546         trans_pcie->command_names = trans_cfg->command_names;
1547 }
1548
1549 void iwl_trans_pcie_free(struct iwl_trans *trans)
1550 {
1551         struct iwl_trans_pcie *trans_pcie =
1552                 IWL_TRANS_GET_PCIE_TRANS(trans);
1553
1554         iwl_trans_pcie_tx_free(trans);
1555 #ifndef CONFIG_IWLWIFI_IDI
1556         iwl_trans_pcie_rx_free(trans);
1557 #endif
1558         if (trans_pcie->irq_requested == true) {
1559                 free_irq(trans_pcie->irq, trans);
1560                 iwl_free_isr_ict(trans);
1561         }
1562
1563         pci_disable_msi(trans_pcie->pci_dev);
1564         iounmap(trans_pcie->hw_base);
1565         pci_release_regions(trans_pcie->pci_dev);
1566         pci_disable_device(trans_pcie->pci_dev);
1567
1568         kfree(trans);
1569 }
1570
1571 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1572 {
1573         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1574
1575         if (state)
1576                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1577         else
1578                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1579 }
1580
1581 #ifdef CONFIG_PM_SLEEP
1582 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1583 {
1584         return 0;
1585 }
1586
1587 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1588 {
1589         bool hw_rfkill;
1590
1591         iwl_enable_rfkill_int(trans);
1592
1593         hw_rfkill = iwl_is_rfkill_set(trans);
1594         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1595
1596         if (!hw_rfkill)
1597                 iwl_enable_interrupts(trans);
1598
1599         return 0;
1600 }
1601 #endif /* CONFIG_PM_SLEEP */
1602
1603 #define IWL_FLUSH_WAIT_MS       2000
1604
1605 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1606 {
1607         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1608         struct iwl_tx_queue *txq;
1609         struct iwl_queue *q;
1610         int cnt;
1611         unsigned long now = jiffies;
1612         int ret = 0;
1613
1614         /* waiting for all the tx frames complete might take a while */
1615         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1616                 if (cnt == trans_pcie->cmd_queue)
1617                         continue;
1618                 txq = &trans_pcie->txq[cnt];
1619                 q = &txq->q;
1620                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1621                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1622                         msleep(1);
1623
1624                 if (q->read_ptr != q->write_ptr) {
1625                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1626                         ret = -ETIMEDOUT;
1627                         break;
1628                 }
1629         }
1630         return ret;
1631 }
1632
1633 static const char *get_fh_string(int cmd)
1634 {
1635 #define IWL_CMD(x) case x: return #x
1636         switch (cmd) {
1637         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1638         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1639         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1640         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1641         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1642         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1643         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1644         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1645         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1646         default:
1647                 return "UNKNOWN";
1648         }
1649 #undef IWL_CMD
1650 }
1651
1652 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1653 {
1654         int i;
1655 #ifdef CONFIG_IWLWIFI_DEBUG
1656         int pos = 0;
1657         size_t bufsz = 0;
1658 #endif
1659         static const u32 fh_tbl[] = {
1660                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1661                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1662                 FH_RSCSR_CHNL0_WPTR,
1663                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1664                 FH_MEM_RSSR_SHARED_CTRL_REG,
1665                 FH_MEM_RSSR_RX_STATUS_REG,
1666                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1667                 FH_TSSR_TX_STATUS_REG,
1668                 FH_TSSR_TX_ERROR_REG
1669         };
1670 #ifdef CONFIG_IWLWIFI_DEBUG
1671         if (display) {
1672                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1673                 *buf = kmalloc(bufsz, GFP_KERNEL);
1674                 if (!*buf)
1675                         return -ENOMEM;
1676                 pos += scnprintf(*buf + pos, bufsz - pos,
1677                                 "FH register values:\n");
1678                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1679                         pos += scnprintf(*buf + pos, bufsz - pos,
1680                                 "  %34s: 0X%08x\n",
1681                                 get_fh_string(fh_tbl[i]),
1682                                 iwl_read_direct32(trans, fh_tbl[i]));
1683                 }
1684                 return pos;
1685         }
1686 #endif
1687         IWL_ERR(trans, "FH register values:\n");
1688         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1689                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1690                         get_fh_string(fh_tbl[i]),
1691                         iwl_read_direct32(trans, fh_tbl[i]));
1692         }
1693         return 0;
1694 }
1695
1696 static const char *get_csr_string(int cmd)
1697 {
1698 #define IWL_CMD(x) case x: return #x
1699         switch (cmd) {
1700         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1701         IWL_CMD(CSR_INT_COALESCING);
1702         IWL_CMD(CSR_INT);
1703         IWL_CMD(CSR_INT_MASK);
1704         IWL_CMD(CSR_FH_INT_STATUS);
1705         IWL_CMD(CSR_GPIO_IN);
1706         IWL_CMD(CSR_RESET);
1707         IWL_CMD(CSR_GP_CNTRL);
1708         IWL_CMD(CSR_HW_REV);
1709         IWL_CMD(CSR_EEPROM_REG);
1710         IWL_CMD(CSR_EEPROM_GP);
1711         IWL_CMD(CSR_OTP_GP_REG);
1712         IWL_CMD(CSR_GIO_REG);
1713         IWL_CMD(CSR_GP_UCODE_REG);
1714         IWL_CMD(CSR_GP_DRIVER_REG);
1715         IWL_CMD(CSR_UCODE_DRV_GP1);
1716         IWL_CMD(CSR_UCODE_DRV_GP2);
1717         IWL_CMD(CSR_LED_REG);
1718         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1719         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1720         IWL_CMD(CSR_ANA_PLL_CFG);
1721         IWL_CMD(CSR_HW_REV_WA_REG);
1722         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1723         default:
1724                 return "UNKNOWN";
1725         }
1726 #undef IWL_CMD
1727 }
1728
1729 void iwl_dump_csr(struct iwl_trans *trans)
1730 {
1731         int i;
1732         static const u32 csr_tbl[] = {
1733                 CSR_HW_IF_CONFIG_REG,
1734                 CSR_INT_COALESCING,
1735                 CSR_INT,
1736                 CSR_INT_MASK,
1737                 CSR_FH_INT_STATUS,
1738                 CSR_GPIO_IN,
1739                 CSR_RESET,
1740                 CSR_GP_CNTRL,
1741                 CSR_HW_REV,
1742                 CSR_EEPROM_REG,
1743                 CSR_EEPROM_GP,
1744                 CSR_OTP_GP_REG,
1745                 CSR_GIO_REG,
1746                 CSR_GP_UCODE_REG,
1747                 CSR_GP_DRIVER_REG,
1748                 CSR_UCODE_DRV_GP1,
1749                 CSR_UCODE_DRV_GP2,
1750                 CSR_LED_REG,
1751                 CSR_DRAM_INT_TBL_REG,
1752                 CSR_GIO_CHICKEN_BITS,
1753                 CSR_ANA_PLL_CFG,
1754                 CSR_HW_REV_WA_REG,
1755                 CSR_DBG_HPET_MEM_REG
1756         };
1757         IWL_ERR(trans, "CSR values:\n");
1758         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1759                 "CSR_INT_PERIODIC_REG)\n");
1760         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1761                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1762                         get_csr_string(csr_tbl[i]),
1763                         iwl_read32(trans, csr_tbl[i]));
1764         }
1765 }
1766
1767 #ifdef CONFIG_IWLWIFI_DEBUGFS
1768 /* create and remove of files */
1769 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1770         if (!debugfs_create_file(#name, mode, parent, trans,            \
1771                                  &iwl_dbgfs_##name##_ops))              \
1772                 return -ENOMEM;                                         \
1773 } while (0)
1774
1775 /* file operation */
1776 #define DEBUGFS_READ_FUNC(name)                                         \
1777 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1778                                         char __user *user_buf,          \
1779                                         size_t count, loff_t *ppos);
1780
1781 #define DEBUGFS_WRITE_FUNC(name)                                        \
1782 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1783                                         const char __user *user_buf,    \
1784                                         size_t count, loff_t *ppos);
1785
1786
1787 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1788         DEBUGFS_READ_FUNC(name);                                        \
1789 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1790         .read = iwl_dbgfs_##name##_read,                                \
1791         .open = simple_open,                                            \
1792         .llseek = generic_file_llseek,                                  \
1793 };
1794
1795 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1796         DEBUGFS_WRITE_FUNC(name);                                       \
1797 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1798         .write = iwl_dbgfs_##name##_write,                              \
1799         .open = simple_open,                                            \
1800         .llseek = generic_file_llseek,                                  \
1801 };
1802
1803 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1804         DEBUGFS_READ_FUNC(name);                                        \
1805         DEBUGFS_WRITE_FUNC(name);                                       \
1806 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1807         .write = iwl_dbgfs_##name##_write,                              \
1808         .read = iwl_dbgfs_##name##_read,                                \
1809         .open = simple_open,                                            \
1810         .llseek = generic_file_llseek,                                  \
1811 };
1812
1813 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1814                                                 char __user *user_buf,
1815                                                 size_t count, loff_t *ppos)
1816 {
1817         struct iwl_trans *trans = file->private_data;
1818         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1819         struct iwl_tx_queue *txq;
1820         struct iwl_queue *q;
1821         char *buf;
1822         int pos = 0;
1823         int cnt;
1824         int ret;
1825         size_t bufsz;
1826
1827         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1828
1829         if (!trans_pcie->txq)
1830                 return -EAGAIN;
1831
1832         buf = kzalloc(bufsz, GFP_KERNEL);
1833         if (!buf)
1834                 return -ENOMEM;
1835
1836         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1837                 txq = &trans_pcie->txq[cnt];
1838                 q = &txq->q;
1839                 pos += scnprintf(buf + pos, bufsz - pos,
1840                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1841                                 cnt, q->read_ptr, q->write_ptr,
1842                                 !!test_bit(cnt, trans_pcie->queue_used),
1843                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1844         }
1845         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1846         kfree(buf);
1847         return ret;
1848 }
1849
1850 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1851                                                 char __user *user_buf,
1852                                                 size_t count, loff_t *ppos) {
1853         struct iwl_trans *trans = file->private_data;
1854         struct iwl_trans_pcie *trans_pcie =
1855                 IWL_TRANS_GET_PCIE_TRANS(trans);
1856         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1857         char buf[256];
1858         int pos = 0;
1859         const size_t bufsz = sizeof(buf);
1860
1861         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1862                                                 rxq->read);
1863         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1864                                                 rxq->write);
1865         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1866                                                 rxq->free_count);
1867         if (rxq->rb_stts) {
1868                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1869                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1870         } else {
1871                 pos += scnprintf(buf + pos, bufsz - pos,
1872                                         "closed_rb_num: Not Allocated\n");
1873         }
1874         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1875 }
1876
1877 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1878                                         char __user *user_buf,
1879                                         size_t count, loff_t *ppos) {
1880
1881         struct iwl_trans *trans = file->private_data;
1882         struct iwl_trans_pcie *trans_pcie =
1883                 IWL_TRANS_GET_PCIE_TRANS(trans);
1884         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1885
1886         int pos = 0;
1887         char *buf;
1888         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1889         ssize_t ret;
1890
1891         buf = kzalloc(bufsz, GFP_KERNEL);
1892         if (!buf)
1893                 return -ENOMEM;
1894
1895         pos += scnprintf(buf + pos, bufsz - pos,
1896                         "Interrupt Statistics Report:\n");
1897
1898         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1899                 isr_stats->hw);
1900         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1901                 isr_stats->sw);
1902         if (isr_stats->sw || isr_stats->hw) {
1903                 pos += scnprintf(buf + pos, bufsz - pos,
1904                         "\tLast Restarting Code:  0x%X\n",
1905                         isr_stats->err_code);
1906         }
1907 #ifdef CONFIG_IWLWIFI_DEBUG
1908         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1909                 isr_stats->sch);
1910         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1911                 isr_stats->alive);
1912 #endif
1913         pos += scnprintf(buf + pos, bufsz - pos,
1914                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1915
1916         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1917                 isr_stats->ctkill);
1918
1919         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1920                 isr_stats->wakeup);
1921
1922         pos += scnprintf(buf + pos, bufsz - pos,
1923                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1924
1925         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1926                 isr_stats->tx);
1927
1928         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1929                 isr_stats->unhandled);
1930
1931         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1932         kfree(buf);
1933         return ret;
1934 }
1935
1936 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1937                                          const char __user *user_buf,
1938                                          size_t count, loff_t *ppos)
1939 {
1940         struct iwl_trans *trans = file->private_data;
1941         struct iwl_trans_pcie *trans_pcie =
1942                 IWL_TRANS_GET_PCIE_TRANS(trans);
1943         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1944
1945         char buf[8];
1946         int buf_size;
1947         u32 reset_flag;
1948
1949         memset(buf, 0, sizeof(buf));
1950         buf_size = min(count, sizeof(buf) -  1);
1951         if (copy_from_user(buf, user_buf, buf_size))
1952                 return -EFAULT;
1953         if (sscanf(buf, "%x", &reset_flag) != 1)
1954                 return -EFAULT;
1955         if (reset_flag == 0)
1956                 memset(isr_stats, 0, sizeof(*isr_stats));
1957
1958         return count;
1959 }
1960
1961 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1962                                          const char __user *user_buf,
1963                                          size_t count, loff_t *ppos)
1964 {
1965         struct iwl_trans *trans = file->private_data;
1966         char buf[8];
1967         int buf_size;
1968         int csr;
1969
1970         memset(buf, 0, sizeof(buf));
1971         buf_size = min(count, sizeof(buf) -  1);
1972         if (copy_from_user(buf, user_buf, buf_size))
1973                 return -EFAULT;
1974         if (sscanf(buf, "%d", &csr) != 1)
1975                 return -EFAULT;
1976
1977         iwl_dump_csr(trans);
1978
1979         return count;
1980 }
1981
1982 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1983                                          char __user *user_buf,
1984                                          size_t count, loff_t *ppos)
1985 {
1986         struct iwl_trans *trans = file->private_data;
1987         char *buf;
1988         int pos = 0;
1989         ssize_t ret = -EFAULT;
1990
1991         ret = pos = iwl_dump_fh(trans, &buf, true);
1992         if (buf) {
1993                 ret = simple_read_from_buffer(user_buf,
1994                                               count, ppos, buf, pos);
1995                 kfree(buf);
1996         }
1997
1998         return ret;
1999 }
2000
2001 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
2002                                           const char __user *user_buf,
2003                                           size_t count, loff_t *ppos)
2004 {
2005         struct iwl_trans *trans = file->private_data;
2006
2007         if (!trans->op_mode)
2008                 return -EAGAIN;
2009
2010         iwl_op_mode_nic_error(trans->op_mode);
2011
2012         return count;
2013 }
2014
2015 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2016 DEBUGFS_READ_FILE_OPS(fh_reg);
2017 DEBUGFS_READ_FILE_OPS(rx_queue);
2018 DEBUGFS_READ_FILE_OPS(tx_queue);
2019 DEBUGFS_WRITE_FILE_OPS(csr);
2020 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2021
2022 /*
2023  * Create the debugfs files and directories
2024  *
2025  */
2026 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2027                                         struct dentry *dir)
2028 {
2029         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2030         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2031         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2032         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2033         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2034         DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2035         return 0;
2036 }
2037 #else
2038 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2039                                         struct dentry *dir)
2040 { return 0; }
2041
2042 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2043
2044 static const struct iwl_trans_ops trans_ops_pcie = {
2045         .start_hw = iwl_trans_pcie_start_hw,
2046         .stop_hw = iwl_trans_pcie_stop_hw,
2047         .fw_alive = iwl_trans_pcie_fw_alive,
2048         .start_fw = iwl_trans_pcie_start_fw,
2049         .stop_device = iwl_trans_pcie_stop_device,
2050
2051         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2052
2053         .send_cmd = iwl_trans_pcie_send_cmd,
2054
2055         .tx = iwl_trans_pcie_tx,
2056         .reclaim = iwl_trans_pcie_reclaim,
2057
2058         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2059         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2060
2061         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2062
2063         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2064
2065 #ifdef CONFIG_PM_SLEEP
2066         .suspend = iwl_trans_pcie_suspend,
2067         .resume = iwl_trans_pcie_resume,
2068 #endif
2069         .write8 = iwl_trans_pcie_write8,
2070         .write32 = iwl_trans_pcie_write32,
2071         .read32 = iwl_trans_pcie_read32,
2072         .configure = iwl_trans_pcie_configure,
2073         .set_pmi = iwl_trans_pcie_set_pmi,
2074 };
2075
2076 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2077                                        const struct pci_device_id *ent,
2078                                        const struct iwl_cfg *cfg)
2079 {
2080         struct iwl_trans_pcie *trans_pcie;
2081         struct iwl_trans *trans;
2082         u16 pci_cmd;
2083         int err;
2084
2085         trans = kzalloc(sizeof(struct iwl_trans) +
2086                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2087
2088         if (WARN_ON(!trans))
2089                 return NULL;
2090
2091         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2092
2093         trans->ops = &trans_ops_pcie;
2094         trans->cfg = cfg;
2095         trans_pcie->trans = trans;
2096         spin_lock_init(&trans_pcie->irq_lock);
2097         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2098
2099         /* W/A - seems to solve weird behavior. We need to remove this if we
2100          * don't want to stay in L1 all the time. This wastes a lot of power */
2101         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2102                                 PCIE_LINK_STATE_CLKPM);
2103
2104         if (pci_enable_device(pdev)) {
2105                 err = -ENODEV;
2106                 goto out_no_pci;
2107         }
2108
2109         pci_set_master(pdev);
2110
2111         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2112         if (!err)
2113                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2114         if (err) {
2115                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2116                 if (!err)
2117                         err = pci_set_consistent_dma_mask(pdev,
2118                                                         DMA_BIT_MASK(32));
2119                 /* both attempts failed: */
2120                 if (err) {
2121                         dev_printk(KERN_ERR, &pdev->dev,
2122                                    "No suitable DMA available.\n");
2123                         goto out_pci_disable_device;
2124                 }
2125         }
2126
2127         err = pci_request_regions(pdev, DRV_NAME);
2128         if (err) {
2129                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2130                 goto out_pci_disable_device;
2131         }
2132
2133         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2134         if (!trans_pcie->hw_base) {
2135                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2136                 err = -ENODEV;
2137                 goto out_pci_release_regions;
2138         }
2139
2140         dev_printk(KERN_INFO, &pdev->dev,
2141                 "pci_resource_len = 0x%08llx\n",
2142                 (unsigned long long) pci_resource_len(pdev, 0));
2143         dev_printk(KERN_INFO, &pdev->dev,
2144                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2145
2146         dev_printk(KERN_INFO, &pdev->dev,
2147                 "HW Revision ID = 0x%X\n", pdev->revision);
2148
2149         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2150          * PCI Tx retries from interfering with C3 CPU state */
2151         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2152
2153         err = pci_enable_msi(pdev);
2154         if (err)
2155                 dev_printk(KERN_ERR, &pdev->dev,
2156                         "pci_enable_msi failed(0X%x)", err);
2157
2158         trans->dev = &pdev->dev;
2159         trans_pcie->irq = pdev->irq;
2160         trans_pcie->pci_dev = pdev;
2161         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2162         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2163         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2164                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2165
2166         /* TODO: Move this away, not needed if not MSI */
2167         /* enable rfkill interrupt: hw bug w/a */
2168         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2169         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2170                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2171                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2172         }
2173
2174         /* Initialize the wait queue for commands */
2175         init_waitqueue_head(&trans->wait_command_queue);
2176         spin_lock_init(&trans->reg_lock);
2177
2178         return trans;
2179
2180 out_pci_release_regions:
2181         pci_release_regions(pdev);
2182 out_pci_disable_device:
2183         pci_disable_device(pdev);
2184 out_no_pci:
2185         kfree(trans);
2186         return NULL;
2187 }
2188