drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  33  *
  34  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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  39  * modification, are permitted provided that the following conditions
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  43  *    notice, this list of conditions and the following disclaimer.
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  46  *    the documentation and/or other materials provided with the
  47  *    distribution.
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  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-agn-hw.h"
  79 #include "iwl-fw-error-dump.h"
  80 #include "internal.h"
  81
  82 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  83 {
  84         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  85
  86         if (!trans_pcie->fw_mon_page)
  87                 return;
  88
  89         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  90                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  91         __free_pages(trans_pcie->fw_mon_page,
  92                      get_order(trans_pcie->fw_mon_size));
  93         trans_pcie->fw_mon_page = NULL;
  94         trans_pcie->fw_mon_phys = 0;
  95         trans_pcie->fw_mon_size = 0;
  96 }
  97
  98 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
  99 {
 100         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 101         struct page *page;
 102         dma_addr_t phys;
 103         u32 size;
 104         u8 power;
 105
 106         if (trans_pcie->fw_mon_page) {
 107                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 108                                            trans_pcie->fw_mon_size,
 109                                            DMA_FROM_DEVICE);
 110                 return;
 111         }
 112
 113         phys = 0;
 114         for (power = 26; power >= 11; power--) {
 115                 int order;
 116
 117                 size = BIT(power);
 118                 order = get_order(size);
 119                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 120                                    order);
 121                 if (!page)
 122                         continue;
 123
 124                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 125                                     DMA_FROM_DEVICE);
 126                 if (dma_mapping_error(trans->dev, phys)) {
 127                         __free_pages(page, order);
 128                         continue;
 129                 }
 130                 IWL_INFO(trans,
 131                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 132                          size, order);
 133                 break;
 134         }
 135
 136         if (WARN_ON_ONCE(!page))
 137                 return;
 138
 139         trans_pcie->fw_mon_page = page;
 140         trans_pcie->fw_mon_phys = phys;
 141         trans_pcie->fw_mon_size = size;
 142 }
 143
 144 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 145 {
 146         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 147                     ((reg & 0x0000ffff) | (2 << 28)));
 148         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 149 }
 150
 151 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 152 {
 153         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 154         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 155                     ((reg & 0x0000ffff) | (3 << 28)));
 156 }
 157
 158 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 159 {
 160         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 161                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 162                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 163                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 164         else
 165                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 166                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 167                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 168 }
 169
 170 /* PCI registers */
 171 #define PCI_CFG_RETRY_TIMEOUT   0x041
 172
 173 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 174 {
 175         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 176         u16 lctl;
 177         u16 cap;
 178
 179         /*
 180          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 181          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 182          * If so (likely), disable L0S, so device moves directly L0->L1;
 183          *    costs negligible amount of power savings.
 184          * If not (unlikely), enable L0S, so there is at least some
 185          *    power savings, even without L1.
 186          */
 187         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 188         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 189                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 190         else
 191                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 192         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 193
 194         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 195         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 196         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 197                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 198                  trans->ltr_enabled ? "En" : "Dis");
 199 }
 200
 201 /*
 202  * Start up NIC's basic functionality after it has been reset
 203  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 204  * NOTE:  This does not load uCode nor start the embedded processor
 205  */
 206 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 207 {
 208         int ret = 0;
 209         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 210
 211         /*
 212          * Use "set_bit" below rather than "write", to preserve any hardware
 213          * bits already set by default after reset.
 214          */
 215
 216         /* Disable L0S exit timer (platform NMI Work/Around) */
 217         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 218                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 219                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 220
 221         /*
 222          * Disable L0s without affecting L1;
 223          *  don't wait for ICH L0s (ICH bug W/A)
 224          */
 225         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 226                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 227
 228         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 229         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 230
 231         /*
 232          * Enable HAP INTA (interrupt from management bus) to
 233          * wake device's PCI Express link L1a -> L0s
 234          */
 235         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 236                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 237
 238         iwl_pcie_apm_config(trans);
 239
 240         /* Configure analog phase-lock-loop before activating to D0A */
 241         if (trans->cfg->base_params->pll_cfg_val)
 242                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 243                             trans->cfg->base_params->pll_cfg_val);
 244
 245         /*
 246          * Set "initialization complete" bit to move adapter from
 247          * D0U* --> D0A* (powered-up active) state.
 248          */
 249         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 250
 251         /*
 252          * Wait for clock stabilization; once stabilized, access to
 253          * device-internal resources is supported, e.g. iwl_write_prph()
 254          * and accesses to uCode SRAM.
 255          */
 256         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 257                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 258                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 259         if (ret < 0) {
 260                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 261                 goto out;
 262         }
 263
 264         if (trans->cfg->host_interrupt_operation_mode) {
 265                 /*
 266                  * This is a bit of an abuse - This is needed for 7260 / 3160
 267                  * only check host_interrupt_operation_mode even if this is
 268                  * not related to host_interrupt_operation_mode.
 269                  *
 270                  * Enable the oscillator to count wake up time for L1 exit. This
 271                  * consumes slightly more power (100uA) - but allows to be sure
 272                  * that we wake up from L1 on time.
 273                  *
 274                  * This looks weird: read twice the same register, discard the
 275                  * value, set a bit, and yet again, read that same register
 276                  * just to discard the value. But that's the way the hardware
 277                  * seems to like it.
 278                  */
 279                 iwl_read_prph(trans, OSC_CLK);
 280                 iwl_read_prph(trans, OSC_CLK);
 281                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 282                 iwl_read_prph(trans, OSC_CLK);
 283                 iwl_read_prph(trans, OSC_CLK);
 284         }
 285
 286         /*
 287          * Enable DMA clock and wait for it to stabilize.
 288          *
 289          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 290          * bits do not disable clocks.  This preserves any hardware
 291          * bits already set by default in "CLK_CTRL_REG" after reset.
 292          */
 293         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 294                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 295                                APMG_CLK_VAL_DMA_CLK_RQT);
 296                 udelay(20);
 297
 298                 /* Disable L1-Active */
 299                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 300                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 301
 302                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 303                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 304                                APMG_RTC_INT_STT_RFKILL);
 305         }
 306
 307         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 308
 309 out:
 310         return ret;
 311 }
 312
 313 /*
 314  * Enable LP XTAL to avoid HW bug where device may consume much power if
 315  * FW is not loaded after device reset. LP XTAL is disabled by default
 316  * after device HW reset. Do it only if XTAL is fed by internal source.
 317  * Configure device's "persistence" mode to avoid resetting XTAL again when
 318  * SHRD_HW_RST occurs in S3.
 319  */
 320 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 321 {
 322         int ret;
 323         u32 apmg_gp1_reg;
 324         u32 apmg_xtal_cfg_reg;
 325         u32 dl_cfg_reg;
 326
 327         /* Force XTAL ON */
 328         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 329                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 330
 331         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 332         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 333
 334         udelay(10);
 335
 336         /*
 337          * Set "initialization complete" bit to move adapter from
 338          * D0U* --> D0A* (powered-up active) state.
 339          */
 340         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 341
 342         /*
 343          * Wait for clock stabilization; once stabilized, access to
 344          * device-internal resources is possible.
 345          */
 346         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 347                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 348                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 349                            25000);
 350         if (WARN_ON(ret < 0)) {
 351                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 352                 /* Release XTAL ON request */
 353                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 354                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 355                 return;
 356         }
 357
 358         /*
 359          * Clear "disable persistence" to avoid LP XTAL resetting when
 360          * SHRD_HW_RST is applied in S3.
 361          */
 362         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 363                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 364
 365         /*
 366          * Force APMG XTAL to be active to prevent its disabling by HW
 367          * caused by APMG idle state.
 368          */
 369         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 370                                                     SHR_APMG_XTAL_CFG_REG);
 371         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 372                                  apmg_xtal_cfg_reg |
 373                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 374
 375         /*
 376          * Reset entire device again - do controller reset (results in
 377          * SHRD_HW_RST). Turn MAC off before proceeding.
 378          */
 379         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 380
 381         udelay(10);
 382
 383         /* Enable LP XTAL by indirect access through CSR */
 384         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 385         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 386                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 387                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 388
 389         /* Clear delay line clock power up */
 390         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 391         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 392                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 393
 394         /*
 395          * Enable persistence mode to avoid LP XTAL resetting when
 396          * SHRD_HW_RST is applied in S3.
 397          */
 398         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 399                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 400
 401         /*
 402          * Clear "initialization complete" bit to move adapter from
 403          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 404          */
 405         iwl_clear_bit(trans, CSR_GP_CNTRL,
 406                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 407
 408         /* Activates XTAL resources monitor */
 409         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 410                                  CSR_MONITOR_XTAL_RESOURCES);
 411
 412         /* Release XTAL ON request */
 413         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 414                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 415         udelay(10);
 416
 417         /* Release APMG XTAL */
 418         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 419                                  apmg_xtal_cfg_reg &
 420                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 421 }
 422
 423 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 424 {
 425         int ret = 0;
 426
 427         /* stop device's busmaster DMA activity */
 428         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 429
 430         ret = iwl_poll_bit(trans, CSR_RESET,
 431                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 432                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 433         if (ret < 0)
 434                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 435
 436         IWL_DEBUG_INFO(trans, "stop master\n");
 437
 438         return ret;
 439 }
 440
 441 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 442 {
 443         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 444
 445         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 446
 447         /* Stop device's DMA activity */
 448         iwl_pcie_apm_stop_master(trans);
 449
 450         if (trans->cfg->lp_xtal_workaround) {
 451                 iwl_pcie_apm_lp_xtal_enable(trans);
 452                 return;
 453         }
 454
 455         /* Reset the entire device */
 456         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 457
 458         udelay(10);
 459
 460         /*
 461          * Clear "initialization complete" bit to move adapter from
 462          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 463          */
 464         iwl_clear_bit(trans, CSR_GP_CNTRL,
 465                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 466 }
 467
 468 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 469 {
 470         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 471
 472         /* nic_init */
 473         spin_lock(&trans_pcie->irq_lock);
 474         iwl_pcie_apm_init(trans);
 475
 476         spin_unlock(&trans_pcie->irq_lock);
 477
 478         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 479                 iwl_pcie_set_pwr(trans, false);
 480
 481         iwl_op_mode_nic_config(trans->op_mode);
 482
 483         /* Allocate the RX queue, or reset if it is already allocated */
 484         iwl_pcie_rx_init(trans);
 485
 486         /* Allocate or reset and init all Tx and Command queues */
 487         if (iwl_pcie_tx_init(trans))
 488                 return -ENOMEM;
 489
 490         if (trans->cfg->base_params->shadow_reg_enable) {
 491                 /* enable shadow regs in HW */
 492                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 493                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 494         }
 495
 496         return 0;
 497 }
 498
 499 #define HW_READY_TIMEOUT (50)
 500
 501 /* Note: returns poll_bit return value, which is >= 0 if success */
 502 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 503 {
 504         int ret;
 505
 506         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 507                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 508
 509         /* See if we got it */
 510         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 511                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 512                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 513                            HW_READY_TIMEOUT);
 514
 515         if (ret >= 0)
 516                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 517
 518         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 519         return ret;
 520 }
 521
 522 /* Note: returns standard 0/-ERROR code */
 523 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 524 {
 525         int ret;
 526         int t = 0;
 527         int iter;
 528
 529         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 530
 531         ret = iwl_pcie_set_hw_ready(trans);
 532         /* If the card is ready, exit 0 */
 533         if (ret >= 0)
 534                 return 0;
 535
 536         for (iter = 0; iter < 10; iter++) {
 537                 /* If HW is not ready, prepare the conditions to check again */
 538                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 539                             CSR_HW_IF_CONFIG_REG_PREPARE);
 540
 541                 do {
 542                         ret = iwl_pcie_set_hw_ready(trans);
 543                         if (ret >= 0)
 544                                 return 0;
 545
 546                         usleep_range(200, 1000);
 547                         t += 200;
 548                 } while (t < 150000);
 549                 msleep(25);
 550         }
 551
 552         IWL_ERR(trans, "Couldn't prepare the card\n");
 553
 554         return ret;
 555 }
 556
 557 /*
 558  * ucode
 559  */
 560 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 561                                    dma_addr_t phy_addr, u32 byte_cnt)
 562 {
 563         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 564         int ret;
 565
 566         trans_pcie->ucode_write_complete = false;
 567
 568         iwl_write_direct32(trans,
 569                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 570                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 571
 572         iwl_write_direct32(trans,
 573                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 574                            dst_addr);
 575
 576         iwl_write_direct32(trans,
 577                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 578                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 579
 580         iwl_write_direct32(trans,
 581                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 582                            (iwl_get_dma_hi_addr(phy_addr)
 583                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 584
 585         iwl_write_direct32(trans,
 586                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 587                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 588                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 589                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 590
 591         iwl_write_direct32(trans,
 592                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 593                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 594                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 595                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 596
 597         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 598                                  trans_pcie->ucode_write_complete, 5 * HZ);
 599         if (!ret) {
 600                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 601                 return -ETIMEDOUT;
 602         }
 603
 604         return 0;
 605 }
 606
 607 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 608                             const struct fw_desc *section)
 609 {
 610         u8 *v_addr;
 611         dma_addr_t p_addr;
 612         u32 offset, chunk_sz = section->len;
 613         int ret = 0;
 614
 615         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 616                      section_num);
 617
 618         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 619                                     GFP_KERNEL | __GFP_NOWARN);
 620         if (!v_addr) {
 621                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 622                 chunk_sz = PAGE_SIZE;
 623                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 624                                             &p_addr, GFP_KERNEL);
 625                 if (!v_addr)
 626                         return -ENOMEM;
 627         }
 628
 629         for (offset = 0; offset < section->len; offset += chunk_sz) {
 630                 u32 copy_size;
 631
 632                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 633
 634                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 635                 ret = iwl_pcie_load_firmware_chunk(trans,
 636                                                    section->offset + offset,
 637                                                    p_addr, copy_size);
 638                 if (ret) {
 639                         IWL_ERR(trans,
 640                                 "Could not load the [%d] uCode section\n",
 641                                 section_num);
 642                         break;
 643                 }
 644         }
 645
 646         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 647         return ret;
 648 }
 649
 650 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
 651                                               const struct fw_img *image,
 652                                               int cpu,
 653                                               int *first_ucode_section)
 654 {
 655         int shift_param;
 656         int i, ret = 0;
 657         u32 last_read_idx = 0;
 658
 659         if (cpu == 1) {
 660                 shift_param = 0;
 661                 *first_ucode_section = 0;
 662         } else {
 663                 shift_param = 16;
 664                 (*first_ucode_section)++;
 665         }
 666
 667         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 668                 last_read_idx = i;
 669
 670                 if (!image->sec[i].data ||
 671                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 672                         IWL_DEBUG_FW(trans,
 673                                      "Break since Data not valid or Empty section, sec = %d\n",
 674                                      i);
 675                         break;
 676                 }
 677
 678                 if (i == (*first_ucode_section) + 1)
 679                         /* set CPU to started */
 680                         iwl_set_bits_prph(trans,
 681                                           CSR_UCODE_LOAD_STATUS_ADDR,
 682                                           LMPM_CPU_HDRS_LOADING_COMPLETED
 683                                           << shift_param);
 684
 685                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 686                 if (ret)
 687                         return ret;
 688         }
 689         /* image loading complete */
 690         iwl_set_bits_prph(trans,
 691                           CSR_UCODE_LOAD_STATUS_ADDR,
 692                           LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
 693
 694         *first_ucode_section = last_read_idx;
 695
 696         return 0;
 697 }
 698
 699 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 700                                       const struct fw_img *image,
 701                                       int cpu,
 702                                       int *first_ucode_section)
 703 {
 704         int shift_param;
 705         int i, ret = 0;
 706         u32 last_read_idx = 0;
 707
 708         if (cpu == 1) {
 709                 shift_param = 0;
 710                 *first_ucode_section = 0;
 711         } else {
 712                 shift_param = 16;
 713                 (*first_ucode_section)++;
 714         }
 715
 716         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 717                 last_read_idx = i;
 718
 719                 if (!image->sec[i].data ||
 720                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 721                         IWL_DEBUG_FW(trans,
 722                                      "Break since Data not valid or Empty section, sec = %d\n",
 723                                      i);
 724                         break;
 725                 }
 726
 727                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 728                 if (ret)
 729                         return ret;
 730         }
 731
 732         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 733                 iwl_set_bits_prph(trans,
 734                                   CSR_UCODE_LOAD_STATUS_ADDR,
 735                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 736                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 737                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 738                                         shift_param);
 739
 740         *first_ucode_section = last_read_idx;
 741
 742         return 0;
 743 }
 744
 745 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 746                                 const struct fw_img *image)
 747 {
 748         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 749         int ret = 0;
 750         int first_ucode_section;
 751
 752         IWL_DEBUG_FW(trans,
 753                      "working with %s CPU\n",
 754                      image->is_dual_cpus ? "Dual" : "Single");
 755
 756         /* configure the ucode to be ready to get the secured image */
 757         if (iwl_has_secure_boot(trans->hw_rev, trans->cfg->device_family)) {
 758                 /* set secure boot inspector addresses */
 759                 iwl_write_prph(trans,
 760                                LMPM_SECURE_INSPECTOR_CODE_ADDR,
 761                                LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
 762
 763                 iwl_write_prph(trans,
 764                                LMPM_SECURE_INSPECTOR_DATA_ADDR,
 765                                LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
 766
 767                 /* set CPU1 header address */
 768                 iwl_write_prph(trans,
 769                                LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
 770                                LMPM_SECURE_CPU1_HDR_MEM_SPACE);
 771
 772                 /* load to FW the binary Secured sections of CPU1 */
 773                 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
 774                                                          &first_ucode_section);
 775                 if (ret)
 776                         return ret;
 777
 778         } else {
 779                 /* load to FW the binary Non secured sections of CPU1 */
 780                 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
 781                                                  &first_ucode_section);
 782                 if (ret)
 783                         return ret;
 784         }
 785
 786         if (image->is_dual_cpus) {
 787                 /* set CPU2 header address */
 788                 iwl_write_prph(trans,
 789                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 790                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 791
 792                 /* load to FW the binary sections of CPU2 */
 793                 if (iwl_has_secure_boot(trans->hw_rev,
 794                                         trans->cfg->device_family))
 795                         ret = iwl_pcie_load_cpu_secured_sections(
 796                                                         trans, image, 2,
 797                                                         &first_ucode_section);
 798                 else
 799                         ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 800                                                          &first_ucode_section);
 801                 if (ret)
 802                         return ret;
 803         }
 804
 805         /* supported for 7000 only for the moment */
 806         if (iwlwifi_mod_params.fw_monitor &&
 807             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 808                 iwl_pcie_alloc_fw_monitor(trans);
 809
 810                 if (trans_pcie->fw_mon_size) {
 811                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 812                                        trans_pcie->fw_mon_phys >> 4);
 813                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 814                                        (trans_pcie->fw_mon_phys +
 815                                         trans_pcie->fw_mon_size) >> 4);
 816                 }
 817         }
 818
 819         /* release CPU reset */
 820         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 821                 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 822         else
 823                 iwl_write32(trans, CSR_RESET, 0);
 824
 825         if (iwl_has_secure_boot(trans->hw_rev, trans->cfg->device_family)) {
 826                 /* wait for image verification to complete  */
 827                 ret = iwl_poll_prph_bit(trans,
 828                                         LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
 829                                         LMPM_SECURE_BOOT_STATUS_SUCCESS,
 830                                         LMPM_SECURE_BOOT_STATUS_SUCCESS,
 831                                         LMPM_SECURE_TIME_OUT);
 832
 833                 if (ret < 0) {
 834                         IWL_ERR(trans, "Time out on secure boot process\n");
 835                         return ret;
 836                 }
 837         }
 838
 839         return 0;
 840 }
 841
 842 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 843                                    const struct fw_img *fw, bool run_in_rfkill)
 844 {
 845         int ret;
 846         bool hw_rfkill;
 847
 848         /* This may fail if AMT took ownership of the device */
 849         if (iwl_pcie_prepare_card_hw(trans)) {
 850                 IWL_WARN(trans, "Exit HW not ready\n");
 851                 return -EIO;
 852         }
 853
 854         iwl_enable_rfkill_int(trans);
 855
 856         /* If platform's RF_KILL switch is NOT set to KILL */
 857         hw_rfkill = iwl_is_rfkill_set(trans);
 858         if (hw_rfkill)
 859                 set_bit(STATUS_RFKILL, &trans->status);
 860         else
 861                 clear_bit(STATUS_RFKILL, &trans->status);
 862         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 863         if (hw_rfkill && !run_in_rfkill)
 864                 return -ERFKILL;
 865
 866         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 867
 868         ret = iwl_pcie_nic_init(trans);
 869         if (ret) {
 870                 IWL_ERR(trans, "Unable to init nic\n");
 871                 return ret;
 872         }
 873
 874         /* make sure rfkill handshake bits are cleared */
 875         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 876         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 877                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 878
 879         /* clear (again), then enable host interrupts */
 880         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 881         iwl_enable_interrupts(trans);
 882
 883         /* really make sure rfkill handshake bits are cleared */
 884         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 885         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 886
 887         /* Load the given image to the HW */
 888         return iwl_pcie_load_given_ucode(trans, fw);
 889 }
 890
 891 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 892 {
 893         iwl_pcie_reset_ict(trans);
 894         iwl_pcie_tx_start(trans, scd_addr);
 895 }
 896
 897 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 898 {
 899         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 900         bool hw_rfkill, was_hw_rfkill;
 901
 902         was_hw_rfkill = iwl_is_rfkill_set(trans);
 903
 904         /* tell the device to stop sending interrupts */
 905         spin_lock(&trans_pcie->irq_lock);
 906         iwl_disable_interrupts(trans);
 907         spin_unlock(&trans_pcie->irq_lock);
 908
 909         /* device going down, Stop using ICT table */
 910         iwl_pcie_disable_ict(trans);
 911
 912         /*
 913          * If a HW restart happens during firmware loading,
 914          * then the firmware loading might call this function
 915          * and later it might be called again due to the
 916          * restart. So don't process again if the device is
 917          * already dead.
 918          */
 919         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
 920                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
 921                 iwl_pcie_tx_stop(trans);
 922                 iwl_pcie_rx_stop(trans);
 923
 924                 /* Power-down device's busmaster DMA clocks */
 925                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 926                                APMG_CLK_VAL_DMA_CLK_RQT);
 927                 udelay(5);
 928         }
 929
 930         /* Make sure (redundant) we've released our request to stay awake */
 931         iwl_clear_bit(trans, CSR_GP_CNTRL,
 932                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 933
 934         /* Stop the device, and put it in low power state */
 935         iwl_pcie_apm_stop(trans);
 936
 937         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 938          * Clean again the interrupt here
 939          */
 940         spin_lock(&trans_pcie->irq_lock);
 941         iwl_disable_interrupts(trans);
 942         spin_unlock(&trans_pcie->irq_lock);
 943
 944         /* stop and reset the on-board processor */
 945         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 946
 947         /* clear all status bits */
 948         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 949         clear_bit(STATUS_INT_ENABLED, &trans->status);
 950         clear_bit(STATUS_TPOWER_PMI, &trans->status);
 951         clear_bit(STATUS_RFKILL, &trans->status);
 952
 953         /*
 954          * Even if we stop the HW, we still want the RF kill
 955          * interrupt
 956          */
 957         iwl_enable_rfkill_int(trans);
 958
 959         /*
 960          * Check again since the RF kill state may have changed while
 961          * all the interrupts were disabled, in this case we couldn't
 962          * receive the RF kill interrupt and update the state in the
 963          * op_mode.
 964          * Don't call the op_mode if the rkfill state hasn't changed.
 965          * This allows the op_mode to call stop_device from the rfkill
 966          * notification without endless recursion. Under very rare
 967          * circumstances, we might have a small recursion if the rfkill
 968          * state changed exactly now while we were called from stop_device.
 969          * This is very unlikely but can happen and is supported.
 970          */
 971         hw_rfkill = iwl_is_rfkill_set(trans);
 972         if (hw_rfkill)
 973                 set_bit(STATUS_RFKILL, &trans->status);
 974         else
 975                 clear_bit(STATUS_RFKILL, &trans->status);
 976         if (hw_rfkill != was_hw_rfkill)
 977                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 978 }
 979
 980 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
 981 {
 982         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
 983                 iwl_trans_pcie_stop_device(trans);
 984 }
 985
 986 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 987 {
 988         iwl_disable_interrupts(trans);
 989
 990         /*
 991          * in testing mode, the host stays awake and the
 992          * hardware won't be reset (not even partially)
 993          */
 994         if (test)
 995                 return;
 996
 997         iwl_pcie_disable_ict(trans);
 998
 999         iwl_clear_bit(trans, CSR_GP_CNTRL,
1000                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1001         iwl_clear_bit(trans, CSR_GP_CNTRL,
1002                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1003
1004         /*
1005          * reset TX queues -- some of their registers reset during S3
1006          * so if we don't reset everything here the D3 image would try
1007          * to execute some invalid memory upon resume
1008          */
1009         iwl_trans_pcie_tx_reset(trans);
1010
1011         iwl_pcie_set_pwr(trans, true);
1012 }
1013
1014 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1015                                     enum iwl_d3_status *status,
1016                                     bool test)
1017 {
1018         u32 val;
1019         int ret;
1020
1021         if (test) {
1022                 iwl_enable_interrupts(trans);
1023                 *status = IWL_D3_STATUS_ALIVE;
1024                 return 0;
1025         }
1026
1027         /*
1028          * Also enables interrupts - none will happen as the device doesn't
1029          * know we're waking it up, only when the opmode actually tells it
1030          * after this call.
1031          */
1032         iwl_pcie_reset_ict(trans);
1033
1034         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1035         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1036
1037         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1038                 udelay(2);
1039
1040         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1041                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1042                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1043                            25000);
1044         if (ret < 0) {
1045                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1046                 return ret;
1047         }
1048
1049         iwl_pcie_set_pwr(trans, false);
1050
1051         iwl_trans_pcie_tx_reset(trans);
1052
1053         ret = iwl_pcie_rx_init(trans);
1054         if (ret) {
1055                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1056                 return ret;
1057         }
1058
1059         val = iwl_read32(trans, CSR_RESET);
1060         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1061                 *status = IWL_D3_STATUS_RESET;
1062         else
1063                 *status = IWL_D3_STATUS_ALIVE;
1064
1065         return 0;
1066 }
1067
1068 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1069 {
1070         bool hw_rfkill;
1071         int err;
1072
1073         err = iwl_pcie_prepare_card_hw(trans);
1074         if (err) {
1075                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1076                 return err;
1077         }
1078
1079         /* Reset the entire device */
1080         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1081
1082         usleep_range(10, 15);
1083
1084         iwl_pcie_apm_init(trans);
1085
1086         /* From now on, the op_mode will be kept updated about RF kill state */
1087         iwl_enable_rfkill_int(trans);
1088
1089         hw_rfkill = iwl_is_rfkill_set(trans);
1090         if (hw_rfkill)
1091                 set_bit(STATUS_RFKILL, &trans->status);
1092         else
1093                 clear_bit(STATUS_RFKILL, &trans->status);
1094         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1095
1096         return 0;
1097 }
1098
1099 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1100 {
1101         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1102
1103         /* disable interrupts - don't enable HW RF kill interrupt */
1104         spin_lock(&trans_pcie->irq_lock);
1105         iwl_disable_interrupts(trans);
1106         spin_unlock(&trans_pcie->irq_lock);
1107
1108         iwl_pcie_apm_stop(trans);
1109
1110         spin_lock(&trans_pcie->irq_lock);
1111         iwl_disable_interrupts(trans);
1112         spin_unlock(&trans_pcie->irq_lock);
1113
1114         iwl_pcie_disable_ict(trans);
1115 }
1116
1117 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1118 {
1119         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1120 }
1121
1122 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1123 {
1124         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1125 }
1126
1127 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1128 {
1129         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1130 }
1131
1132 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1133 {
1134         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1135                                ((reg & 0x000FFFFF) | (3 << 24)));
1136         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1137 }
1138
1139 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1140                                       u32 val)
1141 {
1142         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1143                                ((addr & 0x000FFFFF) | (3 << 24)));
1144         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1145 }
1146
1147 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1148 {
1149         WARN_ON(1);
1150         return 0;
1151 }
1152
1153 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1154                                      const struct iwl_trans_config *trans_cfg)
1155 {
1156         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1157
1158         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1159         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1160         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1161                 trans_pcie->n_no_reclaim_cmds = 0;
1162         else
1163                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1164         if (trans_pcie->n_no_reclaim_cmds)
1165                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1166                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1167
1168         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1169         if (trans_pcie->rx_buf_size_8k)
1170                 trans_pcie->rx_page_order = get_order(8 * 1024);
1171         else
1172                 trans_pcie->rx_page_order = get_order(4 * 1024);
1173
1174         trans_pcie->wd_timeout =
1175                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1176
1177         trans_pcie->command_names = trans_cfg->command_names;
1178         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1179         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1180
1181         /* Initialize NAPI here - it should be before registering to mac80211
1182          * in the opmode but after the HW struct is allocated.
1183          * As this function may be called again in some corner cases don't
1184          * do anything if NAPI was already initialized.
1185          */
1186         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1187                 init_dummy_netdev(&trans_pcie->napi_dev);
1188                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1189                                      &trans_pcie->napi_dev,
1190                                      iwl_pcie_dummy_napi_poll, 64);
1191         }
1192 }
1193
1194 void iwl_trans_pcie_free(struct iwl_trans *trans)
1195 {
1196         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1197
1198         synchronize_irq(trans_pcie->pci_dev->irq);
1199
1200         iwl_pcie_tx_free(trans);
1201         iwl_pcie_rx_free(trans);
1202
1203         free_irq(trans_pcie->pci_dev->irq, trans);
1204         iwl_pcie_free_ict(trans);
1205
1206         pci_disable_msi(trans_pcie->pci_dev);
1207         iounmap(trans_pcie->hw_base);
1208         pci_release_regions(trans_pcie->pci_dev);
1209         pci_disable_device(trans_pcie->pci_dev);
1210         kmem_cache_destroy(trans->dev_cmd_pool);
1211
1212         if (trans_pcie->napi.poll)
1213                 netif_napi_del(&trans_pcie->napi);
1214
1215         iwl_pcie_free_fw_monitor(trans);
1216
1217         kfree(trans);
1218 }
1219
1220 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1221 {
1222         if (state)
1223                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1224         else
1225                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1226 }
1227
1228 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1229                                                 unsigned long *flags)
1230 {
1231         int ret;
1232         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1233
1234         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1235
1236         if (trans_pcie->cmd_in_flight)
1237                 goto out;
1238
1239         /* this bit wakes up the NIC */
1240         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1241                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1242         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1243                 udelay(2);
1244
1245         /*
1246          * These bits say the device is running, and should keep running for
1247          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1248          * but they do not indicate that embedded SRAM is restored yet;
1249          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1250          * to/from host DRAM when sleeping/waking for power-saving.
1251          * Each direction takes approximately 1/4 millisecond; with this
1252          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1253          * series of register accesses are expected (e.g. reading Event Log),
1254          * to keep device from sleeping.
1255          *
1256          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1257          * SRAM is okay/restored.  We don't check that here because this call
1258          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1259          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1260          *
1261          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1262          * and do not save/restore SRAM when power cycling.
1263          */
1264         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1265                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1266                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1267                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1268         if (unlikely(ret < 0)) {
1269                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1270                 if (!silent) {
1271                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1272                         WARN_ONCE(1,
1273                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1274                                   val);
1275                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1276                         return false;
1277                 }
1278         }
1279
1280 out:
1281         /*
1282          * Fool sparse by faking we release the lock - sparse will
1283          * track nic_access anyway.
1284          */
1285         __release(&trans_pcie->reg_lock);
1286         return true;
1287 }
1288
1289 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1290                                               unsigned long *flags)
1291 {
1292         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1293
1294         lockdep_assert_held(&trans_pcie->reg_lock);
1295
1296         /*
1297          * Fool sparse by faking we acquiring the lock - sparse will
1298          * track nic_access anyway.
1299          */
1300         __acquire(&trans_pcie->reg_lock);
1301
1302         if (trans_pcie->cmd_in_flight)
1303                 goto out;
1304
1305         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1306                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1307         /*
1308          * Above we read the CSR_GP_CNTRL register, which will flush
1309          * any previous writes, but we need the write that clears the
1310          * MAC_ACCESS_REQ bit to be performed before any other writes
1311          * scheduled on different CPUs (after we drop reg_lock).
1312          */
1313         mmiowb();
1314 out:
1315         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1316 }
1317
1318 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1319                                    void *buf, int dwords)
1320 {
1321         unsigned long flags;
1322         int offs, ret = 0;
1323         u32 *vals = buf;
1324
1325         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1326                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1327                 for (offs = 0; offs < dwords; offs++)
1328                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1329                 iwl_trans_release_nic_access(trans, &flags);
1330         } else {
1331                 ret = -EBUSY;
1332         }
1333         return ret;
1334 }
1335
1336 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1337                                     const void *buf, int dwords)
1338 {
1339         unsigned long flags;
1340         int offs, ret = 0;
1341         const u32 *vals = buf;
1342
1343         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1344                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1345                 for (offs = 0; offs < dwords; offs++)
1346                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1347                                     vals ? vals[offs] : 0);
1348                 iwl_trans_release_nic_access(trans, &flags);
1349         } else {
1350                 ret = -EBUSY;
1351         }
1352         return ret;
1353 }
1354
1355 #define IWL_FLUSH_WAIT_MS       2000
1356
1357 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1358 {
1359         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1360         struct iwl_txq *txq;
1361         struct iwl_queue *q;
1362         int cnt;
1363         unsigned long now = jiffies;
1364         u32 scd_sram_addr;
1365         u8 buf[16];
1366         int ret = 0;
1367
1368         /* waiting for all the tx frames complete might take a while */
1369         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1370                 u8 wr_ptr;
1371
1372                 if (cnt == trans_pcie->cmd_queue)
1373                         continue;
1374                 if (!test_bit(cnt, trans_pcie->queue_used))
1375                         continue;
1376                 if (!(BIT(cnt) & txq_bm))
1377                         continue;
1378
1379                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1380                 txq = &trans_pcie->txq[cnt];
1381                 q = &txq->q;
1382                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1383
1384                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1385                        !time_after(jiffies,
1386                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1387                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1388
1389                         if (WARN_ONCE(wr_ptr != write_ptr,
1390                                       "WR pointer moved while flushing %d -> %d\n",
1391                                       wr_ptr, write_ptr))
1392                                 return -ETIMEDOUT;
1393                         msleep(1);
1394                 }
1395
1396                 if (q->read_ptr != q->write_ptr) {
1397                         IWL_ERR(trans,
1398                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1399                         ret = -ETIMEDOUT;
1400                         break;
1401                 }
1402                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1403         }
1404
1405         if (!ret)
1406                 return 0;
1407
1408         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1409                 txq->q.read_ptr, txq->q.write_ptr);
1410
1411         scd_sram_addr = trans_pcie->scd_base_addr +
1412                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1413         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1414
1415         iwl_print_hex_error(trans, buf, sizeof(buf));
1416
1417         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1418                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1419                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1420
1421         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1422                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1423                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1424                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1425                 u32 tbl_dw =
1426                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1427                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1428
1429                 if (cnt & 0x1)
1430                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1431                 else
1432                         tbl_dw = tbl_dw & 0x0000FFFF;
1433
1434                 IWL_ERR(trans,
1435                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1436                         cnt, active ? "" : "in", fifo, tbl_dw,
1437                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1438                                 (TFD_QUEUE_SIZE_MAX - 1),
1439                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1440         }
1441
1442         return ret;
1443 }
1444
1445 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1446                                          u32 mask, u32 value)
1447 {
1448         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1449         unsigned long flags;
1450
1451         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1452         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1453         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1454 }
1455
1456 static const char *get_csr_string(int cmd)
1457 {
1458 #define IWL_CMD(x) case x: return #x
1459         switch (cmd) {
1460         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1461         IWL_CMD(CSR_INT_COALESCING);
1462         IWL_CMD(CSR_INT);
1463         IWL_CMD(CSR_INT_MASK);
1464         IWL_CMD(CSR_FH_INT_STATUS);
1465         IWL_CMD(CSR_GPIO_IN);
1466         IWL_CMD(CSR_RESET);
1467         IWL_CMD(CSR_GP_CNTRL);
1468         IWL_CMD(CSR_HW_REV);
1469         IWL_CMD(CSR_EEPROM_REG);
1470         IWL_CMD(CSR_EEPROM_GP);
1471         IWL_CMD(CSR_OTP_GP_REG);
1472         IWL_CMD(CSR_GIO_REG);
1473         IWL_CMD(CSR_GP_UCODE_REG);
1474         IWL_CMD(CSR_GP_DRIVER_REG);
1475         IWL_CMD(CSR_UCODE_DRV_GP1);
1476         IWL_CMD(CSR_UCODE_DRV_GP2);
1477         IWL_CMD(CSR_LED_REG);
1478         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1479         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1480         IWL_CMD(CSR_ANA_PLL_CFG);
1481         IWL_CMD(CSR_HW_REV_WA_REG);
1482         IWL_CMD(CSR_MONITOR_STATUS_REG);
1483         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1484         default:
1485                 return "UNKNOWN";
1486         }
1487 #undef IWL_CMD
1488 }
1489
1490 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1491 {
1492         int i;
1493         static const u32 csr_tbl[] = {
1494                 CSR_HW_IF_CONFIG_REG,
1495                 CSR_INT_COALESCING,
1496                 CSR_INT,
1497                 CSR_INT_MASK,
1498                 CSR_FH_INT_STATUS,
1499                 CSR_GPIO_IN,
1500                 CSR_RESET,
1501                 CSR_GP_CNTRL,
1502                 CSR_HW_REV,
1503                 CSR_EEPROM_REG,
1504                 CSR_EEPROM_GP,
1505                 CSR_OTP_GP_REG,
1506                 CSR_GIO_REG,
1507                 CSR_GP_UCODE_REG,
1508                 CSR_GP_DRIVER_REG,
1509                 CSR_UCODE_DRV_GP1,
1510                 CSR_UCODE_DRV_GP2,
1511                 CSR_LED_REG,
1512                 CSR_DRAM_INT_TBL_REG,
1513                 CSR_GIO_CHICKEN_BITS,
1514                 CSR_ANA_PLL_CFG,
1515                 CSR_MONITOR_STATUS_REG,
1516                 CSR_HW_REV_WA_REG,
1517                 CSR_DBG_HPET_MEM_REG
1518         };
1519         IWL_ERR(trans, "CSR values:\n");
1520         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1521                 "CSR_INT_PERIODIC_REG)\n");
1522         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1523                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1524                         get_csr_string(csr_tbl[i]),
1525                         iwl_read32(trans, csr_tbl[i]));
1526         }
1527 }
1528
1529 #ifdef CONFIG_IWLWIFI_DEBUGFS
1530 /* create and remove of files */
1531 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1532         if (!debugfs_create_file(#name, mode, parent, trans,            \
1533                                  &iwl_dbgfs_##name##_ops))              \
1534                 goto err;                                               \
1535 } while (0)
1536
1537 /* file operation */
1538 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1539 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1540         .read = iwl_dbgfs_##name##_read,                                \
1541         .open = simple_open,                                            \
1542         .llseek = generic_file_llseek,                                  \
1543 };
1544
1545 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1546 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1547         .write = iwl_dbgfs_##name##_write,                              \
1548         .open = simple_open,                                            \
1549         .llseek = generic_file_llseek,                                  \
1550 };
1551
1552 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1553 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1554         .write = iwl_dbgfs_##name##_write,                              \
1555         .read = iwl_dbgfs_##name##_read,                                \
1556         .open = simple_open,                                            \
1557         .llseek = generic_file_llseek,                                  \
1558 };
1559
1560 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1561                                        char __user *user_buf,
1562                                        size_t count, loff_t *ppos)
1563 {
1564         struct iwl_trans *trans = file->private_data;
1565         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1566         struct iwl_txq *txq;
1567         struct iwl_queue *q;
1568         char *buf;
1569         int pos = 0;
1570         int cnt;
1571         int ret;
1572         size_t bufsz;
1573
1574         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1575
1576         if (!trans_pcie->txq)
1577                 return -EAGAIN;
1578
1579         buf = kzalloc(bufsz, GFP_KERNEL);
1580         if (!buf)
1581                 return -ENOMEM;
1582
1583         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1584                 txq = &trans_pcie->txq[cnt];
1585                 q = &txq->q;
1586                 pos += scnprintf(buf + pos, bufsz - pos,
1587                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1588                                 cnt, q->read_ptr, q->write_ptr,
1589                                 !!test_bit(cnt, trans_pcie->queue_used),
1590                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1591                                  txq->need_update,
1592                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1593         }
1594         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1595         kfree(buf);
1596         return ret;
1597 }
1598
1599 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1600                                        char __user *user_buf,
1601                                        size_t count, loff_t *ppos)
1602 {
1603         struct iwl_trans *trans = file->private_data;
1604         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1605         struct iwl_rxq *rxq = &trans_pcie->rxq;
1606         char buf[256];
1607         int pos = 0;
1608         const size_t bufsz = sizeof(buf);
1609
1610         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1611                                                 rxq->read);
1612         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1613                                                 rxq->write);
1614         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1615                                                 rxq->write_actual);
1616         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1617                                                 rxq->need_update);
1618         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1619                                                 rxq->free_count);
1620         if (rxq->rb_stts) {
1621                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1622                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1623         } else {
1624                 pos += scnprintf(buf + pos, bufsz - pos,
1625                                         "closed_rb_num: Not Allocated\n");
1626         }
1627         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1628 }
1629
1630 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1631                                         char __user *user_buf,
1632                                         size_t count, loff_t *ppos)
1633 {
1634         struct iwl_trans *trans = file->private_data;
1635         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1636         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1637
1638         int pos = 0;
1639         char *buf;
1640         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1641         ssize_t ret;
1642
1643         buf = kzalloc(bufsz, GFP_KERNEL);
1644         if (!buf)
1645                 return -ENOMEM;
1646
1647         pos += scnprintf(buf + pos, bufsz - pos,
1648                         "Interrupt Statistics Report:\n");
1649
1650         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1651                 isr_stats->hw);
1652         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1653                 isr_stats->sw);
1654         if (isr_stats->sw || isr_stats->hw) {
1655                 pos += scnprintf(buf + pos, bufsz - pos,
1656                         "\tLast Restarting Code:  0x%X\n",
1657                         isr_stats->err_code);
1658         }
1659 #ifdef CONFIG_IWLWIFI_DEBUG
1660         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1661                 isr_stats->sch);
1662         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1663                 isr_stats->alive);
1664 #endif
1665         pos += scnprintf(buf + pos, bufsz - pos,
1666                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1667
1668         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1669                 isr_stats->ctkill);
1670
1671         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1672                 isr_stats->wakeup);
1673
1674         pos += scnprintf(buf + pos, bufsz - pos,
1675                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1676
1677         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1678                 isr_stats->tx);
1679
1680         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1681                 isr_stats->unhandled);
1682
1683         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1684         kfree(buf);
1685         return ret;
1686 }
1687
1688 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1689                                          const char __user *user_buf,
1690                                          size_t count, loff_t *ppos)
1691 {
1692         struct iwl_trans *trans = file->private_data;
1693         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1694         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1695
1696         char buf[8];
1697         int buf_size;
1698         u32 reset_flag;
1699
1700         memset(buf, 0, sizeof(buf));
1701         buf_size = min(count, sizeof(buf) -  1);
1702         if (copy_from_user(buf, user_buf, buf_size))
1703                 return -EFAULT;
1704         if (sscanf(buf, "%x", &reset_flag) != 1)
1705                 return -EFAULT;
1706         if (reset_flag == 0)
1707                 memset(isr_stats, 0, sizeof(*isr_stats));
1708
1709         return count;
1710 }
1711
1712 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1713                                    const char __user *user_buf,
1714                                    size_t count, loff_t *ppos)
1715 {
1716         struct iwl_trans *trans = file->private_data;
1717         char buf[8];
1718         int buf_size;
1719         int csr;
1720
1721         memset(buf, 0, sizeof(buf));
1722         buf_size = min(count, sizeof(buf) -  1);
1723         if (copy_from_user(buf, user_buf, buf_size))
1724                 return -EFAULT;
1725         if (sscanf(buf, "%d", &csr) != 1)
1726                 return -EFAULT;
1727
1728         iwl_pcie_dump_csr(trans);
1729
1730         return count;
1731 }
1732
1733 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1734                                      char __user *user_buf,
1735                                      size_t count, loff_t *ppos)
1736 {
1737         struct iwl_trans *trans = file->private_data;
1738         char *buf = NULL;
1739         ssize_t ret;
1740
1741         ret = iwl_dump_fh(trans, &buf);
1742         if (ret < 0)
1743                 return ret;
1744         if (!buf)
1745                 return -EINVAL;
1746         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1747         kfree(buf);
1748         return ret;
1749 }
1750
1751 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1752 DEBUGFS_READ_FILE_OPS(fh_reg);
1753 DEBUGFS_READ_FILE_OPS(rx_queue);
1754 DEBUGFS_READ_FILE_OPS(tx_queue);
1755 DEBUGFS_WRITE_FILE_OPS(csr);
1756
1757 /*
1758  * Create the debugfs files and directories
1759  *
1760  */
1761 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1762                                          struct dentry *dir)
1763 {
1764         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1765         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1766         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1767         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1768         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1769         return 0;
1770
1771 err:
1772         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1773         return -ENOMEM;
1774 }
1775 #else
1776 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1777                                          struct dentry *dir)
1778 {
1779         return 0;
1780 }
1781 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1782
1783 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1784 {
1785         u32 cmdlen = 0;
1786         int i;
1787
1788         for (i = 0; i < IWL_NUM_OF_TBS; i++)
1789                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1790
1791         return cmdlen;
1792 }
1793
1794 static const struct {
1795         u32 start, end;
1796 } iwl_prph_dump_addr[] = {
1797         { .start = 0x00a00000, .end = 0x00a00000 },
1798         { .start = 0x00a0000c, .end = 0x00a00024 },
1799         { .start = 0x00a0002c, .end = 0x00a0003c },
1800         { .start = 0x00a00410, .end = 0x00a00418 },
1801         { .start = 0x00a00420, .end = 0x00a00420 },
1802         { .start = 0x00a00428, .end = 0x00a00428 },
1803         { .start = 0x00a00430, .end = 0x00a0043c },
1804         { .start = 0x00a00444, .end = 0x00a00444 },
1805         { .start = 0x00a004c0, .end = 0x00a004cc },
1806         { .start = 0x00a004d8, .end = 0x00a004d8 },
1807         { .start = 0x00a004e0, .end = 0x00a004f0 },
1808         { .start = 0x00a00840, .end = 0x00a00840 },
1809         { .start = 0x00a00850, .end = 0x00a00858 },
1810         { .start = 0x00a01004, .end = 0x00a01008 },
1811         { .start = 0x00a01010, .end = 0x00a01010 },
1812         { .start = 0x00a01018, .end = 0x00a01018 },
1813         { .start = 0x00a01024, .end = 0x00a01024 },
1814         { .start = 0x00a0102c, .end = 0x00a01034 },
1815         { .start = 0x00a0103c, .end = 0x00a01040 },
1816         { .start = 0x00a01048, .end = 0x00a01094 },
1817         { .start = 0x00a01c00, .end = 0x00a01c20 },
1818         { .start = 0x00a01c58, .end = 0x00a01c58 },
1819         { .start = 0x00a01c7c, .end = 0x00a01c7c },
1820         { .start = 0x00a01c28, .end = 0x00a01c54 },
1821         { .start = 0x00a01c5c, .end = 0x00a01c5c },
1822         { .start = 0x00a01c84, .end = 0x00a01c84 },
1823         { .start = 0x00a01ce0, .end = 0x00a01d0c },
1824         { .start = 0x00a01d18, .end = 0x00a01d20 },
1825         { .start = 0x00a01d2c, .end = 0x00a01d30 },
1826         { .start = 0x00a01d40, .end = 0x00a01d5c },
1827         { .start = 0x00a01d80, .end = 0x00a01d80 },
1828         { .start = 0x00a01d98, .end = 0x00a01d98 },
1829         { .start = 0x00a01dc0, .end = 0x00a01dfc },
1830         { .start = 0x00a01e00, .end = 0x00a01e2c },
1831         { .start = 0x00a01e40, .end = 0x00a01e60 },
1832         { .start = 0x00a01e84, .end = 0x00a01e90 },
1833         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1834         { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1835         { .start = 0x00a01f00, .end = 0x00a01f14 },
1836         { .start = 0x00a01f44, .end = 0x00a01f58 },
1837         { .start = 0x00a01f80, .end = 0x00a01fa8 },
1838         { .start = 0x00a01fb0, .end = 0x00a01fbc },
1839         { .start = 0x00a01ff8, .end = 0x00a01ffc },
1840         { .start = 0x00a02000, .end = 0x00a02048 },
1841         { .start = 0x00a02068, .end = 0x00a020f0 },
1842         { .start = 0x00a02100, .end = 0x00a02118 },
1843         { .start = 0x00a02140, .end = 0x00a0214c },
1844         { .start = 0x00a02168, .end = 0x00a0218c },
1845         { .start = 0x00a021c0, .end = 0x00a021c0 },
1846         { .start = 0x00a02400, .end = 0x00a02410 },
1847         { .start = 0x00a02418, .end = 0x00a02420 },
1848         { .start = 0x00a02428, .end = 0x00a0242c },
1849         { .start = 0x00a02434, .end = 0x00a02434 },
1850         { .start = 0x00a02440, .end = 0x00a02460 },
1851         { .start = 0x00a02468, .end = 0x00a024b0 },
1852         { .start = 0x00a024c8, .end = 0x00a024cc },
1853         { .start = 0x00a02500, .end = 0x00a02504 },
1854         { .start = 0x00a0250c, .end = 0x00a02510 },
1855         { .start = 0x00a02540, .end = 0x00a02554 },
1856         { .start = 0x00a02580, .end = 0x00a025f4 },
1857         { .start = 0x00a02600, .end = 0x00a0260c },
1858         { .start = 0x00a02648, .end = 0x00a02650 },
1859         { .start = 0x00a02680, .end = 0x00a02680 },
1860         { .start = 0x00a026c0, .end = 0x00a026d0 },
1861         { .start = 0x00a02700, .end = 0x00a0270c },
1862         { .start = 0x00a02804, .end = 0x00a02804 },
1863         { .start = 0x00a02818, .end = 0x00a0281c },
1864         { .start = 0x00a02c00, .end = 0x00a02db4 },
1865         { .start = 0x00a02df4, .end = 0x00a02fb0 },
1866         { .start = 0x00a03000, .end = 0x00a03014 },
1867         { .start = 0x00a0301c, .end = 0x00a0302c },
1868         { .start = 0x00a03034, .end = 0x00a03038 },
1869         { .start = 0x00a03040, .end = 0x00a03048 },
1870         { .start = 0x00a03060, .end = 0x00a03068 },
1871         { .start = 0x00a03070, .end = 0x00a03074 },
1872         { .start = 0x00a0307c, .end = 0x00a0307c },
1873         { .start = 0x00a03080, .end = 0x00a03084 },
1874         { .start = 0x00a0308c, .end = 0x00a03090 },
1875         { .start = 0x00a03098, .end = 0x00a03098 },
1876         { .start = 0x00a030a0, .end = 0x00a030a0 },
1877         { .start = 0x00a030a8, .end = 0x00a030b4 },
1878         { .start = 0x00a030bc, .end = 0x00a030bc },
1879         { .start = 0x00a030c0, .end = 0x00a0312c },
1880         { .start = 0x00a03c00, .end = 0x00a03c5c },
1881         { .start = 0x00a04400, .end = 0x00a04454 },
1882         { .start = 0x00a04460, .end = 0x00a04474 },
1883         { .start = 0x00a044c0, .end = 0x00a044ec },
1884         { .start = 0x00a04500, .end = 0x00a04504 },
1885         { .start = 0x00a04510, .end = 0x00a04538 },
1886         { .start = 0x00a04540, .end = 0x00a04548 },
1887         { .start = 0x00a04560, .end = 0x00a0457c },
1888         { .start = 0x00a04590, .end = 0x00a04598 },
1889         { .start = 0x00a045c0, .end = 0x00a045f4 },
1890 };
1891
1892 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1893                                     struct iwl_fw_error_dump_data **data)
1894 {
1895         struct iwl_fw_error_dump_prph *prph;
1896         unsigned long flags;
1897         u32 prph_len = 0, i;
1898
1899         if (!iwl_trans_grab_nic_access(trans, false, &flags))
1900                 return 0;
1901
1902         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1903                 /* The range includes both boundaries */
1904                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1905                          iwl_prph_dump_addr[i].start + 4;
1906                 int reg;
1907                 __le32 *val;
1908
1909                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
1910
1911                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
1912                 (*data)->len = cpu_to_le32(sizeof(*prph) +
1913                                         num_bytes_in_chunk);
1914                 prph = (void *)(*data)->data;
1915                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
1916                 val = (void *)prph->data;
1917
1918                 for (reg = iwl_prph_dump_addr[i].start;
1919                      reg <= iwl_prph_dump_addr[i].end;
1920                      reg += 4)
1921                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
1922                                                                       reg));
1923                 *data = iwl_fw_error_next_data(*data);
1924         }
1925
1926         iwl_trans_release_nic_access(trans, &flags);
1927
1928         return prph_len;
1929 }
1930
1931 #define IWL_CSR_TO_DUMP (0x250)
1932
1933 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
1934                                    struct iwl_fw_error_dump_data **data)
1935 {
1936         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
1937         __le32 *val;
1938         int i;
1939
1940         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
1941         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
1942         val = (void *)(*data)->data;
1943
1944         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
1945                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
1946
1947         *data = iwl_fw_error_next_data(*data);
1948
1949         return csr_len;
1950 }
1951
1952 static
1953 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
1954 {
1955         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1956         struct iwl_fw_error_dump_data *data;
1957         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
1958         struct iwl_fw_error_dump_txcmd *txcmd;
1959         struct iwl_trans_dump_data *dump_data;
1960         u32 len;
1961         int i, ptr;
1962
1963         /* transport dump header */
1964         len = sizeof(*dump_data);
1965
1966         /* host commands */
1967         len += sizeof(*data) +
1968                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
1969
1970         /* CSR registers */
1971         len += sizeof(*data) + IWL_CSR_TO_DUMP;
1972
1973         /* PRPH registers */
1974         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1975                 /* The range includes both boundaries */
1976                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1977                         iwl_prph_dump_addr[i].start + 4;
1978
1979                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
1980                         num_bytes_in_chunk;
1981         }
1982
1983         /* FW monitor */
1984         if (trans_pcie->fw_mon_page)
1985                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
1986                         trans_pcie->fw_mon_size;
1987
1988         dump_data = vzalloc(len);
1989         if (!dump_data)
1990                 return NULL;
1991
1992         len = 0;
1993         data = (void *)dump_data->data;
1994         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
1995         txcmd = (void *)data->data;
1996         spin_lock_bh(&cmdq->lock);
1997         ptr = cmdq->q.write_ptr;
1998         for (i = 0; i < cmdq->q.n_window; i++) {
1999                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2000                 u32 caplen, cmdlen;
2001
2002                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2003                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2004
2005                 if (cmdlen) {
2006                         len += sizeof(*txcmd) + caplen;
2007                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2008                         txcmd->caplen = cpu_to_le32(caplen);
2009                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2010                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2011                 }
2012
2013                 ptr = iwl_queue_dec_wrap(ptr);
2014         }
2015         spin_unlock_bh(&cmdq->lock);
2016
2017         data->len = cpu_to_le32(len);
2018         len += sizeof(*data);
2019         data = iwl_fw_error_next_data(data);
2020
2021         len += iwl_trans_pcie_dump_prph(trans, &data);
2022         len += iwl_trans_pcie_dump_csr(trans, &data);
2023         /* data is already pointing to the next section */
2024
2025         if (trans_pcie->fw_mon_page) {
2026                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2027
2028                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2029                 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2030                                         sizeof(*fw_mon_data));
2031                 fw_mon_data = (void *)data->data;
2032                 fw_mon_data->fw_mon_wr_ptr =
2033                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_WRPTR));
2034                 fw_mon_data->fw_mon_cycle_cnt =
2035                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_CYCLE_CNT));
2036                 fw_mon_data->fw_mon_base_ptr =
2037                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_BASE_ADDR));
2038
2039                 /*
2040                  * The firmware is now asserted, it won't write anything to
2041                  * the buffer. CPU can take ownership to fetch the data.
2042                  * The buffer will be handed back to the device before the
2043                  * firmware will be restarted.
2044                  */
2045                 dma_sync_single_for_cpu(trans->dev, trans_pcie->fw_mon_phys,
2046                                         trans_pcie->fw_mon_size,
2047                                         DMA_FROM_DEVICE);
2048                 memcpy(fw_mon_data->data, page_address(trans_pcie->fw_mon_page),
2049                        trans_pcie->fw_mon_size);
2050
2051                 len += sizeof(*data) + sizeof(*fw_mon_data) +
2052                         trans_pcie->fw_mon_size;
2053         }
2054
2055         dump_data->len = len;
2056
2057         return dump_data;
2058 }
2059
2060 static const struct iwl_trans_ops trans_ops_pcie = {
2061         .start_hw = iwl_trans_pcie_start_hw,
2062         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2063         .fw_alive = iwl_trans_pcie_fw_alive,
2064         .start_fw = iwl_trans_pcie_start_fw,
2065         .stop_device = iwl_trans_pcie_stop_device,
2066
2067         .d3_suspend = iwl_trans_pcie_d3_suspend,
2068         .d3_resume = iwl_trans_pcie_d3_resume,
2069
2070         .send_cmd = iwl_trans_pcie_send_hcmd,
2071
2072         .tx = iwl_trans_pcie_tx,
2073         .reclaim = iwl_trans_pcie_reclaim,
2074
2075         .txq_disable = iwl_trans_pcie_txq_disable,
2076         .txq_enable = iwl_trans_pcie_txq_enable,
2077
2078         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2079
2080         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2081
2082         .write8 = iwl_trans_pcie_write8,
2083         .write32 = iwl_trans_pcie_write32,
2084         .read32 = iwl_trans_pcie_read32,
2085         .read_prph = iwl_trans_pcie_read_prph,
2086         .write_prph = iwl_trans_pcie_write_prph,
2087         .read_mem = iwl_trans_pcie_read_mem,
2088         .write_mem = iwl_trans_pcie_write_mem,
2089         .configure = iwl_trans_pcie_configure,
2090         .set_pmi = iwl_trans_pcie_set_pmi,
2091         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2092         .release_nic_access = iwl_trans_pcie_release_nic_access,
2093         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2094
2095         .dump_data = iwl_trans_pcie_dump_data,
2096 };
2097
2098 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2099                                        const struct pci_device_id *ent,
2100                                        const struct iwl_cfg *cfg)
2101 {
2102         struct iwl_trans_pcie *trans_pcie;
2103         struct iwl_trans *trans;
2104         u16 pci_cmd;
2105         int err;
2106
2107         trans = kzalloc(sizeof(struct iwl_trans) +
2108                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2109         if (!trans) {
2110                 err = -ENOMEM;
2111                 goto out;
2112         }
2113
2114         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2115
2116         trans->ops = &trans_ops_pcie;
2117         trans->cfg = cfg;
2118         trans_lockdep_init(trans);
2119         trans_pcie->trans = trans;
2120         spin_lock_init(&trans_pcie->irq_lock);
2121         spin_lock_init(&trans_pcie->reg_lock);
2122         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2123
2124         err = pci_enable_device(pdev);
2125         if (err)
2126                 goto out_no_pci;
2127
2128         if (!cfg->base_params->pcie_l1_allowed) {
2129                 /*
2130                  * W/A - seems to solve weird behavior. We need to remove this
2131                  * if we don't want to stay in L1 all the time. This wastes a
2132                  * lot of power.
2133                  */
2134                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2135                                        PCIE_LINK_STATE_L1 |
2136                                        PCIE_LINK_STATE_CLKPM);
2137         }
2138
2139         pci_set_master(pdev);
2140
2141         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2142         if (!err)
2143                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2144         if (err) {
2145                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2146                 if (!err)
2147                         err = pci_set_consistent_dma_mask(pdev,
2148                                                           DMA_BIT_MASK(32));
2149                 /* both attempts failed: */
2150                 if (err) {
2151                         dev_err(&pdev->dev, "No suitable DMA available\n");
2152                         goto out_pci_disable_device;
2153                 }
2154         }
2155
2156         err = pci_request_regions(pdev, DRV_NAME);
2157         if (err) {
2158                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2159                 goto out_pci_disable_device;
2160         }
2161
2162         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2163         if (!trans_pcie->hw_base) {
2164                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2165                 err = -ENODEV;
2166                 goto out_pci_release_regions;
2167         }
2168
2169         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2170          * PCI Tx retries from interfering with C3 CPU state */
2171         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2172
2173         trans->dev = &pdev->dev;
2174         trans_pcie->pci_dev = pdev;
2175         iwl_disable_interrupts(trans);
2176
2177         err = pci_enable_msi(pdev);
2178         if (err) {
2179                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2180                 /* enable rfkill interrupt: hw bug w/a */
2181                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2182                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2183                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2184                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2185                 }
2186         }
2187
2188         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2189         /*
2190          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2191          * changed, and now the revision step also includes bit 0-1 (no more
2192          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2193          * in the old format.
2194          */
2195         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2196                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2197                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2198
2199         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2200         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2201                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2202
2203         /* Initialize the wait queue for commands */
2204         init_waitqueue_head(&trans_pcie->wait_command_queue);
2205
2206         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2207                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2208
2209         trans->dev_cmd_headroom = 0;
2210         trans->dev_cmd_pool =
2211                 kmem_cache_create(trans->dev_cmd_pool_name,
2212                                   sizeof(struct iwl_device_cmd)
2213                                   + trans->dev_cmd_headroom,
2214                                   sizeof(void *),
2215                                   SLAB_HWCACHE_ALIGN,
2216                                   NULL);
2217
2218         if (!trans->dev_cmd_pool) {
2219                 err = -ENOMEM;
2220                 goto out_pci_disable_msi;
2221         }
2222
2223         if (iwl_pcie_alloc_ict(trans))
2224                 goto out_free_cmd_pool;
2225
2226         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2227                                    iwl_pcie_irq_handler,
2228                                    IRQF_SHARED, DRV_NAME, trans);
2229         if (err) {
2230                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2231                 goto out_free_ict;
2232         }
2233
2234         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2235
2236         return trans;
2237
2238 out_free_ict:
2239         iwl_pcie_free_ict(trans);
2240 out_free_cmd_pool:
2241         kmem_cache_destroy(trans->dev_cmd_pool);
2242 out_pci_disable_msi:
2243         pci_disable_msi(pdev);
2244 out_pci_release_regions:
2245         pci_release_regions(pdev);
2246 out_pci_disable_device:
2247         pci_disable_device(pdev);
2248 out_no_pci:
2249         kfree(trans);
2250 out:
2251         return ERR_PTR(err);
2252 }