drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34 #include <linux/slab.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt2500pci.h"
  39
  40 /*
  41  * Register access.
  42  * All access to the CSR registers will go through the methods
  43  * rt2x00pci_register_read and rt2x00pci_register_write.
  44  * BBP and RF register require indirect register access,
  45  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  46  * These indirect registers work with busy bits,
  47  * and we will try maximal REGISTER_BUSY_COUNT times to access
  48  * the register while taking a REGISTER_BUSY_DELAY us delay
  49  * between each attampt. When the busy bit is still set at that time,
  50  * the access attempt is considered to have failed,
  51  * and we will print an error.
  52  */
  53 #define WAIT_FOR_BBP(__dev, __reg) \
  54         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  55 #define WAIT_FOR_RF(__dev, __reg) \
  56         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  57
  58 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  59                                 const unsigned int word, const u8 value)
  60 {
  61         u32 reg;
  62
  63         mutex_lock(&rt2x00dev->csr_mutex);
  64
  65         /*
  66          * Wait until the BBP becomes available, afterwards we
  67          * can safely write the new data into the register.
  68          */
  69         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  70                 reg = 0;
  71                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  72                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  73                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  74                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  75
  76                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  77         }
  78
  79         mutex_unlock(&rt2x00dev->csr_mutex);
  80 }
  81
  82 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  83                                const unsigned int word, u8 *value)
  84 {
  85         u32 reg;
  86
  87         mutex_lock(&rt2x00dev->csr_mutex);
  88
  89         /*
  90          * Wait until the BBP becomes available, afterwards we
  91          * can safely write the read request into the register.
  92          * After the data has been written, we wait until hardware
  93          * returns the correct value, if at any time the register
  94          * doesn't become available in time, reg will be 0xffffffff
  95          * which means we return 0xff to the caller.
  96          */
  97         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  98                 reg = 0;
  99                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 100                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 101                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 102
 103                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 104
 105                 WAIT_FOR_BBP(rt2x00dev, &reg);
 106         }
 107
 108         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 109
 110         mutex_unlock(&rt2x00dev->csr_mutex);
 111 }
 112
 113 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 114                                const unsigned int word, const u32 value)
 115 {
 116         u32 reg;
 117
 118         mutex_lock(&rt2x00dev->csr_mutex);
 119
 120         /*
 121          * Wait until the RF becomes available, afterwards we
 122          * can safely write the new data into the register.
 123          */
 124         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 125                 reg = 0;
 126                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 127                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 128                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 129                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 130
 131                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 132                 rt2x00_rf_write(rt2x00dev, word, value);
 133         }
 134
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136 }
 137
 138 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 139 {
 140         struct rt2x00_dev *rt2x00dev = eeprom->data;
 141         u32 reg;
 142
 143         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 144
 145         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 146         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 147         eeprom->reg_data_clock =
 148             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 149         eeprom->reg_chip_select =
 150             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 151 }
 152
 153 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 154 {
 155         struct rt2x00_dev *rt2x00dev = eeprom->data;
 156         u32 reg = 0;
 157
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 161                            !!eeprom->reg_data_clock);
 162         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 163                            !!eeprom->reg_chip_select);
 164
 165         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 166 }
 167
 168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 169 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 170         .owner  = THIS_MODULE,
 171         .csr    = {
 172                 .read           = rt2x00pci_register_read,
 173                 .write          = rt2x00pci_register_write,
 174                 .flags          = RT2X00DEBUGFS_OFFSET,
 175                 .word_base      = CSR_REG_BASE,
 176                 .word_size      = sizeof(u32),
 177                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 178         },
 179         .eeprom = {
 180                 .read           = rt2x00_eeprom_read,
 181                 .write          = rt2x00_eeprom_write,
 182                 .word_base      = EEPROM_BASE,
 183                 .word_size      = sizeof(u16),
 184                 .word_count     = EEPROM_SIZE / sizeof(u16),
 185         },
 186         .bbp    = {
 187                 .read           = rt2500pci_bbp_read,
 188                 .write          = rt2500pci_bbp_write,
 189                 .word_base      = BBP_BASE,
 190                 .word_size      = sizeof(u8),
 191                 .word_count     = BBP_SIZE / sizeof(u8),
 192         },
 193         .rf     = {
 194                 .read           = rt2x00_rf_read,
 195                 .write          = rt2500pci_rf_write,
 196                 .word_base      = RF_BASE,
 197                 .word_size      = sizeof(u32),
 198                 .word_count     = RF_SIZE / sizeof(u32),
 199         },
 200 };
 201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 202
 203 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 204 {
 205         u32 reg;
 206
 207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 208         return rt2x00_get_field32(reg, GPIOCSR_VAL0);
 209 }
 210
 211 #ifdef CONFIG_RT2X00_LIB_LEDS
 212 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 213                                      enum led_brightness brightness)
 214 {
 215         struct rt2x00_led *led =
 216             container_of(led_cdev, struct rt2x00_led, led_dev);
 217         unsigned int enabled = brightness != LED_OFF;
 218         u32 reg;
 219
 220         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 221
 222         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 223                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 224         else if (led->type == LED_TYPE_ACTIVITY)
 225                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 226
 227         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 228 }
 229
 230 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 231                                unsigned long *delay_on,
 232                                unsigned long *delay_off)
 233 {
 234         struct rt2x00_led *led =
 235             container_of(led_cdev, struct rt2x00_led, led_dev);
 236         u32 reg;
 237
 238         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 239         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 240         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 241         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 242
 243         return 0;
 244 }
 245
 246 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 247                                struct rt2x00_led *led,
 248                                enum led_type type)
 249 {
 250         led->rt2x00dev = rt2x00dev;
 251         led->type = type;
 252         led->led_dev.brightness_set = rt2500pci_brightness_set;
 253         led->led_dev.blink_set = rt2500pci_blink_set;
 254         led->flags = LED_INITIALIZED;
 255 }
 256 #endif /* CONFIG_RT2X00_LIB_LEDS */
 257
 258 /*
 259  * Configuration handlers.
 260  */
 261 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 262                                     const unsigned int filter_flags)
 263 {
 264         u32 reg;
 265
 266         /*
 267          * Start configuration steps.
 268          * Note that the version error will always be dropped
 269          * and broadcast frames will always be accepted since
 270          * there is no filter for it at this time.
 271          */
 272         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 273         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 274                            !(filter_flags & FIF_FCSFAIL));
 275         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 276                            !(filter_flags & FIF_PLCPFAIL));
 277         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 278                            !(filter_flags & FIF_CONTROL));
 279         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 280                            !(filter_flags & FIF_PROMISC_IN_BSS));
 281         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 282                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 283                            !rt2x00dev->intf_ap_count);
 284         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 285         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 286                            !(filter_flags & FIF_ALLMULTI));
 287         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 288         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 289 }
 290
 291 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 292                                   struct rt2x00_intf *intf,
 293                                   struct rt2x00intf_conf *conf,
 294                                   const unsigned int flags)
 295 {
 296         struct data_queue *queue = rt2x00dev->bcn;
 297         unsigned int bcn_preload;
 298         u32 reg;
 299
 300         if (flags & CONFIG_UPDATE_TYPE) {
 301                 /*
 302                  * Enable beacon config
 303                  */
 304                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 305                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 306                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 307                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 308                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 309
 310                 /*
 311                  * Enable synchronisation.
 312                  */
 313                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 314                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 315                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 316         }
 317
 318         if (flags & CONFIG_UPDATE_MAC)
 319                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 320                                               conf->mac, sizeof(conf->mac));
 321
 322         if (flags & CONFIG_UPDATE_BSSID)
 323                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 324                                               conf->bssid, sizeof(conf->bssid));
 325 }
 326
 327 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 328                                  struct rt2x00lib_erp *erp,
 329                                  u32 changed)
 330 {
 331         int preamble_mask;
 332         u32 reg;
 333
 334         /*
 335          * When short preamble is enabled, we should set bit 0x08
 336          */
 337         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 338                 preamble_mask = erp->short_preamble << 3;
 339
 340                 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 341                 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
 342                 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
 343                 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 344                 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 345                 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 346
 347                 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 348                 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 349                 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 350                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 351                                    GET_DURATION(ACK_SIZE, 10));
 352                 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 353
 354                 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 355                 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 356                 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 357                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 358                                    GET_DURATION(ACK_SIZE, 20));
 359                 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 360
 361                 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 362                 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 363                 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 364                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 365                                    GET_DURATION(ACK_SIZE, 55));
 366                 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 367
 368                 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 369                 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 370                 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 371                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 372                                    GET_DURATION(ACK_SIZE, 110));
 373                 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 374         }
 375
 376         if (changed & BSS_CHANGED_BASIC_RATES)
 377                 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 378
 379         if (changed & BSS_CHANGED_ERP_SLOT) {
 380                 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 381                 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 382                 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 383
 384                 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 385                 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 386                 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 387                 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 388
 389                 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 390                 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 391                 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 392                 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 393         }
 394
 395         if (changed & BSS_CHANGED_BEACON_INT) {
 396                 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 397                 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 398                                    erp->beacon_int * 16);
 399                 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 400                                    erp->beacon_int * 16);
 401                 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 402         }
 403
 404 }
 405
 406 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 407                                  struct antenna_setup *ant)
 408 {
 409         u32 reg;
 410         u8 r14;
 411         u8 r2;
 412
 413         /*
 414          * We should never come here because rt2x00lib is supposed
 415          * to catch this and send us the correct antenna explicitely.
 416          */
 417         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 418                ant->tx == ANTENNA_SW_DIVERSITY);
 419
 420         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 421         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 422         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 423
 424         /*
 425          * Configure the TX antenna.
 426          */
 427         switch (ant->tx) {
 428         case ANTENNA_A:
 429                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 430                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 431                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 432                 break;
 433         case ANTENNA_B:
 434         default:
 435                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 436                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 437                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 438                 break;
 439         }
 440
 441         /*
 442          * Configure the RX antenna.
 443          */
 444         switch (ant->rx) {
 445         case ANTENNA_A:
 446                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 447                 break;
 448         case ANTENNA_B:
 449         default:
 450                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 451                 break;
 452         }
 453
 454         /*
 455          * RT2525E and RT5222 need to flip TX I/Q
 456          */
 457         if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
 458                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 459                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 460                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 461
 462                 /*
 463                  * RT2525E does not need RX I/Q Flip.
 464                  */
 465                 if (rt2x00_rf(rt2x00dev, RF2525E))
 466                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 467         } else {
 468                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 469                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 470         }
 471
 472         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 473         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 474         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 475 }
 476
 477 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 478                                      struct rf_channel *rf, const int txpower)
 479 {
 480         u8 r70;
 481
 482         /*
 483          * Set TXpower.
 484          */
 485         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 486
 487         /*
 488          * Switch on tuning bits.
 489          * For RT2523 devices we do not need to update the R1 register.
 490          */
 491         if (!rt2x00_rf(rt2x00dev, RF2523))
 492                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 493         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 494
 495         /*
 496          * For RT2525 we should first set the channel to half band higher.
 497          */
 498         if (rt2x00_rf(rt2x00dev, RF2525)) {
 499                 static const u32 vals[] = {
 500                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 501                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 502                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 503                         0x00080d2e, 0x00080d3a
 504                 };
 505
 506                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 507                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 508                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 509                 if (rf->rf4)
 510                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 511         }
 512
 513         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 514         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 515         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 516         if (rf->rf4)
 517                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 518
 519         /*
 520          * Channel 14 requires the Japan filter bit to be set.
 521          */
 522         r70 = 0x46;
 523         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 524         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 525
 526         msleep(1);
 527
 528         /*
 529          * Switch off tuning bits.
 530          * For RT2523 devices we do not need to update the R1 register.
 531          */
 532         if (!rt2x00_rf(rt2x00dev, RF2523)) {
 533                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 534                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 535         }
 536
 537         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 538         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 539
 540         /*
 541          * Clear false CRC during channel switch.
 542          */
 543         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 544 }
 545
 546 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 547                                      const int txpower)
 548 {
 549         u32 rf3;
 550
 551         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 552         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 553         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 554 }
 555
 556 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 557                                          struct rt2x00lib_conf *libconf)
 558 {
 559         u32 reg;
 560
 561         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 562         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 563                            libconf->conf->long_frame_max_tx_count);
 564         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 565                            libconf->conf->short_frame_max_tx_count);
 566         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 567 }
 568
 569 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
 570                                 struct rt2x00lib_conf *libconf)
 571 {
 572         enum dev_state state =
 573             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 574                 STATE_SLEEP : STATE_AWAKE;
 575         u32 reg;
 576
 577         if (state == STATE_SLEEP) {
 578                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 579                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 580                                    (rt2x00dev->beacon_int - 20) * 16);
 581                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 582                                    libconf->conf->listen_interval - 1);
 583
 584                 /* We must first disable autowake before it can be enabled */
 585                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 586                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 587
 588                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 589                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 590         } else {
 591                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 592                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 593                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 594         }
 595
 596         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 597 }
 598
 599 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 600                              struct rt2x00lib_conf *libconf,
 601                              const unsigned int flags)
 602 {
 603         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 604                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 605                                          libconf->conf->power_level);
 606         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 607             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 608                 rt2500pci_config_txpower(rt2x00dev,
 609                                          libconf->conf->power_level);
 610         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 611                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 612         if (flags & IEEE80211_CONF_CHANGE_PS)
 613                 rt2500pci_config_ps(rt2x00dev, libconf);
 614 }
 615
 616 /*
 617  * Link tuning
 618  */
 619 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 620                                  struct link_qual *qual)
 621 {
 622         u32 reg;
 623
 624         /*
 625          * Update FCS error count from register.
 626          */
 627         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 628         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 629
 630         /*
 631          * Update False CCA count from register.
 632          */
 633         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 634         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 635 }
 636
 637 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 638                                      struct link_qual *qual, u8 vgc_level)
 639 {
 640         if (qual->vgc_level_reg != vgc_level) {
 641                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
 642                 qual->vgc_level = vgc_level;
 643                 qual->vgc_level_reg = vgc_level;
 644         }
 645 }
 646
 647 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 648                                   struct link_qual *qual)
 649 {
 650         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
 651 }
 652
 653 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 654                                  struct link_qual *qual, const u32 count)
 655 {
 656         /*
 657          * To prevent collisions with MAC ASIC on chipsets
 658          * up to version C the link tuning should halt after 20
 659          * seconds while being associated.
 660          */
 661         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
 662             rt2x00dev->intf_associated && count > 20)
 663                 return;
 664
 665         /*
 666          * Chipset versions C and lower should directly continue
 667          * to the dynamic CCA tuning. Chipset version D and higher
 668          * should go straight to dynamic CCA tuning when they
 669          * are not associated.
 670          */
 671         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
 672             !rt2x00dev->intf_associated)
 673                 goto dynamic_cca_tune;
 674
 675         /*
 676          * A too low RSSI will cause too much false CCA which will
 677          * then corrupt the R17 tuning. To remidy this the tuning should
 678          * be stopped (While making sure the R17 value will not exceed limits)
 679          */
 680         if (qual->rssi < -80 && count > 20) {
 681                 if (qual->vgc_level_reg >= 0x41)
 682                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 683                 return;
 684         }
 685
 686         /*
 687          * Special big-R17 for short distance
 688          */
 689         if (qual->rssi >= -58) {
 690                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
 691                 return;
 692         }
 693
 694         /*
 695          * Special mid-R17 for middle distance
 696          */
 697         if (qual->rssi >= -74) {
 698                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
 699                 return;
 700         }
 701
 702         /*
 703          * Leave short or middle distance condition, restore r17
 704          * to the dynamic tuning range.
 705          */
 706         if (qual->vgc_level_reg >= 0x41) {
 707                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 708                 return;
 709         }
 710
 711 dynamic_cca_tune:
 712
 713         /*
 714          * R17 is inside the dynamic tuning range,
 715          * start tuning the link based on the false cca counter.
 716          */
 717         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
 718                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
 719         else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
 720                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
 721 }
 722
 723 /*
 724  * Queue handlers.
 725  */
 726 static void rt2500pci_start_queue(struct data_queue *queue)
 727 {
 728         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 729         u32 reg;
 730
 731         switch (queue->qid) {
 732         case QID_RX:
 733                 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 734                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
 735                 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 736                 break;
 737         case QID_BEACON:
 738                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 739                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 740                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 741                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
 742                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 743                 break;
 744         default:
 745                 break;
 746         }
 747 }
 748
 749 static void rt2500pci_kick_queue(struct data_queue *queue)
 750 {
 751         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 752         u32 reg;
 753
 754         switch (queue->qid) {
 755         case QID_AC_VO:
 756                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 757                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
 758                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 759                 break;
 760         case QID_AC_VI:
 761                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 762                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
 763                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 764                 break;
 765         case QID_ATIM:
 766                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 767                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
 768                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 769                 break;
 770         default:
 771                 break;
 772         }
 773 }
 774
 775 static void rt2500pci_stop_queue(struct data_queue *queue)
 776 {
 777         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 778         u32 reg;
 779
 780         switch (queue->qid) {
 781         case QID_AC_VO:
 782         case QID_AC_VI:
 783         case QID_ATIM:
 784                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 785                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 786                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 787                 break;
 788         case QID_RX:
 789                 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 790                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
 791                 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 792                 break;
 793         case QID_BEACON:
 794                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 795                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 796                 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 797                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 798                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 799
 800                 /*
 801                  * Wait for possibly running tbtt tasklets.
 802                  */
 803                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 804                 break;
 805         default:
 806                 break;
 807         }
 808 }
 809
 810 /*
 811  * Initialization functions.
 812  */
 813 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
 814 {
 815         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 816         u32 word;
 817
 818         if (entry->queue->qid == QID_RX) {
 819                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 820
 821                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 822         } else {
 823                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 824
 825                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 826                         rt2x00_get_field32(word, TXD_W0_VALID));
 827         }
 828 }
 829
 830 static void rt2500pci_clear_entry(struct queue_entry *entry)
 831 {
 832         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 833         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 834         u32 word;
 835
 836         if (entry->queue->qid == QID_RX) {
 837                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 838                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 839                 rt2x00_desc_write(entry_priv->desc, 1, word);
 840
 841                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 842                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 843                 rt2x00_desc_write(entry_priv->desc, 0, word);
 844         } else {
 845                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 846                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 847                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 848                 rt2x00_desc_write(entry_priv->desc, 0, word);
 849         }
 850 }
 851
 852 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 853 {
 854         struct queue_entry_priv_pci *entry_priv;
 855         u32 reg;
 856
 857         /*
 858          * Initialize registers.
 859          */
 860         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 861         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 862         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 863         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
 864         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 865         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 866
 867         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 868         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 869         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 870                            entry_priv->desc_dma);
 871         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 872
 873         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 874         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 875         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 876                            entry_priv->desc_dma);
 877         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 878
 879         entry_priv = rt2x00dev->atim->entries[0].priv_data;
 880         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 881         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 882                            entry_priv->desc_dma);
 883         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 884
 885         entry_priv = rt2x00dev->bcn->entries[0].priv_data;
 886         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 887         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 888                            entry_priv->desc_dma);
 889         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 890
 891         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 892         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 893         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 894         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 895
 896         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 897         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 898         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 899                            entry_priv->desc_dma);
 900         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 901
 902         return 0;
 903 }
 904
 905 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 906 {
 907         u32 reg;
 908
 909         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 910         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 911         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 912         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 913
 914         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 915         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 916         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 917         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 918         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 919
 920         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 921         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 922                            rt2x00dev->rx->data_size / 128);
 923         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 924
 925         /*
 926          * Always use CWmin and CWmax set in descriptor.
 927          */
 928         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 929         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 930         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 931
 932         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 933         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 934         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 935         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 936         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 937         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 938         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 939         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 940         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 941         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 942
 943         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 944
 945         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 946         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 947         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 948         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 949         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 950         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 951         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 952         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 953         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 954         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 955
 956         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 957         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 958         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 959         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 960         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 961         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 962
 963         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 964         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 965         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 966         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 967         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 968         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 969
 970         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 971         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 972         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 973         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 974         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 975         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 976
 977         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 978         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 979         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 980         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 981         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 982         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 983         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 984         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 985         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 986         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 987
 988         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 989         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 990         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 991         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 992         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 993         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 994         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 995         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 996         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 997
 998         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 999
1000         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
1001         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
1002
1003         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1004                 return -EBUSY;
1005
1006         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
1007         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
1008
1009         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
1010         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
1011         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
1012
1013         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
1014         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1015         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1016         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1017         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1018         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1019         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
1020         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
1021
1022         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1023
1024         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1025
1026         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
1027         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1028         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1029         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
1030         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1031
1032         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
1033         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1034         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1035         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1036
1037         /*
1038          * We must clear the FCS and FIFO error count.
1039          * These registers are cleared on read,
1040          * so we may pass a useless variable to store the value.
1041          */
1042         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1043         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
1044
1045         return 0;
1046 }
1047
1048 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1049 {
1050         unsigned int i;
1051         u8 value;
1052
1053         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1054                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1055                 if ((value != 0xff) && (value != 0x00))
1056                         return 0;
1057                 udelay(REGISTER_BUSY_DELAY);
1058         }
1059
1060         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1061         return -EACCES;
1062 }
1063
1064 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1065 {
1066         unsigned int i;
1067         u16 eeprom;
1068         u8 reg_id;
1069         u8 value;
1070
1071         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1072                 return -EACCES;
1073
1074         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1075         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1076         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1077         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1078         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1079         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1080         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1081         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1082         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1083         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1084         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1085         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1086         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1087         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1088         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1089         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1090         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1091         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1092         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1093         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1094         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1095         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1096         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1097         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1098         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1099         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1100         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1101         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1102         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1103         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1104
1105         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1106                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1107
1108                 if (eeprom != 0xffff && eeprom != 0x0000) {
1109                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1110                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1111                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1112                 }
1113         }
1114
1115         return 0;
1116 }
1117
1118 /*
1119  * Device state switch handlers.
1120  */
1121 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1122                                  enum dev_state state)
1123 {
1124         int mask = (state == STATE_RADIO_IRQ_OFF);
1125         u32 reg;
1126         unsigned long flags;
1127
1128         /*
1129          * When interrupts are being enabled, the interrupt registers
1130          * should clear the register to assure a clean state.
1131          */
1132         if (state == STATE_RADIO_IRQ_ON) {
1133                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1134                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1135         }
1136
1137         /*
1138          * Only toggle the interrupts bits we are going to use.
1139          * Non-checked interrupt bits are disabled by default.
1140          */
1141         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1142
1143         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1144         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1145         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1146         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1147         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1148         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1149         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1150
1151         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1152
1153         if (state == STATE_RADIO_IRQ_OFF) {
1154                 /*
1155                  * Ensure that all tasklets are finished.
1156                  */
1157                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1158                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1159                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1160         }
1161 }
1162
1163 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1164 {
1165         /*
1166          * Initialize all registers.
1167          */
1168         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1169                      rt2500pci_init_registers(rt2x00dev) ||
1170                      rt2500pci_init_bbp(rt2x00dev)))
1171                 return -EIO;
1172
1173         return 0;
1174 }
1175
1176 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1177 {
1178         /*
1179          * Disable power
1180          */
1181         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1182 }
1183
1184 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1185                                enum dev_state state)
1186 {
1187         u32 reg, reg2;
1188         unsigned int i;
1189         char put_to_sleep;
1190         char bbp_state;
1191         char rf_state;
1192
1193         put_to_sleep = (state != STATE_AWAKE);
1194
1195         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1196         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1197         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1198         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1199         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1200         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1201
1202         /*
1203          * Device is not guaranteed to be in the requested state yet.
1204          * We must wait until the register indicates that the
1205          * device has entered the correct state.
1206          */
1207         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1208                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1209                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1210                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1211                 if (bbp_state == state && rf_state == state)
1212                         return 0;
1213                 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1214                 msleep(10);
1215         }
1216
1217         return -EBUSY;
1218 }
1219
1220 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1221                                       enum dev_state state)
1222 {
1223         int retval = 0;
1224
1225         switch (state) {
1226         case STATE_RADIO_ON:
1227                 retval = rt2500pci_enable_radio(rt2x00dev);
1228                 break;
1229         case STATE_RADIO_OFF:
1230                 rt2500pci_disable_radio(rt2x00dev);
1231                 break;
1232         case STATE_RADIO_IRQ_ON:
1233         case STATE_RADIO_IRQ_OFF:
1234                 rt2500pci_toggle_irq(rt2x00dev, state);
1235                 break;
1236         case STATE_DEEP_SLEEP:
1237         case STATE_SLEEP:
1238         case STATE_STANDBY:
1239         case STATE_AWAKE:
1240                 retval = rt2500pci_set_state(rt2x00dev, state);
1241                 break;
1242         default:
1243                 retval = -ENOTSUPP;
1244                 break;
1245         }
1246
1247         if (unlikely(retval))
1248                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1249                       state, retval);
1250
1251         return retval;
1252 }
1253
1254 /*
1255  * TX descriptor initialization
1256  */
1257 static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1258                                     struct txentry_desc *txdesc)
1259 {
1260         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1261         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1262         __le32 *txd = entry_priv->desc;
1263         u32 word;
1264
1265         /*
1266          * Start writing the descriptor words.
1267          */
1268         rt2x00_desc_read(txd, 1, &word);
1269         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1270         rt2x00_desc_write(txd, 1, word);
1271
1272         rt2x00_desc_read(txd, 2, &word);
1273         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1274         rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1275         rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1276         rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
1277         rt2x00_desc_write(txd, 2, word);
1278
1279         rt2x00_desc_read(txd, 3, &word);
1280         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1281         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1282         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1283                            txdesc->u.plcp.length_low);
1284         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1285                            txdesc->u.plcp.length_high);
1286         rt2x00_desc_write(txd, 3, word);
1287
1288         rt2x00_desc_read(txd, 10, &word);
1289         rt2x00_set_field32(&word, TXD_W10_RTS,
1290                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1291         rt2x00_desc_write(txd, 10, word);
1292
1293         /*
1294          * Writing TXD word 0 must the last to prevent a race condition with
1295          * the device, whereby the device may take hold of the TXD before we
1296          * finished updating it.
1297          */
1298         rt2x00_desc_read(txd, 0, &word);
1299         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1300         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1301         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1302                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1303         rt2x00_set_field32(&word, TXD_W0_ACK,
1304                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1305         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1306                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1307         rt2x00_set_field32(&word, TXD_W0_OFDM,
1308                            (txdesc->rate_mode == RATE_MODE_OFDM));
1309         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1310         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1311         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1312                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1313         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1314         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1315         rt2x00_desc_write(txd, 0, word);
1316
1317         /*
1318          * Register descriptor details in skb frame descriptor.
1319          */
1320         skbdesc->desc = txd;
1321         skbdesc->desc_len = TXD_DESC_SIZE;
1322 }
1323
1324 /*
1325  * TX data initialization
1326  */
1327 static void rt2500pci_write_beacon(struct queue_entry *entry,
1328                                    struct txentry_desc *txdesc)
1329 {
1330         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1331         u32 reg;
1332
1333         /*
1334          * Disable beaconing while we are reloading the beacon data,
1335          * otherwise we might be sending out invalid data.
1336          */
1337         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1338         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1339         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1340
1341         if (rt2x00queue_map_txskb(entry)) {
1342                 ERROR(rt2x00dev, "Fail to map beacon, aborting\n");
1343                 goto out;
1344         }
1345
1346         /*
1347          * Write the TX descriptor for the beacon.
1348          */
1349         rt2500pci_write_tx_desc(entry, txdesc);
1350
1351         /*
1352          * Dump beacon to userspace through debugfs.
1353          */
1354         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1355 out:
1356         /*
1357          * Enable beaconing again.
1358          */
1359         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1360         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1361 }
1362
1363 /*
1364  * RX control handlers
1365  */
1366 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1367                                   struct rxdone_entry_desc *rxdesc)
1368 {
1369         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1370         u32 word0;
1371         u32 word2;
1372
1373         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1374         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1375
1376         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1377                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1378         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1379                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1380
1381         /*
1382          * Obtain the status about this packet.
1383          * When frame was received with an OFDM bitrate,
1384          * the signal is the PLCP value. If it was received with
1385          * a CCK bitrate the signal is the rate in 100kbit/s.
1386          */
1387         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1388         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1389             entry->queue->rt2x00dev->rssi_offset;
1390         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1391
1392         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1393                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1394         else
1395                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1396         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1397                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1398 }
1399
1400 /*
1401  * Interrupt functions.
1402  */
1403 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1404                              const enum data_queue_qid queue_idx)
1405 {
1406         struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1407         struct queue_entry_priv_pci *entry_priv;
1408         struct queue_entry *entry;
1409         struct txdone_entry_desc txdesc;
1410         u32 word;
1411
1412         while (!rt2x00queue_empty(queue)) {
1413                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1414                 entry_priv = entry->priv_data;
1415                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1416
1417                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1418                     !rt2x00_get_field32(word, TXD_W0_VALID))
1419                         break;
1420
1421                 /*
1422                  * Obtain the status about this packet.
1423                  */
1424                 txdesc.flags = 0;
1425                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1426                 case 0: /* Success */
1427                 case 1: /* Success with retry */
1428                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1429                         break;
1430                 case 2: /* Failure, excessive retries */
1431                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1432                         /* Don't break, this is a failed frame! */
1433                 default: /* Failure */
1434                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1435                 }
1436                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1437
1438                 rt2x00lib_txdone(entry, &txdesc);
1439         }
1440 }
1441
1442 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1443                                               struct rt2x00_field32 irq_field)
1444 {
1445         u32 reg;
1446
1447         /*
1448          * Enable a single interrupt. The interrupt mask register
1449          * access needs locking.
1450          */
1451         spin_lock_irq(&rt2x00dev->irqmask_lock);
1452
1453         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1454         rt2x00_set_field32(&reg, irq_field, 0);
1455         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1456
1457         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1458 }
1459
1460 static void rt2500pci_txstatus_tasklet(unsigned long data)
1461 {
1462         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1463         u32 reg;
1464
1465         /*
1466          * Handle all tx queues.
1467          */
1468         rt2500pci_txdone(rt2x00dev, QID_ATIM);
1469         rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1470         rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1471
1472         /*
1473          * Enable all TXDONE interrupts again.
1474          */
1475         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1476                 spin_lock_irq(&rt2x00dev->irqmask_lock);
1477
1478                 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1479                 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1480                 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1481                 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1482                 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1483
1484                 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1485         }
1486 }
1487
1488 static void rt2500pci_tbtt_tasklet(unsigned long data)
1489 {
1490         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1491         rt2x00lib_beacondone(rt2x00dev);
1492         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1493                 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1494 }
1495
1496 static void rt2500pci_rxdone_tasklet(unsigned long data)
1497 {
1498         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1499         if (rt2x00pci_rxdone(rt2x00dev))
1500                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1501         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1502                 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1503 }
1504
1505 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1506 {
1507         struct rt2x00_dev *rt2x00dev = dev_instance;
1508         u32 reg, mask;
1509
1510         /*
1511          * Get the interrupt sources & saved to local variable.
1512          * Write register value back to clear pending interrupts.
1513          */
1514         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1515         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1516
1517         if (!reg)
1518                 return IRQ_NONE;
1519
1520         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1521                 return IRQ_HANDLED;
1522
1523         mask = reg;
1524
1525         /*
1526          * Schedule tasklets for interrupt handling.
1527          */
1528         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1529                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1530
1531         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1532                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1533
1534         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1535             rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1536             rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1537                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1538                 /*
1539                  * Mask out all txdone interrupts.
1540                  */
1541                 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1542                 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1543                 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1544         }
1545
1546         /*
1547          * Disable all interrupts for which a tasklet was scheduled right now,
1548          * the tasklet will reenable the appropriate interrupts.
1549          */
1550         spin_lock(&rt2x00dev->irqmask_lock);
1551
1552         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1553         reg |= mask;
1554         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1555
1556         spin_unlock(&rt2x00dev->irqmask_lock);
1557
1558         return IRQ_HANDLED;
1559 }
1560
1561 /*
1562  * Device probe functions.
1563  */
1564 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1565 {
1566         struct eeprom_93cx6 eeprom;
1567         u32 reg;
1568         u16 word;
1569         u8 *mac;
1570
1571         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1572
1573         eeprom.data = rt2x00dev;
1574         eeprom.register_read = rt2500pci_eepromregister_read;
1575         eeprom.register_write = rt2500pci_eepromregister_write;
1576         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1577             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1578         eeprom.reg_data_in = 0;
1579         eeprom.reg_data_out = 0;
1580         eeprom.reg_data_clock = 0;
1581         eeprom.reg_chip_select = 0;
1582
1583         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1584                                EEPROM_SIZE / sizeof(u16));
1585
1586         /*
1587          * Start validation of the data that has been read.
1588          */
1589         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1590         if (!is_valid_ether_addr(mac)) {
1591                 eth_random_addr(mac);
1592                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1593         }
1594
1595         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1596         if (word == 0xffff) {
1597                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1598                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1599                                    ANTENNA_SW_DIVERSITY);
1600                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1601                                    ANTENNA_SW_DIVERSITY);
1602                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1603                                    LED_MODE_DEFAULT);
1604                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1605                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1606                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1607                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1608                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1609         }
1610
1611         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1612         if (word == 0xffff) {
1613                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1614                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1615                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1616                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1617                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1618         }
1619
1620         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1621         if (word == 0xffff) {
1622                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1623                                    DEFAULT_RSSI_OFFSET);
1624                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1625                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1626         }
1627
1628         return 0;
1629 }
1630
1631 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1632 {
1633         u32 reg;
1634         u16 value;
1635         u16 eeprom;
1636
1637         /*
1638          * Read EEPROM word for configuration.
1639          */
1640         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1641
1642         /*
1643          * Identify RF chipset.
1644          */
1645         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1646         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1647         rt2x00_set_chip(rt2x00dev, RT2560, value,
1648                         rt2x00_get_field32(reg, CSR0_REVISION));
1649
1650         if (!rt2x00_rf(rt2x00dev, RF2522) &&
1651             !rt2x00_rf(rt2x00dev, RF2523) &&
1652             !rt2x00_rf(rt2x00dev, RF2524) &&
1653             !rt2x00_rf(rt2x00dev, RF2525) &&
1654             !rt2x00_rf(rt2x00dev, RF2525E) &&
1655             !rt2x00_rf(rt2x00dev, RF5222)) {
1656                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1657                 return -ENODEV;
1658         }
1659
1660         /*
1661          * Identify default antenna configuration.
1662          */
1663         rt2x00dev->default_ant.tx =
1664             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1665         rt2x00dev->default_ant.rx =
1666             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1667
1668         /*
1669          * Store led mode, for correct led behaviour.
1670          */
1671 #ifdef CONFIG_RT2X00_LIB_LEDS
1672         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1673
1674         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1675         if (value == LED_MODE_TXRX_ACTIVITY ||
1676             value == LED_MODE_DEFAULT ||
1677             value == LED_MODE_ASUS)
1678                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1679                                    LED_TYPE_ACTIVITY);
1680 #endif /* CONFIG_RT2X00_LIB_LEDS */
1681
1682         /*
1683          * Detect if this device has an hardware controlled radio.
1684          */
1685         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1686                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1687
1688         /*
1689          * Check if the BBP tuning should be enabled.
1690          */
1691         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1692         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1693                 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1694
1695         /*
1696          * Read the RSSI <-> dBm offset information.
1697          */
1698         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1699         rt2x00dev->rssi_offset =
1700             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1701
1702         return 0;
1703 }
1704
1705 /*
1706  * RF value list for RF2522
1707  * Supports: 2.4 GHz
1708  */
1709 static const struct rf_channel rf_vals_bg_2522[] = {
1710         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1711         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1712         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1713         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1714         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1715         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1716         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1717         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1718         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1719         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1720         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1721         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1722         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1723         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1724 };
1725
1726 /*
1727  * RF value list for RF2523
1728  * Supports: 2.4 GHz
1729  */
1730 static const struct rf_channel rf_vals_bg_2523[] = {
1731         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1732         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1733         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1734         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1735         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1736         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1737         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1738         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1739         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1740         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1741         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1742         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1743         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1744         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1745 };
1746
1747 /*
1748  * RF value list for RF2524
1749  * Supports: 2.4 GHz
1750  */
1751 static const struct rf_channel rf_vals_bg_2524[] = {
1752         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1753         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1754         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1755         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1756         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1757         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1758         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1759         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1760         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1761         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1762         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1763         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1764         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1765         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1766 };
1767
1768 /*
1769  * RF value list for RF2525
1770  * Supports: 2.4 GHz
1771  */
1772 static const struct rf_channel rf_vals_bg_2525[] = {
1773         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1774         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1775         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1776         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1777         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1778         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1779         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1780         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1781         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1782         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1783         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1784         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1785         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1786         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1787 };
1788
1789 /*
1790  * RF value list for RF2525e
1791  * Supports: 2.4 GHz
1792  */
1793 static const struct rf_channel rf_vals_bg_2525e[] = {
1794         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1795         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1796         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1797         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1798         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1799         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1800         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1801         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1802         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1803         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1804         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1805         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1806         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1807         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1808 };
1809
1810 /*
1811  * RF value list for RF5222
1812  * Supports: 2.4 GHz & 5.2 GHz
1813  */
1814 static const struct rf_channel rf_vals_5222[] = {
1815         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1816         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1817         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1818         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1819         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1820         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1821         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1822         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1823         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1824         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1825         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1826         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1827         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1828         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1829
1830         /* 802.11 UNI / HyperLan 2 */
1831         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1832         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1833         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1834         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1835         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1836         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1837         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1838         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1839
1840         /* 802.11 HyperLan 2 */
1841         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1842         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1843         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1844         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1845         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1846         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1847         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1848         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1849         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1850         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1851
1852         /* 802.11 UNII */
1853         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1854         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1855         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1856         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1857         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1858 };
1859
1860 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1861 {
1862         struct hw_mode_spec *spec = &rt2x00dev->spec;
1863         struct channel_info *info;
1864         char *tx_power;
1865         unsigned int i;
1866
1867         /*
1868          * Initialize all hw fields.
1869          */
1870         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1871                                IEEE80211_HW_SIGNAL_DBM |
1872                                IEEE80211_HW_SUPPORTS_PS |
1873                                IEEE80211_HW_PS_NULLFUNC_STACK;
1874
1875         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1876         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1877                                 rt2x00_eeprom_addr(rt2x00dev,
1878                                                    EEPROM_MAC_ADDR_0));
1879
1880         /*
1881          * Initialize hw_mode information.
1882          */
1883         spec->supported_bands = SUPPORT_BAND_2GHZ;
1884         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1885
1886         if (rt2x00_rf(rt2x00dev, RF2522)) {
1887                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1888                 spec->channels = rf_vals_bg_2522;
1889         } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1890                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1891                 spec->channels = rf_vals_bg_2523;
1892         } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1893                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1894                 spec->channels = rf_vals_bg_2524;
1895         } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1896                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1897                 spec->channels = rf_vals_bg_2525;
1898         } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1899                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1900                 spec->channels = rf_vals_bg_2525e;
1901         } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1902                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1903                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1904                 spec->channels = rf_vals_5222;
1905         }
1906
1907         /*
1908          * Create channel information array
1909          */
1910         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1911         if (!info)
1912                 return -ENOMEM;
1913
1914         spec->channels_info = info;
1915
1916         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1917         for (i = 0; i < 14; i++) {
1918                 info[i].max_power = MAX_TXPOWER;
1919                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1920         }
1921
1922         if (spec->num_channels > 14) {
1923                 for (i = 14; i < spec->num_channels; i++) {
1924                         info[i].max_power = MAX_TXPOWER;
1925                         info[i].default_power1 = DEFAULT_TXPOWER;
1926                 }
1927         }
1928
1929         return 0;
1930 }
1931
1932 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1933 {
1934         int retval;
1935         u32 reg;
1936
1937         /*
1938          * Allocate eeprom data.
1939          */
1940         retval = rt2500pci_validate_eeprom(rt2x00dev);
1941         if (retval)
1942                 return retval;
1943
1944         retval = rt2500pci_init_eeprom(rt2x00dev);
1945         if (retval)
1946                 return retval;
1947
1948         /*
1949          * Enable rfkill polling by setting GPIO direction of the
1950          * rfkill switch GPIO pin correctly.
1951          */
1952         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
1953         rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1954         rt2x00pci_register_write(rt2x00dev, GPIOCSR, reg);
1955
1956         /*
1957          * Initialize hw specifications.
1958          */
1959         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1960         if (retval)
1961                 return retval;
1962
1963         /*
1964          * This device requires the atim queue and DMA-mapped skbs.
1965          */
1966         __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1967         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1968         __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1969
1970         /*
1971          * Set the rssi offset.
1972          */
1973         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1974
1975         return 0;
1976 }
1977
1978 /*
1979  * IEEE80211 stack callback functions.
1980  */
1981 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw,
1982                              struct ieee80211_vif *vif)
1983 {
1984         struct rt2x00_dev *rt2x00dev = hw->priv;
1985         u64 tsf;
1986         u32 reg;
1987
1988         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1989         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1990         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1991         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1992
1993         return tsf;
1994 }
1995
1996 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1997 {
1998         struct rt2x00_dev *rt2x00dev = hw->priv;
1999         u32 reg;
2000
2001         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
2002         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
2003 }
2004
2005 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
2006         .tx                     = rt2x00mac_tx,
2007         .start                  = rt2x00mac_start,
2008         .stop                   = rt2x00mac_stop,
2009         .add_interface          = rt2x00mac_add_interface,
2010         .remove_interface       = rt2x00mac_remove_interface,
2011         .config                 = rt2x00mac_config,
2012         .configure_filter       = rt2x00mac_configure_filter,
2013         .sw_scan_start          = rt2x00mac_sw_scan_start,
2014         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2015         .get_stats              = rt2x00mac_get_stats,
2016         .bss_info_changed       = rt2x00mac_bss_info_changed,
2017         .conf_tx                = rt2x00mac_conf_tx,
2018         .get_tsf                = rt2500pci_get_tsf,
2019         .tx_last_beacon         = rt2500pci_tx_last_beacon,
2020         .rfkill_poll            = rt2x00mac_rfkill_poll,
2021         .flush                  = rt2x00mac_flush,
2022         .set_antenna            = rt2x00mac_set_antenna,
2023         .get_antenna            = rt2x00mac_get_antenna,
2024         .get_ringparam          = rt2x00mac_get_ringparam,
2025         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
2026 };
2027
2028 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
2029         .irq_handler            = rt2500pci_interrupt,
2030         .txstatus_tasklet       = rt2500pci_txstatus_tasklet,
2031         .tbtt_tasklet           = rt2500pci_tbtt_tasklet,
2032         .rxdone_tasklet         = rt2500pci_rxdone_tasklet,
2033         .probe_hw               = rt2500pci_probe_hw,
2034         .initialize             = rt2x00pci_initialize,
2035         .uninitialize           = rt2x00pci_uninitialize,
2036         .get_entry_state        = rt2500pci_get_entry_state,
2037         .clear_entry            = rt2500pci_clear_entry,
2038         .set_device_state       = rt2500pci_set_device_state,
2039         .rfkill_poll            = rt2500pci_rfkill_poll,
2040         .link_stats             = rt2500pci_link_stats,
2041         .reset_tuner            = rt2500pci_reset_tuner,
2042         .link_tuner             = rt2500pci_link_tuner,
2043         .start_queue            = rt2500pci_start_queue,
2044         .kick_queue             = rt2500pci_kick_queue,
2045         .stop_queue             = rt2500pci_stop_queue,
2046         .flush_queue            = rt2x00pci_flush_queue,
2047         .write_tx_desc          = rt2500pci_write_tx_desc,
2048         .write_beacon           = rt2500pci_write_beacon,
2049         .fill_rxdone            = rt2500pci_fill_rxdone,
2050         .config_filter          = rt2500pci_config_filter,
2051         .config_intf            = rt2500pci_config_intf,
2052         .config_erp             = rt2500pci_config_erp,
2053         .config_ant             = rt2500pci_config_ant,
2054         .config                 = rt2500pci_config,
2055 };
2056
2057 static const struct data_queue_desc rt2500pci_queue_rx = {
2058         .entry_num              = 32,
2059         .data_size              = DATA_FRAME_SIZE,
2060         .desc_size              = RXD_DESC_SIZE,
2061         .priv_size              = sizeof(struct queue_entry_priv_pci),
2062 };
2063
2064 static const struct data_queue_desc rt2500pci_queue_tx = {
2065         .entry_num              = 32,
2066         .data_size              = DATA_FRAME_SIZE,
2067         .desc_size              = TXD_DESC_SIZE,
2068         .priv_size              = sizeof(struct queue_entry_priv_pci),
2069 };
2070
2071 static const struct data_queue_desc rt2500pci_queue_bcn = {
2072         .entry_num              = 1,
2073         .data_size              = MGMT_FRAME_SIZE,
2074         .desc_size              = TXD_DESC_SIZE,
2075         .priv_size              = sizeof(struct queue_entry_priv_pci),
2076 };
2077
2078 static const struct data_queue_desc rt2500pci_queue_atim = {
2079         .entry_num              = 8,
2080         .data_size              = DATA_FRAME_SIZE,
2081         .desc_size              = TXD_DESC_SIZE,
2082         .priv_size              = sizeof(struct queue_entry_priv_pci),
2083 };
2084
2085 static const struct rt2x00_ops rt2500pci_ops = {
2086         .name                   = KBUILD_MODNAME,
2087         .max_ap_intf            = 1,
2088         .eeprom_size            = EEPROM_SIZE,
2089         .rf_size                = RF_SIZE,
2090         .tx_queues              = NUM_TX_QUEUES,
2091         .extra_tx_headroom      = 0,
2092         .rx                     = &rt2500pci_queue_rx,
2093         .tx                     = &rt2500pci_queue_tx,
2094         .bcn                    = &rt2500pci_queue_bcn,
2095         .atim                   = &rt2500pci_queue_atim,
2096         .lib                    = &rt2500pci_rt2x00_ops,
2097         .hw                     = &rt2500pci_mac80211_ops,
2098 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2099         .debugfs                = &rt2500pci_rt2x00debug,
2100 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2101 };
2102
2103 /*
2104  * RT2500pci module information.
2105  */
2106 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
2107         { PCI_DEVICE(0x1814, 0x0201) },
2108         { 0, }
2109 };
2110
2111 MODULE_AUTHOR(DRV_PROJECT);
2112 MODULE_VERSION(DRV_VERSION);
2113 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
2114 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
2115 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
2116 MODULE_LICENSE("GPL");
2117
2118 static int rt2500pci_probe(struct pci_dev *pci_dev,
2119                            const struct pci_device_id *id)
2120 {
2121         return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2122 }
2123
2124 static struct pci_driver rt2500pci_driver = {
2125         .name           = KBUILD_MODNAME,
2126         .id_table       = rt2500pci_device_table,
2127         .probe          = rt2500pci_probe,
2128         .remove         = rt2x00pci_remove,
2129         .suspend        = rt2x00pci_suspend,
2130         .resume         = rt2x00pci_resume,
2131 };
2132
2133 module_pci_driver(rt2500pci_driver);