drivers/net/wireless/rtlwifi/rtl8723be/rf.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "reg.h"
  28 #include "def.h"
  29 #include "phy.h"
  30 #include "rf.h"
  31 #include "dm.h"
  32
  33 static bool _rtl8723be_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
  34
  35 void rtl8723be_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
  36 {
  37         struct rtl_priv *rtlpriv = rtl_priv(hw);
  38         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  39
  40         switch (bandwidth) {
  41         case HT_CHANNEL_WIDTH_20:
  42                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  43                                              0xfffff3ff) | BIT(10) | BIT(11));
  44                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  45                               rtlphy->rfreg_chnlval[0]);
  46                 break;
  47         case HT_CHANNEL_WIDTH_20_40:
  48                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  49                                              0xfffff3ff) | BIT(10));
  50                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  51                               rtlphy->rfreg_chnlval[0]);
  52                 break;
  53         default:
  54                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  55                          "unknown bandwidth: %#X\n", bandwidth);
  56                 break;
  57         }
  58 }
  59
  60 void rtl8723be_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
  61                                           u8 *ppowerlevel)
  62 {
  63         struct rtl_priv *rtlpriv = rtl_priv(hw);
  64         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  65         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  66         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  67         u32 tx_agc[2] = {0, 0}, tmpval;
  68         bool turbo_scanoff = false;
  69         u8 idx1, idx2;
  70         u8 *ptr;
  71         u8 direction;
  72         u32 pwrtrac_value;
  73
  74         if (rtlefuse->eeprom_regulatory != 0)
  75                 turbo_scanoff = true;
  76
  77         if (mac->act_scanning) {
  78                 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
  79                 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
  80
  81                 if (turbo_scanoff) {
  82                         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  83                                 tx_agc[idx1] = ppowerlevel[idx1] |
  84                                                (ppowerlevel[idx1] << 8) |
  85                                                (ppowerlevel[idx1] << 16) |
  86                                                (ppowerlevel[idx1] << 24);
  87                         }
  88                 }
  89         } else {
  90                 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  91                         tx_agc[idx1] = ppowerlevel[idx1] |
  92                                        (ppowerlevel[idx1] << 8) |
  93                                        (ppowerlevel[idx1] << 16) |
  94                                        (ppowerlevel[idx1] << 24);
  95                 }
  96
  97                 if (rtlefuse->eeprom_regulatory == 0) {
  98                         tmpval =
  99                             (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
 100                             (rtlphy->mcs_txpwrlevel_origoffset[0][7] << 8);
 101                         tx_agc[RF90_PATH_A] += tmpval;
 102
 103                         tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
 104                                  (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
 105                                   24);
 106                         tx_agc[RF90_PATH_B] += tmpval;
 107                 }
 108         }
 109
 110         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
 111                 ptr = (u8 *)(&(tx_agc[idx1]));
 112                 for (idx2 = 0; idx2 < 4; idx2++) {
 113                         if (*ptr > RF6052_MAX_TX_PWR)
 114                                 *ptr = RF6052_MAX_TX_PWR;
 115                         ptr++;
 116                 }
 117         }
 118         rtl8723be_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
 119         if (direction == 1) {
 120                 tx_agc[0] += pwrtrac_value;
 121                 tx_agc[1] += pwrtrac_value;
 122         } else if (direction == 2) {
 123                 tx_agc[0] -= pwrtrac_value;
 124                 tx_agc[1] -= pwrtrac_value;
 125         }
 126         tmpval = tx_agc[RF90_PATH_A] & 0xff;
 127         rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
 128
 129         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 130                 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 131                  RTXAGC_A_CCK1_MCS32);
 132
 133         tmpval = tx_agc[RF90_PATH_A] >> 8;
 134
 135         /*tmpval = tmpval & 0xff00ffff;*/
 136
 137         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 138
 139         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 140                 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 141                  RTXAGC_B_CCK11_A_CCK2_11);
 142
 143         tmpval = tx_agc[RF90_PATH_B] >> 24;
 144         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
 145
 146         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 147                 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 148                  RTXAGC_B_CCK11_A_CCK2_11);
 149
 150         tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
 151         rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
 152
 153         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 154                 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 155                  RTXAGC_B_CCK1_55_MCS32);
 156 }
 157
 158 static void rtl8723be_phy_get_power_base(struct ieee80211_hw *hw,
 159                                          u8 *ppowerlevel_ofdm,
 160                                          u8 *ppowerlevel_bw20,
 161                                          u8 *ppowerlevel_bw40,
 162                                          u8 channel, u32 *ofdmbase,
 163                                          u32 *mcsbase)
 164 {
 165         struct rtl_priv *rtlpriv = rtl_priv(hw);
 166         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 167         u32 powerbase0, powerbase1;
 168         u8 i, powerlevel[2];
 169
 170         for (i = 0; i < 2; i++) {
 171                 powerbase0 = ppowerlevel_ofdm[i];
 172
 173                 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
 174                     (powerbase0 << 8) | powerbase0;
 175                 *(ofdmbase + i) = powerbase0;
 176                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 177                         " [OFDM power base index rf(%c) = 0x%x]\n",
 178                          ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
 179         }
 180
 181         for (i = 0; i < 2; i++) {
 182                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
 183                         powerlevel[i] = ppowerlevel_bw20[i];
 184                 else
 185                         powerlevel[i] = ppowerlevel_bw40[i];
 186
 187                 powerbase1 = powerlevel[i];
 188                 powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
 189                              (powerbase1 << 8) | powerbase1;
 190
 191                 *(mcsbase + i) = powerbase1;
 192
 193                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 194                         " [MCS power base index rf(%c) = 0x%x]\n",
 195                          ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
 196         }
 197 }
 198
 199 static void _rtl8723be_get_txpower_writeval_by_regulatory(
 200                                                         struct ieee80211_hw *hw,
 201                                                         u8 channel, u8 index,
 202                                                         u32 *powerbase0,
 203                                                         u32 *powerbase1,
 204                                                         u32 *p_outwriteval)
 205 {
 206         struct rtl_priv *rtlpriv = rtl_priv(hw);
 207         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 208         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 209         u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
 210         u32 writeval, customer_limit, rf;
 211
 212         for (rf = 0; rf < 2; rf++) {
 213                 switch (rtlefuse->eeprom_regulatory) {
 214                 case 0:
 215                         chnlgroup = 0;
 216
 217                         writeval =
 218                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
 219                                                                 (rf ? 8 : 0)]
 220                             + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 221
 222                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 223                                 "RTK better performance, writeval(%c) = 0x%x\n",
 224                                 ((rf == 0) ? 'A' : 'B'), writeval);
 225                         break;
 226                 case 1:
 227                         if (rtlphy->pwrgroup_cnt == 1) {
 228                                 chnlgroup = 0;
 229                         } else {
 230                                 if (channel < 3)
 231                                         chnlgroup = 0;
 232                                 else if (channel < 6)
 233                                         chnlgroup = 1;
 234                                 else if (channel < 9)
 235                                         chnlgroup = 2;
 236                                 else if (channel < 12)
 237                                         chnlgroup = 3;
 238                                 else if (channel < 14)
 239                                         chnlgroup = 4;
 240                                 else if (channel == 14)
 241                                         chnlgroup = 5;
 242                         }
 243
 244                         writeval =
 245                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 246                             [index + (rf ? 8 : 0)] + ((index < 2) ?
 247                                                       powerbase0[rf] :
 248                                                       powerbase1[rf]);
 249
 250                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 251                                 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
 252                                 ((rf == 0) ? 'A' : 'B'), writeval);
 253
 254                         break;
 255                 case 2:
 256                         writeval =
 257                             ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 258
 259                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 260                                 "Better regulatory, writeval(%c) = 0x%x\n",
 261                                 ((rf == 0) ? 'A' : 'B'), writeval);
 262                         break;
 263                 case 3:
 264                         chnlgroup = 0;
 265
 266                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
 267                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 268                                         "customer's limit, 40MHz rf(%c) = 0x%x\n",
 269                                         ((rf == 0) ? 'A' : 'B'),
 270                                         rtlefuse->pwrgroup_ht40
 271                                         [rf][channel - 1]);
 272                         } else {
 273                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 274                                         "customer's limit, 20MHz rf(%c) = 0x%x\n",
 275                                         ((rf == 0) ? 'A' : 'B'),
 276                                         rtlefuse->pwrgroup_ht20
 277                                         [rf][channel - 1]);
 278                         }
 279
 280                         if (index < 2)
 281                                 pwr_diff =
 282                                     rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
 283                         else if (rtlphy->current_chan_bw ==
 284                                  HT_CHANNEL_WIDTH_20)
 285                                 pwr_diff =
 286                                     rtlefuse->txpwr_ht20diff[rf][channel-1];
 287
 288                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
 289                                 customer_pwr_diff =
 290                                         rtlefuse->pwrgroup_ht40[rf][channel-1];
 291                         else
 292                                 customer_pwr_diff =
 293                                         rtlefuse->pwrgroup_ht20[rf][channel-1];
 294
 295                         if (pwr_diff > customer_pwr_diff)
 296                                 pwr_diff = 0;
 297                         else
 298                                 pwr_diff = customer_pwr_diff - pwr_diff;
 299
 300                         for (i = 0; i < 4; i++) {
 301                                 pwr_diff_limit[i] =
 302                                     (u8)((rtlphy->mcs_txpwrlevel_origoffset
 303                                            [chnlgroup][index + (rf ? 8 : 0)] &
 304                                               (0x7f << (i * 8))) >> (i * 8));
 305
 306                                         if (pwr_diff_limit[i] > pwr_diff)
 307                                                 pwr_diff_limit[i] = pwr_diff;
 308                         }
 309
 310                         customer_limit = (pwr_diff_limit[3] << 24) |
 311                                          (pwr_diff_limit[2] << 16) |
 312                                          (pwr_diff_limit[1] << 8) |
 313                                          (pwr_diff_limit[0]);
 314
 315                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 316                                 "Customer's limit rf(%c) = 0x%x\n",
 317                                  ((rf == 0) ? 'A' : 'B'), customer_limit);
 318
 319                         writeval = customer_limit + ((index < 2) ?
 320                                                       powerbase0[rf] :
 321                                                       powerbase1[rf]);
 322
 323                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 324                                 "Customer, writeval rf(%c)= 0x%x\n",
 325                                  ((rf == 0) ? 'A' : 'B'), writeval);
 326                         break;
 327                 default:
 328                         chnlgroup = 0;
 329                         writeval =
 330                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 331                             [index + (rf ? 8 : 0)]
 332                             + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 333
 334                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 335                                 "RTK better performance, writeval rf(%c) = 0x%x\n",
 336                                 ((rf == 0) ? 'A' : 'B'), writeval);
 337                         break;
 338                 }
 339
 340                 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
 341                         writeval = writeval - 0x06060606;
 342                 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 343                          TXHIGHPWRLEVEL_BT2)
 344                         writeval = writeval - 0x0c0c0c0c;
 345                 *(p_outwriteval + rf) = writeval;
 346         }
 347 }
 348
 349 static void _rtl8723be_write_ofdm_power_reg(struct ieee80211_hw *hw,
 350                                          u8 index, u32 *pvalue)
 351 {
 352         struct rtl_priv *rtlpriv = rtl_priv(hw);
 353         u16 regoffset_a[6] = {
 354                 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
 355                 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
 356                 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
 357         };
 358         u16 regoffset_b[6] = {
 359                 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
 360                 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
 361                 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
 362         };
 363         u8 i, rf, pwr_val[4];
 364         u32 writeval;
 365         u16 regoffset;
 366
 367         for (rf = 0; rf < 2; rf++) {
 368                 writeval = pvalue[rf];
 369                 for (i = 0; i < 4; i++) {
 370                         pwr_val[i] = (u8)((writeval & (0x7f <<
 371                                                         (i * 8))) >> (i * 8));
 372
 373                         if (pwr_val[i] > RF6052_MAX_TX_PWR)
 374                                 pwr_val[i] = RF6052_MAX_TX_PWR;
 375                 }
 376                 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
 377                     (pwr_val[1] << 8) | pwr_val[0];
 378
 379                 if (rf == 0)
 380                         regoffset = regoffset_a[index];
 381                 else
 382                         regoffset = regoffset_b[index];
 383                 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
 384
 385                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 386                         "Set 0x%x = %08x\n", regoffset, writeval);
 387         }
 388 }
 389
 390 void rtl8723be_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
 391                                            u8 *ppowerlevel_ofdm,
 392                                            u8 *ppowerlevel_bw20,
 393                                            u8 *ppowerlevel_bw40, u8 channel)
 394 {
 395         u32 writeval[2], powerbase0[2], powerbase1[2];
 396         u8 index;
 397         u8 direction;
 398         u32 pwrtrac_value;
 399
 400         rtl8723be_phy_get_power_base(hw, ppowerlevel_ofdm, ppowerlevel_bw20,
 401                                      ppowerlevel_bw40, channel,
 402                                      &powerbase0[0], &powerbase1[0]);
 403
 404         rtl8723be_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
 405
 406         for (index = 0; index < 6; index++) {
 407                 _rtl8723be_get_txpower_writeval_by_regulatory(hw,
 408                                                               channel, index,
 409                                                               &powerbase0[0],
 410                                                               &powerbase1[0],
 411                                                               &writeval[0]);
 412                 if (direction == 1) {
 413                         writeval[0] += pwrtrac_value;
 414                         writeval[1] += pwrtrac_value;
 415                 } else if (direction == 2) {
 416                         writeval[0] -= pwrtrac_value;
 417                         writeval[1] -= pwrtrac_value;
 418                 }
 419                 _rtl8723be_write_ofdm_power_reg(hw, index, &writeval[0]);
 420         }
 421 }
 422
 423 bool rtl8723be_phy_rf6052_config(struct ieee80211_hw *hw)
 424 {
 425         struct rtl_priv *rtlpriv = rtl_priv(hw);
 426         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 427
 428         if (rtlphy->rf_type == RF_1T1R)
 429                 rtlphy->num_total_rfpath = 1;
 430         else
 431                 rtlphy->num_total_rfpath = 2;
 432
 433         return _rtl8723be_phy_rf6052_config_parafile(hw);
 434
 435 }
 436
 437 static bool _rtl8723be_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
 438 {
 439         struct rtl_priv *rtlpriv = rtl_priv(hw);
 440         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 441         u32 u4_regvalue = 0;
 442         u8 rfpath;
 443         bool rtstatus = true;
 444         struct bb_reg_def *pphyreg;
 445
 446         for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
 447                 pphyreg = &rtlphy->phyreg_def[rfpath];
 448
 449                 switch (rfpath) {
 450                 case RF90_PATH_A:
 451                 case RF90_PATH_C:
 452                         u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
 453                                                     BRFSI_RFENV);
 454                         break;
 455                 case RF90_PATH_B:
 456                 case RF90_PATH_D:
 457                         u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
 458                                                     BRFSI_RFENV << 16);
 459                         break;
 460                 }
 461
 462                 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
 463                 udelay(1);
 464
 465                 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
 466                 udelay(1);
 467
 468                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
 469                               B3WIREADDREAALENGTH, 0x0);
 470                 udelay(1);
 471
 472                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
 473                 udelay(1);
 474
 475                 switch (rfpath) {
 476                 case RF90_PATH_A:
 477                         rtstatus = rtl8723be_phy_config_rf_with_headerfile(hw,
 478                                                       (enum radio_path)rfpath);
 479                         break;
 480                 case RF90_PATH_B:
 481                         rtstatus = rtl8723be_phy_config_rf_with_headerfile(hw,
 482                                                       (enum radio_path)rfpath);
 483                         break;
 484                 case RF90_PATH_C:
 485                         break;
 486                 case RF90_PATH_D:
 487                         break;
 488                 }
 489
 490                 switch (rfpath) {
 491                 case RF90_PATH_A:
 492                 case RF90_PATH_C:
 493                         rtl_set_bbreg(hw, pphyreg->rfintfs,
 494                                       BRFSI_RFENV, u4_regvalue);
 495                         break;
 496                 case RF90_PATH_B:
 497                 case RF90_PATH_D:
 498                         rtl_set_bbreg(hw, pphyreg->rfintfs,
 499                                       BRFSI_RFENV << 16, u4_regvalue);
 500                         break;
 501                 }
 502
 503                 if (!rtstatus) {
 504                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 505                                  "Radio[%d] Fail!!", rfpath);
 506                         return false;
 507                 }
 508         }
 509
 510         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
 511         return rtstatus;
 512 }