3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/irqdomain.h>
26 static int pci_msi_enable = 1;
27 int pci_msi_ignore_mask;
29 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
31 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
32 static struct irq_domain *pci_msi_default_domain;
33 static DEFINE_MUTEX(pci_msi_domain_lock);
35 struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
37 return pci_msi_default_domain;
40 static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
42 struct irq_domain *domain;
44 domain = dev_get_msi_domain(&dev->dev);
48 return arch_get_pci_msi_domain(dev);
51 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
53 struct irq_domain *domain;
55 domain = pci_msi_get_domain(dev);
57 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
59 return arch_setup_msi_irqs(dev, nvec, type);
62 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
64 struct irq_domain *domain;
66 domain = pci_msi_get_domain(dev);
68 pci_msi_domain_free_irqs(domain, dev);
70 arch_teardown_msi_irqs(dev);
73 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
74 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
79 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
81 struct msi_controller *chip = dev->bus->msi;
84 if (!chip || !chip->setup_irq)
87 err = chip->setup_irq(chip, dev, desc);
91 irq_set_chip_data(desc->irq, chip);
96 void __weak arch_teardown_msi_irq(unsigned int irq)
98 struct msi_controller *chip = irq_get_chip_data(irq);
100 if (!chip || !chip->teardown_irq)
103 chip->teardown_irq(chip, irq);
106 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
108 struct msi_controller *chip = dev->bus->msi;
109 struct msi_desc *entry;
112 if (chip && chip->setup_irqs)
113 return chip->setup_irqs(chip, dev, nvec, type);
115 * If an architecture wants to support multiple MSI, it needs to
116 * override arch_setup_msi_irqs()
118 if (type == PCI_CAP_ID_MSI && nvec > 1)
121 for_each_pci_msi_entry(entry, dev) {
122 ret = arch_setup_msi_irq(dev, entry);
133 * We have a default implementation available as a separate non-weak
134 * function, as it is used by the Xen x86 PCI code
136 void default_teardown_msi_irqs(struct pci_dev *dev)
139 struct msi_desc *entry;
141 for_each_pci_msi_entry(entry, dev)
143 for (i = 0; i < entry->nvec_used; i++)
144 arch_teardown_msi_irq(entry->irq + i);
147 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
149 return default_teardown_msi_irqs(dev);
152 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
154 struct msi_desc *entry;
157 if (dev->msix_enabled) {
158 for_each_pci_msi_entry(entry, dev) {
159 if (irq == entry->irq)
162 } else if (dev->msi_enabled) {
163 entry = irq_get_msi_desc(irq);
167 __pci_write_msi_msg(entry, &entry->msg);
170 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
172 return default_restore_msi_irqs(dev);
175 static inline __attribute_const__ u32 msi_mask(unsigned x)
177 /* Don't shift by >= width of type */
180 return (1 << (1 << x)) - 1;
184 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
185 * mask all MSI interrupts by clearing the MSI enable bit does not work
186 * reliably as devices without an INTx disable bit will then generate a
187 * level IRQ which will never be cleared.
189 u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
191 u32 mask_bits = desc->masked;
193 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
198 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
204 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
206 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
210 * This internal function does not flush PCI writes to the device.
211 * All users must ensure that they read from the device before either
212 * assuming that the device state is up to date, or returning out of this
213 * file. This saves a few milliseconds when initialising devices with lots
214 * of MSI-X interrupts.
216 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
218 u32 mask_bits = desc->masked;
219 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
220 PCI_MSIX_ENTRY_VECTOR_CTRL;
222 if (pci_msi_ignore_mask)
225 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
227 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
228 writel(mask_bits, desc->mask_base + offset);
233 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
235 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
238 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
240 struct msi_desc *desc = irq_data_get_msi_desc(data);
242 if (desc->msi_attrib.is_msix) {
243 msix_mask_irq(desc, flag);
244 readl(desc->mask_base); /* Flush write to device */
246 unsigned offset = data->irq - desc->irq;
247 msi_mask_irq(desc, 1 << offset, flag << offset);
252 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
253 * @data: pointer to irqdata associated to that interrupt
255 void pci_msi_mask_irq(struct irq_data *data)
257 msi_set_mask_bit(data, 1);
261 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
262 * @data: pointer to irqdata associated to that interrupt
264 void pci_msi_unmask_irq(struct irq_data *data)
266 msi_set_mask_bit(data, 0);
269 void default_restore_msi_irqs(struct pci_dev *dev)
271 struct msi_desc *entry;
273 for_each_pci_msi_entry(entry, dev)
274 default_restore_msi_irq(dev, entry->irq);
277 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
279 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
281 BUG_ON(dev->current_state != PCI_D0);
283 if (entry->msi_attrib.is_msix) {
284 void __iomem *base = entry->mask_base +
285 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
287 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
288 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
289 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
291 int pos = dev->msi_cap;
294 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
296 if (entry->msi_attrib.is_64) {
297 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
299 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
302 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
308 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
310 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
312 if (dev->current_state != PCI_D0) {
313 /* Don't touch the hardware now */
314 } else if (entry->msi_attrib.is_msix) {
316 base = entry->mask_base +
317 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
319 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
320 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
321 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
323 int pos = dev->msi_cap;
326 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
327 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
328 msgctl |= entry->msi_attrib.multiple << 4;
329 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
331 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
333 if (entry->msi_attrib.is_64) {
334 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
336 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
339 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
346 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
348 struct msi_desc *entry = irq_get_msi_desc(irq);
350 __pci_write_msi_msg(entry, msg);
352 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
354 static void free_msi_irqs(struct pci_dev *dev)
356 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
357 struct msi_desc *entry, *tmp;
358 struct attribute **msi_attrs;
359 struct device_attribute *dev_attr;
362 for_each_pci_msi_entry(entry, dev)
364 for (i = 0; i < entry->nvec_used; i++)
365 BUG_ON(irq_has_action(entry->irq + i));
367 pci_msi_teardown_msi_irqs(dev);
369 list_for_each_entry_safe(entry, tmp, msi_list, list) {
370 if (entry->msi_attrib.is_msix) {
371 if (list_is_last(&entry->list, msi_list))
372 iounmap(entry->mask_base);
375 list_del(&entry->list);
379 if (dev->msi_irq_groups) {
380 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
381 msi_attrs = dev->msi_irq_groups[0]->attrs;
382 while (msi_attrs[count]) {
383 dev_attr = container_of(msi_attrs[count],
384 struct device_attribute, attr);
385 kfree(dev_attr->attr.name);
390 kfree(dev->msi_irq_groups[0]);
391 kfree(dev->msi_irq_groups);
392 dev->msi_irq_groups = NULL;
396 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
398 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
399 pci_intx(dev, enable);
402 static void __pci_restore_msi_state(struct pci_dev *dev)
405 struct msi_desc *entry;
407 if (!dev->msi_enabled)
410 entry = irq_get_msi_desc(dev->irq);
412 pci_intx_for_msi(dev, 0);
413 pci_msi_set_enable(dev, 0);
414 arch_restore_msi_irqs(dev);
416 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
417 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
419 control &= ~PCI_MSI_FLAGS_QSIZE;
420 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
421 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
424 static void __pci_restore_msix_state(struct pci_dev *dev)
426 struct msi_desc *entry;
428 if (!dev->msix_enabled)
430 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
432 /* route the table */
433 pci_intx_for_msi(dev, 0);
434 pci_msix_clear_and_set_ctrl(dev, 0,
435 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
437 arch_restore_msi_irqs(dev);
438 for_each_pci_msi_entry(entry, dev)
439 msix_mask_irq(entry, entry->masked);
441 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
444 void pci_restore_msi_state(struct pci_dev *dev)
446 __pci_restore_msi_state(dev);
447 __pci_restore_msix_state(dev);
449 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
451 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
454 struct msi_desc *entry;
458 retval = kstrtoul(attr->attr.name, 10, &irq);
462 entry = irq_get_msi_desc(irq);
464 return sprintf(buf, "%s\n",
465 entry->msi_attrib.is_msix ? "msix" : "msi");
470 static int populate_msi_sysfs(struct pci_dev *pdev)
472 struct attribute **msi_attrs;
473 struct attribute *msi_attr;
474 struct device_attribute *msi_dev_attr;
475 struct attribute_group *msi_irq_group;
476 const struct attribute_group **msi_irq_groups;
477 struct msi_desc *entry;
482 /* Determine how many msi entries we have */
483 for_each_pci_msi_entry(entry, pdev)
488 /* Dynamically create the MSI attributes for the PCI device */
489 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
492 for_each_pci_msi_entry(entry, pdev) {
493 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
496 msi_attrs[count] = &msi_dev_attr->attr;
498 sysfs_attr_init(&msi_dev_attr->attr);
499 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
501 if (!msi_dev_attr->attr.name)
503 msi_dev_attr->attr.mode = S_IRUGO;
504 msi_dev_attr->show = msi_mode_show;
508 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
511 msi_irq_group->name = "msi_irqs";
512 msi_irq_group->attrs = msi_attrs;
514 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
516 goto error_irq_group;
517 msi_irq_groups[0] = msi_irq_group;
519 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
521 goto error_irq_groups;
522 pdev->msi_irq_groups = msi_irq_groups;
527 kfree(msi_irq_groups);
529 kfree(msi_irq_group);
532 msi_attr = msi_attrs[count];
534 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
535 kfree(msi_attr->name);
538 msi_attr = msi_attrs[count];
544 static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
547 struct msi_desc *entry;
549 /* MSI Entry Initialization */
550 entry = alloc_msi_entry(&dev->dev);
554 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
556 entry->msi_attrib.is_msix = 0;
557 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
558 entry->msi_attrib.entry_nr = 0;
559 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
560 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
561 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
562 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
563 entry->nvec_used = nvec;
565 if (control & PCI_MSI_FLAGS_64BIT)
566 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
568 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
570 /* Save the initial mask status */
571 if (entry->msi_attrib.maskbit)
572 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
577 static int msi_verify_entries(struct pci_dev *dev)
579 struct msi_desc *entry;
581 for_each_pci_msi_entry(entry, dev) {
582 if (!dev->no_64bit_msi || !entry->msg.address_hi)
584 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
585 " tried to assign one above 4G\n");
592 * msi_capability_init - configure device's MSI capability structure
593 * @dev: pointer to the pci_dev data structure of MSI device function
594 * @nvec: number of interrupts to allocate
596 * Setup the MSI capability structure of the device with the requested
597 * number of interrupts. A return value of zero indicates the successful
598 * setup of an entry with the new MSI irq. A negative return value indicates
599 * an error, and a positive return value indicates the number of interrupts
600 * which could have been allocated.
602 static int msi_capability_init(struct pci_dev *dev, int nvec)
604 struct msi_desc *entry;
608 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
610 entry = msi_setup_entry(dev, nvec);
614 /* All MSIs are unmasked by default, Mask them all */
615 mask = msi_mask(entry->msi_attrib.multi_cap);
616 msi_mask_irq(entry, mask, mask);
618 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
620 /* Configure MSI capability structure */
621 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
623 msi_mask_irq(entry, mask, ~mask);
628 ret = msi_verify_entries(dev);
630 msi_mask_irq(entry, mask, ~mask);
635 ret = populate_msi_sysfs(dev);
637 msi_mask_irq(entry, mask, ~mask);
642 /* Set MSI enabled bits */
643 pci_intx_for_msi(dev, 0);
644 pci_msi_set_enable(dev, 1);
645 dev->msi_enabled = 1;
647 pcibios_free_irq(dev);
648 dev->irq = entry->irq;
652 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
654 resource_size_t phys_addr;
659 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
661 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
662 flags = pci_resource_flags(dev, bir);
663 if (!flags || (flags & IORESOURCE_UNSET))
666 table_offset &= PCI_MSIX_TABLE_OFFSET;
667 phys_addr = pci_resource_start(dev, bir) + table_offset;
669 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
672 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
673 struct msix_entry *entries, int nvec)
675 struct msi_desc *entry;
678 for (i = 0; i < nvec; i++) {
679 entry = alloc_msi_entry(&dev->dev);
685 /* No enough memory. Don't try again */
689 entry->msi_attrib.is_msix = 1;
690 entry->msi_attrib.is_64 = 1;
691 entry->msi_attrib.entry_nr = entries[i].entry;
692 entry->msi_attrib.default_irq = dev->irq;
693 entry->mask_base = base;
694 entry->nvec_used = 1;
696 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
702 static void msix_program_entries(struct pci_dev *dev,
703 struct msix_entry *entries)
705 struct msi_desc *entry;
708 for_each_pci_msi_entry(entry, dev) {
709 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
710 PCI_MSIX_ENTRY_VECTOR_CTRL;
712 entries[i].vector = entry->irq;
713 entry->masked = readl(entry->mask_base + offset);
714 msix_mask_irq(entry, 1);
720 * msix_capability_init - configure device's MSI-X capability
721 * @dev: pointer to the pci_dev data structure of MSI-X device function
722 * @entries: pointer to an array of struct msix_entry entries
723 * @nvec: number of @entries
725 * Setup the MSI-X capability structure of device function with a
726 * single MSI-X irq. A return of zero indicates the successful setup of
727 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
729 static int msix_capability_init(struct pci_dev *dev,
730 struct msix_entry *entries, int nvec)
736 /* Ensure MSI-X is disabled while it is set up */
737 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
739 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
740 /* Request & Map MSI-X table region */
741 base = msix_map_region(dev, msix_table_size(control));
745 ret = msix_setup_entries(dev, base, entries, nvec);
749 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
753 /* Check if all MSI entries honor device restrictions */
754 ret = msi_verify_entries(dev);
759 * Some devices require MSI-X to be enabled before we can touch the
760 * MSI-X registers. We need to mask all the vectors to prevent
761 * interrupts coming in before they're fully set up.
763 pci_msix_clear_and_set_ctrl(dev, 0,
764 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
766 msix_program_entries(dev, entries);
768 ret = populate_msi_sysfs(dev);
772 /* Set MSI-X enabled bits and unmask the function */
773 pci_intx_for_msi(dev, 0);
774 dev->msix_enabled = 1;
775 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
777 pcibios_free_irq(dev);
783 * If we had some success, report the number of irqs
784 * we succeeded in setting up.
786 struct msi_desc *entry;
789 for_each_pci_msi_entry(entry, dev) {
804 * pci_msi_supported - check whether MSI may be enabled on a device
805 * @dev: pointer to the pci_dev data structure of MSI device function
806 * @nvec: how many MSIs have been requested ?
808 * Look at global flags, the device itself, and its parent buses
809 * to determine if MSI/-X are supported for the device. If MSI/-X is
810 * supported return 1, else return 0.
812 static int pci_msi_supported(struct pci_dev *dev, int nvec)
816 /* MSI must be globally enabled and supported by the device */
820 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
824 * You can't ask to have 0 or less MSIs configured.
826 * b) the list manipulation code assumes nvec >= 1.
832 * Any bridge which does NOT route MSI transactions from its
833 * secondary bus to its primary bus must set NO_MSI flag on
834 * the secondary pci_bus.
835 * We expect only arch-specific PCI host bus controller driver
836 * or quirks for specific PCI bridges to be setting NO_MSI.
838 for (bus = dev->bus; bus; bus = bus->parent)
839 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
846 * pci_msi_vec_count - Return the number of MSI vectors a device can send
847 * @dev: device to report about
849 * This function returns the number of MSI vectors a device requested via
850 * Multiple Message Capable register. It returns a negative errno if the
851 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
852 * and returns a power of two, up to a maximum of 2^5 (32), according to the
855 int pci_msi_vec_count(struct pci_dev *dev)
863 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
864 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
868 EXPORT_SYMBOL(pci_msi_vec_count);
870 void pci_msi_shutdown(struct pci_dev *dev)
872 struct msi_desc *desc;
875 if (!pci_msi_enable || !dev || !dev->msi_enabled)
878 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
879 desc = first_pci_msi_entry(dev);
881 pci_msi_set_enable(dev, 0);
882 pci_intx_for_msi(dev, 1);
883 dev->msi_enabled = 0;
885 /* Return the device with MSI unmasked as initial states */
886 mask = msi_mask(desc->msi_attrib.multi_cap);
887 /* Keep cached state to be restored */
888 __pci_msi_desc_mask_irq(desc, mask, ~mask);
890 /* Restore dev->irq to its default pin-assertion irq */
891 dev->irq = desc->msi_attrib.default_irq;
892 pcibios_alloc_irq(dev);
895 void pci_disable_msi(struct pci_dev *dev)
897 if (!pci_msi_enable || !dev || !dev->msi_enabled)
900 pci_msi_shutdown(dev);
903 EXPORT_SYMBOL(pci_disable_msi);
906 * pci_msix_vec_count - return the number of device's MSI-X table entries
907 * @dev: pointer to the pci_dev data structure of MSI-X device function
908 * This function returns the number of device's MSI-X table entries and
909 * therefore the number of MSI-X vectors device is capable of sending.
910 * It returns a negative errno if the device is not capable of sending MSI-X
913 int pci_msix_vec_count(struct pci_dev *dev)
920 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
921 return msix_table_size(control);
923 EXPORT_SYMBOL(pci_msix_vec_count);
926 * pci_enable_msix - configure device's MSI-X capability structure
927 * @dev: pointer to the pci_dev data structure of MSI-X device function
928 * @entries: pointer to an array of MSI-X entries
929 * @nvec: number of MSI-X irqs requested for allocation by device driver
931 * Setup the MSI-X capability structure of device function with the number
932 * of requested irqs upon its software driver call to request for
933 * MSI-X mode enabled on its hardware device function. A return of zero
934 * indicates the successful configuration of MSI-X capability structure
935 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
936 * Or a return of > 0 indicates that driver request is exceeding the number
937 * of irqs or MSI-X vectors available. Driver should use the returned value to
938 * re-send its request.
940 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
945 if (!pci_msi_supported(dev, nvec))
951 nr_entries = pci_msix_vec_count(dev);
954 if (nvec > nr_entries)
957 /* Check for any invalid entries */
958 for (i = 0; i < nvec; i++) {
959 if (entries[i].entry >= nr_entries)
960 return -EINVAL; /* invalid entry */
961 for (j = i + 1; j < nvec; j++) {
962 if (entries[i].entry == entries[j].entry)
963 return -EINVAL; /* duplicate entry */
966 WARN_ON(!!dev->msix_enabled);
968 /* Check whether driver already requested for MSI irq */
969 if (dev->msi_enabled) {
970 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
973 return msix_capability_init(dev, entries, nvec);
975 EXPORT_SYMBOL(pci_enable_msix);
977 void pci_msix_shutdown(struct pci_dev *dev)
979 struct msi_desc *entry;
981 if (!pci_msi_enable || !dev || !dev->msix_enabled)
984 /* Return the device with MSI-X masked as initial states */
985 for_each_pci_msi_entry(entry, dev) {
986 /* Keep cached states to be restored */
987 __pci_msix_desc_mask_irq(entry, 1);
990 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
991 pci_intx_for_msi(dev, 1);
992 dev->msix_enabled = 0;
993 pcibios_alloc_irq(dev);
996 void pci_disable_msix(struct pci_dev *dev)
998 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1001 pci_msix_shutdown(dev);
1004 EXPORT_SYMBOL(pci_disable_msix);
1006 void pci_no_msi(void)
1012 * pci_msi_enabled - is MSI enabled?
1014 * Returns true if MSI has not been disabled by the command-line option
1017 int pci_msi_enabled(void)
1019 return pci_msi_enable;
1021 EXPORT_SYMBOL(pci_msi_enabled);
1023 void pci_msi_init_pci_dev(struct pci_dev *dev)
1028 * pci_enable_msi_range - configure device's MSI capability structure
1029 * @dev: device to configure
1030 * @minvec: minimal number of interrupts to configure
1031 * @maxvec: maximum number of interrupts to configure
1033 * This function tries to allocate a maximum possible number of interrupts in a
1034 * range between @minvec and @maxvec. It returns a negative errno if an error
1035 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1036 * and updates the @dev's irq member to the lowest new interrupt number;
1037 * the other interrupt numbers allocated to this device are consecutive.
1039 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1044 if (!pci_msi_supported(dev, minvec))
1047 WARN_ON(!!dev->msi_enabled);
1049 /* Check whether driver already requested MSI-X irqs */
1050 if (dev->msix_enabled) {
1052 "can't enable MSI (MSI-X already enabled)\n");
1056 if (maxvec < minvec)
1059 nvec = pci_msi_vec_count(dev);
1062 else if (nvec < minvec)
1064 else if (nvec > maxvec)
1068 rc = msi_capability_init(dev, nvec);
1071 } else if (rc > 0) {
1080 EXPORT_SYMBOL(pci_enable_msi_range);
1083 * pci_enable_msix_range - configure device's MSI-X capability structure
1084 * @dev: pointer to the pci_dev data structure of MSI-X device function
1085 * @entries: pointer to an array of MSI-X entries
1086 * @minvec: minimum number of MSI-X irqs requested
1087 * @maxvec: maximum number of MSI-X irqs requested
1089 * Setup the MSI-X capability structure of device function with a maximum
1090 * possible number of interrupts in the range between @minvec and @maxvec
1091 * upon its software driver call to request for MSI-X mode enabled on its
1092 * hardware device function. It returns a negative errno if an error occurs.
1093 * If it succeeds, it returns the actual number of interrupts allocated and
1094 * indicates the successful configuration of MSI-X capability structure
1095 * with new allocated MSI-X interrupts.
1097 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1098 int minvec, int maxvec)
1103 if (maxvec < minvec)
1107 rc = pci_enable_msix(dev, entries, nvec);
1110 } else if (rc > 0) {
1119 EXPORT_SYMBOL(pci_enable_msix_range);
1121 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1123 return to_pci_dev(desc->dev);
1126 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1128 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1130 return dev->bus->sysdata;
1132 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1134 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1136 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1137 * @irq_data: Pointer to interrupt data of the MSI interrupt
1138 * @msg: Pointer to the message
1140 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1142 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1145 * For MSI-X desc->irq is always equal to irq_data->irq. For
1146 * MSI only the first interrupt of MULTI MSI passes the test.
1148 if (desc->irq == irq_data->irq)
1149 __pci_write_msi_msg(desc, msg);
1153 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1154 * @dev: Pointer to the PCI device
1155 * @desc: Pointer to the msi descriptor
1157 * The ID number is only used within the irqdomain.
1159 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1160 struct msi_desc *desc)
1162 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1163 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1164 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1167 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1169 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1173 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1174 * @domain: The interrupt domain to check
1175 * @info: The domain info for verification
1176 * @dev: The device to check
1179 * 0 if the functionality is supported
1180 * 1 if Multi MSI is requested, but the domain does not support it
1181 * -ENOTSUPP otherwise
1183 int pci_msi_domain_check_cap(struct irq_domain *domain,
1184 struct msi_domain_info *info, struct device *dev)
1186 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1188 /* Special handling to support pci_enable_msi_range() */
1189 if (pci_msi_desc_is_multi_msi(desc) &&
1190 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1192 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1198 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1199 struct msi_desc *desc, int error)
1201 /* Special handling to support pci_enable_msi_range() */
1202 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1208 #ifdef GENERIC_MSI_DOMAIN_OPS
1209 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1210 struct msi_desc *desc)
1213 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1217 #define pci_msi_domain_set_desc NULL
1220 static struct msi_domain_ops pci_msi_domain_ops_default = {
1221 .set_desc = pci_msi_domain_set_desc,
1222 .msi_check = pci_msi_domain_check_cap,
1223 .handle_error = pci_msi_domain_handle_error,
1226 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1228 struct msi_domain_ops *ops = info->ops;
1231 info->ops = &pci_msi_domain_ops_default;
1233 if (ops->set_desc == NULL)
1234 ops->set_desc = pci_msi_domain_set_desc;
1235 if (ops->msi_check == NULL)
1236 ops->msi_check = pci_msi_domain_check_cap;
1237 if (ops->handle_error == NULL)
1238 ops->handle_error = pci_msi_domain_handle_error;
1242 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1244 struct irq_chip *chip = info->chip;
1247 if (!chip->irq_write_msi_msg)
1248 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1252 * pci_msi_create_irq_domain - Creat a MSI interrupt domain
1253 * @node: Optional device-tree node of the interrupt controller
1254 * @info: MSI domain info
1255 * @parent: Parent irq domain
1257 * Updates the domain and chip ops and creates a MSI interrupt domain.
1260 * A domain pointer or NULL in case of failure.
1262 struct irq_domain *pci_msi_create_irq_domain(struct device_node *node,
1263 struct msi_domain_info *info,
1264 struct irq_domain *parent)
1266 struct irq_domain *domain;
1268 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1269 pci_msi_domain_update_dom_ops(info);
1270 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1271 pci_msi_domain_update_chip_ops(info);
1273 domain = msi_create_irq_domain(node, info, parent);
1277 domain->bus_token = DOMAIN_BUS_PCI_MSI;
1282 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1283 * @domain: The interrupt domain to allocate from
1284 * @dev: The device for which to allocate
1285 * @nvec: The number of interrupts to allocate
1286 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1289 * A virtual interrupt number or an error code in case of failure
1291 int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1294 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1298 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1299 * @domain: The interrupt domain
1300 * @dev: The device for which to free interrupts
1302 void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1304 msi_domain_free_irqs(domain, &dev->dev);
1308 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1309 * @node: Optional device-tree node of the interrupt controller
1310 * @info: MSI domain info
1311 * @parent: Parent irq domain
1313 * Returns: A domain pointer or NULL in case of failure. If successful
1314 * the default PCI/MSI irqdomain pointer is updated.
1316 struct irq_domain *pci_msi_create_default_irq_domain(struct device_node *node,
1317 struct msi_domain_info *info, struct irq_domain *parent)
1319 struct irq_domain *domain;
1321 mutex_lock(&pci_msi_domain_lock);
1322 if (pci_msi_default_domain) {
1323 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1326 domain = pci_msi_create_irq_domain(node, info, parent);
1327 pci_msi_default_domain = domain;
1329 mutex_unlock(&pci_msi_domain_lock);
1333 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */