2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
14 #include <linux/of_pci.h>
15 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
21 #include <linux/log2.h>
22 #include <linux/pci-aspm.h>
23 #include <linux/pm_wakeup.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pci_hotplug.h>
28 #include <asm-generic/pci-bridge.h>
29 #include <asm/setup.h>
30 #include <linux/aer.h>
33 const char *pci_power_names[] = {
34 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
36 EXPORT_SYMBOL_GPL(pci_power_names);
38 int isa_dma_bridge_buggy;
39 EXPORT_SYMBOL(isa_dma_bridge_buggy);
42 EXPORT_SYMBOL(pci_pci_problems);
44 unsigned int pci_pm_d3_delay;
46 static void pci_pme_list_scan(struct work_struct *work);
48 static LIST_HEAD(pci_pme_list);
49 static DEFINE_MUTEX(pci_pme_list_mutex);
50 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
52 struct pci_pme_device {
53 struct list_head list;
57 #define PME_TIMEOUT 1000 /* How long between PME checks */
59 static void pci_dev_d3_sleep(struct pci_dev *dev)
61 unsigned int delay = dev->d3_delay;
63 if (delay < pci_pm_d3_delay)
64 delay = pci_pm_d3_delay;
69 #ifdef CONFIG_PCI_DOMAINS
70 int pci_domains_supported = 1;
73 #define DEFAULT_CARDBUS_IO_SIZE (256)
74 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
75 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
76 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
77 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
79 #define DEFAULT_HOTPLUG_IO_SIZE (256)
80 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
81 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
82 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
83 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
85 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
88 * The default CLS is used if arch didn't set CLS explicitly and not
89 * all pci devices agree on the same value. Arch can override either
90 * the dfl or actual value as it sees fit. Don't forget this is
91 * measured in 32-bit words, not bytes.
93 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
94 u8 pci_cache_line_size;
97 * If we set up a device for bus mastering, we need to check the latency
98 * timer as certain BIOSes forget to set it properly.
100 unsigned int pcibios_max_latency = 255;
102 /* If set, the PCIe ARI capability will not be used. */
103 static bool pcie_ari_disabled;
106 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
107 * @bus: pointer to PCI bus structure to search
109 * Given a PCI bus, returns the highest PCI bus number present in the set
110 * including the given PCI bus and its list of child PCI buses.
112 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
115 unsigned char max, n;
117 max = bus->busn_res.end;
118 list_for_each_entry(tmp, &bus->children, node) {
119 n = pci_bus_max_busnr(tmp);
125 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
127 #ifdef CONFIG_HAS_IOMEM
128 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
130 struct resource *res = &pdev->resource[bar];
133 * Make sure the BAR is actually a memory resource, not an IO resource
135 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
136 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
139 return ioremap_nocache(res->start, resource_size(res));
141 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
143 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
146 * Make sure the BAR is actually a memory resource, not an IO resource
148 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
152 return ioremap_wc(pci_resource_start(pdev, bar),
153 pci_resource_len(pdev, bar));
155 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
159 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
160 u8 pos, int cap, int *ttl)
165 pci_bus_read_config_byte(bus, devfn, pos, &pos);
171 pci_bus_read_config_word(bus, devfn, pos, &ent);
183 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
186 int ttl = PCI_FIND_CAP_TTL;
188 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
191 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
193 return __pci_find_next_cap(dev->bus, dev->devfn,
194 pos + PCI_CAP_LIST_NEXT, cap);
196 EXPORT_SYMBOL_GPL(pci_find_next_capability);
198 static int __pci_bus_find_cap_start(struct pci_bus *bus,
199 unsigned int devfn, u8 hdr_type)
203 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
204 if (!(status & PCI_STATUS_CAP_LIST))
208 case PCI_HEADER_TYPE_NORMAL:
209 case PCI_HEADER_TYPE_BRIDGE:
210 return PCI_CAPABILITY_LIST;
211 case PCI_HEADER_TYPE_CARDBUS:
212 return PCI_CB_CAPABILITY_LIST;
219 * pci_find_capability - query for devices' capabilities
220 * @dev: PCI device to query
221 * @cap: capability code
223 * Tell if a device supports a given PCI capability.
224 * Returns the address of the requested capability structure within the
225 * device's PCI configuration space or 0 in case the device does not
226 * support it. Possible values for @cap:
228 * %PCI_CAP_ID_PM Power Management
229 * %PCI_CAP_ID_AGP Accelerated Graphics Port
230 * %PCI_CAP_ID_VPD Vital Product Data
231 * %PCI_CAP_ID_SLOTID Slot Identification
232 * %PCI_CAP_ID_MSI Message Signalled Interrupts
233 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
234 * %PCI_CAP_ID_PCIX PCI-X
235 * %PCI_CAP_ID_EXP PCI Express
237 int pci_find_capability(struct pci_dev *dev, int cap)
241 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
243 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
247 EXPORT_SYMBOL(pci_find_capability);
250 * pci_bus_find_capability - query for devices' capabilities
251 * @bus: the PCI bus to query
252 * @devfn: PCI device to query
253 * @cap: capability code
255 * Like pci_find_capability() but works for pci devices that do not have a
256 * pci_dev structure set up yet.
258 * Returns the address of the requested capability structure within the
259 * device's PCI configuration space or 0 in case the device does not
262 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
267 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
269 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
271 pos = __pci_find_next_cap(bus, devfn, pos, cap);
275 EXPORT_SYMBOL(pci_bus_find_capability);
278 * pci_find_next_ext_capability - Find an extended capability
279 * @dev: PCI device to query
280 * @start: address at which to start looking (0 to start at beginning of list)
281 * @cap: capability code
283 * Returns the address of the next matching extended capability structure
284 * within the device's PCI configuration space or 0 if the device does
285 * not support it. Some capabilities can occur several times, e.g., the
286 * vendor-specific capability, and this provides a way to find them all.
288 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
292 int pos = PCI_CFG_SPACE_SIZE;
294 /* minimum 8 bytes per capability */
295 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
297 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
303 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
307 * If we have no capabilities, this is indicated by cap ID,
308 * cap version and next pointer all being 0.
314 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
317 pos = PCI_EXT_CAP_NEXT(header);
318 if (pos < PCI_CFG_SPACE_SIZE)
321 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
327 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
330 * pci_find_ext_capability - Find an extended capability
331 * @dev: PCI device to query
332 * @cap: capability code
334 * Returns the address of the requested extended capability structure
335 * within the device's PCI configuration space or 0 if the device does
336 * not support it. Possible values for @cap:
338 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
339 * %PCI_EXT_CAP_ID_VC Virtual Channel
340 * %PCI_EXT_CAP_ID_DSN Device Serial Number
341 * %PCI_EXT_CAP_ID_PWR Power Budgeting
343 int pci_find_ext_capability(struct pci_dev *dev, int cap)
345 return pci_find_next_ext_capability(dev, 0, cap);
347 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
349 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
351 int rc, ttl = PCI_FIND_CAP_TTL;
354 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
355 mask = HT_3BIT_CAP_MASK;
357 mask = HT_5BIT_CAP_MASK;
359 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
360 PCI_CAP_ID_HT, &ttl);
362 rc = pci_read_config_byte(dev, pos + 3, &cap);
363 if (rc != PCIBIOS_SUCCESSFUL)
366 if ((cap & mask) == ht_cap)
369 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
370 pos + PCI_CAP_LIST_NEXT,
371 PCI_CAP_ID_HT, &ttl);
377 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
378 * @dev: PCI device to query
379 * @pos: Position from which to continue searching
380 * @ht_cap: Hypertransport capability code
382 * To be used in conjunction with pci_find_ht_capability() to search for
383 * all capabilities matching @ht_cap. @pos should always be a value returned
384 * from pci_find_ht_capability().
386 * NB. To be 100% safe against broken PCI devices, the caller should take
387 * steps to avoid an infinite loop.
389 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
391 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
393 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
396 * pci_find_ht_capability - query a device's Hypertransport capabilities
397 * @dev: PCI device to query
398 * @ht_cap: Hypertransport capability code
400 * Tell if a device supports a given Hypertransport capability.
401 * Returns an address within the device's PCI configuration space
402 * or 0 in case the device does not support the request capability.
403 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
404 * which has a Hypertransport capability matching @ht_cap.
406 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
410 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
412 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
416 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
419 * pci_find_parent_resource - return resource region of parent bus of given region
420 * @dev: PCI device structure contains resources to be searched
421 * @res: child resource record for which parent is sought
423 * For given resource region of given device, return the resource
424 * region of parent bus the given region is contained in.
426 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
427 struct resource *res)
429 const struct pci_bus *bus = dev->bus;
433 pci_bus_for_each_resource(bus, r, i) {
436 if (res->start && resource_contains(r, res)) {
439 * If the window is prefetchable but the BAR is
440 * not, the allocator made a mistake.
442 if (r->flags & IORESOURCE_PREFETCH &&
443 !(res->flags & IORESOURCE_PREFETCH))
447 * If we're below a transparent bridge, there may
448 * be both a positively-decoded aperture and a
449 * subtractively-decoded region that contain the BAR.
450 * We want the positively-decoded one, so this depends
451 * on pci_bus_for_each_resource() giving us those
459 EXPORT_SYMBOL(pci_find_parent_resource);
462 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
463 * @dev: the PCI device to operate on
464 * @pos: config space offset of status word
465 * @mask: mask of bit(s) to care about in status word
467 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
469 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
473 /* Wait for Transaction Pending bit clean */
474 for (i = 0; i < 4; i++) {
477 msleep((1 << (i - 1)) * 100);
479 pci_read_config_word(dev, pos, &status);
480 if (!(status & mask))
488 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
489 * @dev: PCI device to have its BARs restored
491 * Restore the BAR values for a given device, so as to make it
492 * accessible by its driver.
494 static void pci_restore_bars(struct pci_dev *dev)
498 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
499 pci_update_resource(dev, i);
502 static struct pci_platform_pm_ops *pci_platform_pm;
504 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
506 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
509 pci_platform_pm = ops;
513 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
515 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
518 static inline int platform_pci_set_power_state(struct pci_dev *dev,
521 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
524 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
526 return pci_platform_pm ?
527 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
530 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
532 return pci_platform_pm ?
533 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
536 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
538 return pci_platform_pm ?
539 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
542 static inline bool platform_pci_need_resume(struct pci_dev *dev)
544 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
548 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
550 * @dev: PCI device to handle.
551 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
554 * -EINVAL if the requested state is invalid.
555 * -EIO if device does not support PCI PM or its PM capabilities register has a
556 * wrong version, or device doesn't support the requested state.
557 * 0 if device already is in the requested state.
558 * 0 if device's power state has been successfully changed.
560 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
563 bool need_restore = false;
565 /* Check if we're already there */
566 if (dev->current_state == state)
572 if (state < PCI_D0 || state > PCI_D3hot)
575 /* Validate current state:
576 * Can enter D0 from any state, but if we can only go deeper
577 * to sleep if we're already in a low power state
579 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
580 && dev->current_state > state) {
581 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
582 dev->current_state, state);
586 /* check if this device supports the desired state */
587 if ((state == PCI_D1 && !dev->d1_support)
588 || (state == PCI_D2 && !dev->d2_support))
591 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
593 /* If we're (effectively) in D3, force entire word to 0.
594 * This doesn't affect PME_Status, disables PME_En, and
595 * sets PowerState to 0.
597 switch (dev->current_state) {
601 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
606 case PCI_UNKNOWN: /* Boot-up */
607 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
608 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
610 /* Fall-through: force to D0 */
616 /* enter specified state */
617 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
619 /* Mandatory power management transition delays */
620 /* see PCI PM 1.1 5.6.1 table 18 */
621 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
622 pci_dev_d3_sleep(dev);
623 else if (state == PCI_D2 || dev->current_state == PCI_D2)
624 udelay(PCI_PM_D2_DELAY);
626 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
627 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
628 if (dev->current_state != state && printk_ratelimit())
629 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
633 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
634 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
635 * from D3hot to D0 _may_ perform an internal reset, thereby
636 * going to "D0 Uninitialized" rather than "D0 Initialized".
637 * For example, at least some versions of the 3c905B and the
638 * 3c556B exhibit this behaviour.
640 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
641 * devices in a D3hot state at boot. Consequently, we need to
642 * restore at least the BARs so that the device will be
643 * accessible to its driver.
646 pci_restore_bars(dev);
649 pcie_aspm_pm_state_change(dev->bus->self);
655 * pci_update_current_state - Read PCI power state of given device from its
656 * PCI PM registers and cache it
657 * @dev: PCI device to handle.
658 * @state: State to cache in case the device doesn't have the PM capability
660 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
666 * Configuration space is not accessible for device in
667 * D3cold, so just keep or set D3cold for safety
669 if (dev->current_state == PCI_D3cold)
671 if (state == PCI_D3cold) {
672 dev->current_state = PCI_D3cold;
675 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
676 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
678 dev->current_state = state;
683 * pci_power_up - Put the given device into D0 forcibly
684 * @dev: PCI device to power up
686 void pci_power_up(struct pci_dev *dev)
688 if (platform_pci_power_manageable(dev))
689 platform_pci_set_power_state(dev, PCI_D0);
691 pci_raw_set_power_state(dev, PCI_D0);
692 pci_update_current_state(dev, PCI_D0);
696 * pci_platform_power_transition - Use platform to change device power state
697 * @dev: PCI device to handle.
698 * @state: State to put the device into.
700 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
704 if (platform_pci_power_manageable(dev)) {
705 error = platform_pci_set_power_state(dev, state);
707 pci_update_current_state(dev, state);
711 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
712 dev->current_state = PCI_D0;
718 * pci_wakeup - Wake up a PCI device
719 * @pci_dev: Device to handle.
720 * @ign: ignored parameter
722 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
724 pci_wakeup_event(pci_dev);
725 pm_request_resume(&pci_dev->dev);
730 * pci_wakeup_bus - Walk given bus and wake up devices on it
731 * @bus: Top bus of the subtree to walk.
733 static void pci_wakeup_bus(struct pci_bus *bus)
736 pci_walk_bus(bus, pci_wakeup, NULL);
740 * __pci_start_power_transition - Start power transition of a PCI device
741 * @dev: PCI device to handle.
742 * @state: State to put the device into.
744 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
746 if (state == PCI_D0) {
747 pci_platform_power_transition(dev, PCI_D0);
749 * Mandatory power management transition delays, see
750 * PCI Express Base Specification Revision 2.0 Section
751 * 6.6.1: Conventional Reset. Do not delay for
752 * devices powered on/off by corresponding bridge,
753 * because have already delayed for the bridge.
755 if (dev->runtime_d3cold) {
756 msleep(dev->d3cold_delay);
758 * When powering on a bridge from D3cold, the
759 * whole hierarchy may be powered on into
760 * D0uninitialized state, resume them to give
761 * them a chance to suspend again
763 pci_wakeup_bus(dev->subordinate);
769 * __pci_dev_set_current_state - Set current state of a PCI device
770 * @dev: Device to handle
771 * @data: pointer to state to be set
773 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
775 pci_power_t state = *(pci_power_t *)data;
777 dev->current_state = state;
782 * __pci_bus_set_current_state - Walk given bus and set current state of devices
783 * @bus: Top bus of the subtree to walk.
784 * @state: state to be set
786 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
789 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
793 * __pci_complete_power_transition - Complete power transition of a PCI device
794 * @dev: PCI device to handle.
795 * @state: State to put the device into.
797 * This function should not be called directly by device drivers.
799 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
805 ret = pci_platform_power_transition(dev, state);
806 /* Power off the bridge may power off the whole hierarchy */
807 if (!ret && state == PCI_D3cold)
808 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
811 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
814 * pci_set_power_state - Set the power state of a PCI device
815 * @dev: PCI device to handle.
816 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
818 * Transition a device to a new power state, using the platform firmware and/or
819 * the device's PCI PM registers.
822 * -EINVAL if the requested state is invalid.
823 * -EIO if device does not support PCI PM or its PM capabilities register has a
824 * wrong version, or device doesn't support the requested state.
825 * 0 if device already is in the requested state.
826 * 0 if device's power state has been successfully changed.
828 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
832 /* bound the state we're entering */
833 if (state > PCI_D3cold)
835 else if (state < PCI_D0)
837 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
839 * If the device or the parent bridge do not support PCI PM,
840 * ignore the request if we're doing anything other than putting
841 * it into D0 (which would only happen on boot).
845 /* Check if we're already there */
846 if (dev->current_state == state)
849 __pci_start_power_transition(dev, state);
851 /* This device is quirked not to be put into D3, so
852 don't put it in D3 */
853 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
857 * To put device in D3cold, we put device into D3hot in native
858 * way, then put device into D3cold with platform ops
860 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
863 if (!__pci_complete_power_transition(dev, state))
868 EXPORT_SYMBOL(pci_set_power_state);
871 * pci_choose_state - Choose the power state of a PCI device
872 * @dev: PCI device to be suspended
873 * @state: target sleep state for the whole system. This is the value
874 * that is passed to suspend() function.
876 * Returns PCI power state suitable for given device and given system
880 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
887 ret = platform_pci_choose_state(dev);
888 if (ret != PCI_POWER_ERROR)
891 switch (state.event) {
894 case PM_EVENT_FREEZE:
895 case PM_EVENT_PRETHAW:
896 /* REVISIT both freeze and pre-thaw "should" use D0 */
897 case PM_EVENT_SUSPEND:
898 case PM_EVENT_HIBERNATE:
901 dev_info(&dev->dev, "unrecognized suspend event %d\n",
907 EXPORT_SYMBOL(pci_choose_state);
909 #define PCI_EXP_SAVE_REGS 7
911 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
912 u16 cap, bool extended)
914 struct pci_cap_saved_state *tmp;
916 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
917 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
923 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
925 return _pci_find_saved_cap(dev, cap, false);
928 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
930 return _pci_find_saved_cap(dev, cap, true);
933 static int pci_save_pcie_state(struct pci_dev *dev)
936 struct pci_cap_saved_state *save_state;
939 if (!pci_is_pcie(dev))
942 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
944 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
948 cap = (u16 *)&save_state->cap.data[0];
949 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
950 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
951 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
952 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
953 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
954 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
955 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
960 static void pci_restore_pcie_state(struct pci_dev *dev)
963 struct pci_cap_saved_state *save_state;
966 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
970 cap = (u16 *)&save_state->cap.data[0];
971 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
972 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
973 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
974 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
975 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
976 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
977 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
981 static int pci_save_pcix_state(struct pci_dev *dev)
984 struct pci_cap_saved_state *save_state;
986 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
990 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
992 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
996 pci_read_config_word(dev, pos + PCI_X_CMD,
997 (u16 *)save_state->cap.data);
1002 static void pci_restore_pcix_state(struct pci_dev *dev)
1005 struct pci_cap_saved_state *save_state;
1008 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1009 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1010 if (!save_state || !pos)
1012 cap = (u16 *)&save_state->cap.data[0];
1014 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1019 * pci_save_state - save the PCI configuration space of a device before suspending
1020 * @dev: - PCI device that we're dealing with
1022 int pci_save_state(struct pci_dev *dev)
1025 /* XXX: 100% dword access ok here? */
1026 for (i = 0; i < 16; i++)
1027 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1028 dev->state_saved = true;
1030 i = pci_save_pcie_state(dev);
1034 i = pci_save_pcix_state(dev);
1038 return pci_save_vc_state(dev);
1040 EXPORT_SYMBOL(pci_save_state);
1042 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1043 u32 saved_val, int retry)
1047 pci_read_config_dword(pdev, offset, &val);
1048 if (val == saved_val)
1052 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1053 offset, val, saved_val);
1054 pci_write_config_dword(pdev, offset, saved_val);
1058 pci_read_config_dword(pdev, offset, &val);
1059 if (val == saved_val)
1066 static void pci_restore_config_space_range(struct pci_dev *pdev,
1067 int start, int end, int retry)
1071 for (index = end; index >= start; index--)
1072 pci_restore_config_dword(pdev, 4 * index,
1073 pdev->saved_config_space[index],
1077 static void pci_restore_config_space(struct pci_dev *pdev)
1079 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1080 pci_restore_config_space_range(pdev, 10, 15, 0);
1081 /* Restore BARs before the command register. */
1082 pci_restore_config_space_range(pdev, 4, 9, 10);
1083 pci_restore_config_space_range(pdev, 0, 3, 0);
1085 pci_restore_config_space_range(pdev, 0, 15, 0);
1090 * pci_restore_state - Restore the saved state of a PCI device
1091 * @dev: - PCI device that we're dealing with
1093 void pci_restore_state(struct pci_dev *dev)
1095 if (!dev->state_saved)
1098 /* PCI Express register must be restored first */
1099 pci_restore_pcie_state(dev);
1100 pci_restore_ats_state(dev);
1101 pci_restore_vc_state(dev);
1103 pci_cleanup_aer_error_status_regs(dev);
1105 pci_restore_config_space(dev);
1107 pci_restore_pcix_state(dev);
1108 pci_restore_msi_state(dev);
1110 /* Restore ACS and IOV configuration state */
1111 pci_enable_acs(dev);
1112 pci_restore_iov_state(dev);
1114 dev->state_saved = false;
1116 EXPORT_SYMBOL(pci_restore_state);
1118 struct pci_saved_state {
1119 u32 config_space[16];
1120 struct pci_cap_saved_data cap[0];
1124 * pci_store_saved_state - Allocate and return an opaque struct containing
1125 * the device saved state.
1126 * @dev: PCI device that we're dealing with
1128 * Return NULL if no state or error.
1130 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1132 struct pci_saved_state *state;
1133 struct pci_cap_saved_state *tmp;
1134 struct pci_cap_saved_data *cap;
1137 if (!dev->state_saved)
1140 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1142 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1143 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1145 state = kzalloc(size, GFP_KERNEL);
1149 memcpy(state->config_space, dev->saved_config_space,
1150 sizeof(state->config_space));
1153 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1154 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1155 memcpy(cap, &tmp->cap, len);
1156 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1158 /* Empty cap_save terminates list */
1162 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1165 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1166 * @dev: PCI device that we're dealing with
1167 * @state: Saved state returned from pci_store_saved_state()
1169 int pci_load_saved_state(struct pci_dev *dev,
1170 struct pci_saved_state *state)
1172 struct pci_cap_saved_data *cap;
1174 dev->state_saved = false;
1179 memcpy(dev->saved_config_space, state->config_space,
1180 sizeof(state->config_space));
1184 struct pci_cap_saved_state *tmp;
1186 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1187 if (!tmp || tmp->cap.size != cap->size)
1190 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1191 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1192 sizeof(struct pci_cap_saved_data) + cap->size);
1195 dev->state_saved = true;
1198 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1201 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1202 * and free the memory allocated for it.
1203 * @dev: PCI device that we're dealing with
1204 * @state: Pointer to saved state returned from pci_store_saved_state()
1206 int pci_load_and_free_saved_state(struct pci_dev *dev,
1207 struct pci_saved_state **state)
1209 int ret = pci_load_saved_state(dev, *state);
1214 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1216 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1218 return pci_enable_resources(dev, bars);
1221 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1224 struct pci_dev *bridge;
1228 err = pci_set_power_state(dev, PCI_D0);
1229 if (err < 0 && err != -EIO)
1232 bridge = pci_upstream_bridge(dev);
1234 pcie_aspm_powersave_config_link(bridge);
1236 err = pcibios_enable_device(dev, bars);
1239 pci_fixup_device(pci_fixup_enable, dev);
1241 if (dev->msi_enabled || dev->msix_enabled)
1244 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1246 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1247 if (cmd & PCI_COMMAND_INTX_DISABLE)
1248 pci_write_config_word(dev, PCI_COMMAND,
1249 cmd & ~PCI_COMMAND_INTX_DISABLE);
1256 * pci_reenable_device - Resume abandoned device
1257 * @dev: PCI device to be resumed
1259 * Note this function is a backend of pci_default_resume and is not supposed
1260 * to be called by normal code, write proper resume handler and use it instead.
1262 int pci_reenable_device(struct pci_dev *dev)
1264 if (pci_is_enabled(dev))
1265 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1268 EXPORT_SYMBOL(pci_reenable_device);
1270 static void pci_enable_bridge(struct pci_dev *dev)
1272 struct pci_dev *bridge;
1275 bridge = pci_upstream_bridge(dev);
1277 pci_enable_bridge(bridge);
1279 if (pci_is_enabled(dev)) {
1280 if (!dev->is_busmaster)
1281 pci_set_master(dev);
1285 retval = pci_enable_device(dev);
1287 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1289 pci_set_master(dev);
1292 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1294 struct pci_dev *bridge;
1299 * Power state could be unknown at this point, either due to a fresh
1300 * boot or a device removal call. So get the current power state
1301 * so that things like MSI message writing will behave as expected
1302 * (e.g. if the device really is in D0 at enable time).
1306 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1307 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1310 if (atomic_inc_return(&dev->enable_cnt) > 1)
1311 return 0; /* already enabled */
1313 bridge = pci_upstream_bridge(dev);
1315 pci_enable_bridge(bridge);
1317 /* only skip sriov related */
1318 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1319 if (dev->resource[i].flags & flags)
1321 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1322 if (dev->resource[i].flags & flags)
1325 err = do_pci_enable_device(dev, bars);
1327 atomic_dec(&dev->enable_cnt);
1332 * pci_enable_device_io - Initialize a device for use with IO space
1333 * @dev: PCI device to be initialized
1335 * Initialize device before it's used by a driver. Ask low-level code
1336 * to enable I/O resources. Wake up the device if it was suspended.
1337 * Beware, this function can fail.
1339 int pci_enable_device_io(struct pci_dev *dev)
1341 return pci_enable_device_flags(dev, IORESOURCE_IO);
1343 EXPORT_SYMBOL(pci_enable_device_io);
1346 * pci_enable_device_mem - Initialize a device for use with Memory space
1347 * @dev: PCI device to be initialized
1349 * Initialize device before it's used by a driver. Ask low-level code
1350 * to enable Memory resources. Wake up the device if it was suspended.
1351 * Beware, this function can fail.
1353 int pci_enable_device_mem(struct pci_dev *dev)
1355 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1357 EXPORT_SYMBOL(pci_enable_device_mem);
1360 * pci_enable_device - Initialize device before it's used by a driver.
1361 * @dev: PCI device to be initialized
1363 * Initialize device before it's used by a driver. Ask low-level code
1364 * to enable I/O and memory. Wake up the device if it was suspended.
1365 * Beware, this function can fail.
1367 * Note we don't actually enable the device many times if we call
1368 * this function repeatedly (we just increment the count).
1370 int pci_enable_device(struct pci_dev *dev)
1372 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1374 EXPORT_SYMBOL(pci_enable_device);
1377 * Managed PCI resources. This manages device on/off, intx/msi/msix
1378 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1379 * there's no need to track it separately. pci_devres is initialized
1380 * when a device is enabled using managed PCI device enable interface.
1383 unsigned int enabled:1;
1384 unsigned int pinned:1;
1385 unsigned int orig_intx:1;
1386 unsigned int restore_intx:1;
1390 static void pcim_release(struct device *gendev, void *res)
1392 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1393 struct pci_devres *this = res;
1396 if (dev->msi_enabled)
1397 pci_disable_msi(dev);
1398 if (dev->msix_enabled)
1399 pci_disable_msix(dev);
1401 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1402 if (this->region_mask & (1 << i))
1403 pci_release_region(dev, i);
1405 if (this->restore_intx)
1406 pci_intx(dev, this->orig_intx);
1408 if (this->enabled && !this->pinned)
1409 pci_disable_device(dev);
1412 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1414 struct pci_devres *dr, *new_dr;
1416 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1420 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1423 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1426 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1428 if (pci_is_managed(pdev))
1429 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1434 * pcim_enable_device - Managed pci_enable_device()
1435 * @pdev: PCI device to be initialized
1437 * Managed pci_enable_device().
1439 int pcim_enable_device(struct pci_dev *pdev)
1441 struct pci_devres *dr;
1444 dr = get_pci_dr(pdev);
1450 rc = pci_enable_device(pdev);
1452 pdev->is_managed = 1;
1457 EXPORT_SYMBOL(pcim_enable_device);
1460 * pcim_pin_device - Pin managed PCI device
1461 * @pdev: PCI device to pin
1463 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1464 * driver detach. @pdev must have been enabled with
1465 * pcim_enable_device().
1467 void pcim_pin_device(struct pci_dev *pdev)
1469 struct pci_devres *dr;
1471 dr = find_pci_dr(pdev);
1472 WARN_ON(!dr || !dr->enabled);
1476 EXPORT_SYMBOL(pcim_pin_device);
1479 * pcibios_add_device - provide arch specific hooks when adding device dev
1480 * @dev: the PCI device being added
1482 * Permits the platform to provide architecture specific functionality when
1483 * devices are added. This is the default implementation. Architecture
1484 * implementations can override this.
1486 int __weak pcibios_add_device(struct pci_dev *dev)
1492 * pcibios_release_device - provide arch specific hooks when releasing device dev
1493 * @dev: the PCI device being released
1495 * Permits the platform to provide architecture specific functionality when
1496 * devices are released. This is the default implementation. Architecture
1497 * implementations can override this.
1499 void __weak pcibios_release_device(struct pci_dev *dev) {}
1502 * pcibios_disable_device - disable arch specific PCI resources for device dev
1503 * @dev: the PCI device to disable
1505 * Disables architecture specific PCI resources for the device. This
1506 * is the default implementation. Architecture implementations can
1509 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1512 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1513 * @irq: ISA IRQ to penalize
1514 * @active: IRQ active or not
1516 * Permits the platform to provide architecture-specific functionality when
1517 * penalizing ISA IRQs. This is the default implementation. Architecture
1518 * implementations can override this.
1520 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1522 static void do_pci_disable_device(struct pci_dev *dev)
1526 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1527 if (pci_command & PCI_COMMAND_MASTER) {
1528 pci_command &= ~PCI_COMMAND_MASTER;
1529 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1532 pcibios_disable_device(dev);
1536 * pci_disable_enabled_device - Disable device without updating enable_cnt
1537 * @dev: PCI device to disable
1539 * NOTE: This function is a backend of PCI power management routines and is
1540 * not supposed to be called drivers.
1542 void pci_disable_enabled_device(struct pci_dev *dev)
1544 if (pci_is_enabled(dev))
1545 do_pci_disable_device(dev);
1549 * pci_disable_device - Disable PCI device after use
1550 * @dev: PCI device to be disabled
1552 * Signal to the system that the PCI device is not in use by the system
1553 * anymore. This only involves disabling PCI bus-mastering, if active.
1555 * Note we don't actually disable the device until all callers of
1556 * pci_enable_device() have called pci_disable_device().
1558 void pci_disable_device(struct pci_dev *dev)
1560 struct pci_devres *dr;
1562 dr = find_pci_dr(dev);
1566 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1567 "disabling already-disabled device");
1569 if (atomic_dec_return(&dev->enable_cnt) != 0)
1572 do_pci_disable_device(dev);
1574 dev->is_busmaster = 0;
1576 EXPORT_SYMBOL(pci_disable_device);
1579 * pcibios_set_pcie_reset_state - set reset state for device dev
1580 * @dev: the PCIe device reset
1581 * @state: Reset state to enter into
1584 * Sets the PCIe reset state for the device. This is the default
1585 * implementation. Architecture implementations can override this.
1587 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1588 enum pcie_reset_state state)
1594 * pci_set_pcie_reset_state - set reset state for device dev
1595 * @dev: the PCIe device reset
1596 * @state: Reset state to enter into
1599 * Sets the PCI reset state for the device.
1601 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1603 return pcibios_set_pcie_reset_state(dev, state);
1605 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1608 * pci_check_pme_status - Check if given device has generated PME.
1609 * @dev: Device to check.
1611 * Check the PME status of the device and if set, clear it and clear PME enable
1612 * (if set). Return 'true' if PME status and PME enable were both set or
1613 * 'false' otherwise.
1615 bool pci_check_pme_status(struct pci_dev *dev)
1624 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1625 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1626 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1629 /* Clear PME status. */
1630 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1631 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1632 /* Disable PME to avoid interrupt flood. */
1633 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1637 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1643 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1644 * @dev: Device to handle.
1645 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1647 * Check if @dev has generated PME and queue a resume request for it in that
1650 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1652 if (pme_poll_reset && dev->pme_poll)
1653 dev->pme_poll = false;
1655 if (pci_check_pme_status(dev)) {
1656 pci_wakeup_event(dev);
1657 pm_request_resume(&dev->dev);
1663 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1664 * @bus: Top bus of the subtree to walk.
1666 void pci_pme_wakeup_bus(struct pci_bus *bus)
1669 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1674 * pci_pme_capable - check the capability of PCI device to generate PME#
1675 * @dev: PCI device to handle.
1676 * @state: PCI state from which device will issue PME#.
1678 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1683 return !!(dev->pme_support & (1 << state));
1685 EXPORT_SYMBOL(pci_pme_capable);
1687 static void pci_pme_list_scan(struct work_struct *work)
1689 struct pci_pme_device *pme_dev, *n;
1691 mutex_lock(&pci_pme_list_mutex);
1692 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1693 if (pme_dev->dev->pme_poll) {
1694 struct pci_dev *bridge;
1696 bridge = pme_dev->dev->bus->self;
1698 * If bridge is in low power state, the
1699 * configuration space of subordinate devices
1700 * may be not accessible
1702 if (bridge && bridge->current_state != PCI_D0)
1704 pci_pme_wakeup(pme_dev->dev, NULL);
1706 list_del(&pme_dev->list);
1710 if (!list_empty(&pci_pme_list))
1711 schedule_delayed_work(&pci_pme_work,
1712 msecs_to_jiffies(PME_TIMEOUT));
1713 mutex_unlock(&pci_pme_list_mutex);
1717 * pci_pme_active - enable or disable PCI device's PME# function
1718 * @dev: PCI device to handle.
1719 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1721 * The caller must verify that the device is capable of generating PME# before
1722 * calling this function with @enable equal to 'true'.
1724 void pci_pme_active(struct pci_dev *dev, bool enable)
1728 if (!dev->pme_support)
1731 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1732 /* Clear PME_Status by writing 1 to it and enable PME# */
1733 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1735 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1737 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1740 * PCI (as opposed to PCIe) PME requires that the device have
1741 * its PME# line hooked up correctly. Not all hardware vendors
1742 * do this, so the PME never gets delivered and the device
1743 * remains asleep. The easiest way around this is to
1744 * periodically walk the list of suspended devices and check
1745 * whether any have their PME flag set. The assumption is that
1746 * we'll wake up often enough anyway that this won't be a huge
1747 * hit, and the power savings from the devices will still be a
1750 * Although PCIe uses in-band PME message instead of PME# line
1751 * to report PME, PME does not work for some PCIe devices in
1752 * reality. For example, there are devices that set their PME
1753 * status bits, but don't really bother to send a PME message;
1754 * there are PCI Express Root Ports that don't bother to
1755 * trigger interrupts when they receive PME messages from the
1756 * devices below. So PME poll is used for PCIe devices too.
1759 if (dev->pme_poll) {
1760 struct pci_pme_device *pme_dev;
1762 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1765 dev_warn(&dev->dev, "can't enable PME#\n");
1769 mutex_lock(&pci_pme_list_mutex);
1770 list_add(&pme_dev->list, &pci_pme_list);
1771 if (list_is_singular(&pci_pme_list))
1772 schedule_delayed_work(&pci_pme_work,
1773 msecs_to_jiffies(PME_TIMEOUT));
1774 mutex_unlock(&pci_pme_list_mutex);
1776 mutex_lock(&pci_pme_list_mutex);
1777 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1778 if (pme_dev->dev == dev) {
1779 list_del(&pme_dev->list);
1784 mutex_unlock(&pci_pme_list_mutex);
1788 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1790 EXPORT_SYMBOL(pci_pme_active);
1793 * __pci_enable_wake - enable PCI device as wakeup event source
1794 * @dev: PCI device affected
1795 * @state: PCI state from which device will issue wakeup events
1796 * @runtime: True if the events are to be generated at run time
1797 * @enable: True to enable event generation; false to disable
1799 * This enables the device as a wakeup event source, or disables it.
1800 * When such events involves platform-specific hooks, those hooks are
1801 * called automatically by this routine.
1803 * Devices with legacy power management (no standard PCI PM capabilities)
1804 * always require such platform hooks.
1807 * 0 is returned on success
1808 * -EINVAL is returned if device is not supposed to wake up the system
1809 * Error code depending on the platform is returned if both the platform and
1810 * the native mechanism fail to enable the generation of wake-up events
1812 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1813 bool runtime, bool enable)
1817 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1820 /* Don't do the same thing twice in a row for one device. */
1821 if (!!enable == !!dev->wakeup_prepared)
1825 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1826 * Anderson we should be doing PME# wake enable followed by ACPI wake
1827 * enable. To disable wake-up we call the platform first, for symmetry.
1833 if (pci_pme_capable(dev, state))
1834 pci_pme_active(dev, true);
1837 error = runtime ? platform_pci_run_wake(dev, true) :
1838 platform_pci_sleep_wake(dev, true);
1842 dev->wakeup_prepared = true;
1845 platform_pci_run_wake(dev, false);
1847 platform_pci_sleep_wake(dev, false);
1848 pci_pme_active(dev, false);
1849 dev->wakeup_prepared = false;
1854 EXPORT_SYMBOL(__pci_enable_wake);
1857 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1858 * @dev: PCI device to prepare
1859 * @enable: True to enable wake-up event generation; false to disable
1861 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1862 * and this function allows them to set that up cleanly - pci_enable_wake()
1863 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1864 * ordering constraints.
1866 * This function only returns error code if the device is not capable of
1867 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1868 * enable wake-up power for it.
1870 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1872 return pci_pme_capable(dev, PCI_D3cold) ?
1873 pci_enable_wake(dev, PCI_D3cold, enable) :
1874 pci_enable_wake(dev, PCI_D3hot, enable);
1876 EXPORT_SYMBOL(pci_wake_from_d3);
1879 * pci_target_state - find an appropriate low power state for a given PCI dev
1882 * Use underlying platform code to find a supported low power state for @dev.
1883 * If the platform can't manage @dev, return the deepest state from which it
1884 * can generate wake events, based on any available PME info.
1886 static pci_power_t pci_target_state(struct pci_dev *dev)
1888 pci_power_t target_state = PCI_D3hot;
1890 if (platform_pci_power_manageable(dev)) {
1892 * Call the platform to choose the target state of the device
1893 * and enable wake-up from this state if supported.
1895 pci_power_t state = platform_pci_choose_state(dev);
1898 case PCI_POWER_ERROR:
1903 if (pci_no_d1d2(dev))
1906 target_state = state;
1908 } else if (!dev->pm_cap) {
1909 target_state = PCI_D0;
1910 } else if (device_may_wakeup(&dev->dev)) {
1912 * Find the deepest state from which the device can generate
1913 * wake-up events, make it the target state and enable device
1916 if (dev->pme_support) {
1918 && !(dev->pme_support & (1 << target_state)))
1923 return target_state;
1927 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1928 * @dev: Device to handle.
1930 * Choose the power state appropriate for the device depending on whether
1931 * it can wake up the system and/or is power manageable by the platform
1932 * (PCI_D3hot is the default) and put the device into that state.
1934 int pci_prepare_to_sleep(struct pci_dev *dev)
1936 pci_power_t target_state = pci_target_state(dev);
1939 if (target_state == PCI_POWER_ERROR)
1942 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1944 error = pci_set_power_state(dev, target_state);
1947 pci_enable_wake(dev, target_state, false);
1951 EXPORT_SYMBOL(pci_prepare_to_sleep);
1954 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1955 * @dev: Device to handle.
1957 * Disable device's system wake-up capability and put it into D0.
1959 int pci_back_from_sleep(struct pci_dev *dev)
1961 pci_enable_wake(dev, PCI_D0, false);
1962 return pci_set_power_state(dev, PCI_D0);
1964 EXPORT_SYMBOL(pci_back_from_sleep);
1967 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1968 * @dev: PCI device being suspended.
1970 * Prepare @dev to generate wake-up events at run time and put it into a low
1973 int pci_finish_runtime_suspend(struct pci_dev *dev)
1975 pci_power_t target_state = pci_target_state(dev);
1978 if (target_state == PCI_POWER_ERROR)
1981 dev->runtime_d3cold = target_state == PCI_D3cold;
1983 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1985 error = pci_set_power_state(dev, target_state);
1988 __pci_enable_wake(dev, target_state, true, false);
1989 dev->runtime_d3cold = false;
1996 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1997 * @dev: Device to check.
1999 * Return true if the device itself is capable of generating wake-up events
2000 * (through the platform or using the native PCIe PME) or if the device supports
2001 * PME and one of its upstream bridges can generate wake-up events.
2003 bool pci_dev_run_wake(struct pci_dev *dev)
2005 struct pci_bus *bus = dev->bus;
2007 if (device_run_wake(&dev->dev))
2010 if (!dev->pme_support)
2013 while (bus->parent) {
2014 struct pci_dev *bridge = bus->self;
2016 if (device_run_wake(&bridge->dev))
2022 /* We have reached the root bus. */
2024 return device_run_wake(bus->bridge);
2028 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2031 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2032 * @pci_dev: Device to check.
2034 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2035 * reconfigured due to wakeup settings difference between system and runtime
2036 * suspend and the current power state of it is suitable for the upcoming
2037 * (system) transition.
2039 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2041 struct device *dev = &pci_dev->dev;
2043 if (!pm_runtime_suspended(dev)
2044 || (device_can_wakeup(dev) && !device_may_wakeup(dev))
2045 || platform_pci_need_resume(pci_dev))
2048 return pci_target_state(pci_dev) == pci_dev->current_state;
2051 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2053 struct device *dev = &pdev->dev;
2054 struct device *parent = dev->parent;
2057 pm_runtime_get_sync(parent);
2058 pm_runtime_get_noresume(dev);
2060 * pdev->current_state is set to PCI_D3cold during suspending,
2061 * so wait until suspending completes
2063 pm_runtime_barrier(dev);
2065 * Only need to resume devices in D3cold, because config
2066 * registers are still accessible for devices suspended but
2069 if (pdev->current_state == PCI_D3cold)
2070 pm_runtime_resume(dev);
2073 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2075 struct device *dev = &pdev->dev;
2076 struct device *parent = dev->parent;
2078 pm_runtime_put(dev);
2080 pm_runtime_put_sync(parent);
2084 * pci_pm_init - Initialize PM functions of given PCI device
2085 * @dev: PCI device to handle.
2087 void pci_pm_init(struct pci_dev *dev)
2092 pm_runtime_forbid(&dev->dev);
2093 pm_runtime_set_active(&dev->dev);
2094 pm_runtime_enable(&dev->dev);
2095 device_enable_async_suspend(&dev->dev);
2096 dev->wakeup_prepared = false;
2099 dev->pme_support = 0;
2101 /* find PCI PM capability in list */
2102 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2105 /* Check device's ability to generate PME# */
2106 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2108 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2109 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2110 pmc & PCI_PM_CAP_VER_MASK);
2115 dev->d3_delay = PCI_PM_D3_WAIT;
2116 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2117 dev->d3cold_allowed = true;
2119 dev->d1_support = false;
2120 dev->d2_support = false;
2121 if (!pci_no_d1d2(dev)) {
2122 if (pmc & PCI_PM_CAP_D1)
2123 dev->d1_support = true;
2124 if (pmc & PCI_PM_CAP_D2)
2125 dev->d2_support = true;
2127 if (dev->d1_support || dev->d2_support)
2128 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2129 dev->d1_support ? " D1" : "",
2130 dev->d2_support ? " D2" : "");
2133 pmc &= PCI_PM_CAP_PME_MASK;
2135 dev_printk(KERN_DEBUG, &dev->dev,
2136 "PME# supported from%s%s%s%s%s\n",
2137 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2138 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2139 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2140 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2141 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2142 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2143 dev->pme_poll = true;
2145 * Make device's PM flags reflect the wake-up capability, but
2146 * let the user space enable it to wake up the system as needed.
2148 device_set_wakeup_capable(&dev->dev, true);
2149 /* Disable the PME# generation functionality */
2150 pci_pme_active(dev, false);
2154 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2155 struct pci_cap_saved_state *new_cap)
2157 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2161 * _pci_add_cap_save_buffer - allocate buffer for saving given
2162 * capability registers
2163 * @dev: the PCI device
2164 * @cap: the capability to allocate the buffer for
2165 * @extended: Standard or Extended capability ID
2166 * @size: requested size of the buffer
2168 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2169 bool extended, unsigned int size)
2172 struct pci_cap_saved_state *save_state;
2175 pos = pci_find_ext_capability(dev, cap);
2177 pos = pci_find_capability(dev, cap);
2182 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2186 save_state->cap.cap_nr = cap;
2187 save_state->cap.cap_extended = extended;
2188 save_state->cap.size = size;
2189 pci_add_saved_cap(dev, save_state);
2194 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2196 return _pci_add_cap_save_buffer(dev, cap, false, size);
2199 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2201 return _pci_add_cap_save_buffer(dev, cap, true, size);
2205 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2206 * @dev: the PCI device
2208 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2212 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2213 PCI_EXP_SAVE_REGS * sizeof(u16));
2216 "unable to preallocate PCI Express save buffer\n");
2218 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2221 "unable to preallocate PCI-X save buffer\n");
2223 pci_allocate_vc_save_buffers(dev);
2226 void pci_free_cap_save_buffers(struct pci_dev *dev)
2228 struct pci_cap_saved_state *tmp;
2229 struct hlist_node *n;
2231 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2236 * pci_configure_ari - enable or disable ARI forwarding
2237 * @dev: the PCI device
2239 * If @dev and its upstream bridge both support ARI, enable ARI in the
2240 * bridge. Otherwise, disable ARI in the bridge.
2242 void pci_configure_ari(struct pci_dev *dev)
2245 struct pci_dev *bridge;
2247 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2250 bridge = dev->bus->self;
2254 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2255 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2258 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2259 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2260 PCI_EXP_DEVCTL2_ARI);
2261 bridge->ari_enabled = 1;
2263 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2264 PCI_EXP_DEVCTL2_ARI);
2265 bridge->ari_enabled = 0;
2269 static int pci_acs_enable;
2272 * pci_request_acs - ask for ACS to be enabled if supported
2274 void pci_request_acs(void)
2280 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2281 * @dev: the PCI device
2283 static int pci_std_enable_acs(struct pci_dev *dev)
2289 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2293 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2294 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2296 /* Source Validation */
2297 ctrl |= (cap & PCI_ACS_SV);
2299 /* P2P Request Redirect */
2300 ctrl |= (cap & PCI_ACS_RR);
2302 /* P2P Completion Redirect */
2303 ctrl |= (cap & PCI_ACS_CR);
2305 /* Upstream Forwarding */
2306 ctrl |= (cap & PCI_ACS_UF);
2308 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2314 * pci_enable_acs - enable ACS if hardware support it
2315 * @dev: the PCI device
2317 void pci_enable_acs(struct pci_dev *dev)
2319 if (!pci_acs_enable)
2322 if (!pci_std_enable_acs(dev))
2325 pci_dev_specific_enable_acs(dev);
2328 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2333 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2338 * Except for egress control, capabilities are either required
2339 * or only required if controllable. Features missing from the
2340 * capability field can therefore be assumed as hard-wired enabled.
2342 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2343 acs_flags &= (cap | PCI_ACS_EC);
2345 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2346 return (ctrl & acs_flags) == acs_flags;
2350 * pci_acs_enabled - test ACS against required flags for a given device
2351 * @pdev: device to test
2352 * @acs_flags: required PCI ACS flags
2354 * Return true if the device supports the provided flags. Automatically
2355 * filters out flags that are not implemented on multifunction devices.
2357 * Note that this interface checks the effective ACS capabilities of the
2358 * device rather than the actual capabilities. For instance, most single
2359 * function endpoints are not required to support ACS because they have no
2360 * opportunity for peer-to-peer access. We therefore return 'true'
2361 * regardless of whether the device exposes an ACS capability. This makes
2362 * it much easier for callers of this function to ignore the actual type
2363 * or topology of the device when testing ACS support.
2365 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2369 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2374 * Conventional PCI and PCI-X devices never support ACS, either
2375 * effectively or actually. The shared bus topology implies that
2376 * any device on the bus can receive or snoop DMA.
2378 if (!pci_is_pcie(pdev))
2381 switch (pci_pcie_type(pdev)) {
2383 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2384 * but since their primary interface is PCI/X, we conservatively
2385 * handle them as we would a non-PCIe device.
2387 case PCI_EXP_TYPE_PCIE_BRIDGE:
2389 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2390 * applicable... must never implement an ACS Extended Capability...".
2391 * This seems arbitrary, but we take a conservative interpretation
2392 * of this statement.
2394 case PCI_EXP_TYPE_PCI_BRIDGE:
2395 case PCI_EXP_TYPE_RC_EC:
2398 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2399 * implement ACS in order to indicate their peer-to-peer capabilities,
2400 * regardless of whether they are single- or multi-function devices.
2402 case PCI_EXP_TYPE_DOWNSTREAM:
2403 case PCI_EXP_TYPE_ROOT_PORT:
2404 return pci_acs_flags_enabled(pdev, acs_flags);
2406 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2407 * implemented by the remaining PCIe types to indicate peer-to-peer
2408 * capabilities, but only when they are part of a multifunction
2409 * device. The footnote for section 6.12 indicates the specific
2410 * PCIe types included here.
2412 case PCI_EXP_TYPE_ENDPOINT:
2413 case PCI_EXP_TYPE_UPSTREAM:
2414 case PCI_EXP_TYPE_LEG_END:
2415 case PCI_EXP_TYPE_RC_END:
2416 if (!pdev->multifunction)
2419 return pci_acs_flags_enabled(pdev, acs_flags);
2423 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2424 * to single function devices with the exception of downstream ports.
2430 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2431 * @start: starting downstream device
2432 * @end: ending upstream device or NULL to search to the root bus
2433 * @acs_flags: required flags
2435 * Walk up a device tree from start to end testing PCI ACS support. If
2436 * any step along the way does not support the required flags, return false.
2438 bool pci_acs_path_enabled(struct pci_dev *start,
2439 struct pci_dev *end, u16 acs_flags)
2441 struct pci_dev *pdev, *parent = start;
2446 if (!pci_acs_enabled(pdev, acs_flags))
2449 if (pci_is_root_bus(pdev->bus))
2450 return (end == NULL);
2452 parent = pdev->bus->self;
2453 } while (pdev != end);
2459 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2460 * @dev: the PCI device
2461 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2463 * Perform INTx swizzling for a device behind one level of bridge. This is
2464 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2465 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2466 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2467 * the PCI Express Base Specification, Revision 2.1)
2469 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2473 if (pci_ari_enabled(dev->bus))
2476 slot = PCI_SLOT(dev->devfn);
2478 return (((pin - 1) + slot) % 4) + 1;
2481 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2489 while (!pci_is_root_bus(dev->bus)) {
2490 pin = pci_swizzle_interrupt_pin(dev, pin);
2491 dev = dev->bus->self;
2498 * pci_common_swizzle - swizzle INTx all the way to root bridge
2499 * @dev: the PCI device
2500 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2502 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2503 * bridges all the way up to a PCI root bus.
2505 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2509 while (!pci_is_root_bus(dev->bus)) {
2510 pin = pci_swizzle_interrupt_pin(dev, pin);
2511 dev = dev->bus->self;
2514 return PCI_SLOT(dev->devfn);
2516 EXPORT_SYMBOL_GPL(pci_common_swizzle);
2519 * pci_release_region - Release a PCI bar
2520 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2521 * @bar: BAR to release
2523 * Releases the PCI I/O and memory resources previously reserved by a
2524 * successful call to pci_request_region. Call this function only
2525 * after all use of the PCI regions has ceased.
2527 void pci_release_region(struct pci_dev *pdev, int bar)
2529 struct pci_devres *dr;
2531 if (pci_resource_len(pdev, bar) == 0)
2533 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2534 release_region(pci_resource_start(pdev, bar),
2535 pci_resource_len(pdev, bar));
2536 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2537 release_mem_region(pci_resource_start(pdev, bar),
2538 pci_resource_len(pdev, bar));
2540 dr = find_pci_dr(pdev);
2542 dr->region_mask &= ~(1 << bar);
2544 EXPORT_SYMBOL(pci_release_region);
2547 * __pci_request_region - Reserved PCI I/O and memory resource
2548 * @pdev: PCI device whose resources are to be reserved
2549 * @bar: BAR to be reserved
2550 * @res_name: Name to be associated with resource.
2551 * @exclusive: whether the region access is exclusive or not
2553 * Mark the PCI region associated with PCI device @pdev BR @bar as
2554 * being reserved by owner @res_name. Do not access any
2555 * address inside the PCI regions unless this call returns
2558 * If @exclusive is set, then the region is marked so that userspace
2559 * is explicitly not allowed to map the resource via /dev/mem or
2560 * sysfs MMIO access.
2562 * Returns 0 on success, or %EBUSY on error. A warning
2563 * message is also printed on failure.
2565 static int __pci_request_region(struct pci_dev *pdev, int bar,
2566 const char *res_name, int exclusive)
2568 struct pci_devres *dr;
2570 if (pci_resource_len(pdev, bar) == 0)
2573 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2574 if (!request_region(pci_resource_start(pdev, bar),
2575 pci_resource_len(pdev, bar), res_name))
2577 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2578 if (!__request_mem_region(pci_resource_start(pdev, bar),
2579 pci_resource_len(pdev, bar), res_name,
2584 dr = find_pci_dr(pdev);
2586 dr->region_mask |= 1 << bar;
2591 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2592 &pdev->resource[bar]);
2597 * pci_request_region - Reserve PCI I/O and memory resource
2598 * @pdev: PCI device whose resources are to be reserved
2599 * @bar: BAR to be reserved
2600 * @res_name: Name to be associated with resource
2602 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2603 * being reserved by owner @res_name. Do not access any
2604 * address inside the PCI regions unless this call returns
2607 * Returns 0 on success, or %EBUSY on error. A warning
2608 * message is also printed on failure.
2610 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2612 return __pci_request_region(pdev, bar, res_name, 0);
2614 EXPORT_SYMBOL(pci_request_region);
2617 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2618 * @pdev: PCI device whose resources are to be reserved
2619 * @bar: BAR to be reserved
2620 * @res_name: Name to be associated with resource.
2622 * Mark the PCI region associated with PCI device @pdev BR @bar as
2623 * being reserved by owner @res_name. Do not access any
2624 * address inside the PCI regions unless this call returns
2627 * Returns 0 on success, or %EBUSY on error. A warning
2628 * message is also printed on failure.
2630 * The key difference that _exclusive makes it that userspace is
2631 * explicitly not allowed to map the resource via /dev/mem or
2634 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
2635 const char *res_name)
2637 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2639 EXPORT_SYMBOL(pci_request_region_exclusive);
2642 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2643 * @pdev: PCI device whose resources were previously reserved
2644 * @bars: Bitmask of BARs to be released
2646 * Release selected PCI I/O and memory resources previously reserved.
2647 * Call this function only after all use of the PCI regions has ceased.
2649 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2653 for (i = 0; i < 6; i++)
2654 if (bars & (1 << i))
2655 pci_release_region(pdev, i);
2657 EXPORT_SYMBOL(pci_release_selected_regions);
2659 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2660 const char *res_name, int excl)
2664 for (i = 0; i < 6; i++)
2665 if (bars & (1 << i))
2666 if (__pci_request_region(pdev, i, res_name, excl))
2672 if (bars & (1 << i))
2673 pci_release_region(pdev, i);
2680 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2681 * @pdev: PCI device whose resources are to be reserved
2682 * @bars: Bitmask of BARs to be requested
2683 * @res_name: Name to be associated with resource
2685 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2686 const char *res_name)
2688 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2690 EXPORT_SYMBOL(pci_request_selected_regions);
2692 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
2693 const char *res_name)
2695 return __pci_request_selected_regions(pdev, bars, res_name,
2696 IORESOURCE_EXCLUSIVE);
2698 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2701 * pci_release_regions - Release reserved PCI I/O and memory resources
2702 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2704 * Releases all PCI I/O and memory resources previously reserved by a
2705 * successful call to pci_request_regions. Call this function only
2706 * after all use of the PCI regions has ceased.
2709 void pci_release_regions(struct pci_dev *pdev)
2711 pci_release_selected_regions(pdev, (1 << 6) - 1);
2713 EXPORT_SYMBOL(pci_release_regions);
2716 * pci_request_regions - Reserved PCI I/O and memory resources
2717 * @pdev: PCI device whose resources are to be reserved
2718 * @res_name: Name to be associated with resource.
2720 * Mark all PCI regions associated with PCI device @pdev as
2721 * being reserved by owner @res_name. Do not access any
2722 * address inside the PCI regions unless this call returns
2725 * Returns 0 on success, or %EBUSY on error. A warning
2726 * message is also printed on failure.
2728 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2730 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2732 EXPORT_SYMBOL(pci_request_regions);
2735 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2736 * @pdev: PCI device whose resources are to be reserved
2737 * @res_name: Name to be associated with resource.
2739 * Mark all PCI regions associated with PCI device @pdev as
2740 * being reserved by owner @res_name. Do not access any
2741 * address inside the PCI regions unless this call returns
2744 * pci_request_regions_exclusive() will mark the region so that
2745 * /dev/mem and the sysfs MMIO access will not be allowed.
2747 * Returns 0 on success, or %EBUSY on error. A warning
2748 * message is also printed on failure.
2750 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2752 return pci_request_selected_regions_exclusive(pdev,
2753 ((1 << 6) - 1), res_name);
2755 EXPORT_SYMBOL(pci_request_regions_exclusive);
2758 * pci_remap_iospace - Remap the memory mapped I/O space
2759 * @res: Resource describing the I/O space
2760 * @phys_addr: physical address of range to be mapped
2762 * Remap the memory mapped I/O space described by the @res
2763 * and the CPU physical address @phys_addr into virtual address space.
2764 * Only architectures that have memory mapped IO functions defined
2765 * (and the PCI_IOBASE value defined) should call this function.
2767 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
2769 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
2770 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
2772 if (!(res->flags & IORESOURCE_IO))
2775 if (res->end > IO_SPACE_LIMIT)
2778 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
2779 pgprot_device(PAGE_KERNEL));
2781 /* this architecture does not have memory mapped I/O space,
2782 so this function should never be called */
2783 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
2788 static void __pci_set_master(struct pci_dev *dev, bool enable)
2792 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2794 cmd = old_cmd | PCI_COMMAND_MASTER;
2796 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2797 if (cmd != old_cmd) {
2798 dev_dbg(&dev->dev, "%s bus mastering\n",
2799 enable ? "enabling" : "disabling");
2800 pci_write_config_word(dev, PCI_COMMAND, cmd);
2802 dev->is_busmaster = enable;
2806 * pcibios_setup - process "pci=" kernel boot arguments
2807 * @str: string used to pass in "pci=" kernel boot arguments
2809 * Process kernel boot arguments. This is the default implementation.
2810 * Architecture specific implementations can override this as necessary.
2812 char * __weak __init pcibios_setup(char *str)
2818 * pcibios_set_master - enable PCI bus-mastering for device dev
2819 * @dev: the PCI device to enable
2821 * Enables PCI bus-mastering for the device. This is the default
2822 * implementation. Architecture specific implementations can override
2823 * this if necessary.
2825 void __weak pcibios_set_master(struct pci_dev *dev)
2829 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2830 if (pci_is_pcie(dev))
2833 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2835 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2836 else if (lat > pcibios_max_latency)
2837 lat = pcibios_max_latency;
2841 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2845 * pci_set_master - enables bus-mastering for device dev
2846 * @dev: the PCI device to enable
2848 * Enables bus-mastering on the device and calls pcibios_set_master()
2849 * to do the needed arch specific settings.
2851 void pci_set_master(struct pci_dev *dev)
2853 __pci_set_master(dev, true);
2854 pcibios_set_master(dev);
2856 EXPORT_SYMBOL(pci_set_master);
2859 * pci_clear_master - disables bus-mastering for device dev
2860 * @dev: the PCI device to disable
2862 void pci_clear_master(struct pci_dev *dev)
2864 __pci_set_master(dev, false);
2866 EXPORT_SYMBOL(pci_clear_master);
2869 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2870 * @dev: the PCI device for which MWI is to be enabled
2872 * Helper function for pci_set_mwi.
2873 * Originally copied from drivers/net/acenic.c.
2874 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2876 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2878 int pci_set_cacheline_size(struct pci_dev *dev)
2882 if (!pci_cache_line_size)
2885 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2886 equal to or multiple of the right value. */
2887 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2888 if (cacheline_size >= pci_cache_line_size &&
2889 (cacheline_size % pci_cache_line_size) == 0)
2892 /* Write the correct value. */
2893 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2895 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2896 if (cacheline_size == pci_cache_line_size)
2899 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
2900 pci_cache_line_size << 2);
2904 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2907 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2908 * @dev: the PCI device for which MWI is enabled
2910 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2912 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2914 int pci_set_mwi(struct pci_dev *dev)
2916 #ifdef PCI_DISABLE_MWI
2922 rc = pci_set_cacheline_size(dev);
2926 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2927 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
2928 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2929 cmd |= PCI_COMMAND_INVALIDATE;
2930 pci_write_config_word(dev, PCI_COMMAND, cmd);
2935 EXPORT_SYMBOL(pci_set_mwi);
2938 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2939 * @dev: the PCI device for which MWI is enabled
2941 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2942 * Callers are not required to check the return value.
2944 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2946 int pci_try_set_mwi(struct pci_dev *dev)
2948 #ifdef PCI_DISABLE_MWI
2951 return pci_set_mwi(dev);
2954 EXPORT_SYMBOL(pci_try_set_mwi);
2957 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2958 * @dev: the PCI device to disable
2960 * Disables PCI Memory-Write-Invalidate transaction on the device
2962 void pci_clear_mwi(struct pci_dev *dev)
2964 #ifndef PCI_DISABLE_MWI
2967 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2968 if (cmd & PCI_COMMAND_INVALIDATE) {
2969 cmd &= ~PCI_COMMAND_INVALIDATE;
2970 pci_write_config_word(dev, PCI_COMMAND, cmd);
2974 EXPORT_SYMBOL(pci_clear_mwi);
2977 * pci_intx - enables/disables PCI INTx for device dev
2978 * @pdev: the PCI device to operate on
2979 * @enable: boolean: whether to enable or disable PCI INTx
2981 * Enables/disables PCI INTx for device dev
2983 void pci_intx(struct pci_dev *pdev, int enable)
2985 u16 pci_command, new;
2987 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2990 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2992 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2994 if (new != pci_command) {
2995 struct pci_devres *dr;
2997 pci_write_config_word(pdev, PCI_COMMAND, new);
2999 dr = find_pci_dr(pdev);
3000 if (dr && !dr->restore_intx) {
3001 dr->restore_intx = 1;
3002 dr->orig_intx = !enable;
3006 EXPORT_SYMBOL_GPL(pci_intx);
3009 * pci_intx_mask_supported - probe for INTx masking support
3010 * @dev: the PCI device to operate on
3012 * Check if the device dev support INTx masking via the config space
3015 bool pci_intx_mask_supported(struct pci_dev *dev)
3017 bool mask_supported = false;
3020 if (dev->broken_intx_masking)
3023 pci_cfg_access_lock(dev);
3025 pci_read_config_word(dev, PCI_COMMAND, &orig);
3026 pci_write_config_word(dev, PCI_COMMAND,
3027 orig ^ PCI_COMMAND_INTX_DISABLE);
3028 pci_read_config_word(dev, PCI_COMMAND, &new);
3031 * There's no way to protect against hardware bugs or detect them
3032 * reliably, but as long as we know what the value should be, let's
3033 * go ahead and check it.
3035 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3036 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3038 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3039 mask_supported = true;
3040 pci_write_config_word(dev, PCI_COMMAND, orig);
3043 pci_cfg_access_unlock(dev);
3044 return mask_supported;
3046 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3048 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3050 struct pci_bus *bus = dev->bus;
3051 bool mask_updated = true;
3052 u32 cmd_status_dword;
3053 u16 origcmd, newcmd;
3054 unsigned long flags;
3058 * We do a single dword read to retrieve both command and status.
3059 * Document assumptions that make this possible.
3061 BUILD_BUG_ON(PCI_COMMAND % 4);
3062 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3064 raw_spin_lock_irqsave(&pci_lock, flags);
3066 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3068 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3071 * Check interrupt status register to see whether our device
3072 * triggered the interrupt (when masking) or the next IRQ is
3073 * already pending (when unmasking).
3075 if (mask != irq_pending) {
3076 mask_updated = false;
3080 origcmd = cmd_status_dword;
3081 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3083 newcmd |= PCI_COMMAND_INTX_DISABLE;
3084 if (newcmd != origcmd)
3085 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3088 raw_spin_unlock_irqrestore(&pci_lock, flags);
3090 return mask_updated;
3094 * pci_check_and_mask_intx - mask INTx on pending interrupt
3095 * @dev: the PCI device to operate on
3097 * Check if the device dev has its INTx line asserted, mask it and
3098 * return true in that case. False is returned if not interrupt was
3101 bool pci_check_and_mask_intx(struct pci_dev *dev)
3103 return pci_check_and_set_intx_mask(dev, true);
3105 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3108 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3109 * @dev: the PCI device to operate on
3111 * Check if the device dev has its INTx line asserted, unmask it if not
3112 * and return true. False is returned and the mask remains active if
3113 * there was still an interrupt pending.
3115 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3117 return pci_check_and_set_intx_mask(dev, false);
3119 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3121 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3123 return dma_set_max_seg_size(&dev->dev, size);
3125 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3127 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3129 return dma_set_seg_boundary(&dev->dev, mask);
3131 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3134 * pci_wait_for_pending_transaction - waits for pending transaction
3135 * @dev: the PCI device to operate on
3137 * Return 0 if transaction is pending 1 otherwise.
3139 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3141 if (!pci_is_pcie(dev))
3144 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3145 PCI_EXP_DEVSTA_TRPND);
3147 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3149 static int pcie_flr(struct pci_dev *dev, int probe)
3153 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3154 if (!(cap & PCI_EXP_DEVCAP_FLR))
3160 if (!pci_wait_for_pending_transaction(dev))
3161 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3163 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3168 static int pci_af_flr(struct pci_dev *dev, int probe)
3173 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3177 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3178 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3185 * Wait for Transaction Pending bit to clear. A word-aligned test
3186 * is used, so we use the conrol offset rather than status and shift
3187 * the test bit to match.
3189 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3190 PCI_AF_STATUS_TP << 8))
3191 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3193 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3199 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3200 * @dev: Device to reset.
3201 * @probe: If set, only check if the device can be reset this way.
3203 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3204 * unset, it will be reinitialized internally when going from PCI_D3hot to
3205 * PCI_D0. If that's the case and the device is not in a low-power state
3206 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3208 * NOTE: This causes the caller to sleep for twice the device power transition
3209 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3210 * by default (i.e. unless the @dev's d3_delay field has a different value).
3211 * Moreover, only devices in D0 can be reset by this function.
3213 static int pci_pm_reset(struct pci_dev *dev, int probe)
3217 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3220 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3221 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3227 if (dev->current_state != PCI_D0)
3230 csr &= ~PCI_PM_CTRL_STATE_MASK;
3232 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3233 pci_dev_d3_sleep(dev);
3235 csr &= ~PCI_PM_CTRL_STATE_MASK;
3237 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3238 pci_dev_d3_sleep(dev);
3243 void pci_reset_secondary_bus(struct pci_dev *dev)
3247 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3248 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3249 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3251 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3252 * this to 2ms to ensure that we meet the minimum requirement.
3256 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3257 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3260 * Trhfa for conventional PCI is 2^25 clock cycles.
3261 * Assuming a minimum 33MHz clock this results in a 1s
3262 * delay before we can consider subordinate devices to
3263 * be re-initialized. PCIe has some ways to shorten this,
3264 * but we don't make use of them yet.
3269 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3271 pci_reset_secondary_bus(dev);
3275 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3276 * @dev: Bridge device
3278 * Use the bridge control register to assert reset on the secondary bus.
3279 * Devices on the secondary bus are left in power-on state.
3281 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3283 pcibios_reset_secondary_bus(dev);
3285 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3287 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3289 struct pci_dev *pdev;
3291 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3292 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3295 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3302 pci_reset_bridge_secondary_bus(dev->bus->self);
3307 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3311 if (!hotplug || !try_module_get(hotplug->ops->owner))
3314 if (hotplug->ops->reset_slot)
3315 rc = hotplug->ops->reset_slot(hotplug, probe);
3317 module_put(hotplug->ops->owner);
3322 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3324 struct pci_dev *pdev;
3326 if (dev->subordinate || !dev->slot ||
3327 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3330 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3331 if (pdev != dev && pdev->slot == dev->slot)
3334 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3337 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3343 rc = pci_dev_specific_reset(dev, probe);
3347 rc = pcie_flr(dev, probe);
3351 rc = pci_af_flr(dev, probe);
3355 rc = pci_pm_reset(dev, probe);
3359 rc = pci_dev_reset_slot_function(dev, probe);
3363 rc = pci_parent_bus_reset(dev, probe);
3368 static void pci_dev_lock(struct pci_dev *dev)
3370 pci_cfg_access_lock(dev);
3371 /* block PM suspend, driver probe, etc. */
3372 device_lock(&dev->dev);
3375 /* Return 1 on successful lock, 0 on contention */
3376 static int pci_dev_trylock(struct pci_dev *dev)
3378 if (pci_cfg_access_trylock(dev)) {
3379 if (device_trylock(&dev->dev))
3381 pci_cfg_access_unlock(dev);
3387 static void pci_dev_unlock(struct pci_dev *dev)
3389 device_unlock(&dev->dev);
3390 pci_cfg_access_unlock(dev);
3394 * pci_reset_notify - notify device driver of reset
3395 * @dev: device to be notified of reset
3396 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3399 * Must be called prior to device access being disabled and after device
3400 * access is restored.
3402 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3404 const struct pci_error_handlers *err_handler =
3405 dev->driver ? dev->driver->err_handler : NULL;
3406 if (err_handler && err_handler->reset_notify)
3407 err_handler->reset_notify(dev, prepare);
3410 static void pci_dev_save_and_disable(struct pci_dev *dev)
3412 pci_reset_notify(dev, true);
3415 * Wake-up device prior to save. PM registers default to D0 after
3416 * reset and a simple register restore doesn't reliably return
3417 * to a non-D0 state anyway.
3419 pci_set_power_state(dev, PCI_D0);
3421 pci_save_state(dev);
3423 * Disable the device by clearing the Command register, except for
3424 * INTx-disable which is set. This not only disables MMIO and I/O port
3425 * BARs, but also prevents the device from being Bus Master, preventing
3426 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3427 * compliant devices, INTx-disable prevents legacy interrupts.
3429 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3432 static void pci_dev_restore(struct pci_dev *dev)
3434 pci_restore_state(dev);
3435 pci_reset_notify(dev, false);
3438 static int pci_dev_reset(struct pci_dev *dev, int probe)
3445 rc = __pci_dev_reset(dev, probe);
3448 pci_dev_unlock(dev);
3454 * __pci_reset_function - reset a PCI device function
3455 * @dev: PCI device to reset
3457 * Some devices allow an individual function to be reset without affecting
3458 * other functions in the same device. The PCI device must be responsive
3459 * to PCI config space in order to use this function.
3461 * The device function is presumed to be unused when this function is called.
3462 * Resetting the device will make the contents of PCI configuration space
3463 * random, so any caller of this must be prepared to reinitialise the
3464 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3467 * Returns 0 if the device function was successfully reset or negative if the
3468 * device doesn't support resetting a single function.
3470 int __pci_reset_function(struct pci_dev *dev)
3472 return pci_dev_reset(dev, 0);
3474 EXPORT_SYMBOL_GPL(__pci_reset_function);
3477 * __pci_reset_function_locked - reset a PCI device function while holding
3478 * the @dev mutex lock.
3479 * @dev: PCI device to reset
3481 * Some devices allow an individual function to be reset without affecting
3482 * other functions in the same device. The PCI device must be responsive
3483 * to PCI config space in order to use this function.
3485 * The device function is presumed to be unused and the caller is holding
3486 * the device mutex lock when this function is called.
3487 * Resetting the device will make the contents of PCI configuration space
3488 * random, so any caller of this must be prepared to reinitialise the
3489 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3492 * Returns 0 if the device function was successfully reset or negative if the
3493 * device doesn't support resetting a single function.
3495 int __pci_reset_function_locked(struct pci_dev *dev)
3497 return __pci_dev_reset(dev, 0);
3499 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3502 * pci_probe_reset_function - check whether the device can be safely reset
3503 * @dev: PCI device to reset
3505 * Some devices allow an individual function to be reset without affecting
3506 * other functions in the same device. The PCI device must be responsive
3507 * to PCI config space in order to use this function.
3509 * Returns 0 if the device function can be reset or negative if the
3510 * device doesn't support resetting a single function.
3512 int pci_probe_reset_function(struct pci_dev *dev)
3514 return pci_dev_reset(dev, 1);
3518 * pci_reset_function - quiesce and reset a PCI device function
3519 * @dev: PCI device to reset
3521 * Some devices allow an individual function to be reset without affecting
3522 * other functions in the same device. The PCI device must be responsive
3523 * to PCI config space in order to use this function.
3525 * This function does not just reset the PCI portion of a device, but
3526 * clears all the state associated with the device. This function differs
3527 * from __pci_reset_function in that it saves and restores device state
3530 * Returns 0 if the device function was successfully reset or negative if the
3531 * device doesn't support resetting a single function.
3533 int pci_reset_function(struct pci_dev *dev)
3537 rc = pci_dev_reset(dev, 1);
3541 pci_dev_save_and_disable(dev);
3543 rc = pci_dev_reset(dev, 0);
3545 pci_dev_restore(dev);
3549 EXPORT_SYMBOL_GPL(pci_reset_function);
3552 * pci_try_reset_function - quiesce and reset a PCI device function
3553 * @dev: PCI device to reset
3555 * Same as above, except return -EAGAIN if unable to lock device.
3557 int pci_try_reset_function(struct pci_dev *dev)
3561 rc = pci_dev_reset(dev, 1);
3565 pci_dev_save_and_disable(dev);
3567 if (pci_dev_trylock(dev)) {
3568 rc = __pci_dev_reset(dev, 0);
3569 pci_dev_unlock(dev);
3573 pci_dev_restore(dev);
3577 EXPORT_SYMBOL_GPL(pci_try_reset_function);
3579 /* Do any devices on or below this bus prevent a bus reset? */
3580 static bool pci_bus_resetable(struct pci_bus *bus)
3582 struct pci_dev *dev;
3584 list_for_each_entry(dev, &bus->devices, bus_list) {
3585 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3586 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3593 /* Lock devices from the top of the tree down */
3594 static void pci_bus_lock(struct pci_bus *bus)
3596 struct pci_dev *dev;
3598 list_for_each_entry(dev, &bus->devices, bus_list) {
3600 if (dev->subordinate)
3601 pci_bus_lock(dev->subordinate);
3605 /* Unlock devices from the bottom of the tree up */
3606 static void pci_bus_unlock(struct pci_bus *bus)
3608 struct pci_dev *dev;
3610 list_for_each_entry(dev, &bus->devices, bus_list) {
3611 if (dev->subordinate)
3612 pci_bus_unlock(dev->subordinate);
3613 pci_dev_unlock(dev);
3617 /* Return 1 on successful lock, 0 on contention */
3618 static int pci_bus_trylock(struct pci_bus *bus)
3620 struct pci_dev *dev;
3622 list_for_each_entry(dev, &bus->devices, bus_list) {
3623 if (!pci_dev_trylock(dev))
3625 if (dev->subordinate) {
3626 if (!pci_bus_trylock(dev->subordinate)) {
3627 pci_dev_unlock(dev);
3635 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3636 if (dev->subordinate)
3637 pci_bus_unlock(dev->subordinate);
3638 pci_dev_unlock(dev);
3643 /* Do any devices on or below this slot prevent a bus reset? */
3644 static bool pci_slot_resetable(struct pci_slot *slot)
3646 struct pci_dev *dev;
3648 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3649 if (!dev->slot || dev->slot != slot)
3651 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3652 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3659 /* Lock devices from the top of the tree down */
3660 static void pci_slot_lock(struct pci_slot *slot)
3662 struct pci_dev *dev;
3664 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3665 if (!dev->slot || dev->slot != slot)
3668 if (dev->subordinate)
3669 pci_bus_lock(dev->subordinate);
3673 /* Unlock devices from the bottom of the tree up */
3674 static void pci_slot_unlock(struct pci_slot *slot)
3676 struct pci_dev *dev;
3678 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3679 if (!dev->slot || dev->slot != slot)
3681 if (dev->subordinate)
3682 pci_bus_unlock(dev->subordinate);
3683 pci_dev_unlock(dev);
3687 /* Return 1 on successful lock, 0 on contention */
3688 static int pci_slot_trylock(struct pci_slot *slot)
3690 struct pci_dev *dev;
3692 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3693 if (!dev->slot || dev->slot != slot)
3695 if (!pci_dev_trylock(dev))
3697 if (dev->subordinate) {
3698 if (!pci_bus_trylock(dev->subordinate)) {
3699 pci_dev_unlock(dev);
3707 list_for_each_entry_continue_reverse(dev,
3708 &slot->bus->devices, bus_list) {
3709 if (!dev->slot || dev->slot != slot)
3711 if (dev->subordinate)
3712 pci_bus_unlock(dev->subordinate);
3713 pci_dev_unlock(dev);
3718 /* Save and disable devices from the top of the tree down */
3719 static void pci_bus_save_and_disable(struct pci_bus *bus)
3721 struct pci_dev *dev;
3723 list_for_each_entry(dev, &bus->devices, bus_list) {
3724 pci_dev_save_and_disable(dev);
3725 if (dev->subordinate)
3726 pci_bus_save_and_disable(dev->subordinate);
3731 * Restore devices from top of the tree down - parent bridges need to be
3732 * restored before we can get to subordinate devices.
3734 static void pci_bus_restore(struct pci_bus *bus)
3736 struct pci_dev *dev;
3738 list_for_each_entry(dev, &bus->devices, bus_list) {
3739 pci_dev_restore(dev);
3740 if (dev->subordinate)
3741 pci_bus_restore(dev->subordinate);
3745 /* Save and disable devices from the top of the tree down */
3746 static void pci_slot_save_and_disable(struct pci_slot *slot)
3748 struct pci_dev *dev;
3750 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3751 if (!dev->slot || dev->slot != slot)
3753 pci_dev_save_and_disable(dev);
3754 if (dev->subordinate)
3755 pci_bus_save_and_disable(dev->subordinate);
3760 * Restore devices from top of the tree down - parent bridges need to be
3761 * restored before we can get to subordinate devices.
3763 static void pci_slot_restore(struct pci_slot *slot)
3765 struct pci_dev *dev;
3767 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3768 if (!dev->slot || dev->slot != slot)
3770 pci_dev_restore(dev);
3771 if (dev->subordinate)
3772 pci_bus_restore(dev->subordinate);
3776 static int pci_slot_reset(struct pci_slot *slot, int probe)
3780 if (!slot || !pci_slot_resetable(slot))
3784 pci_slot_lock(slot);
3788 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3791 pci_slot_unlock(slot);
3797 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3798 * @slot: PCI slot to probe
3800 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3802 int pci_probe_reset_slot(struct pci_slot *slot)
3804 return pci_slot_reset(slot, 1);
3806 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3809 * pci_reset_slot - reset a PCI slot
3810 * @slot: PCI slot to reset
3812 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3813 * independent of other slots. For instance, some slots may support slot power
3814 * control. In the case of a 1:1 bus to slot architecture, this function may
3815 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3816 * Generally a slot reset should be attempted before a bus reset. All of the
3817 * function of the slot and any subordinate buses behind the slot are reset
3818 * through this function. PCI config space of all devices in the slot and
3819 * behind the slot is saved before and restored after reset.
3821 * Return 0 on success, non-zero on error.
3823 int pci_reset_slot(struct pci_slot *slot)
3827 rc = pci_slot_reset(slot, 1);
3831 pci_slot_save_and_disable(slot);
3833 rc = pci_slot_reset(slot, 0);
3835 pci_slot_restore(slot);
3839 EXPORT_SYMBOL_GPL(pci_reset_slot);
3842 * pci_try_reset_slot - Try to reset a PCI slot
3843 * @slot: PCI slot to reset
3845 * Same as above except return -EAGAIN if the slot cannot be locked
3847 int pci_try_reset_slot(struct pci_slot *slot)
3851 rc = pci_slot_reset(slot, 1);
3855 pci_slot_save_and_disable(slot);
3857 if (pci_slot_trylock(slot)) {
3859 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
3860 pci_slot_unlock(slot);
3864 pci_slot_restore(slot);
3868 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
3870 static int pci_bus_reset(struct pci_bus *bus, int probe)
3872 if (!bus->self || !pci_bus_resetable(bus))
3882 pci_reset_bridge_secondary_bus(bus->self);
3884 pci_bus_unlock(bus);
3890 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3891 * @bus: PCI bus to probe
3893 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3895 int pci_probe_reset_bus(struct pci_bus *bus)
3897 return pci_bus_reset(bus, 1);
3899 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3902 * pci_reset_bus - reset a PCI bus
3903 * @bus: top level PCI bus to reset
3905 * Do a bus reset on the given bus and any subordinate buses, saving
3906 * and restoring state of all devices.
3908 * Return 0 on success, non-zero on error.
3910 int pci_reset_bus(struct pci_bus *bus)
3914 rc = pci_bus_reset(bus, 1);
3918 pci_bus_save_and_disable(bus);
3920 rc = pci_bus_reset(bus, 0);
3922 pci_bus_restore(bus);
3926 EXPORT_SYMBOL_GPL(pci_reset_bus);
3929 * pci_try_reset_bus - Try to reset a PCI bus
3930 * @bus: top level PCI bus to reset
3932 * Same as above except return -EAGAIN if the bus cannot be locked
3934 int pci_try_reset_bus(struct pci_bus *bus)
3938 rc = pci_bus_reset(bus, 1);
3942 pci_bus_save_and_disable(bus);
3944 if (pci_bus_trylock(bus)) {
3946 pci_reset_bridge_secondary_bus(bus->self);
3947 pci_bus_unlock(bus);
3951 pci_bus_restore(bus);
3955 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
3958 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3959 * @dev: PCI device to query
3961 * Returns mmrbc: maximum designed memory read count in bytes
3962 * or appropriate error value.
3964 int pcix_get_max_mmrbc(struct pci_dev *dev)
3969 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3973 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3976 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3978 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3981 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3982 * @dev: PCI device to query
3984 * Returns mmrbc: maximum memory read count in bytes
3985 * or appropriate error value.
3987 int pcix_get_mmrbc(struct pci_dev *dev)
3992 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3996 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3999 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4001 EXPORT_SYMBOL(pcix_get_mmrbc);
4004 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4005 * @dev: PCI device to query
4006 * @mmrbc: maximum memory read count in bytes
4007 * valid values are 512, 1024, 2048, 4096
4009 * If possible sets maximum memory read byte count, some bridges have erratas
4010 * that prevent this.
4012 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4018 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4021 v = ffs(mmrbc) - 10;
4023 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4027 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4030 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4033 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4036 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4038 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4041 cmd &= ~PCI_X_CMD_MAX_READ;
4043 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4048 EXPORT_SYMBOL(pcix_set_mmrbc);
4051 * pcie_get_readrq - get PCI Express read request size
4052 * @dev: PCI device to query
4054 * Returns maximum memory read request in bytes
4055 * or appropriate error value.
4057 int pcie_get_readrq(struct pci_dev *dev)
4061 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4063 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4065 EXPORT_SYMBOL(pcie_get_readrq);
4068 * pcie_set_readrq - set PCI Express maximum memory read request
4069 * @dev: PCI device to query
4070 * @rq: maximum memory read count in bytes
4071 * valid values are 128, 256, 512, 1024, 2048, 4096
4073 * If possible sets maximum memory read request in bytes
4075 int pcie_set_readrq(struct pci_dev *dev, int rq)
4079 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4083 * If using the "performance" PCIe config, we clamp the
4084 * read rq size to the max packet size to prevent the
4085 * host bridge generating requests larger than we can
4088 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4089 int mps = pcie_get_mps(dev);
4095 v = (ffs(rq) - 8) << 12;
4097 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4098 PCI_EXP_DEVCTL_READRQ, v);
4100 EXPORT_SYMBOL(pcie_set_readrq);
4103 * pcie_get_mps - get PCI Express maximum payload size
4104 * @dev: PCI device to query
4106 * Returns maximum payload size in bytes
4108 int pcie_get_mps(struct pci_dev *dev)
4112 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4114 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4116 EXPORT_SYMBOL(pcie_get_mps);
4119 * pcie_set_mps - set PCI Express maximum payload size
4120 * @dev: PCI device to query
4121 * @mps: maximum payload size in bytes
4122 * valid values are 128, 256, 512, 1024, 2048, 4096
4124 * If possible sets maximum payload size
4126 int pcie_set_mps(struct pci_dev *dev, int mps)
4130 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4134 if (v > dev->pcie_mpss)
4138 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4139 PCI_EXP_DEVCTL_PAYLOAD, v);
4141 EXPORT_SYMBOL(pcie_set_mps);
4144 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4145 * @dev: PCI device to query
4146 * @speed: storage for minimum speed
4147 * @width: storage for minimum width
4149 * This function will walk up the PCI device chain and determine the minimum
4150 * link width and speed of the device.
4152 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4153 enum pcie_link_width *width)
4157 *speed = PCI_SPEED_UNKNOWN;
4158 *width = PCIE_LNK_WIDTH_UNKNOWN;
4162 enum pci_bus_speed next_speed;
4163 enum pcie_link_width next_width;
4165 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4169 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4170 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4171 PCI_EXP_LNKSTA_NLW_SHIFT;
4173 if (next_speed < *speed)
4174 *speed = next_speed;
4176 if (next_width < *width)
4177 *width = next_width;
4179 dev = dev->bus->self;
4184 EXPORT_SYMBOL(pcie_get_minimum_link);
4187 * pci_select_bars - Make BAR mask from the type of resource
4188 * @dev: the PCI device for which BAR mask is made
4189 * @flags: resource type mask to be selected
4191 * This helper routine makes bar mask from the type of resource.
4193 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4196 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4197 if (pci_resource_flags(dev, i) & flags)
4201 EXPORT_SYMBOL(pci_select_bars);
4204 * pci_resource_bar - get position of the BAR associated with a resource
4205 * @dev: the PCI device
4206 * @resno: the resource number
4207 * @type: the BAR type to be filled in
4209 * Returns BAR position in config space, or 0 if the BAR is invalid.
4211 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4215 if (resno < PCI_ROM_RESOURCE) {
4216 *type = pci_bar_unknown;
4217 return PCI_BASE_ADDRESS_0 + 4 * resno;
4218 } else if (resno == PCI_ROM_RESOURCE) {
4219 *type = pci_bar_mem32;
4220 return dev->rom_base_reg;
4221 } else if (resno < PCI_BRIDGE_RESOURCES) {
4222 /* device specific resource */
4223 *type = pci_bar_unknown;
4224 reg = pci_iov_resource_bar(dev, resno);
4229 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4233 /* Some architectures require additional programming to enable VGA */
4234 static arch_set_vga_state_t arch_set_vga_state;
4236 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4238 arch_set_vga_state = func; /* NULL disables */
4241 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4242 unsigned int command_bits, u32 flags)
4244 if (arch_set_vga_state)
4245 return arch_set_vga_state(dev, decode, command_bits,
4251 * pci_set_vga_state - set VGA decode state on device and parents if requested
4252 * @dev: the PCI device
4253 * @decode: true = enable decoding, false = disable decoding
4254 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4255 * @flags: traverse ancestors and change bridges
4256 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4258 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4259 unsigned int command_bits, u32 flags)
4261 struct pci_bus *bus;
4262 struct pci_dev *bridge;
4266 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4268 /* ARCH specific VGA enables */
4269 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4273 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4274 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4276 cmd |= command_bits;
4278 cmd &= ~command_bits;
4279 pci_write_config_word(dev, PCI_COMMAND, cmd);
4282 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4289 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4292 cmd |= PCI_BRIDGE_CTL_VGA;
4294 cmd &= ~PCI_BRIDGE_CTL_VGA;
4295 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4303 bool pci_device_is_present(struct pci_dev *pdev)
4307 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4309 EXPORT_SYMBOL_GPL(pci_device_is_present);
4311 void pci_ignore_hotplug(struct pci_dev *dev)
4313 struct pci_dev *bridge = dev->bus->self;
4315 dev->ignore_hotplug = 1;
4316 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4318 bridge->ignore_hotplug = 1;
4320 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4322 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4323 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4324 static DEFINE_SPINLOCK(resource_alignment_lock);
4327 * pci_specified_resource_alignment - get resource alignment specified by user.
4328 * @dev: the PCI device to get
4330 * RETURNS: Resource alignment if it is specified.
4331 * Zero if it is not specified.
4333 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4335 int seg, bus, slot, func, align_order, count;
4336 resource_size_t align = 0;
4339 spin_lock(&resource_alignment_lock);
4340 p = resource_alignment_param;
4343 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4349 if (sscanf(p, "%x:%x:%x.%x%n",
4350 &seg, &bus, &slot, &func, &count) != 4) {
4352 if (sscanf(p, "%x:%x.%x%n",
4353 &bus, &slot, &func, &count) != 3) {
4354 /* Invalid format */
4355 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4361 if (seg == pci_domain_nr(dev->bus) &&
4362 bus == dev->bus->number &&
4363 slot == PCI_SLOT(dev->devfn) &&
4364 func == PCI_FUNC(dev->devfn)) {
4365 if (align_order == -1)
4368 align = 1 << align_order;
4372 if (*p != ';' && *p != ',') {
4373 /* End of param or invalid format */
4378 spin_unlock(&resource_alignment_lock);
4383 * This function disables memory decoding and releases memory resources
4384 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4385 * It also rounds up size to specified alignment.
4386 * Later on, the kernel will assign page-aligned memory resource back
4389 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4393 resource_size_t align, size;
4396 /* check if specified PCI is target device to reassign */
4397 align = pci_specified_resource_alignment(dev);
4401 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4402 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4404 "Can't reassign resources to host bridge.\n");
4409 "Disabling memory decoding and releasing memory resources.\n");
4410 pci_read_config_word(dev, PCI_COMMAND, &command);
4411 command &= ~PCI_COMMAND_MEMORY;
4412 pci_write_config_word(dev, PCI_COMMAND, command);
4414 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4415 r = &dev->resource[i];
4416 if (!(r->flags & IORESOURCE_MEM))
4418 size = resource_size(r);
4422 "Rounding up size of resource #%d to %#llx.\n",
4423 i, (unsigned long long)size);
4425 r->flags |= IORESOURCE_UNSET;
4429 /* Need to disable bridge's resource window,
4430 * to enable the kernel to reassign new resource
4433 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4434 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4435 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4436 r = &dev->resource[i];
4437 if (!(r->flags & IORESOURCE_MEM))
4439 r->flags |= IORESOURCE_UNSET;
4440 r->end = resource_size(r) - 1;
4443 pci_disable_bridge_window(dev);
4447 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4449 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4450 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4451 spin_lock(&resource_alignment_lock);
4452 strncpy(resource_alignment_param, buf, count);
4453 resource_alignment_param[count] = '\0';
4454 spin_unlock(&resource_alignment_lock);
4458 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4461 spin_lock(&resource_alignment_lock);
4462 count = snprintf(buf, size, "%s", resource_alignment_param);
4463 spin_unlock(&resource_alignment_lock);
4467 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4469 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4472 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4473 const char *buf, size_t count)
4475 return pci_set_resource_alignment_param(buf, count);
4478 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4479 pci_resource_alignment_store);
4481 static int __init pci_resource_alignment_sysfs_init(void)
4483 return bus_create_file(&pci_bus_type,
4484 &bus_attr_resource_alignment);
4486 late_initcall(pci_resource_alignment_sysfs_init);
4488 static void pci_no_domains(void)
4490 #ifdef CONFIG_PCI_DOMAINS
4491 pci_domains_supported = 0;
4495 #ifdef CONFIG_PCI_DOMAINS
4496 static atomic_t __domain_nr = ATOMIC_INIT(-1);
4498 int pci_get_new_domain_nr(void)
4500 return atomic_inc_return(&__domain_nr);
4503 #ifdef CONFIG_PCI_DOMAINS_GENERIC
4504 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
4506 static int use_dt_domains = -1;
4507 int domain = of_get_pci_domain_nr(parent->of_node);
4510 * Check DT domain and use_dt_domains values.
4512 * If DT domain property is valid (domain >= 0) and
4513 * use_dt_domains != 0, the DT assignment is valid since this means
4514 * we have not previously allocated a domain number by using
4515 * pci_get_new_domain_nr(); we should also update use_dt_domains to
4516 * 1, to indicate that we have just assigned a domain number from
4519 * If DT domain property value is not valid (ie domain < 0), and we
4520 * have not previously assigned a domain number from DT
4521 * (use_dt_domains != 1) we should assign a domain number by
4524 * pci_get_new_domain_nr()
4526 * API and update the use_dt_domains value to keep track of method we
4527 * are using to assign domain numbers (use_dt_domains = 0).
4529 * All other combinations imply we have a platform that is trying
4530 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
4531 * which is a recipe for domain mishandling and it is prevented by
4532 * invalidating the domain value (domain = -1) and printing a
4533 * corresponding error.
4535 if (domain >= 0 && use_dt_domains) {
4537 } else if (domain < 0 && use_dt_domains != 1) {
4539 domain = pci_get_new_domain_nr();
4541 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
4542 parent->of_node->full_name);
4546 bus->domain_nr = domain;
4552 * pci_ext_cfg_avail - can we access extended PCI config space?
4554 * Returns 1 if we can access PCI extended config space (offsets
4555 * greater than 0xff). This is the default implementation. Architecture
4556 * implementations can override this.
4558 int __weak pci_ext_cfg_avail(void)
4563 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4566 EXPORT_SYMBOL(pci_fixup_cardbus);
4568 static int __init pci_setup(char *str)
4571 char *k = strchr(str, ',');
4574 if (*str && (str = pcibios_setup(str)) && *str) {
4575 if (!strcmp(str, "nomsi")) {
4577 } else if (!strcmp(str, "noaer")) {
4579 } else if (!strncmp(str, "realloc=", 8)) {
4580 pci_realloc_get_opt(str + 8);
4581 } else if (!strncmp(str, "realloc", 7)) {
4582 pci_realloc_get_opt("on");
4583 } else if (!strcmp(str, "nodomains")) {
4585 } else if (!strncmp(str, "noari", 5)) {
4586 pcie_ari_disabled = true;
4587 } else if (!strncmp(str, "cbiosize=", 9)) {
4588 pci_cardbus_io_size = memparse(str + 9, &str);
4589 } else if (!strncmp(str, "cbmemsize=", 10)) {
4590 pci_cardbus_mem_size = memparse(str + 10, &str);
4591 } else if (!strncmp(str, "resource_alignment=", 19)) {
4592 pci_set_resource_alignment_param(str + 19,
4594 } else if (!strncmp(str, "ecrc=", 5)) {
4595 pcie_ecrc_get_policy(str + 5);
4596 } else if (!strncmp(str, "hpiosize=", 9)) {
4597 pci_hotplug_io_size = memparse(str + 9, &str);
4598 } else if (!strncmp(str, "hpmemsize=", 10)) {
4599 pci_hotplug_mem_size = memparse(str + 10, &str);
4600 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4601 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4602 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4603 pcie_bus_config = PCIE_BUS_SAFE;
4604 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4605 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4606 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4607 pcie_bus_config = PCIE_BUS_PEER2PEER;
4608 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4609 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4611 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4619 early_param("pci", pci_setup);