drivers/pinctrl/pinctrl-tz1090.c

   1 /*
   2  * Pinctrl driver for the Toumaz Xenif TZ1090 SoC
   3  *
   4  * Copyright (c) 2013, Imagination Technologies Ltd.
   5  *
   6  * Derived from Tegra code:
   7  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   8  *
   9  * Derived from code:
  10  * Copyright (C) 2010 Google, Inc.
  11  * Copyright (C) 2010 NVIDIA Corporation
  12  * Copyright (C) 2009-2011 ST-Ericsson AB
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms and conditions of the GNU General Public License,
  16  * version 2, as published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/bitops.h>
  25 #include <linux/io.h>
  26 #include <linux/module.h>
  27 #include <linux/of.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pinctrl/machine.h>
  30 #include <linux/pinctrl/pinconf-generic.h>
  31 #include <linux/pinctrl/pinctrl.h>
  32 #include <linux/pinctrl/pinmux.h>
  33 #include <linux/slab.h>
  34 #include <linux/spinlock.h>
  35
  36 /*
  37  * The registers may be shared with other threads/cores, so we need to use the
  38  * metag global lock2 for atomicity.
  39  */
  40 #include <asm/global_lock.h>
  41
  42 #include "core.h"
  43 #include "pinconf.h"
  44
  45 /* Register offsets from bank base address */
  46 #define REG_PINCTRL_SELECT      0x10
  47 #define REG_PINCTRL_SCHMITT     0x90
  48 #define REG_PINCTRL_PU_PD       0xa0
  49 #define REG_PINCTRL_SR          0xc0
  50 #define REG_PINCTRL_DR          0xd0
  51 #define REG_PINCTRL_IF_CTL      0xe0
  52
  53 /* REG_PINCTRL_PU_PD field values */
  54 #define REG_PU_PD_TRISTATE      0
  55 #define REG_PU_PD_UP            1
  56 #define REG_PU_PD_DOWN          2
  57 #define REG_PU_PD_REPEATER      3
  58
  59 /* REG_PINCTRL_DR field values */
  60 #define REG_DR_2mA              0
  61 #define REG_DR_4mA              1
  62 #define REG_DR_8mA              2
  63 #define REG_DR_12mA             3
  64
  65 /**
  66  * struct tz1090_function - TZ1090 pinctrl mux function
  67  * @name:       The name of the function, exported to pinctrl core.
  68  * @groups:     An array of pin groups that may select this function.
  69  * @ngroups:    The number of entries in @groups.
  70  */
  71 struct tz1090_function {
  72         const char              *name;
  73         const char * const      *groups;
  74         unsigned int            ngroups;
  75 };
  76
  77 /**
  78  * struct tz1090_muxdesc - TZ1090 individual mux description
  79  * @funcs:      Function for each mux value.
  80  * @reg:        Mux register offset. 0 if unsupported.
  81  * @bit:        Mux register bit. 0 if unsupported.
  82  * @width:      Mux field width. 0 if unsupported.
  83  *
  84  * A representation of a group of signals (possibly just one signal) in the
  85  * TZ1090 which can be muxed to a set of functions or sub muxes.
  86  */
  87 struct tz1090_muxdesc {
  88         int     funcs[5];
  89         u16     reg;
  90         u8      bit;
  91         u8      width;
  92 };
  93
  94 /**
  95  * struct tz1090_pingroup - TZ1090 pin group
  96  * @name:       Name of pin group.
  97  * @pins:       Array of pin numbers in this pin group.
  98  * @npins:      Number of pins in this pin group.
  99  * @mux:        Top level mux.
 100  * @drv:        Drive control supported, 0 if unsupported.
 101  *              This means Schmitt, Slew, and Drive strength.
 102  * @slw_bit:    Slew register bit. 0 if unsupported.
 103  *              The same bit is used for Schmitt, and Drive (*2).
 104  * @func:       Currently muxed function.
 105  * @func_count: Number of pins using current mux function.
 106  *
 107  * A representation of a group of pins (possibly just one pin) in the TZ1090
 108  * pin controller. Each group allows some parameter or parameters to be
 109  * configured. The most common is mux function selection.
 110  */
 111 struct tz1090_pingroup {
 112         const char              *name;
 113         const unsigned int      *pins;
 114         unsigned int            npins;
 115         struct tz1090_muxdesc   mux;
 116
 117         bool                    drv;
 118         u8                      slw_bit;
 119
 120         int                     func;
 121         unsigned int            func_count;
 122 };
 123
 124 /*
 125  * Most pins affected by the pinmux can also be GPIOs. Define these first.
 126  * These must match how the GPIO driver names/numbers its pins.
 127  */
 128
 129 enum tz1090_pin {
 130         /* GPIO pins */
 131         TZ1090_PIN_SDIO_CLK,
 132         TZ1090_PIN_SDIO_CMD,
 133         TZ1090_PIN_SDIO_D0,
 134         TZ1090_PIN_SDIO_D1,
 135         TZ1090_PIN_SDIO_D2,
 136         TZ1090_PIN_SDIO_D3,
 137         TZ1090_PIN_SDH_CD,
 138         TZ1090_PIN_SDH_WP,
 139         TZ1090_PIN_SPI0_MCLK,
 140         TZ1090_PIN_SPI0_CS0,
 141         TZ1090_PIN_SPI0_CS1,
 142         TZ1090_PIN_SPI0_CS2,
 143         TZ1090_PIN_SPI0_DOUT,
 144         TZ1090_PIN_SPI0_DIN,
 145         TZ1090_PIN_SPI1_MCLK,
 146         TZ1090_PIN_SPI1_CS0,
 147         TZ1090_PIN_SPI1_CS1,
 148         TZ1090_PIN_SPI1_CS2,
 149         TZ1090_PIN_SPI1_DOUT,
 150         TZ1090_PIN_SPI1_DIN,
 151         TZ1090_PIN_UART0_RXD,
 152         TZ1090_PIN_UART0_TXD,
 153         TZ1090_PIN_UART0_CTS,
 154         TZ1090_PIN_UART0_RTS,
 155         TZ1090_PIN_UART1_RXD,
 156         TZ1090_PIN_UART1_TXD,
 157         TZ1090_PIN_SCB0_SDAT,
 158         TZ1090_PIN_SCB0_SCLK,
 159         TZ1090_PIN_SCB1_SDAT,
 160         TZ1090_PIN_SCB1_SCLK,
 161         TZ1090_PIN_SCB2_SDAT,
 162         TZ1090_PIN_SCB2_SCLK,
 163         TZ1090_PIN_I2S_MCLK,
 164         TZ1090_PIN_I2S_BCLK_OUT,
 165         TZ1090_PIN_I2S_LRCLK_OUT,
 166         TZ1090_PIN_I2S_DOUT0,
 167         TZ1090_PIN_I2S_DOUT1,
 168         TZ1090_PIN_I2S_DOUT2,
 169         TZ1090_PIN_I2S_DIN,
 170         TZ1090_PIN_PDM_A,
 171         TZ1090_PIN_PDM_B,
 172         TZ1090_PIN_PDM_C,
 173         TZ1090_PIN_PDM_D,
 174         TZ1090_PIN_TFT_RED0,
 175         TZ1090_PIN_TFT_RED1,
 176         TZ1090_PIN_TFT_RED2,
 177         TZ1090_PIN_TFT_RED3,
 178         TZ1090_PIN_TFT_RED4,
 179         TZ1090_PIN_TFT_RED5,
 180         TZ1090_PIN_TFT_RED6,
 181         TZ1090_PIN_TFT_RED7,
 182         TZ1090_PIN_TFT_GREEN0,
 183         TZ1090_PIN_TFT_GREEN1,
 184         TZ1090_PIN_TFT_GREEN2,
 185         TZ1090_PIN_TFT_GREEN3,
 186         TZ1090_PIN_TFT_GREEN4,
 187         TZ1090_PIN_TFT_GREEN5,
 188         TZ1090_PIN_TFT_GREEN6,
 189         TZ1090_PIN_TFT_GREEN7,
 190         TZ1090_PIN_TFT_BLUE0,
 191         TZ1090_PIN_TFT_BLUE1,
 192         TZ1090_PIN_TFT_BLUE2,
 193         TZ1090_PIN_TFT_BLUE3,
 194         TZ1090_PIN_TFT_BLUE4,
 195         TZ1090_PIN_TFT_BLUE5,
 196         TZ1090_PIN_TFT_BLUE6,
 197         TZ1090_PIN_TFT_BLUE7,
 198         TZ1090_PIN_TFT_VDDEN_GD,
 199         TZ1090_PIN_TFT_PANELCLK,
 200         TZ1090_PIN_TFT_BLANK_LS,
 201         TZ1090_PIN_TFT_VSYNC_NS,
 202         TZ1090_PIN_TFT_HSYNC_NR,
 203         TZ1090_PIN_TFT_VD12ACB,
 204         TZ1090_PIN_TFT_PWRSAVE,
 205         TZ1090_PIN_TX_ON,
 206         TZ1090_PIN_RX_ON,
 207         TZ1090_PIN_PLL_ON,
 208         TZ1090_PIN_PA_ON,
 209         TZ1090_PIN_RX_HP,
 210         TZ1090_PIN_GAIN0,
 211         TZ1090_PIN_GAIN1,
 212         TZ1090_PIN_GAIN2,
 213         TZ1090_PIN_GAIN3,
 214         TZ1090_PIN_GAIN4,
 215         TZ1090_PIN_GAIN5,
 216         TZ1090_PIN_GAIN6,
 217         TZ1090_PIN_GAIN7,
 218         TZ1090_PIN_ANT_SEL0,
 219         TZ1090_PIN_ANT_SEL1,
 220         TZ1090_PIN_SDH_CLK_IN,
 221
 222         /* Non-GPIO pins */
 223         TZ1090_PIN_TCK,
 224         TZ1090_PIN_TRST,
 225         TZ1090_PIN_TDI,
 226         TZ1090_PIN_TDO,
 227         TZ1090_PIN_TMS,
 228         TZ1090_PIN_CLK_OUT0,
 229         TZ1090_PIN_CLK_OUT1,
 230
 231         NUM_GPIOS = TZ1090_PIN_TCK,
 232 };
 233
 234 /* Pin names */
 235
 236 static const struct pinctrl_pin_desc tz1090_pins[] = {
 237         /* GPIO pins */
 238         PINCTRL_PIN(TZ1090_PIN_SDIO_CLK,        "sdio_clk"),
 239         PINCTRL_PIN(TZ1090_PIN_SDIO_CMD,        "sdio_cmd"),
 240         PINCTRL_PIN(TZ1090_PIN_SDIO_D0,         "sdio_d0"),
 241         PINCTRL_PIN(TZ1090_PIN_SDIO_D1,         "sdio_d1"),
 242         PINCTRL_PIN(TZ1090_PIN_SDIO_D2,         "sdio_d2"),
 243         PINCTRL_PIN(TZ1090_PIN_SDIO_D3,         "sdio_d3"),
 244         PINCTRL_PIN(TZ1090_PIN_SDH_CD,          "sdh_cd"),
 245         PINCTRL_PIN(TZ1090_PIN_SDH_WP,          "sdh_wp"),
 246         PINCTRL_PIN(TZ1090_PIN_SPI0_MCLK,       "spi0_mclk"),
 247         PINCTRL_PIN(TZ1090_PIN_SPI0_CS0,        "spi0_cs0"),
 248         PINCTRL_PIN(TZ1090_PIN_SPI0_CS1,        "spi0_cs1"),
 249         PINCTRL_PIN(TZ1090_PIN_SPI0_CS2,        "spi0_cs2"),
 250         PINCTRL_PIN(TZ1090_PIN_SPI0_DOUT,       "spi0_dout"),
 251         PINCTRL_PIN(TZ1090_PIN_SPI0_DIN,        "spi0_din"),
 252         PINCTRL_PIN(TZ1090_PIN_SPI1_MCLK,       "spi1_mclk"),
 253         PINCTRL_PIN(TZ1090_PIN_SPI1_CS0,        "spi1_cs0"),
 254         PINCTRL_PIN(TZ1090_PIN_SPI1_CS1,        "spi1_cs1"),
 255         PINCTRL_PIN(TZ1090_PIN_SPI1_CS2,        "spi1_cs2"),
 256         PINCTRL_PIN(TZ1090_PIN_SPI1_DOUT,       "spi1_dout"),
 257         PINCTRL_PIN(TZ1090_PIN_SPI1_DIN,        "spi1_din"),
 258         PINCTRL_PIN(TZ1090_PIN_UART0_RXD,       "uart0_rxd"),
 259         PINCTRL_PIN(TZ1090_PIN_UART0_TXD,       "uart0_txd"),
 260         PINCTRL_PIN(TZ1090_PIN_UART0_CTS,       "uart0_cts"),
 261         PINCTRL_PIN(TZ1090_PIN_UART0_RTS,       "uart0_rts"),
 262         PINCTRL_PIN(TZ1090_PIN_UART1_RXD,       "uart1_rxd"),
 263         PINCTRL_PIN(TZ1090_PIN_UART1_TXD,       "uart1_txd"),
 264         PINCTRL_PIN(TZ1090_PIN_SCB0_SDAT,       "scb0_sdat"),
 265         PINCTRL_PIN(TZ1090_PIN_SCB0_SCLK,       "scb0_sclk"),
 266         PINCTRL_PIN(TZ1090_PIN_SCB1_SDAT,       "scb1_sdat"),
 267         PINCTRL_PIN(TZ1090_PIN_SCB1_SCLK,       "scb1_sclk"),
 268         PINCTRL_PIN(TZ1090_PIN_SCB2_SDAT,       "scb2_sdat"),
 269         PINCTRL_PIN(TZ1090_PIN_SCB2_SCLK,       "scb2_sclk"),
 270         PINCTRL_PIN(TZ1090_PIN_I2S_MCLK,        "i2s_mclk"),
 271         PINCTRL_PIN(TZ1090_PIN_I2S_BCLK_OUT,    "i2s_bclk_out"),
 272         PINCTRL_PIN(TZ1090_PIN_I2S_LRCLK_OUT,   "i2s_lrclk_out"),
 273         PINCTRL_PIN(TZ1090_PIN_I2S_DOUT0,       "i2s_dout0"),
 274         PINCTRL_PIN(TZ1090_PIN_I2S_DOUT1,       "i2s_dout1"),
 275         PINCTRL_PIN(TZ1090_PIN_I2S_DOUT2,       "i2s_dout2"),
 276         PINCTRL_PIN(TZ1090_PIN_I2S_DIN,         "i2s_din"),
 277         PINCTRL_PIN(TZ1090_PIN_PDM_A,           "pdm_a"),
 278         PINCTRL_PIN(TZ1090_PIN_PDM_B,           "pdm_b"),
 279         PINCTRL_PIN(TZ1090_PIN_PDM_C,           "pdm_c"),
 280         PINCTRL_PIN(TZ1090_PIN_PDM_D,           "pdm_d"),
 281         PINCTRL_PIN(TZ1090_PIN_TFT_RED0,        "tft_red0"),
 282         PINCTRL_PIN(TZ1090_PIN_TFT_RED1,        "tft_red1"),
 283         PINCTRL_PIN(TZ1090_PIN_TFT_RED2,        "tft_red2"),
 284         PINCTRL_PIN(TZ1090_PIN_TFT_RED3,        "tft_red3"),
 285         PINCTRL_PIN(TZ1090_PIN_TFT_RED4,        "tft_red4"),
 286         PINCTRL_PIN(TZ1090_PIN_TFT_RED5,        "tft_red5"),
 287         PINCTRL_PIN(TZ1090_PIN_TFT_RED6,        "tft_red6"),
 288         PINCTRL_PIN(TZ1090_PIN_TFT_RED7,        "tft_red7"),
 289         PINCTRL_PIN(TZ1090_PIN_TFT_GREEN0,      "tft_green0"),
 290         PINCTRL_PIN(TZ1090_PIN_TFT_GREEN1,      "tft_green1"),
 291         PINCTRL_PIN(TZ1090_PIN_TFT_GREEN2,      "tft_green2"),
 292         PINCTRL_PIN(TZ1090_PIN_TFT_GREEN3,      "tft_green3"),
 293         PINCTRL_PIN(TZ1090_PIN_TFT_GREEN4,      "tft_green4"),
 294         PINCTRL_PIN(TZ1090_PIN_TFT_GREEN5,      "tft_green5"),
 295         PINCTRL_PIN(TZ1090_PIN_TFT_GREEN6,      "tft_green6"),
 296         PINCTRL_PIN(TZ1090_PIN_TFT_GREEN7,      "tft_green7"),
 297         PINCTRL_PIN(TZ1090_PIN_TFT_BLUE0,       "tft_blue0"),
 298         PINCTRL_PIN(TZ1090_PIN_TFT_BLUE1,       "tft_blue1"),
 299         PINCTRL_PIN(TZ1090_PIN_TFT_BLUE2,       "tft_blue2"),
 300         PINCTRL_PIN(TZ1090_PIN_TFT_BLUE3,       "tft_blue3"),
 301         PINCTRL_PIN(TZ1090_PIN_TFT_BLUE4,       "tft_blue4"),
 302         PINCTRL_PIN(TZ1090_PIN_TFT_BLUE5,       "tft_blue5"),
 303         PINCTRL_PIN(TZ1090_PIN_TFT_BLUE6,       "tft_blue6"),
 304         PINCTRL_PIN(TZ1090_PIN_TFT_BLUE7,       "tft_blue7"),
 305         PINCTRL_PIN(TZ1090_PIN_TFT_VDDEN_GD,    "tft_vdden_gd"),
 306         PINCTRL_PIN(TZ1090_PIN_TFT_PANELCLK,    "tft_panelclk"),
 307         PINCTRL_PIN(TZ1090_PIN_TFT_BLANK_LS,    "tft_blank_ls"),
 308         PINCTRL_PIN(TZ1090_PIN_TFT_VSYNC_NS,    "tft_vsync_ns"),
 309         PINCTRL_PIN(TZ1090_PIN_TFT_HSYNC_NR,    "tft_hsync_nr"),
 310         PINCTRL_PIN(TZ1090_PIN_TFT_VD12ACB,     "tft_vd12acb"),
 311         PINCTRL_PIN(TZ1090_PIN_TFT_PWRSAVE,     "tft_pwrsave"),
 312         PINCTRL_PIN(TZ1090_PIN_TX_ON,           "tx_on"),
 313         PINCTRL_PIN(TZ1090_PIN_RX_ON,           "rx_on"),
 314         PINCTRL_PIN(TZ1090_PIN_PLL_ON,          "pll_on"),
 315         PINCTRL_PIN(TZ1090_PIN_PA_ON,           "pa_on"),
 316         PINCTRL_PIN(TZ1090_PIN_RX_HP,           "rx_hp"),
 317         PINCTRL_PIN(TZ1090_PIN_GAIN0,           "gain0"),
 318         PINCTRL_PIN(TZ1090_PIN_GAIN1,           "gain1"),
 319         PINCTRL_PIN(TZ1090_PIN_GAIN2,           "gain2"),
 320         PINCTRL_PIN(TZ1090_PIN_GAIN3,           "gain3"),
 321         PINCTRL_PIN(TZ1090_PIN_GAIN4,           "gain4"),
 322         PINCTRL_PIN(TZ1090_PIN_GAIN5,           "gain5"),
 323         PINCTRL_PIN(TZ1090_PIN_GAIN6,           "gain6"),
 324         PINCTRL_PIN(TZ1090_PIN_GAIN7,           "gain7"),
 325         PINCTRL_PIN(TZ1090_PIN_ANT_SEL0,        "ant_sel0"),
 326         PINCTRL_PIN(TZ1090_PIN_ANT_SEL1,        "ant_sel1"),
 327         PINCTRL_PIN(TZ1090_PIN_SDH_CLK_IN,      "sdh_clk_in"),
 328
 329         /* Non-GPIO pins */
 330         PINCTRL_PIN(TZ1090_PIN_TCK,             "tck"),
 331         PINCTRL_PIN(TZ1090_PIN_TRST,            "trst"),
 332         PINCTRL_PIN(TZ1090_PIN_TDI,             "tdi"),
 333         PINCTRL_PIN(TZ1090_PIN_TDO,             "tdo"),
 334         PINCTRL_PIN(TZ1090_PIN_TMS,             "tms"),
 335         PINCTRL_PIN(TZ1090_PIN_CLK_OUT0,        "clk_out0"),
 336         PINCTRL_PIN(TZ1090_PIN_CLK_OUT1,        "clk_out1"),
 337 };
 338
 339 /* Pins in each pin group */
 340
 341 static const unsigned int spi1_cs2_pins[] = {
 342         TZ1090_PIN_SPI1_CS2,
 343 };
 344
 345 static const unsigned int pdm_d_pins[] = {
 346         TZ1090_PIN_PDM_D,
 347 };
 348
 349 static const unsigned int tft_pins[] = {
 350         TZ1090_PIN_TFT_RED0,
 351         TZ1090_PIN_TFT_RED1,
 352         TZ1090_PIN_TFT_RED2,
 353         TZ1090_PIN_TFT_RED3,
 354         TZ1090_PIN_TFT_RED4,
 355         TZ1090_PIN_TFT_RED5,
 356         TZ1090_PIN_TFT_RED6,
 357         TZ1090_PIN_TFT_RED7,
 358         TZ1090_PIN_TFT_GREEN0,
 359         TZ1090_PIN_TFT_GREEN1,
 360         TZ1090_PIN_TFT_GREEN2,
 361         TZ1090_PIN_TFT_GREEN3,
 362         TZ1090_PIN_TFT_GREEN4,
 363         TZ1090_PIN_TFT_GREEN5,
 364         TZ1090_PIN_TFT_GREEN6,
 365         TZ1090_PIN_TFT_GREEN7,
 366         TZ1090_PIN_TFT_BLUE0,
 367         TZ1090_PIN_TFT_BLUE1,
 368         TZ1090_PIN_TFT_BLUE2,
 369         TZ1090_PIN_TFT_BLUE3,
 370         TZ1090_PIN_TFT_BLUE4,
 371         TZ1090_PIN_TFT_BLUE5,
 372         TZ1090_PIN_TFT_BLUE6,
 373         TZ1090_PIN_TFT_BLUE7,
 374         TZ1090_PIN_TFT_VDDEN_GD,
 375         TZ1090_PIN_TFT_PANELCLK,
 376         TZ1090_PIN_TFT_BLANK_LS,
 377         TZ1090_PIN_TFT_VSYNC_NS,
 378         TZ1090_PIN_TFT_HSYNC_NR,
 379         TZ1090_PIN_TFT_VD12ACB,
 380         TZ1090_PIN_TFT_PWRSAVE,
 381 };
 382
 383 static const unsigned int afe_pins[] = {
 384         TZ1090_PIN_TX_ON,
 385         TZ1090_PIN_RX_ON,
 386         TZ1090_PIN_PLL_ON,
 387         TZ1090_PIN_PA_ON,
 388         TZ1090_PIN_RX_HP,
 389         TZ1090_PIN_ANT_SEL0,
 390         TZ1090_PIN_ANT_SEL1,
 391         TZ1090_PIN_GAIN0,
 392         TZ1090_PIN_GAIN1,
 393         TZ1090_PIN_GAIN2,
 394         TZ1090_PIN_GAIN3,
 395         TZ1090_PIN_GAIN4,
 396         TZ1090_PIN_GAIN5,
 397         TZ1090_PIN_GAIN6,
 398         TZ1090_PIN_GAIN7,
 399 };
 400
 401 static const unsigned int sdio_pins[] = {
 402         TZ1090_PIN_SDIO_CLK,
 403         TZ1090_PIN_SDIO_CMD,
 404         TZ1090_PIN_SDIO_D0,
 405         TZ1090_PIN_SDIO_D1,
 406         TZ1090_PIN_SDIO_D2,
 407         TZ1090_PIN_SDIO_D3,
 408 };
 409
 410 static const unsigned int sdh_pins[] = {
 411         TZ1090_PIN_SDH_CD,
 412         TZ1090_PIN_SDH_WP,
 413         TZ1090_PIN_SDH_CLK_IN,
 414 };
 415
 416 static const unsigned int spi0_pins[] = {
 417         TZ1090_PIN_SPI0_MCLK,
 418         TZ1090_PIN_SPI0_CS0,
 419         TZ1090_PIN_SPI0_CS1,
 420         TZ1090_PIN_SPI0_CS2,
 421         TZ1090_PIN_SPI0_DOUT,
 422         TZ1090_PIN_SPI0_DIN,
 423 };
 424
 425 static const unsigned int spi1_pins[] = {
 426         TZ1090_PIN_SPI1_MCLK,
 427         TZ1090_PIN_SPI1_CS0,
 428         TZ1090_PIN_SPI1_CS1,
 429         TZ1090_PIN_SPI1_CS2,
 430         TZ1090_PIN_SPI1_DOUT,
 431         TZ1090_PIN_SPI1_DIN,
 432 };
 433
 434 static const unsigned int uart0_pins[] = {
 435         TZ1090_PIN_UART0_RTS,
 436         TZ1090_PIN_UART0_CTS,
 437         TZ1090_PIN_UART0_TXD,
 438         TZ1090_PIN_UART0_RXD,
 439 };
 440
 441 static const unsigned int uart1_pins[] = {
 442         TZ1090_PIN_UART1_TXD,
 443         TZ1090_PIN_UART1_RXD,
 444 };
 445
 446 static const unsigned int uart_pins[] = {
 447         TZ1090_PIN_UART1_TXD,
 448         TZ1090_PIN_UART1_RXD,
 449         TZ1090_PIN_UART0_RTS,
 450         TZ1090_PIN_UART0_CTS,
 451         TZ1090_PIN_UART0_TXD,
 452         TZ1090_PIN_UART0_RXD,
 453 };
 454
 455 static const unsigned int scb0_pins[] = {
 456         TZ1090_PIN_SCB0_SDAT,
 457         TZ1090_PIN_SCB0_SCLK,
 458 };
 459
 460 static const unsigned int scb1_pins[] = {
 461         TZ1090_PIN_SCB1_SDAT,
 462         TZ1090_PIN_SCB1_SCLK,
 463 };
 464
 465 static const unsigned int scb2_pins[] = {
 466         TZ1090_PIN_SCB2_SDAT,
 467         TZ1090_PIN_SCB2_SCLK,
 468 };
 469
 470 static const unsigned int i2s_pins[] = {
 471         TZ1090_PIN_I2S_MCLK,
 472         TZ1090_PIN_I2S_BCLK_OUT,
 473         TZ1090_PIN_I2S_LRCLK_OUT,
 474         TZ1090_PIN_I2S_DOUT0,
 475         TZ1090_PIN_I2S_DOUT1,
 476         TZ1090_PIN_I2S_DOUT2,
 477         TZ1090_PIN_I2S_DIN,
 478 };
 479
 480 static const unsigned int jtag_pins[] = {
 481         TZ1090_PIN_TCK,
 482         TZ1090_PIN_TRST,
 483         TZ1090_PIN_TDI,
 484         TZ1090_PIN_TDO,
 485         TZ1090_PIN_TMS,
 486 };
 487
 488 /* Pins in each drive pin group */
 489
 490 static const unsigned int drive_sdio_pins[] = {
 491         TZ1090_PIN_SDIO_CLK,
 492         TZ1090_PIN_SDIO_CMD,
 493         TZ1090_PIN_SDIO_D0,
 494         TZ1090_PIN_SDIO_D1,
 495         TZ1090_PIN_SDIO_D2,
 496         TZ1090_PIN_SDIO_D3,
 497         TZ1090_PIN_SDH_WP,
 498         TZ1090_PIN_SDH_CD,
 499         TZ1090_PIN_SDH_CLK_IN,
 500 };
 501
 502 static const unsigned int drive_i2s_pins[] = {
 503         TZ1090_PIN_CLK_OUT1,
 504         TZ1090_PIN_I2S_DIN,
 505         TZ1090_PIN_I2S_DOUT0,
 506         TZ1090_PIN_I2S_DOUT1,
 507         TZ1090_PIN_I2S_DOUT2,
 508         TZ1090_PIN_I2S_LRCLK_OUT,
 509         TZ1090_PIN_I2S_BCLK_OUT,
 510         TZ1090_PIN_I2S_MCLK,
 511 };
 512
 513 static const unsigned int drive_scb0_pins[] = {
 514         TZ1090_PIN_SCB0_SCLK,
 515         TZ1090_PIN_SCB0_SDAT,
 516         TZ1090_PIN_PDM_D,
 517         TZ1090_PIN_PDM_C,
 518 };
 519
 520 static const unsigned int drive_pdm_pins[] = {
 521         TZ1090_PIN_CLK_OUT0,
 522         TZ1090_PIN_PDM_B,
 523         TZ1090_PIN_PDM_A,
 524 };
 525
 526 /* Pin groups each function can be muxed to */
 527
 528 /*
 529  * The magic "perip" function allows otherwise non-muxing pins to be enabled in
 530  * peripheral mode.
 531  */
 532 static const char * const perip_groups[] = {
 533         /* non-muxing convenient gpio pingroups */
 534         "uart",
 535         "uart0",
 536         "uart1",
 537         "spi0",
 538         "spi1",
 539         "scb0",
 540         "scb1",
 541         "scb2",
 542         "i2s",
 543         /* individual pins not part of a pin mux group */
 544         "spi0_mclk",
 545         "spi0_cs0",
 546         "spi0_cs1",
 547         "spi0_cs2",
 548         "spi0_dout",
 549         "spi0_din",
 550         "spi1_mclk",
 551         "spi1_cs0",
 552         "spi1_cs1",
 553         "spi1_dout",
 554         "spi1_din",
 555         "uart0_rxd",
 556         "uart0_txd",
 557         "uart0_cts",
 558         "uart0_rts",
 559         "uart1_rxd",
 560         "uart1_txd",
 561         "scb0_sdat",
 562         "scb0_sclk",
 563         "scb1_sdat",
 564         "scb1_sclk",
 565         "scb2_sdat",
 566         "scb2_sclk",
 567         "i2s_mclk",
 568         "i2s_bclk_out",
 569         "i2s_lrclk_out",
 570         "i2s_dout0",
 571         "i2s_dout1",
 572         "i2s_dout2",
 573         "i2s_din",
 574         "pdm_a",
 575         "pdm_b",
 576         "pdm_c",
 577 };
 578
 579 static const char * const sdh_sdio_groups[] = {
 580         "sdh",
 581         "sdio",
 582         /* sdh pins */
 583         "sdh_cd",
 584         "sdh_wp",
 585         "sdh_clk_in",
 586         /* sdio pins */
 587         "sdio_clk",
 588         "sdio_cmd",
 589         "sdio_d0",
 590         "sdio_d1",
 591         "sdio_d2",
 592         "sdio_d3",
 593 };
 594
 595 static const char * const spi1_cs2_groups[] = {
 596         "spi1_cs2",
 597 };
 598
 599 static const char * const pdm_dac_groups[] = {
 600         "pdm_d",
 601 };
 602
 603 static const char * const usb_vbus_groups[] = {
 604         "spi1_cs2",
 605         "pdm_d",
 606 };
 607
 608 static const char * const afe_groups[] = {
 609         "afe",
 610         /* afe pins */
 611         "tx_on",
 612         "rx_on",
 613         "pll_on",
 614         "pa_on",
 615         "rx_hp",
 616         "ant_sel0",
 617         "ant_sel1",
 618         "gain0",
 619         "gain1",
 620         "gain2",
 621         "gain3",
 622         "gain4",
 623         "gain5",
 624         "gain6",
 625         "gain7",
 626 };
 627
 628 static const char * const tft_groups[] = {
 629         "tft",
 630         /* tft pins */
 631         "tft_red0",
 632         "tft_red1",
 633         "tft_red2",
 634         "tft_red3",
 635         "tft_red4",
 636         "tft_red5",
 637         "tft_red6",
 638         "tft_red7",
 639         "tft_green0",
 640         "tft_green1",
 641         "tft_green2",
 642         "tft_green3",
 643         "tft_green4",
 644         "tft_green5",
 645         "tft_green6",
 646         "tft_green7",
 647         "tft_blue0",
 648         "tft_blue1",
 649         "tft_blue2",
 650         "tft_blue3",
 651         "tft_blue4",
 652         "tft_blue5",
 653         "tft_blue6",
 654         "tft_blue7",
 655         "tft_vdden_gd",
 656         "tft_panelclk",
 657         "tft_blank_ls",
 658         "tft_vsync_ns",
 659         "tft_hsync_nr",
 660         "tft_vd12acb",
 661         "tft_pwrsave",
 662 };
 663
 664 /* Mux functions that can be used by a mux */
 665
 666 enum tz1090_mux {
 667         /* internal placeholder */
 668         TZ1090_MUX_NA = -1,
 669         /* magic per-non-muxing-GPIO-pin peripheral mode mux */
 670         TZ1090_MUX_PERIP,
 671         /* SDH/SDIO mux */
 672         TZ1090_MUX_SDH,
 673         TZ1090_MUX_SDIO,
 674         /* USB_VBUS muxes */
 675         TZ1090_MUX_SPI1_CS2,
 676         TZ1090_MUX_PDM_DAC,
 677         TZ1090_MUX_USB_VBUS,
 678         /* AFE mux */
 679         TZ1090_MUX_AFE,
 680         TZ1090_MUX_TS_OUT_0,
 681         /* EXT_DAC mux */
 682         TZ1090_MUX_DAC,
 683         TZ1090_MUX_NOT_IQADC_STB,
 684         TZ1090_MUX_IQDAC_STB,
 685         /* TFT mux */
 686         TZ1090_MUX_TFT,
 687         TZ1090_MUX_EXT_DAC,
 688         TZ1090_MUX_TS_OUT_1,
 689         TZ1090_MUX_LCD_TRACE,
 690         TZ1090_MUX_PHY_RINGOSC,
 691 };
 692
 693 #define FUNCTION(mux, fname, group)                     \
 694         [(TZ1090_MUX_ ## mux)] = {                      \
 695                 .name = #fname,                         \
 696                 .groups = group##_groups,               \
 697                 .ngroups = ARRAY_SIZE(group##_groups),  \
 698         }
 699 /* For intermediate functions with submuxes */
 700 #define NULL_FUNCTION(mux, fname)                       \
 701         [(TZ1090_MUX_ ## mux)] = {                      \
 702                 .name = #fname,                         \
 703         }
 704
 705 /* Must correlate with enum tz1090_mux */
 706 static const struct tz1090_function tz1090_functions[] = {
 707         /*       FUNCTION       function name   pingroups */
 708         FUNCTION(PERIP,         perip,          perip),
 709         FUNCTION(SDH,           sdh,            sdh_sdio),
 710         FUNCTION(SDIO,          sdio,           sdh_sdio),
 711         FUNCTION(SPI1_CS2,      spi1_cs2,       spi1_cs2),
 712         FUNCTION(PDM_DAC,       pdm_dac,        pdm_dac),
 713         FUNCTION(USB_VBUS,      usb_vbus,       usb_vbus),
 714         FUNCTION(AFE,           afe,            afe),
 715         FUNCTION(TS_OUT_0,      ts_out_0,       afe),
 716         FUNCTION(DAC,           ext_dac,        tft),
 717         FUNCTION(NOT_IQADC_STB, not_iqadc_stb,  tft),
 718         FUNCTION(IQDAC_STB,     iqdac_stb,      tft),
 719         FUNCTION(TFT,           tft,            tft),
 720         NULL_FUNCTION(EXT_DAC,  _ext_dac),
 721         FUNCTION(TS_OUT_1,      ts_out_1,       tft),
 722         FUNCTION(LCD_TRACE,     lcd_trace,      tft),
 723         FUNCTION(PHY_RINGOSC,   phy_ringosc,    tft),
 724 };
 725
 726 /* Sub muxes */
 727
 728 /**
 729  * MUX() - Initialise a mux description.
 730  * @f0:         Function 0 (TZ1090_MUX_ is prepended, NA for none)
 731  * @f1:         Function 1 (TZ1090_MUX_ is prepended, NA for none)
 732  * @f2:         Function 2 (TZ1090_MUX_ is prepended, NA for none)
 733  * @f3:         Function 3 (TZ1090_MUX_ is prepended, NA for none)
 734  * @f4:         Function 4 (TZ1090_MUX_ is prepended, NA for none)
 735  * @mux_r:      Mux register (REG_PINCTRL_ is prepended)
 736  * @mux_b:      Bit number in register that the mux field begins
 737  * @mux_w:      Width of mux field in register
 738  */
 739 #define MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w)            \
 740         {                                                       \
 741                 .funcs = {                                      \
 742                         TZ1090_MUX_ ## f0,                      \
 743                         TZ1090_MUX_ ## f1,                      \
 744                         TZ1090_MUX_ ## f2,                      \
 745                         TZ1090_MUX_ ## f3,                      \
 746                         TZ1090_MUX_ ## f4,                      \
 747                 },                                              \
 748                 .reg = (REG_PINCTRL_ ## mux_r),                 \
 749                 .bit = (mux_b),                                 \
 750                 .width = (mux_w),                               \
 751         }
 752
 753 /**
 754  * DEFINE_SUBMUX() - Defines a submux description separate from a pin group.
 755  * @mux:        Mux name (_submux is appended)
 756  * @f0:         Function 0 (TZ1090_MUX_ is prepended, NA for none)
 757  * @f1:         Function 1 (TZ1090_MUX_ is prepended, NA for none)
 758  * @f2:         Function 2 (TZ1090_MUX_ is prepended, NA for none)
 759  * @f3:         Function 3 (TZ1090_MUX_ is prepended, NA for none)
 760  * @f4:         Function 4 (TZ1090_MUX_ is prepended, NA for none)
 761  * @mux_r:      Mux register (REG_PINCTRL_ is prepended)
 762  * @mux_b:      Bit number in register that the mux field begins
 763  * @mux_w:      Width of mux field in register
 764  *
 765  * A sub mux is a nested mux that can be bound to a magic function number used
 766  * by another mux description. For example value 4 of the top level mux might
 767  * correspond to a function which has a submux pointed to in tz1090_submux[].
 768  * The outer mux can then take on any function in the top level mux or the
 769  * submux, and if a submux function is chosen both muxes are updated to route
 770  * the signal from the submux.
 771  *
 772  * The submux can be defined with DEFINE_SUBMUX and pointed to from
 773  * tz1090_submux[] using SUBMUX.
 774  */
 775 #define DEFINE_SUBMUX(mux, f0, f1, f2, f3, f4, mux_r, mux_b, mux_w)     \
 776         static struct tz1090_muxdesc mux ## _submux =                   \
 777                 MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w)
 778
 779 /**
 780  * SUBMUX() - Link a submux to a function number.
 781  * @f:          Function name (TZ1090_MUX_ is prepended)
 782  * @submux:     Submux name (_submux is appended)
 783  *
 784  * For use in tz1090_submux[] initialisation to link an intermediate function
 785  * number to a particular submux description. It indicates that when the
 786  * function is chosen the signal is connected to the submux.
 787  */
 788 #define SUBMUX(f, submux)       [(TZ1090_MUX_ ## f)] = &(submux ## _submux)
 789
 790 /**
 791  * MUX_PG() - Initialise a pin group with mux control
 792  * @pg_name:    Pin group name (stringified, _pins appended to get pins array)
 793  * @f0:         Function 0 (TZ1090_MUX_ is prepended, NA for none)
 794  * @f1:         Function 1 (TZ1090_MUX_ is prepended, NA for none)
 795  * @f2:         Function 2 (TZ1090_MUX_ is prepended, NA for none)
 796  * @f3:         Function 3 (TZ1090_MUX_ is prepended, NA for none)
 797  * @f4:         Function 4 (TZ1090_MUX_ is prepended, NA for none)
 798  * @mux_r:      Mux register (REG_PINCTRL_ is prepended)
 799  * @mux_b:      Bit number in register that the mux field begins
 800  * @mux_w:      Width of mux field in register
 801  */
 802 #define MUX_PG(pg_name, f0, f1, f2, f3, f4,                     \
 803                mux_r, mux_b, mux_w)                             \
 804         {                                                       \
 805                 .name = #pg_name,                               \
 806                 .pins = pg_name##_pins,                         \
 807                 .npins = ARRAY_SIZE(pg_name##_pins),            \
 808                 .mux = MUX(f0, f1, f2, f3, f4,                  \
 809                            mux_r, mux_b, mux_w),                \
 810         }
 811
 812 /**
 813  * SIMPLE_PG() - Initialise a simple convenience pin group
 814  * @pg_name:    Pin group name (stringified, _pins appended to get pins array)
 815  *
 816  * A simple pin group is simply used for binding pins together so they can be
 817  * referred to by a single name instead of having to list every pin
 818  * individually.
 819  */
 820 #define SIMPLE_PG(pg_name)                                      \
 821         {                                                       \
 822                 .name = #pg_name,                               \
 823                 .pins = pg_name##_pins,                         \
 824                 .npins = ARRAY_SIZE(pg_name##_pins),            \
 825         }
 826
 827 /**
 828  * DRV_PG() - Initialise a pin group with drive control
 829  * @pg_name:    Pin group name (stringified, _pins appended to get pins array)
 830  * @slw_b:      Slew register bit.
 831  *              The same bit is used for Schmitt, and Drive (*2).
 832  */
 833 #define DRV_PG(pg_name, slw_b)                                  \
 834         {                                                       \
 835                 .name = #pg_name,                               \
 836                 .pins = pg_name##_pins,                         \
 837                 .npins = ARRAY_SIZE(pg_name##_pins),            \
 838                 .drv = true,                                    \
 839                 .slw_bit = (slw_b),                             \
 840         }
 841
 842 /*
 843  * Define main muxing pin groups
 844  */
 845
 846 /* submuxes */
 847
 848 /*            name     f0,  f1,            f2,        f3, f4, mux r/b/w */
 849 DEFINE_SUBMUX(ext_dac, DAC, NOT_IQADC_STB, IQDAC_STB, NA, NA, IF_CTL, 6, 2);
 850
 851 /* bind submuxes to internal functions */
 852 static struct tz1090_muxdesc *tz1090_submux[] = {
 853         SUBMUX(EXT_DAC, ext_dac),
 854 };
 855
 856 /*
 857  * These are the pin mux groups. Pin muxing can be enabled and disabled for each
 858  * pin individually so these groups are internal. The mapping of pins to pin mux
 859  * group is below (tz1090_mux_pins).
 860  */
 861 static struct tz1090_pingroup tz1090_mux_groups[] = {
 862         /* Muxing pin groups */
 863         /*     pg_name,  f0,       f1,       f2,       f3,        f4,          mux r/b/w */
 864         MUX_PG(sdh,      SDH,      SDIO,     NA,       NA,        NA,          IF_CTL, 20, 2),
 865         MUX_PG(sdio,     SDIO,     SDH,      NA,       NA,        NA,          IF_CTL, 16, 2),
 866         MUX_PG(spi1_cs2, SPI1_CS2, USB_VBUS, NA,       NA,        NA,          IF_CTL, 10, 2),
 867         MUX_PG(pdm_d,    PDM_DAC,  USB_VBUS, NA,       NA,        NA,          IF_CTL,  8, 2),
 868         MUX_PG(afe,      AFE,      TS_OUT_0, NA,       NA,        NA,          IF_CTL,  4, 2),
 869         MUX_PG(tft,      TFT,      EXT_DAC,  TS_OUT_1, LCD_TRACE, PHY_RINGOSC, IF_CTL,  0, 3),
 870 };
 871
 872 /*
 873  * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[].
 874  * Pins which aren't muxable to multiple peripherals are set to
 875  * TZ1090_MUX_GROUP_MAX to enable the "perip" function to enable/disable
 876  * peripheral control of the pin.
 877  *
 878  * This array is initialised in tz1090_init_mux_pins().
 879  */
 880 static u8 tz1090_mux_pins[NUM_GPIOS];
 881
 882 /* TZ1090_MUX_GROUP_MAX is used in tz1090_mux_pins[] for non-muxing pins */
 883 #define TZ1090_MUX_GROUP_MAX ARRAY_SIZE(tz1090_mux_groups)
 884
 885 /**
 886  * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping.
 887  *
 888  * Initialises the tz1090_mux_pins[] array to be the inverse of the pin lists in
 889  * each pin mux group in tz1090_mux_groups[].
 890  *
 891  * It is assumed that no pin mux groups overlap (share pins).
 892  */
 893 static void __init tz1090_init_mux_pins(void)
 894 {
 895         unsigned int g, p;
 896         const struct tz1090_pingroup *grp;
 897         const unsigned int *pin;
 898
 899         for (p = 0; p < NUM_GPIOS; ++p)
 900                 tz1090_mux_pins[p] = TZ1090_MUX_GROUP_MAX;
 901
 902         grp = tz1090_mux_groups;
 903         for (g = 0, grp = tz1090_mux_groups;
 904              g < ARRAY_SIZE(tz1090_mux_groups); ++g, ++grp)
 905                 for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin)
 906                         tz1090_mux_pins[*pin] = g;
 907 }
 908
 909 /*
 910  * These are the externally visible pin groups. Some of them allow group control
 911  * of drive configuration. Some are just simple convenience pingroups. All the
 912  * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the
 913  * same pins.
 914  * Pseudo pin groups follow in the group numbers after this array for each GPIO
 915  * pin. Any group used for muxing must have all pins belonging to the same pin
 916  * mux group.
 917  */
 918 static struct tz1090_pingroup tz1090_groups[] = {
 919         /* Pin groups with drive control (with no out of place pins) */
 920         /*     pg_name,         slw/schmitt/drv b */
 921         DRV_PG(jtag,            11 /* 11, 22 */),
 922         DRV_PG(tft,             10 /* 10, 20 */),
 923         DRV_PG(scb2,            9  /*  9, 18 */),
 924         DRV_PG(spi0,            7  /*  7, 14 */),
 925         DRV_PG(uart,            5  /*  5, 10 */),
 926         DRV_PG(scb1,            4  /*  4,  8 */),
 927         DRV_PG(spi1,            3  /*  3,  6 */),
 928         DRV_PG(afe,             0  /*  0,  0 */),
 929
 930         /*
 931          * Drive specific pin groups (with odd combinations of pins which makes
 932          * the pin group naming somewhat arbitrary)
 933          */
 934         /*     pg_name,         slw/schmitt/drv b */
 935         DRV_PG(drive_sdio,      8  /*  8, 16 */), /* sdio_* + sdh_* */
 936         DRV_PG(drive_i2s,       6  /*  6, 12 */), /* i2s_* + clk_out1 */
 937         DRV_PG(drive_scb0,      2  /*  2,  4 */), /* scb0_* + pdm_{c,d} */
 938         DRV_PG(drive_pdm,       1  /*  1,  2 */), /* pdm_{a,b} + clk_out0 */
 939
 940         /* Convenience pin groups */
 941         /*        pg_name */
 942         SIMPLE_PG(uart0),
 943         SIMPLE_PG(uart1),
 944         SIMPLE_PG(scb0),
 945         SIMPLE_PG(i2s),
 946         SIMPLE_PG(sdh),
 947         SIMPLE_PG(sdio),
 948
 949         /* pseudo-pingroups for each GPIO pin follow */
 950 };
 951
 952 /**
 953  * struct tz1090_pmx - Private pinctrl data
 954  * @dev:        Platform device
 955  * @pctl:       Pin control device
 956  * @regs:       Register region
 957  * @lock:       Lock protecting coherency of pin_en, gpio_en, and SELECT regs
 958  * @pin_en:     Pins that have been enabled (32 pins packed into each element)
 959  * @gpio_en:    GPIOs that have been enabled (32 pins packed into each element)
 960  */
 961 struct tz1090_pmx {
 962         struct device           *dev;
 963         struct pinctrl_dev      *pctl;
 964         void __iomem            *regs;
 965         spinlock_t              lock;
 966         u32                     pin_en[3];
 967         u32                     gpio_en[3];
 968 };
 969
 970 static inline u32 pmx_read(struct tz1090_pmx *pmx, u32 reg)
 971 {
 972         return ioread32(pmx->regs + reg);
 973 }
 974
 975 static inline void pmx_write(struct tz1090_pmx *pmx, u32 val, u32 reg)
 976 {
 977         iowrite32(val, pmx->regs + reg);
 978 }
 979
 980 /*
 981  * Pin control operations
 982  */
 983
 984 /* each GPIO pin has it's own pseudo pingroup containing only itself */
 985
 986 static int tz1090_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 987 {
 988         return ARRAY_SIZE(tz1090_groups) + NUM_GPIOS;
 989 }
 990
 991 static const char *tz1090_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 992                                                  unsigned int group)
 993 {
 994         if (group < ARRAY_SIZE(tz1090_groups)) {
 995                 /* normal pingroup */
 996                 return tz1090_groups[group].name;
 997         } else {
 998                 /* individual gpio pin pseudo-pingroup */
 999                 unsigned int pin = group - ARRAY_SIZE(tz1090_groups);
1000                 return tz1090_pins[pin].name;
1001         }
1002 }
1003
1004 static int tz1090_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1005                                          unsigned int group,
1006                                          const unsigned int **pins,
1007                                          unsigned int *num_pins)
1008 {
1009         if (group < ARRAY_SIZE(tz1090_groups)) {
1010                 /* normal pingroup */
1011                 *pins = tz1090_groups[group].pins;
1012                 *num_pins = tz1090_groups[group].npins;
1013         } else {
1014                 /* individual gpio pin pseudo-pingroup */
1015                 unsigned int pin = group - ARRAY_SIZE(tz1090_groups);
1016                 *pins = &tz1090_pins[pin].number;
1017                 *num_pins = 1;
1018         }
1019
1020         return 0;
1021 }
1022
1023 #ifdef CONFIG_DEBUG_FS
1024 static void tz1090_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1025                                         struct seq_file *s,
1026                                         unsigned int offset)
1027 {
1028         seq_printf(s, " %s", dev_name(pctldev->dev));
1029 }
1030 #endif
1031
1032 static int reserve_map(struct device *dev, struct pinctrl_map **map,
1033                        unsigned int *reserved_maps, unsigned int *num_maps,
1034                        unsigned int reserve)
1035 {
1036         unsigned int old_num = *reserved_maps;
1037         unsigned int new_num = *num_maps + reserve;
1038         struct pinctrl_map *new_map;
1039
1040         if (old_num >= new_num)
1041                 return 0;
1042
1043         new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1044         if (!new_map) {
1045                 dev_err(dev, "krealloc(map) failed\n");
1046                 return -ENOMEM;
1047         }
1048
1049         memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1050
1051         *map = new_map;
1052         *reserved_maps = new_num;
1053
1054         return 0;
1055 }
1056
1057 static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
1058                        unsigned int *num_maps, const char *group,
1059                        const char *function)
1060 {
1061         if (WARN_ON(*num_maps == *reserved_maps))
1062                 return -ENOSPC;
1063
1064         (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1065         (*map)[*num_maps].data.mux.group = group;
1066         (*map)[*num_maps].data.mux.function = function;
1067         (*num_maps)++;
1068
1069         return 0;
1070 }
1071
1072 static int add_map_configs(struct device *dev,
1073                            struct pinctrl_map **map,
1074                            unsigned int *reserved_maps, unsigned int *num_maps,
1075                            const char *group, unsigned long *configs,
1076                            unsigned int num_configs)
1077 {
1078         unsigned long *dup_configs;
1079
1080         if (WARN_ON(*num_maps == *reserved_maps))
1081                 return -ENOSPC;
1082
1083         dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1084                               GFP_KERNEL);
1085         if (!dup_configs) {
1086                 dev_err(dev, "kmemdup(configs) failed\n");
1087                 return -ENOMEM;
1088         }
1089
1090         (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
1091         (*map)[*num_maps].data.configs.group_or_pin = group;
1092         (*map)[*num_maps].data.configs.configs = dup_configs;
1093         (*map)[*num_maps].data.configs.num_configs = num_configs;
1094         (*num_maps)++;
1095
1096         return 0;
1097 }
1098
1099 static void tz1090_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1100                                        struct pinctrl_map *map,
1101                                        unsigned int num_maps)
1102 {
1103         int i;
1104
1105         for (i = 0; i < num_maps; i++)
1106                 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
1107                         kfree(map[i].data.configs.configs);
1108
1109         kfree(map);
1110 }
1111
1112 static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev,
1113                                             struct device_node *np,
1114                                             struct pinctrl_map **map,
1115                                             unsigned int *reserved_maps,
1116                                             unsigned int *num_maps)
1117 {
1118         int ret;
1119         const char *function;
1120         unsigned long *configs = NULL;
1121         unsigned int num_configs = 0;
1122         unsigned int reserve;
1123         struct property *prop;
1124         const char *group;
1125
1126         ret = of_property_read_string(np, "tz1090,function", &function);
1127         if (ret < 0) {
1128                 /* EINVAL=missing, which is fine since it's optional */
1129                 if (ret != -EINVAL)
1130                         dev_err(dev, "could not parse property function\n");
1131                 function = NULL;
1132         }
1133
1134         ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
1135         if (ret)
1136                 return ret;
1137
1138         reserve = 0;
1139         if (function != NULL)
1140                 reserve++;
1141         if (num_configs)
1142                 reserve++;
1143         ret = of_property_count_strings(np, "tz1090,pins");
1144         if (ret < 0) {
1145                 dev_err(dev, "could not parse property pins\n");
1146                 goto exit;
1147         }
1148         reserve *= ret;
1149
1150         ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
1151         if (ret < 0)
1152                 goto exit;
1153
1154         of_property_for_each_string(np, "tz1090,pins", prop, group) {
1155                 if (function) {
1156                         ret = add_map_mux(map, reserved_maps, num_maps,
1157                                           group, function);
1158                         if (ret < 0)
1159                                 goto exit;
1160                 }
1161
1162                 if (num_configs) {
1163                         ret = add_map_configs(dev, map, reserved_maps,
1164                                               num_maps, group, configs,
1165                                               num_configs);
1166                         if (ret < 0)
1167                                 goto exit;
1168                 }
1169         }
1170
1171         ret = 0;
1172
1173 exit:
1174         kfree(configs);
1175         return ret;
1176 }
1177
1178 static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1179                                          struct device_node *np_config,
1180                                          struct pinctrl_map **map,
1181                                          unsigned int *num_maps)
1182 {
1183         unsigned int reserved_maps;
1184         struct device_node *np;
1185         int ret;
1186
1187         reserved_maps = 0;
1188         *map = NULL;
1189         *num_maps = 0;
1190
1191         for_each_child_of_node(np_config, np) {
1192                 ret = tz1090_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
1193                                                        &reserved_maps,
1194                                                        num_maps);
1195                 if (ret < 0) {
1196                         tz1090_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1197                         return ret;
1198                 }
1199         }
1200
1201         return 0;
1202 }
1203
1204 static struct pinctrl_ops tz1090_pinctrl_ops = {
1205         .get_groups_count       = tz1090_pinctrl_get_groups_count,
1206         .get_group_name         = tz1090_pinctrl_get_group_name,
1207         .get_group_pins         = tz1090_pinctrl_get_group_pins,
1208 #ifdef CONFIG_DEBUG_FS
1209         .pin_dbg_show           = tz1090_pinctrl_pin_dbg_show,
1210 #endif
1211         .dt_node_to_map         = tz1090_pinctrl_dt_node_to_map,
1212         .dt_free_map            = tz1090_pinctrl_dt_free_map,
1213 };
1214
1215 /*
1216  * Pin mux operations
1217  */
1218
1219 static int tz1090_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
1220 {
1221         return ARRAY_SIZE(tz1090_functions);
1222 }
1223
1224 static const char *tz1090_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
1225                                                 unsigned int function)
1226 {
1227         return tz1090_functions[function].name;
1228 }
1229
1230 static int tz1090_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
1231                                           unsigned int function,
1232                                           const char * const **groups,
1233                                           unsigned int * const num_groups)
1234 {
1235         /* pingroup functions */
1236         *groups = tz1090_functions[function].groups;
1237         *num_groups = tz1090_functions[function].ngroups;
1238         return 0;
1239 }
1240
1241 /**
1242  * tz1090_pinctrl_select() - update bit in SELECT register
1243  * @pmx:                Pinmux data
1244  * @pin:                Pin number (must be within GPIO range)
1245  */
1246 static void tz1090_pinctrl_select(struct tz1090_pmx *pmx,
1247                                   unsigned int pin)
1248 {
1249         u32 reg, reg_shift, select, val;
1250         unsigned int pmx_index, pmx_shift;
1251         unsigned long flags;
1252
1253         /* uses base 32 instead of base 30 */
1254         pmx_index = pin >> 5;
1255         pmx_shift = pin & 0x1f;
1256
1257         /* select = !perip || gpio */
1258         select = ((~pmx->pin_en[pmx_index] |
1259                    pmx->gpio_en[pmx_index]) >> pmx_shift) & 1;
1260
1261         /* find register and bit offset (base 30) */
1262         reg = REG_PINCTRL_SELECT + 4*(pin / 30);
1263         reg_shift = pin % 30;
1264
1265         /* modify gpio select bit */
1266         __global_lock2(flags);
1267         val = pmx_read(pmx, reg);
1268         val &= ~BIT(reg_shift);
1269         val |= select << reg_shift;
1270         pmx_write(pmx, val, reg);
1271         __global_unlock2(flags);
1272 }
1273
1274 /**
1275  * tz1090_pinctrl_gpio_select() - enable/disable GPIO usage for a pin
1276  * @pmx:                Pinmux data
1277  * @pin:                Pin number
1278  * @gpio_select:        true to enable pin as GPIO,
1279  *                      false to leave control to whatever function is enabled
1280  *
1281  * Records that GPIO usage is enabled/disabled so that enabling a function
1282  * doesn't override the SELECT register bit.
1283  */
1284 static void tz1090_pinctrl_gpio_select(struct tz1090_pmx *pmx,
1285                                        unsigned int pin,
1286                                        bool gpio_select)
1287 {
1288         unsigned int index, shift;
1289         u32 gpio_en;
1290
1291         if (pin >= NUM_GPIOS)
1292                 return;
1293
1294         /* uses base 32 instead of base 30 */
1295         index = pin >> 5;
1296         shift = pin & 0x1f;
1297
1298         spin_lock(&pmx->lock);
1299
1300         /* keep a record whether gpio is selected */
1301         gpio_en = pmx->gpio_en[index];
1302         gpio_en &= ~BIT(shift);
1303         if (gpio_select)
1304                 gpio_en |= BIT(shift);
1305         pmx->gpio_en[index] = gpio_en;
1306
1307         /* update the select bit */
1308         tz1090_pinctrl_select(pmx, pin);
1309
1310         spin_unlock(&pmx->lock);
1311 }
1312
1313 /**
1314  * tz1090_pinctrl_perip_select() - enable/disable peripheral interface for a pin
1315  * @pmx:                Pinmux data
1316  * @pin:                Pin number
1317  * @perip_select:       true to enable peripheral interface when not GPIO,
1318  *                      false to leave pin in GPIO mode
1319  *
1320  * Records that peripheral usage is enabled/disabled so that SELECT register can
1321  * be set appropriately when GPIO is disabled.
1322  */
1323 static void tz1090_pinctrl_perip_select(struct tz1090_pmx *pmx,
1324                                         unsigned int pin,
1325                                         bool perip_select)
1326 {
1327         unsigned int index, shift;
1328         u32 pin_en;
1329
1330         if (pin >= NUM_GPIOS)
1331                 return;
1332
1333         /* uses base 32 instead of base 30 */
1334         index = pin >> 5;
1335         shift = pin & 0x1f;
1336
1337         spin_lock(&pmx->lock);
1338
1339         /* keep a record whether peripheral is selected */
1340         pin_en = pmx->pin_en[index];
1341         pin_en &= ~BIT(shift);
1342         if (perip_select)
1343                 pin_en |= BIT(shift);
1344         pmx->pin_en[index] = pin_en;
1345
1346         /* update the select bit */
1347         tz1090_pinctrl_select(pmx, pin);
1348
1349         spin_unlock(&pmx->lock);
1350 }
1351
1352 /**
1353  * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function.
1354  * @pmx:                Pinmux data
1355  * @desc:               Pinmux description
1356  * @function:           Function to switch to
1357  *
1358  * Enable a particular function on a pin mux group. Since pin mux descriptions
1359  * are nested this function is recursive.
1360  */
1361 static int tz1090_pinctrl_enable_mux(struct tz1090_pmx *pmx,
1362                                      const struct tz1090_muxdesc *desc,
1363                                      unsigned int function)
1364 {
1365         const int *fit;
1366         unsigned long flags;
1367         int mux;
1368         unsigned int func, ret;
1369         u32 reg, mask;
1370
1371         /* find the mux value for this function, searching recursively */
1372         for (mux = 0, fit = desc->funcs;
1373              mux < ARRAY_SIZE(desc->funcs); ++mux, ++fit) {
1374                 func = *fit;
1375                 if (func == function)
1376                         goto found_mux;
1377
1378                 /* maybe it's a sub-mux */
1379                 if (func < ARRAY_SIZE(tz1090_submux) && tz1090_submux[func]) {
1380                         ret = tz1090_pinctrl_enable_mux(pmx,
1381                                                         tz1090_submux[func],
1382                                                         function);
1383                         if (!ret)
1384                                 goto found_mux;
1385                 }
1386         }
1387
1388         return -EINVAL;
1389 found_mux:
1390
1391         /* Set up the mux */
1392         if (desc->width) {
1393                 mask = (BIT(desc->width) - 1) << desc->bit;
1394                 __global_lock2(flags);
1395                 reg = pmx_read(pmx, desc->reg);
1396                 reg &= ~mask;
1397                 reg |= (mux << desc->bit) & mask;
1398                 pmx_write(pmx, reg, desc->reg);
1399                 __global_unlock2(flags);
1400         }
1401
1402         return 0;
1403 }
1404
1405 /**
1406  * tz1090_pinctrl_enable() - Enable a function on a pin group.
1407  * @pctldev:            Pin control data
1408  * @function:           Function index to enable
1409  * @group:              Group index to enable
1410  *
1411  * Enable a particular function on a group of pins. The per GPIO pin pseudo pin
1412  * groups can be used (in which case the pin will be enabled in peripheral mode
1413  * and if it belongs to a pin mux group the mux will be switched if it isn't
1414  * already in use. Some convenience pin groups can also be used in which case
1415  * the effect is the same as enabling the function on each individual pin in the
1416  * group.
1417  */
1418 static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev,
1419                                  unsigned int function, unsigned int group)
1420 {
1421         struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1422         struct tz1090_pingroup *grp;
1423         int ret;
1424         unsigned int pin_num, mux_group, i, npins;
1425         const unsigned int *pins;
1426
1427         /* group of pins? */
1428         if (group < ARRAY_SIZE(tz1090_groups)) {
1429                 grp = &tz1090_groups[group];
1430                 npins = grp->npins;
1431                 pins = grp->pins;
1432                 /*
1433                  * All pins in the group must belong to the same mux group,
1434                  * which allows us to just use the mux group of the first pin.
1435                  * By explicitly listing permitted pingroups for each function
1436                  * the pinmux core should ensure this is always the case.
1437                  */
1438         } else {
1439                 pin_num = group - ARRAY_SIZE(tz1090_groups);
1440                 npins = 1;
1441                 pins = &pin_num;
1442         }
1443         mux_group = tz1090_mux_pins[*pins];
1444
1445         /* no mux group, but can still be individually muxed to peripheral */
1446         if (mux_group >= TZ1090_MUX_GROUP_MAX) {
1447                 if (function == TZ1090_MUX_PERIP)
1448                         goto mux_pins;
1449                 return -EINVAL;
1450         }
1451
1452         /* mux group already set to a different function? */
1453         grp = &tz1090_mux_groups[mux_group];
1454         if (grp->func_count && grp->func != function) {
1455                 dev_err(pctldev->dev,
1456                         "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n",
1457                         __func__, tz1090_functions[function].name,
1458                         tz1090_functions[grp->func].name);
1459                 return -EBUSY;
1460         }
1461
1462         dev_dbg(pctldev->dev, "%s: muxing %u pin(s) in '%s' to '%s'\n",
1463                 __func__, npins, grp->name, tz1090_functions[function].name);
1464
1465         /* if first pin in mux group to be enabled, enable the group mux */
1466         if (!grp->func_count) {
1467                 grp->func = function;
1468                 ret = tz1090_pinctrl_enable_mux(pmx, &grp->mux, function);
1469                 if (ret)
1470                         return ret;
1471         }
1472         /* add pins to ref count and mux individually to peripheral */
1473         grp->func_count += npins;
1474 mux_pins:
1475         for (i = 0; i < npins; ++i)
1476                 tz1090_pinctrl_perip_select(pmx, pins[i], true);
1477
1478         return 0;
1479 }
1480
1481 /**
1482  * tz1090_pinctrl_disable() - Disable a function on a pin group.
1483  * @pctldev:            Pin control data
1484  * @function:           Function index to disable
1485  * @group:              Group index to disable
1486  *
1487  * Disable a particular function on a group of pins. The per GPIO pin pseudo pin
1488  * groups can be used (in which case the pin will be taken out of peripheral
1489  * mode. Some convenience pin groups can also be used in which case the effect
1490  * is the same as enabling the function on each individual pin in the group.
1491  */
1492 static void tz1090_pinctrl_disable(struct pinctrl_dev *pctldev,
1493                                    unsigned int function, unsigned int group)
1494 {
1495         struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1496         struct tz1090_pingroup *grp;
1497         unsigned int pin_num, mux_group, i, npins;
1498         const unsigned int *pins;
1499
1500         /* group of pins? */
1501         if (group < ARRAY_SIZE(tz1090_groups)) {
1502                 grp = &tz1090_groups[group];
1503                 npins = grp->npins;
1504                 pins = grp->pins;
1505                 /*
1506                  * All pins in the group must belong to the same mux group,
1507                  * which allows us to just use the mux group of the first pin.
1508                  * By explicitly listing permitted pingroups for each function
1509                  * the pinmux core should ensure this is always the case.
1510                  */
1511         } else {
1512                 pin_num = group - ARRAY_SIZE(tz1090_groups);
1513                 npins = 1;
1514                 pins = &pin_num;
1515         }
1516         mux_group = tz1090_mux_pins[*pins];
1517
1518         /* no mux group, but can still be individually muxed to peripheral */
1519         if (mux_group >= TZ1090_MUX_GROUP_MAX) {
1520                 if (function == TZ1090_MUX_PERIP)
1521                         goto unmux_pins;
1522                 return;
1523         }
1524
1525         /* mux group already set to a different function? */
1526         grp = &tz1090_mux_groups[mux_group];
1527         dev_dbg(pctldev->dev, "%s: unmuxing %u pin(s) in '%s' from '%s'\n",
1528                 __func__, npins, grp->name, tz1090_functions[function].name);
1529
1530         /* subtract pins from ref count and unmux individually */
1531         WARN_ON(grp->func_count < npins);
1532         grp->func_count -= npins;
1533 unmux_pins:
1534         for (i = 0; i < npins; ++i)
1535                 tz1090_pinctrl_perip_select(pmx, pins[i], false);
1536 }
1537
1538 /**
1539  * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode.
1540  * @pctldev:            Pin control data
1541  * @range:              GPIO range
1542  * @pin:                Pin number
1543  *
1544  * Puts a particular pin into GPIO mode, disabling peripheral control until it's
1545  * disabled again.
1546  */
1547 static int tz1090_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
1548                                               struct pinctrl_gpio_range *range,
1549                                               unsigned int pin)
1550 {
1551         struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1552         tz1090_pinctrl_gpio_select(pmx, pin, true);
1553         return 0;
1554 }
1555
1556 /**
1557  * tz1090_pinctrl_gpio_disable_free() - Take pin out of GPIO mode.
1558  * @pctldev:            Pin control data
1559  * @range:              GPIO range
1560  * @pin:                Pin number
1561  *
1562  * Take a particular pin out of GPIO mode. If the pin is enabled for a
1563  * peripheral it will return to peripheral mode.
1564  */
1565 static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
1566                                              struct pinctrl_gpio_range *range,
1567                                              unsigned int pin)
1568 {
1569         struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1570         tz1090_pinctrl_gpio_select(pmx, pin, false);
1571 }
1572
1573 static struct pinmux_ops tz1090_pinmux_ops = {
1574         .get_functions_count    = tz1090_pinctrl_get_funcs_count,
1575         .get_function_name      = tz1090_pinctrl_get_func_name,
1576         .get_function_groups    = tz1090_pinctrl_get_func_groups,
1577         .enable                 = tz1090_pinctrl_enable,
1578         .disable                = tz1090_pinctrl_disable,
1579         .gpio_request_enable    = tz1090_pinctrl_gpio_request_enable,
1580         .gpio_disable_free      = tz1090_pinctrl_gpio_disable_free,
1581 };
1582
1583 /*
1584  * Pin config operations
1585  */
1586
1587 struct tz1090_pinconf_pullup {
1588         unsigned char index;
1589         unsigned char shift;
1590 };
1591
1592 /* The mapping of pin to pull up/down register index and shift */
1593 static struct tz1090_pinconf_pullup tz1090_pinconf_pullup[] = {
1594         {5, 22}, /*  0 - TZ1090_PIN_SDIO_CLK */
1595         {0, 14}, /*  1 - TZ1090_PIN_SDIO_CMD */
1596         {0,  6}, /*  2 - TZ1090_PIN_SDIO_D0 */
1597         {0,  8}, /*  3 - TZ1090_PIN_SDIO_D1 */
1598         {0, 10}, /*  4 - TZ1090_PIN_SDIO_D2 */
1599         {0, 12}, /*  5 - TZ1090_PIN_SDIO_D3 */
1600         {0,  2}, /*  6 - TZ1090_PIN_SDH_CD */
1601         {0,  4}, /*  7 - TZ1090_PIN_SDH_WP */
1602         {0, 16}, /*  8 - TZ1090_PIN_SPI0_MCLK */
1603         {0, 18}, /*  9 - TZ1090_PIN_SPI0_CS0 */
1604         {0, 20}, /* 10 - TZ1090_PIN_SPI0_CS1 */
1605         {0, 22}, /* 11 - TZ1090_PIN_SPI0_CS2 */
1606         {0, 24}, /* 12 - TZ1090_PIN_SPI0_DOUT */
1607         {0, 26}, /* 13 - TZ1090_PIN_SPI0_DIN */
1608         {0, 28}, /* 14 - TZ1090_PIN_SPI1_MCLK */
1609         {0, 30}, /* 15 - TZ1090_PIN_SPI1_CS0 */
1610         {1,  0}, /* 16 - TZ1090_PIN_SPI1_CS1 */
1611         {1,  2}, /* 17 - TZ1090_PIN_SPI1_CS2 */
1612         {1,  4}, /* 18 - TZ1090_PIN_SPI1_DOUT */
1613         {1,  6}, /* 19 - TZ1090_PIN_SPI1_DIN */
1614         {1,  8}, /* 20 - TZ1090_PIN_UART0_RXD */
1615         {1, 10}, /* 21 - TZ1090_PIN_UART0_TXD */
1616         {1, 12}, /* 22 - TZ1090_PIN_UART0_CTS */
1617         {1, 14}, /* 23 - TZ1090_PIN_UART0_RTS */
1618         {1, 16}, /* 24 - TZ1090_PIN_UART1_RXD */
1619         {1, 18}, /* 25 - TZ1090_PIN_UART1_TXD */
1620         {1, 20}, /* 26 - TZ1090_PIN_SCB0_SDAT */
1621         {1, 22}, /* 27 - TZ1090_PIN_SCB0_SCLK */
1622         {1, 24}, /* 28 - TZ1090_PIN_SCB1_SDAT */
1623         {1, 26}, /* 29 - TZ1090_PIN_SCB1_SCLK */
1624
1625         {1, 28}, /* 30 - TZ1090_PIN_SCB2_SDAT */
1626         {1, 30}, /* 31 - TZ1090_PIN_SCB2_SCLK */
1627         {2,  0}, /* 32 - TZ1090_PIN_I2S_MCLK */
1628         {2,  2}, /* 33 - TZ1090_PIN_I2S_BCLK_OUT */
1629         {2,  4}, /* 34 - TZ1090_PIN_I2S_LRCLK_OUT */
1630         {2,  6}, /* 35 - TZ1090_PIN_I2S_DOUT0 */
1631         {2,  8}, /* 36 - TZ1090_PIN_I2S_DOUT1 */
1632         {2, 10}, /* 37 - TZ1090_PIN_I2S_DOUT2 */
1633         {2, 12}, /* 38 - TZ1090_PIN_I2S_DIN */
1634         {4, 12}, /* 39 - TZ1090_PIN_PDM_A */
1635         {4, 14}, /* 40 - TZ1090_PIN_PDM_B */
1636         {4, 18}, /* 41 - TZ1090_PIN_PDM_C */
1637         {4, 20}, /* 42 - TZ1090_PIN_PDM_D */
1638         {2, 14}, /* 43 - TZ1090_PIN_TFT_RED0 */
1639         {2, 16}, /* 44 - TZ1090_PIN_TFT_RED1 */
1640         {2, 18}, /* 45 - TZ1090_PIN_TFT_RED2 */
1641         {2, 20}, /* 46 - TZ1090_PIN_TFT_RED3 */
1642         {2, 22}, /* 47 - TZ1090_PIN_TFT_RED4 */
1643         {2, 24}, /* 48 - TZ1090_PIN_TFT_RED5 */
1644         {2, 26}, /* 49 - TZ1090_PIN_TFT_RED6 */
1645         {2, 28}, /* 50 - TZ1090_PIN_TFT_RED7 */
1646         {2, 30}, /* 51 - TZ1090_PIN_TFT_GREEN0 */
1647         {3,  0}, /* 52 - TZ1090_PIN_TFT_GREEN1 */
1648         {3,  2}, /* 53 - TZ1090_PIN_TFT_GREEN2 */
1649         {3,  4}, /* 54 - TZ1090_PIN_TFT_GREEN3 */
1650         {3,  6}, /* 55 - TZ1090_PIN_TFT_GREEN4 */
1651         {3,  8}, /* 56 - TZ1090_PIN_TFT_GREEN5 */
1652         {3, 10}, /* 57 - TZ1090_PIN_TFT_GREEN6 */
1653         {3, 12}, /* 58 - TZ1090_PIN_TFT_GREEN7 */
1654         {3, 14}, /* 59 - TZ1090_PIN_TFT_BLUE0 */
1655
1656         {3, 16}, /* 60 - TZ1090_PIN_TFT_BLUE1 */
1657         {3, 18}, /* 61 - TZ1090_PIN_TFT_BLUE2 */
1658         {3, 20}, /* 62 - TZ1090_PIN_TFT_BLUE3 */
1659         {3, 22}, /* 63 - TZ1090_PIN_TFT_BLUE4 */
1660         {3, 24}, /* 64 - TZ1090_PIN_TFT_BLUE5 */
1661         {3, 26}, /* 65 - TZ1090_PIN_TFT_BLUE6 */
1662         {3, 28}, /* 66 - TZ1090_PIN_TFT_BLUE7 */
1663         {3, 30}, /* 67 - TZ1090_PIN_TFT_VDDEN_GD */
1664         {4,  0}, /* 68 - TZ1090_PIN_TFT_PANELCLK */
1665         {4,  2}, /* 69 - TZ1090_PIN_TFT_BLANK_LS */
1666         {4,  4}, /* 70 - TZ1090_PIN_TFT_VSYNC_NS */
1667         {4,  6}, /* 71 - TZ1090_PIN_TFT_HSYNC_NR */
1668         {4,  8}, /* 72 - TZ1090_PIN_TFT_VD12ACB */
1669         {4, 10}, /* 73 - TZ1090_PIN_TFT_PWRSAVE */
1670         {4, 24}, /* 74 - TZ1090_PIN_TX_ON */
1671         {4, 26}, /* 75 - TZ1090_PIN_RX_ON */
1672         {4, 28}, /* 76 - TZ1090_PIN_PLL_ON */
1673         {4, 30}, /* 77 - TZ1090_PIN_PA_ON */
1674         {5,  0}, /* 78 - TZ1090_PIN_RX_HP */
1675         {5,  6}, /* 79 - TZ1090_PIN_GAIN0 */
1676         {5,  8}, /* 80 - TZ1090_PIN_GAIN1 */
1677         {5, 10}, /* 81 - TZ1090_PIN_GAIN2 */
1678         {5, 12}, /* 82 - TZ1090_PIN_GAIN3 */
1679         {5, 14}, /* 83 - TZ1090_PIN_GAIN4 */
1680         {5, 16}, /* 84 - TZ1090_PIN_GAIN5 */
1681         {5, 18}, /* 85 - TZ1090_PIN_GAIN6 */
1682         {5, 20}, /* 86 - TZ1090_PIN_GAIN7 */
1683         {5,  2}, /* 87 - TZ1090_PIN_ANT_SEL0 */
1684         {5,  4}, /* 88 - TZ1090_PIN_ANT_SEL1 */
1685         {0,  0}, /* 89 - TZ1090_PIN_SDH_CLK_IN */
1686
1687         {5, 24}, /* 90 - TZ1090_PIN_TCK */
1688         {5, 26}, /* 91 - TZ1090_PIN_TRST */
1689         {5, 28}, /* 92 - TZ1090_PIN_TDI */
1690         {5, 30}, /* 93 - TZ1090_PIN_TDO */
1691         {6,  0}, /* 94 - TZ1090_PIN_TMS */
1692         {4, 16}, /* 95 - TZ1090_PIN_CLK_OUT0 */
1693         {4, 22}, /* 96 - TZ1090_PIN_CLK_OUT1 */
1694 };
1695
1696 static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev,
1697                               unsigned int pin,
1698                               enum pin_config_param param,
1699                               bool report_err,
1700                               u32 *reg, u32 *width, u32 *mask, u32 *shift,
1701                               u32 *val)
1702 {
1703         struct tz1090_pinconf_pullup *pu;
1704
1705         /* All supported pins have controllable input bias */
1706         switch (param) {
1707         case PIN_CONFIG_BIAS_DISABLE:
1708         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1709                 *val = REG_PU_PD_TRISTATE;
1710                 break;
1711         case PIN_CONFIG_BIAS_PULL_UP:
1712                 *val = REG_PU_PD_UP;
1713                 break;
1714         case PIN_CONFIG_BIAS_PULL_DOWN:
1715                 *val = REG_PU_PD_DOWN;
1716                 break;
1717         case PIN_CONFIG_BIAS_BUS_HOLD:
1718                 *val = REG_PU_PD_REPEATER;
1719                 break;
1720         default:
1721                 return -ENOTSUPP;
1722         };
1723
1724         /* Only input bias parameters supported */
1725         pu = &tz1090_pinconf_pullup[pin];
1726         *reg = REG_PINCTRL_PU_PD + 4*pu->index;
1727         *shift = pu->shift;
1728         *width = 2;
1729
1730         /* Calculate field information */
1731         *mask = (BIT(*width) - 1) << *shift;
1732
1733         return 0;
1734 }
1735
1736 static int tz1090_pinconf_get(struct pinctrl_dev *pctldev,
1737                               unsigned int pin, unsigned long *config)
1738 {
1739         struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1740         enum pin_config_param param = pinconf_to_config_param(*config);
1741         int ret;
1742         u32 reg, width, mask, shift, val, tmp, arg;
1743
1744         /* Get register information */
1745         ret = tz1090_pinconf_reg(pctldev, pin, param, true,
1746                                  &reg, &width, &mask, &shift, &val);
1747         if (ret < 0)
1748                 return ret;
1749
1750         /* Extract field from register */
1751         tmp = pmx_read(pmx, reg);
1752         arg = ((tmp & mask) >> shift) == val;
1753
1754         /* Config not active */
1755         if (!arg)
1756                 return -EINVAL;
1757
1758         /* And pack config */
1759         *config = pinconf_to_config_packed(param, arg);
1760
1761         return 0;
1762 }
1763
1764 static int tz1090_pinconf_set(struct pinctrl_dev *pctldev,
1765                               unsigned int pin, unsigned long *configs,
1766                               unsigned num_configs)
1767 {
1768         struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1769         enum pin_config_param param;
1770         unsigned int arg;
1771         int ret;
1772         u32 reg, width, mask, shift, val, tmp;
1773         unsigned long flags;
1774         int i;
1775
1776         for (i = 0; i < num_configs; i++) {
1777                 param = pinconf_to_config_param(configs[i]);
1778                 arg = pinconf_to_config_argument(configs[i]);
1779
1780                 dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
1781                         __func__, tz1090_pins[pin].name, configs[i]);
1782
1783                 /* Get register information */
1784                 ret = tz1090_pinconf_reg(pctldev, pin, param, true,
1785                                          &reg, &width, &mask, &shift, &val);
1786                 if (ret < 0)
1787                         return ret;
1788
1789                 /* Unpack argument and range check it */
1790                 if (arg > 1) {
1791                         dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
1792                                 __func__, arg);
1793                         return -EINVAL;
1794                 }
1795
1796                 /* Write register field */
1797                 __global_lock2(flags);
1798                 tmp = pmx_read(pmx, reg);
1799                 tmp &= ~mask;
1800                 if (arg)
1801                         tmp |= val << shift;
1802                 pmx_write(pmx, tmp, reg);
1803                 __global_unlock2(flags);
1804         } /* for each config */
1805
1806         return 0;
1807 }
1808
1809 static const int tz1090_boolean_map[] = {
1810         [0]             = -EINVAL,
1811         [1]             = 1,
1812 };
1813
1814 static const int tz1090_dr_map[] = {
1815         [REG_DR_2mA]    = 2,
1816         [REG_DR_4mA]    = 4,
1817         [REG_DR_8mA]    = 8,
1818         [REG_DR_12mA]   = 12,
1819 };
1820
1821 static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev,
1822                                     const struct tz1090_pingroup *g,
1823                                     enum pin_config_param param,
1824                                     bool report_err,
1825                                     u32 *reg, u32 *width, u32 *mask, u32 *shift,
1826                                     const int **map)
1827 {
1828         /* Drive configuration applies in groups, but not to all groups. */
1829         if (!g->drv) {
1830                 if (report_err)
1831                         dev_dbg(pctldev->dev,
1832                                 "%s: group %s has no drive control\n",
1833                                 __func__, g->name);
1834                 return -ENOTSUPP;
1835         }
1836
1837         /* Find information about drive parameter's register */
1838         switch (param) {
1839         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1840                 *reg = REG_PINCTRL_SCHMITT;
1841                 *width = 1;
1842                 *map = tz1090_boolean_map;
1843                 break;
1844         case PIN_CONFIG_DRIVE_STRENGTH:
1845                 *reg = REG_PINCTRL_DR;
1846                 *width = 2;
1847                 *map = tz1090_dr_map;
1848                 break;
1849         default:
1850                 return -ENOTSUPP;
1851         };
1852
1853         /* Calculate field information */
1854         *shift = g->slw_bit * *width;
1855         *mask = (BIT(*width) - 1) << *shift;
1856
1857         return 0;
1858 }
1859
1860 static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev,
1861                                     unsigned int group,
1862                                     unsigned long *config)
1863 {
1864         struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1865         const struct tz1090_pingroup *g;
1866         enum pin_config_param param = pinconf_to_config_param(*config);
1867         int ret, arg;
1868         unsigned int pin;
1869         u32 reg, width, mask, shift, val;
1870         const int *map;
1871
1872         if (group >= ARRAY_SIZE(tz1090_groups)) {
1873                 pin = group - ARRAY_SIZE(tz1090_groups);
1874                 return tz1090_pinconf_get(pctldev, pin, config);
1875         }
1876
1877         g = &tz1090_groups[group];
1878         if (g->npins == 1) {
1879                 pin = g->pins[0];
1880                 ret = tz1090_pinconf_get(pctldev, pin, config);
1881                 if (ret != -ENOTSUPP)
1882                         return ret;
1883         }
1884
1885         /* Get register information */
1886         ret = tz1090_pinconf_group_reg(pctldev, g, param, true,
1887                                        &reg, &width, &mask, &shift, &map);
1888         if (ret < 0)
1889                 return ret;
1890
1891         /* Extract field from register */
1892         val = pmx_read(pmx, reg);
1893         arg = map[(val & mask) >> shift];
1894         if (arg < 0)
1895                 return arg;
1896
1897         /* And pack config */
1898         *config = pinconf_to_config_packed(param, arg);
1899
1900         return 0;
1901 }
1902
1903 static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev,
1904                                     unsigned int group, unsigned long *configs,
1905                                     unsigned num_configs)
1906 {
1907         struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1908         const struct tz1090_pingroup *g;
1909         enum pin_config_param param;
1910         unsigned int arg, pin, i;
1911         const unsigned int *pit;
1912         int ret;
1913         u32 reg, width, mask, shift, val;
1914         unsigned long flags;
1915         const int *map;
1916         int j;
1917
1918         if (group >= ARRAY_SIZE(tz1090_groups)) {
1919                 pin = group - ARRAY_SIZE(tz1090_groups);
1920                 return tz1090_pinconf_set(pctldev, pin, configs, num_configs);
1921         }
1922
1923         g = &tz1090_groups[group];
1924         if (g->npins == 1) {
1925                 pin = g->pins[0];
1926                 ret = tz1090_pinconf_set(pctldev, pin, configs, num_configs);
1927                 if (ret != -ENOTSUPP)
1928                         return ret;
1929         }
1930
1931         for (j = 0; j < num_configs; j++) {
1932                 param = pinconf_to_config_param(configs[j]);
1933
1934                 dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
1935                         __func__, g->name, configs[j]);
1936
1937                 /* Get register information */
1938                 ret = tz1090_pinconf_group_reg(pctldev, g, param, true, &reg,
1939                                                 &width, &mask, &shift, &map);
1940                 if (ret < 0) {
1941                         /*
1942                          * Maybe we're trying to set a per-pin configuration
1943                          * of a group, so do the pins one by one. This is
1944                          * mainly as a convenience.
1945                          */
1946                         for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
1947                                 ret = tz1090_pinconf_set(pctldev, *pit, configs,
1948                                         num_configs);
1949                                 if (ret)
1950                                         return ret;
1951                         }
1952                         return 0;
1953                 }
1954
1955                 /* Unpack argument and map it to register value */
1956                 arg = pinconf_to_config_argument(configs[j]);
1957                 for (i = 0; i < BIT(width); ++i) {
1958                         if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
1959                                 /* Write register field */
1960                                 __global_lock2(flags);
1961                                 val = pmx_read(pmx, reg);
1962                                 val &= ~mask;
1963                                 val |= i << shift;
1964                                 pmx_write(pmx, val, reg);
1965                                 __global_unlock2(flags);
1966                                 goto next_config;
1967                         }
1968                 }
1969
1970                 dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
1971                         __func__, arg);
1972                 return -EINVAL;
1973
1974 next_config:
1975                 ;
1976         } /* for each config */
1977
1978         return 0;
1979 }
1980
1981 static struct pinconf_ops tz1090_pinconf_ops = {
1982         .is_generic                     = true,
1983         .pin_config_get                 = tz1090_pinconf_get,
1984         .pin_config_set                 = tz1090_pinconf_set,
1985         .pin_config_group_get           = tz1090_pinconf_group_get,
1986         .pin_config_group_set           = tz1090_pinconf_group_set,
1987         .pin_config_config_dbg_show     = pinconf_generic_dump_config,
1988 };
1989
1990 /*
1991  * Pin control driver setup
1992  */
1993
1994 static struct pinctrl_desc tz1090_pinctrl_desc = {
1995         .pctlops        = &tz1090_pinctrl_ops,
1996         .pmxops         = &tz1090_pinmux_ops,
1997         .confops        = &tz1090_pinconf_ops,
1998         .owner          = THIS_MODULE,
1999 };
2000
2001 static int tz1090_pinctrl_probe(struct platform_device *pdev)
2002 {
2003         struct tz1090_pmx *pmx;
2004         struct resource *res;
2005
2006         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
2007         if (!pmx) {
2008                 dev_err(&pdev->dev, "Can't alloc tz1090_pmx\n");
2009                 return -ENOMEM;
2010         }
2011         pmx->dev = &pdev->dev;
2012         spin_lock_init(&pmx->lock);
2013
2014         tz1090_pinctrl_desc.name = dev_name(&pdev->dev);
2015         tz1090_pinctrl_desc.pins = tz1090_pins;
2016         tz1090_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pins);
2017
2018         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2019         pmx->regs = devm_ioremap_resource(&pdev->dev, res);
2020         if (IS_ERR(pmx->regs))
2021                 return PTR_ERR(pmx->regs);
2022
2023         pmx->pctl = pinctrl_register(&tz1090_pinctrl_desc, &pdev->dev, pmx);
2024         if (!pmx->pctl) {
2025                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
2026                 return -ENODEV;
2027         }
2028
2029         platform_set_drvdata(pdev, pmx);
2030
2031         dev_info(&pdev->dev, "TZ1090 pinctrl driver initialised\n");
2032
2033         return 0;
2034 }
2035
2036 static int tz1090_pinctrl_remove(struct platform_device *pdev)
2037 {
2038         struct tz1090_pmx *pmx = platform_get_drvdata(pdev);
2039
2040         pinctrl_unregister(pmx->pctl);
2041
2042         return 0;
2043 }
2044
2045 static struct of_device_id tz1090_pinctrl_of_match[] = {
2046         { .compatible = "img,tz1090-pinctrl", },
2047         { },
2048 };
2049
2050 static struct platform_driver tz1090_pinctrl_driver = {
2051         .driver = {
2052                 .name           = "tz1090-pinctrl",
2053                 .owner          = THIS_MODULE,
2054                 .of_match_table = tz1090_pinctrl_of_match,
2055         },
2056         .probe  = tz1090_pinctrl_probe,
2057         .remove = tz1090_pinctrl_remove,
2058 };
2059
2060 static int __init tz1090_pinctrl_init(void)
2061 {
2062         tz1090_init_mux_pins();
2063         return platform_driver_register(&tz1090_pinctrl_driver);
2064 }
2065 arch_initcall(tz1090_pinctrl_init);
2066
2067 static void __exit tz1090_pinctrl_exit(void)
2068 {
2069         platform_driver_unregister(&tz1090_pinctrl_driver);
2070 }
2071 module_exit(tz1090_pinctrl_exit);
2072
2073 MODULE_AUTHOR("Imagination Technologies Ltd.");
2074 MODULE_DESCRIPTION("Toumaz Xenif TZ1090 pinctrl driver");
2075 MODULE_LICENSE("GPL v2");
2076 MODULE_DEVICE_TABLE(of, tz1090_pinctrl_of_match);