1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/firmware.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
71 #warning this driver is still not properly converted to the DMA API
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
76 /* Enable driver tracing. */
82 * Any instance where a 32-bit long or pointer type is assumed
83 * for precision or HW defined structures, the following define
84 * types must be used. In Linux the char, short, and int types
85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
86 * and long types are 64 bits on Alpha and UltraSPARC.
88 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
89 #define ASC_VADDR __u32 /* Virtual address data type. */
90 #define ASC_DCNT __u32 /* Unsigned Data count type. */
91 #define ASC_SDCNT __s32 /* Signed Data count type. */
93 typedef unsigned char uchar;
103 #define UW_ERR (uint)(0xFFFF)
104 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
106 #define PCI_VENDOR_ID_ASP 0x10cd
107 #define PCI_DEVICE_ID_ASP_1200A 0x1100
108 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
109 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
110 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
111 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
112 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
115 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
116 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
117 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
120 #define CC_VERY_LONG_SG_LIST 0
121 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
123 #define PortAddr unsigned int /* port address size */
124 #define inp(port) inb(port)
125 #define outp(port, byte) outb((byte), (port))
127 #define inpw(port) inw(port)
128 #define outpw(port, word) outw((word), (port))
130 #define ASC_MAX_SG_QUEUE 7
131 #define ASC_MAX_SG_LIST 255
133 #define ASC_CS_TYPE unsigned short
135 #define ASC_IS_ISA (0x0001)
136 #define ASC_IS_ISAPNP (0x0081)
137 #define ASC_IS_EISA (0x0002)
138 #define ASC_IS_PCI (0x0004)
139 #define ASC_IS_PCI_ULTRA (0x0104)
140 #define ASC_IS_PCMCIA (0x0008)
141 #define ASC_IS_MCA (0x0020)
142 #define ASC_IS_VL (0x0040)
143 #define ASC_IS_WIDESCSI_16 (0x0100)
144 #define ASC_IS_WIDESCSI_32 (0x0200)
145 #define ASC_IS_BIG_ENDIAN (0x8000)
147 #define ASC_CHIP_MIN_VER_VL (0x01)
148 #define ASC_CHIP_MAX_VER_VL (0x07)
149 #define ASC_CHIP_MIN_VER_PCI (0x09)
150 #define ASC_CHIP_MAX_VER_PCI (0x0F)
151 #define ASC_CHIP_VER_PCI_BIT (0x08)
152 #define ASC_CHIP_MIN_VER_ISA (0x11)
153 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
154 #define ASC_CHIP_MAX_VER_ISA (0x27)
155 #define ASC_CHIP_VER_ISA_BIT (0x30)
156 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
157 #define ASC_CHIP_VER_ASYN_BUG (0x21)
158 #define ASC_CHIP_VER_PCI 0x08
159 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
160 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
161 #define ASC_CHIP_MIN_VER_EISA (0x41)
162 #define ASC_CHIP_MAX_VER_EISA (0x47)
163 #define ASC_CHIP_VER_EISA_BIT (0x40)
164 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
165 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
166 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
167 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
169 #define ASC_SCSI_ID_BITS 3
170 #define ASC_SCSI_TIX_TYPE uchar
171 #define ASC_ALL_DEVICE_BIT_SET 0xFF
172 #define ASC_SCSI_BIT_ID_TYPE uchar
173 #define ASC_MAX_TID 7
174 #define ASC_MAX_LUN 7
175 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
176 #define ASC_MAX_SENSE_LEN 32
177 #define ASC_MIN_SENSE_LEN 14
178 #define ASC_SCSI_RESET_HOLD_TIME_US 60
181 * Narrow boards only support 12-byte commands, while wide boards
182 * extend to 16-byte commands.
184 #define ASC_MAX_CDB_LEN 12
185 #define ADV_MAX_CDB_LEN 16
187 #define MS_SDTR_LEN 0x03
188 #define MS_WDTR_LEN 0x02
190 #define ASC_SG_LIST_PER_Q 7
192 #define QS_READY 0x01
193 #define QS_DISC1 0x02
194 #define QS_DISC2 0x04
196 #define QS_ABORTED 0x40
198 #define QC_NO_CALLBACK 0x01
199 #define QC_SG_SWAP_QUEUE 0x02
200 #define QC_SG_HEAD 0x04
201 #define QC_DATA_IN 0x08
202 #define QC_DATA_OUT 0x10
203 #define QC_URGENT 0x20
204 #define QC_MSG_OUT 0x40
205 #define QC_REQ_SENSE 0x80
206 #define QCSG_SG_XFER_LIST 0x02
207 #define QCSG_SG_XFER_MORE 0x04
208 #define QCSG_SG_XFER_END 0x08
209 #define QD_IN_PROGRESS 0x00
210 #define QD_NO_ERROR 0x01
211 #define QD_ABORTED_BY_HOST 0x02
212 #define QD_WITH_ERROR 0x04
213 #define QD_INVALID_REQUEST 0x80
214 #define QD_INVALID_HOST_NUM 0x81
215 #define QD_INVALID_DEVICE 0x82
216 #define QD_ERR_INTERNAL 0xFF
217 #define QHSTA_NO_ERROR 0x00
218 #define QHSTA_M_SEL_TIMEOUT 0x11
219 #define QHSTA_M_DATA_OVER_RUN 0x12
220 #define QHSTA_M_DATA_UNDER_RUN 0x12
221 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
222 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
223 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
224 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
225 #define QHSTA_D_HOST_ABORT_FAILED 0x23
226 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
227 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
228 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
229 #define QHSTA_M_WTM_TIMEOUT 0x41
230 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
231 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
232 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
233 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
234 #define QHSTA_M_BAD_TAG_CODE 0x46
235 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
236 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
237 #define QHSTA_D_LRAM_CMP_ERROR 0x81
238 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
239 #define ASC_FLAG_SCSIQ_REQ 0x01
240 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
241 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
242 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
243 #define ASC_FLAG_WIN16 0x10
244 #define ASC_FLAG_WIN32 0x20
245 #define ASC_FLAG_ISA_OVER_16MB 0x40
246 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
247 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
248 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
249 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
250 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
251 #define ASC_SCSIQ_CPY_BEG 4
252 #define ASC_SCSIQ_SGHD_CPY_BEG 2
253 #define ASC_SCSIQ_B_FWD 0
254 #define ASC_SCSIQ_B_BWD 1
255 #define ASC_SCSIQ_B_STATUS 2
256 #define ASC_SCSIQ_B_QNO 3
257 #define ASC_SCSIQ_B_CNTL 4
258 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
259 #define ASC_SCSIQ_D_DATA_ADDR 8
260 #define ASC_SCSIQ_D_DATA_CNT 12
261 #define ASC_SCSIQ_B_SENSE_LEN 20
262 #define ASC_SCSIQ_DONE_INFO_BEG 22
263 #define ASC_SCSIQ_D_SRBPTR 22
264 #define ASC_SCSIQ_B_TARGET_IX 26
265 #define ASC_SCSIQ_B_CDB_LEN 28
266 #define ASC_SCSIQ_B_TAG_CODE 29
267 #define ASC_SCSIQ_W_VM_ID 30
268 #define ASC_SCSIQ_DONE_STATUS 32
269 #define ASC_SCSIQ_HOST_STATUS 33
270 #define ASC_SCSIQ_SCSI_STATUS 34
271 #define ASC_SCSIQ_CDB_BEG 36
272 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
273 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
274 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
275 #define ASC_SCSIQ_B_SG_WK_QP 49
276 #define ASC_SCSIQ_B_SG_WK_IX 50
277 #define ASC_SCSIQ_W_ALT_DC1 52
278 #define ASC_SCSIQ_B_LIST_CNT 6
279 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
280 #define ASC_SGQ_B_SG_CNTL 4
281 #define ASC_SGQ_B_SG_HEAD_QP 5
282 #define ASC_SGQ_B_SG_LIST_CNT 6
283 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
284 #define ASC_SGQ_LIST_BEG 8
285 #define ASC_DEF_SCSI1_QNG 4
286 #define ASC_MAX_SCSI1_QNG 4
287 #define ASC_DEF_SCSI2_QNG 16
288 #define ASC_MAX_SCSI2_QNG 32
289 #define ASC_TAG_CODE_MASK 0x23
290 #define ASC_STOP_REQ_RISC_STOP 0x01
291 #define ASC_STOP_ACK_RISC_STOP 0x03
292 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
293 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
294 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
295 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
296 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
297 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
298 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
299 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
300 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
301 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
303 typedef struct asc_scsiq_1 {
312 ASC_PADDR sense_addr;
317 typedef struct asc_scsiq_2 {
326 typedef struct asc_scsiq_3 {
333 typedef struct asc_scsiq_4 {
334 uchar cdb[ASC_MAX_CDB_LEN];
335 uchar y_first_sg_list_qp;
336 uchar y_working_sg_qp;
337 uchar y_working_sg_ix;
340 ushort x_reconnect_rtn;
341 ASC_PADDR x_saved_data_addr;
342 ASC_DCNT x_saved_data_cnt;
345 typedef struct asc_q_done_info {
354 ASC_DCNT remain_bytes;
357 typedef struct asc_sg_list {
362 typedef struct asc_sg_head {
365 ushort entry_to_copy;
367 ASC_SG_LIST sg_list[0];
370 typedef struct asc_scsi_q {
374 ASC_SG_HEAD *sg_head;
375 ushort remain_sg_entry_cnt;
376 ushort next_sg_index;
379 typedef struct asc_scsi_req_q {
383 ASC_SG_HEAD *sg_head;
386 uchar cdb[ASC_MAX_CDB_LEN];
387 uchar sense[ASC_MIN_SENSE_LEN];
390 typedef struct asc_scsi_bios_req_q {
394 ASC_SG_HEAD *sg_head;
397 uchar cdb[ASC_MAX_CDB_LEN];
398 uchar sense[ASC_MIN_SENSE_LEN];
399 } ASC_SCSI_BIOS_REQ_Q;
401 typedef struct asc_risc_q {
410 typedef struct asc_sg_list_q {
416 uchar sg_cur_list_cnt;
419 typedef struct asc_risc_sg_list_q {
423 ASC_SG_LIST sg_list[7];
424 } ASC_RISC_SG_LIST_Q;
426 #define ASCQ_ERR_Q_STATUS 0x0D
427 #define ASCQ_ERR_CUR_QNG 0x17
428 #define ASCQ_ERR_SG_Q_LINKS 0x18
429 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
430 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
431 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
434 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
436 #define ASC_WARN_NO_ERROR 0x0000
437 #define ASC_WARN_IO_PORT_ROTATE 0x0001
438 #define ASC_WARN_EEPROM_CHKSUM 0x0002
439 #define ASC_WARN_IRQ_MODIFIED 0x0004
440 #define ASC_WARN_AUTO_CONFIG 0x0008
441 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
442 #define ASC_WARN_EEPROM_RECOVER 0x0020
443 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
446 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
448 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
449 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
450 #define ASC_IERR_SET_PC_ADDR 0x0004
451 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
452 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
453 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
454 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
455 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
456 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
457 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
458 #define ASC_IERR_NO_BUS_TYPE 0x0400
459 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
460 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
461 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
463 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
464 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
465 #define ASC_MIN_FREE_Q (0x02)
466 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
467 #define ASC_MAX_TOTAL_QNG 240
468 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
469 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
470 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
471 #define ASC_MAX_INRAM_TAG_QNG 16
472 #define ASC_IOADR_GAP 0x10
473 #define ASC_SYN_MAX_OFFSET 0x0F
474 #define ASC_DEF_SDTR_OFFSET 0x0F
475 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
476 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
478 /* The narrow chip only supports a limited selection of transfer rates.
479 * These are encoded in the range 0..7 or 0..15 depending whether the chip
480 * is Ultra-capable or not. These tables let us convert from one to the other.
482 static const unsigned char asc_syn_xfer_period[8] = {
483 25, 30, 35, 40, 50, 60, 70, 85
486 static const unsigned char asc_syn_ultra_xfer_period[16] = {
487 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
490 typedef struct ext_msg {
496 uchar sdtr_xfer_period;
497 uchar sdtr_req_ack_offset;
512 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
513 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
514 #define wdtr_width u_ext_msg.wdtr.wdtr_width
515 #define mdp_b3 u_ext_msg.mdp_b3
516 #define mdp_b2 u_ext_msg.mdp_b2
517 #define mdp_b1 u_ext_msg.mdp_b1
518 #define mdp_b0 u_ext_msg.mdp_b0
520 typedef struct asc_dvc_cfg {
521 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
522 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
523 ASC_SCSI_BIT_ID_TYPE disc_enable;
524 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
527 uchar isa_dma_channel;
530 ushort mcode_version;
531 uchar max_tag_qng[ASC_MAX_TID + 1];
532 uchar sdtr_period_offset[ASC_MAX_TID + 1];
533 uchar adapter_info[6];
536 #define ASC_DEF_DVC_CNTL 0xFFFF
537 #define ASC_DEF_CHIP_SCSI_ID 7
538 #define ASC_DEF_ISA_DMA_SPEED 4
539 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
540 #define ASC_INIT_STATE_END_GET_CFG 0x0002
541 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
542 #define ASC_INIT_STATE_END_SET_CFG 0x0008
543 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
544 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
545 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
546 #define ASC_INIT_STATE_END_INQUIRY 0x0080
547 #define ASC_INIT_RESET_SCSI_DONE 0x0100
548 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
549 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
550 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
551 #define ASC_MIN_TAGGED_CMD 7
552 #define ASC_MAX_SCSI_RESET_WAIT 30
553 #define ASC_OVERRUN_BSIZE 64
555 struct asc_dvc_var; /* Forward Declaration. */
557 typedef struct asc_dvc_var {
563 ASC_SCSI_BIT_ID_TYPE init_sdtr;
564 ASC_SCSI_BIT_ID_TYPE sdtr_done;
565 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
566 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
567 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
568 ASC_SCSI_BIT_ID_TYPE start_motor;
570 dma_addr_t overrun_dma;
571 uchar scsi_reset_wait;
576 uchar in_critical_cnt;
577 uchar last_q_shortage;
579 uchar cur_dvc_qng[ASC_MAX_TID + 1];
580 uchar max_dvc_qng[ASC_MAX_TID + 1];
581 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
582 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
583 const uchar *sdtr_period_tbl;
585 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
588 uchar dos_int13_table[ASC_MAX_TID + 1];
589 ASC_DCNT max_dma_count;
590 ASC_SCSI_BIT_ID_TYPE no_scam;
591 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
592 uchar min_sdtr_index;
593 uchar max_sdtr_index;
594 struct asc_board *drv_ptr;
598 typedef struct asc_dvc_inq_info {
599 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
602 typedef struct asc_cap_info {
607 typedef struct asc_cap_info_array {
608 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
609 } ASC_CAP_INFO_ARRAY;
611 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
612 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
613 #define ASC_CNTL_INITIATOR (ushort)0x0001
614 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
615 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
616 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
617 #define ASC_CNTL_NO_SCAM (ushort)0x0010
618 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
619 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
620 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
621 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
622 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
623 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
624 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
625 #define ASC_CNTL_BURST_MODE (ushort)0x2000
626 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
627 #define ASC_EEP_DVC_CFG_BEG_VL 2
628 #define ASC_EEP_MAX_DVC_ADDR_VL 15
629 #define ASC_EEP_DVC_CFG_BEG 32
630 #define ASC_EEP_MAX_DVC_ADDR 45
631 #define ASC_EEP_MAX_RETRY 20
634 * These macros keep the chip SCSI id and ISA DMA speed
635 * bitfields in board order. C bitfields aren't portable
636 * between big and little-endian platforms so they are
640 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
641 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
642 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
643 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
644 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
645 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
647 typedef struct asceep_config {
659 uchar id_speed; /* low order 4 bits is chip scsi id */
660 /* high order 4 bits is isa dma speed */
661 uchar dos_int13_table[ASC_MAX_TID + 1];
662 uchar adapter_info[6];
667 #define ASC_EEP_CMD_READ 0x80
668 #define ASC_EEP_CMD_WRITE 0x40
669 #define ASC_EEP_CMD_WRITE_ABLE 0x30
670 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
671 #define ASCV_MSGOUT_BEG 0x0000
672 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
673 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
674 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
675 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
676 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
677 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
678 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
679 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
680 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
681 #define ASCV_BREAK_ADDR (ushort)0x0028
682 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
683 #define ASCV_BREAK_CONTROL (ushort)0x002C
684 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
686 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
687 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
688 #define ASCV_MCODE_SIZE_W (ushort)0x0034
689 #define ASCV_STOP_CODE_B (ushort)0x0036
690 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
691 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
692 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
693 #define ASCV_HALTCODE_W (ushort)0x0040
694 #define ASCV_CHKSUM_W (ushort)0x0042
695 #define ASCV_MC_DATE_W (ushort)0x0044
696 #define ASCV_MC_VER_W (ushort)0x0046
697 #define ASCV_NEXTRDY_B (ushort)0x0048
698 #define ASCV_DONENEXT_B (ushort)0x0049
699 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
700 #define ASCV_SCSIBUSY_B (ushort)0x004B
701 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
702 #define ASCV_CURCDB_B (ushort)0x004D
703 #define ASCV_RCLUN_B (ushort)0x004E
704 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
705 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
706 #define ASCV_DISC_ENABLE_B (ushort)0x0052
707 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
708 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
709 #define ASCV_MCODE_CNTL_B (ushort)0x0056
710 #define ASCV_NULL_TARGET_B (ushort)0x0057
711 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
712 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
713 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
714 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
715 #define ASCV_HOST_FLAG_B (ushort)0x005D
716 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
717 #define ASCV_VER_SERIAL_B (ushort)0x0065
718 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
719 #define ASCV_WTM_FLAG_B (ushort)0x0068
720 #define ASCV_RISC_FLAG_B (ushort)0x006A
721 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
722 #define ASC_HOST_FLAG_IN_ISR 0x01
723 #define ASC_HOST_FLAG_ACK_INT 0x02
724 #define ASC_RISC_FLAG_GEN_INT 0x01
725 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
726 #define IOP_CTRL (0x0F)
727 #define IOP_STATUS (0x0E)
728 #define IOP_INT_ACK IOP_STATUS
729 #define IOP_REG_IFC (0x0D)
730 #define IOP_SYN_OFFSET (0x0B)
731 #define IOP_EXTRA_CONTROL (0x0D)
732 #define IOP_REG_PC (0x0C)
733 #define IOP_RAM_ADDR (0x0A)
734 #define IOP_RAM_DATA (0x08)
735 #define IOP_EEP_DATA (0x06)
736 #define IOP_EEP_CMD (0x07)
737 #define IOP_VERSION (0x03)
738 #define IOP_CONFIG_HIGH (0x04)
739 #define IOP_CONFIG_LOW (0x02)
740 #define IOP_SIG_BYTE (0x01)
741 #define IOP_SIG_WORD (0x00)
742 #define IOP_REG_DC1 (0x0E)
743 #define IOP_REG_DC0 (0x0C)
744 #define IOP_REG_SB (0x0B)
745 #define IOP_REG_DA1 (0x0A)
746 #define IOP_REG_DA0 (0x08)
747 #define IOP_REG_SC (0x09)
748 #define IOP_DMA_SPEED (0x07)
749 #define IOP_REG_FLAG (0x07)
750 #define IOP_FIFO_H (0x06)
751 #define IOP_FIFO_L (0x04)
752 #define IOP_REG_ID (0x05)
753 #define IOP_REG_QP (0x03)
754 #define IOP_REG_IH (0x02)
755 #define IOP_REG_IX (0x01)
756 #define IOP_REG_AX (0x00)
757 #define IFC_REG_LOCK (0x00)
758 #define IFC_REG_UNLOCK (0x09)
759 #define IFC_WR_EN_FILTER (0x10)
760 #define IFC_RD_NO_EEPROM (0x10)
761 #define IFC_SLEW_RATE (0x20)
762 #define IFC_ACT_NEG (0x40)
763 #define IFC_INP_FILTER (0x80)
764 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
765 #define SC_SEL (uchar)(0x80)
766 #define SC_BSY (uchar)(0x40)
767 #define SC_ACK (uchar)(0x20)
768 #define SC_REQ (uchar)(0x10)
769 #define SC_ATN (uchar)(0x08)
770 #define SC_IO (uchar)(0x04)
771 #define SC_CD (uchar)(0x02)
772 #define SC_MSG (uchar)(0x01)
773 #define SEC_SCSI_CTL (uchar)(0x80)
774 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
775 #define SEC_SLEW_RATE (uchar)(0x20)
776 #define SEC_ENABLE_FILTER (uchar)(0x10)
777 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
778 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
779 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
780 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
781 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
782 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
783 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
784 #define ASC_MAX_QNO 0xF8
785 #define ASC_DATA_SEC_BEG (ushort)0x0080
786 #define ASC_DATA_SEC_END (ushort)0x0080
787 #define ASC_CODE_SEC_BEG (ushort)0x0080
788 #define ASC_CODE_SEC_END (ushort)0x0080
789 #define ASC_QADR_BEG (0x4000)
790 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
791 #define ASC_QADR_END (ushort)0x7FFF
792 #define ASC_QLAST_ADR (ushort)0x7FC0
793 #define ASC_QBLK_SIZE 0x40
794 #define ASC_BIOS_DATA_QBEG 0xF8
795 #define ASC_MIN_ACTIVE_QNO 0x01
796 #define ASC_QLINK_END 0xFF
797 #define ASC_EEPROM_WORDS 0x10
798 #define ASC_MAX_MGS_LEN 0x10
799 #define ASC_BIOS_ADDR_DEF 0xDC00
800 #define ASC_BIOS_SIZE 0x3800
801 #define ASC_BIOS_RAM_OFF 0x3800
802 #define ASC_BIOS_RAM_SIZE 0x800
803 #define ASC_BIOS_MIN_ADDR 0xC000
804 #define ASC_BIOS_MAX_ADDR 0xEC00
805 #define ASC_BIOS_BANK_SIZE 0x0400
806 #define ASC_MCODE_START_ADDR 0x0080
807 #define ASC_CFG0_HOST_INT_ON 0x0020
808 #define ASC_CFG0_BIOS_ON 0x0040
809 #define ASC_CFG0_VERA_BURST_ON 0x0080
810 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
811 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
812 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
813 #define ASC_CFG_MSW_CLR_MASK 0x3080
814 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
815 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
816 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
817 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
818 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
819 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
820 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
821 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
822 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
823 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
824 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
825 #define CSW_HALTED (ASC_CS_TYPE)0x0010
826 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
827 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
828 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
829 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
830 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
831 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
832 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
833 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
834 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
835 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
836 #define CC_CHIP_RESET (uchar)0x80
837 #define CC_SCSI_RESET (uchar)0x40
838 #define CC_HALT (uchar)0x20
839 #define CC_SINGLE_STEP (uchar)0x10
840 #define CC_DMA_ABLE (uchar)0x08
841 #define CC_TEST (uchar)0x04
842 #define CC_BANK_ONE (uchar)0x02
843 #define CC_DIAG (uchar)0x01
844 #define ASC_1000_ID0W 0x04C1
845 #define ASC_1000_ID0W_FIX 0x00C1
846 #define ASC_1000_ID1B 0x25
847 #define ASC_EISA_REV_IOP_MASK (0x0C83)
848 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
849 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
850 #define INS_HALTINT (ushort)0x6281
851 #define INS_HALT (ushort)0x6280
852 #define INS_SINT (ushort)0x6200
853 #define INS_RFLAG_WTM (ushort)0x7380
854 #define ASC_MC_SAVE_CODE_WSIZE 0x500
855 #define ASC_MC_SAVE_DATA_WSIZE 0x40
857 typedef struct asc_mc_saved {
858 ushort data[ASC_MC_SAVE_DATA_WSIZE];
859 ushort code[ASC_MC_SAVE_CODE_WSIZE];
862 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
863 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
864 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
865 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
866 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
867 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
868 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
869 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
870 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
871 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
872 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
873 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
874 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
875 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
876 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
877 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
878 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
879 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
880 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
881 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
882 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
883 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
884 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
885 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
886 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
887 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
888 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
889 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
890 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
891 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
892 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
893 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
894 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
895 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
896 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
897 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
898 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
899 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
900 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
901 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
902 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
903 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
904 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
905 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
906 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
907 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
908 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
909 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
910 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
911 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
912 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
913 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
914 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
915 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
916 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
917 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
918 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
919 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
920 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
921 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
922 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
923 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
924 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
925 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
926 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
927 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
928 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
931 * Portable Data Types
933 * Any instance where a 32-bit long or pointer type is assumed
934 * for precision or HW defined structures, the following define
935 * types must be used. In Linux the char, short, and int types
936 * are all consistent at 8, 16, and 32 bits respectively. Pointers
937 * and long types are 64 bits on Alpha and UltraSPARC.
939 #define ADV_PADDR __u32 /* Physical address data type. */
940 #define ADV_VADDR __u32 /* Virtual address data type. */
941 #define ADV_DCNT __u32 /* Unsigned Data count type. */
942 #define ADV_SDCNT __s32 /* Signed Data count type. */
945 * These macros are used to convert a virtual address to a
946 * 32-bit value. This currently can be used on Linux Alpha
947 * which uses 64-bit virtual address but a 32-bit bus address.
948 * This is likely to break in the future, but doing this now
949 * will give us time to change the HW and FW to handle 64-bit
952 #define ADV_VADDR_TO_U32 virt_to_bus
953 #define ADV_U32_TO_VADDR bus_to_virt
955 #define AdvPortAddr void __iomem * /* Virtual memory address size */
958 * Define Adv Library required memory access macros.
960 #define ADV_MEM_READB(addr) readb(addr)
961 #define ADV_MEM_READW(addr) readw(addr)
962 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
963 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
964 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
967 * Define total number of simultaneous maximum element scatter-gather
968 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
969 * maximum number of outstanding commands per wide host adapter. Each
970 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
971 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
972 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
973 * structures or 255 scatter-gather elements.
975 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
978 * Define maximum number of scatter-gather elements per request.
980 #define ADV_MAX_SG_LIST 255
981 #define NO_OF_SG_PER_BLOCK 15
983 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
984 #define ADV_EEP_DVC_CFG_END (0x15)
985 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
986 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
988 #define ADV_EEP_DELAY_MS 100
990 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
991 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
993 * For the ASC3550 Bit 13 is Termination Polarity control bit.
994 * For later ICs Bit 13 controls whether the CIS (Card Information
995 * Service Section) is loaded from EEPROM.
997 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
998 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1002 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1003 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1004 * Function 0 will specify INT B.
1006 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1007 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1008 * Function 1 will specify INT A.
1010 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1012 typedef struct adveep_3550_config {
1013 /* Word Offset, Description */
1015 ushort cfg_lsw; /* 00 power up initialization */
1016 /* bit 13 set - Term Polarity Control */
1017 /* bit 14 set - BIOS Enable */
1018 /* bit 15 set - Big Endian Mode */
1019 ushort cfg_msw; /* 01 unused */
1020 ushort disc_enable; /* 02 disconnect enable */
1021 ushort wdtr_able; /* 03 Wide DTR able */
1022 ushort sdtr_able; /* 04 Synchronous DTR able */
1023 ushort start_motor; /* 05 send start up motor */
1024 ushort tagqng_able; /* 06 tag queuing able */
1025 ushort bios_scan; /* 07 BIOS device control */
1026 ushort scam_tolerant; /* 08 no scam */
1028 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1029 uchar bios_boot_delay; /* power up wait */
1031 uchar scsi_reset_delay; /* 10 reset delay */
1032 uchar bios_id_lun; /* first boot device scsi id & lun */
1033 /* high nibble is lun */
1034 /* low nibble is scsi id */
1036 uchar termination; /* 11 0 - automatic */
1037 /* 1 - low off / high off */
1038 /* 2 - low off / high on */
1039 /* 3 - low on / high on */
1040 /* There is no low on / high off */
1042 uchar reserved1; /* reserved byte (not used) */
1044 ushort bios_ctrl; /* 12 BIOS control bits */
1045 /* bit 0 BIOS don't act as initiator. */
1046 /* bit 1 BIOS > 1 GB support */
1047 /* bit 2 BIOS > 2 Disk Support */
1048 /* bit 3 BIOS don't support removables */
1049 /* bit 4 BIOS support bootable CD */
1050 /* bit 5 BIOS scan enabled */
1051 /* bit 6 BIOS support multiple LUNs */
1052 /* bit 7 BIOS display of message */
1053 /* bit 8 SCAM disabled */
1054 /* bit 9 Reset SCSI bus during init. */
1056 /* bit 11 No verbose initialization. */
1057 /* bit 12 SCSI parity enabled */
1061 ushort ultra_able; /* 13 ULTRA speed able */
1062 ushort reserved2; /* 14 reserved */
1063 uchar max_host_qng; /* 15 maximum host queuing */
1064 uchar max_dvc_qng; /* maximum per device queuing */
1065 ushort dvc_cntl; /* 16 control bit for driver */
1066 ushort bug_fix; /* 17 control bit for bug fix */
1067 ushort serial_number_word1; /* 18 Board serial number word 1 */
1068 ushort serial_number_word2; /* 19 Board serial number word 2 */
1069 ushort serial_number_word3; /* 20 Board serial number word 3 */
1070 ushort check_sum; /* 21 EEP check sum */
1071 uchar oem_name[16]; /* 22 OEM name */
1072 ushort dvc_err_code; /* 30 last device driver error code */
1073 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1074 ushort adv_err_addr; /* 32 last uc error address */
1075 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1076 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1077 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1078 ushort num_of_err; /* 36 number of error */
1079 } ADVEEP_3550_CONFIG;
1081 typedef struct adveep_38C0800_config {
1082 /* Word Offset, Description */
1084 ushort cfg_lsw; /* 00 power up initialization */
1085 /* bit 13 set - Load CIS */
1086 /* bit 14 set - BIOS Enable */
1087 /* bit 15 set - Big Endian Mode */
1088 ushort cfg_msw; /* 01 unused */
1089 ushort disc_enable; /* 02 disconnect enable */
1090 ushort wdtr_able; /* 03 Wide DTR able */
1091 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1092 ushort start_motor; /* 05 send start up motor */
1093 ushort tagqng_able; /* 06 tag queuing able */
1094 ushort bios_scan; /* 07 BIOS device control */
1095 ushort scam_tolerant; /* 08 no scam */
1097 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1098 uchar bios_boot_delay; /* power up wait */
1100 uchar scsi_reset_delay; /* 10 reset delay */
1101 uchar bios_id_lun; /* first boot device scsi id & lun */
1102 /* high nibble is lun */
1103 /* low nibble is scsi id */
1105 uchar termination_se; /* 11 0 - automatic */
1106 /* 1 - low off / high off */
1107 /* 2 - low off / high on */
1108 /* 3 - low on / high on */
1109 /* There is no low on / high off */
1111 uchar termination_lvd; /* 11 0 - automatic */
1112 /* 1 - low off / high off */
1113 /* 2 - low off / high on */
1114 /* 3 - low on / high on */
1115 /* There is no low on / high off */
1117 ushort bios_ctrl; /* 12 BIOS control bits */
1118 /* bit 0 BIOS don't act as initiator. */
1119 /* bit 1 BIOS > 1 GB support */
1120 /* bit 2 BIOS > 2 Disk Support */
1121 /* bit 3 BIOS don't support removables */
1122 /* bit 4 BIOS support bootable CD */
1123 /* bit 5 BIOS scan enabled */
1124 /* bit 6 BIOS support multiple LUNs */
1125 /* bit 7 BIOS display of message */
1126 /* bit 8 SCAM disabled */
1127 /* bit 9 Reset SCSI bus during init. */
1129 /* bit 11 No verbose initialization. */
1130 /* bit 12 SCSI parity enabled */
1134 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1135 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1136 uchar max_host_qng; /* 15 maximum host queueing */
1137 uchar max_dvc_qng; /* maximum per device queuing */
1138 ushort dvc_cntl; /* 16 control bit for driver */
1139 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1140 ushort serial_number_word1; /* 18 Board serial number word 1 */
1141 ushort serial_number_word2; /* 19 Board serial number word 2 */
1142 ushort serial_number_word3; /* 20 Board serial number word 3 */
1143 ushort check_sum; /* 21 EEP check sum */
1144 uchar oem_name[16]; /* 22 OEM name */
1145 ushort dvc_err_code; /* 30 last device driver error code */
1146 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1147 ushort adv_err_addr; /* 32 last uc error address */
1148 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1149 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1150 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1151 ushort reserved36; /* 36 reserved */
1152 ushort reserved37; /* 37 reserved */
1153 ushort reserved38; /* 38 reserved */
1154 ushort reserved39; /* 39 reserved */
1155 ushort reserved40; /* 40 reserved */
1156 ushort reserved41; /* 41 reserved */
1157 ushort reserved42; /* 42 reserved */
1158 ushort reserved43; /* 43 reserved */
1159 ushort reserved44; /* 44 reserved */
1160 ushort reserved45; /* 45 reserved */
1161 ushort reserved46; /* 46 reserved */
1162 ushort reserved47; /* 47 reserved */
1163 ushort reserved48; /* 48 reserved */
1164 ushort reserved49; /* 49 reserved */
1165 ushort reserved50; /* 50 reserved */
1166 ushort reserved51; /* 51 reserved */
1167 ushort reserved52; /* 52 reserved */
1168 ushort reserved53; /* 53 reserved */
1169 ushort reserved54; /* 54 reserved */
1170 ushort reserved55; /* 55 reserved */
1171 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1172 ushort cisprt_msw; /* 57 CIS PTR MSW */
1173 ushort subsysvid; /* 58 SubSystem Vendor ID */
1174 ushort subsysid; /* 59 SubSystem ID */
1175 ushort reserved60; /* 60 reserved */
1176 ushort reserved61; /* 61 reserved */
1177 ushort reserved62; /* 62 reserved */
1178 ushort reserved63; /* 63 reserved */
1179 } ADVEEP_38C0800_CONFIG;
1181 typedef struct adveep_38C1600_config {
1182 /* Word Offset, Description */
1184 ushort cfg_lsw; /* 00 power up initialization */
1185 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1186 /* clear - Func. 0 INTA, Func. 1 INTB */
1187 /* bit 13 set - Load CIS */
1188 /* bit 14 set - BIOS Enable */
1189 /* bit 15 set - Big Endian Mode */
1190 ushort cfg_msw; /* 01 unused */
1191 ushort disc_enable; /* 02 disconnect enable */
1192 ushort wdtr_able; /* 03 Wide DTR able */
1193 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1194 ushort start_motor; /* 05 send start up motor */
1195 ushort tagqng_able; /* 06 tag queuing able */
1196 ushort bios_scan; /* 07 BIOS device control */
1197 ushort scam_tolerant; /* 08 no scam */
1199 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1200 uchar bios_boot_delay; /* power up wait */
1202 uchar scsi_reset_delay; /* 10 reset delay */
1203 uchar bios_id_lun; /* first boot device scsi id & lun */
1204 /* high nibble is lun */
1205 /* low nibble is scsi id */
1207 uchar termination_se; /* 11 0 - automatic */
1208 /* 1 - low off / high off */
1209 /* 2 - low off / high on */
1210 /* 3 - low on / high on */
1211 /* There is no low on / high off */
1213 uchar termination_lvd; /* 11 0 - automatic */
1214 /* 1 - low off / high off */
1215 /* 2 - low off / high on */
1216 /* 3 - low on / high on */
1217 /* There is no low on / high off */
1219 ushort bios_ctrl; /* 12 BIOS control bits */
1220 /* bit 0 BIOS don't act as initiator. */
1221 /* bit 1 BIOS > 1 GB support */
1222 /* bit 2 BIOS > 2 Disk Support */
1223 /* bit 3 BIOS don't support removables */
1224 /* bit 4 BIOS support bootable CD */
1225 /* bit 5 BIOS scan enabled */
1226 /* bit 6 BIOS support multiple LUNs */
1227 /* bit 7 BIOS display of message */
1228 /* bit 8 SCAM disabled */
1229 /* bit 9 Reset SCSI bus during init. */
1230 /* bit 10 Basic Integrity Checking disabled */
1231 /* bit 11 No verbose initialization. */
1232 /* bit 12 SCSI parity enabled */
1233 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1236 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1237 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1238 uchar max_host_qng; /* 15 maximum host queueing */
1239 uchar max_dvc_qng; /* maximum per device queuing */
1240 ushort dvc_cntl; /* 16 control bit for driver */
1241 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1242 ushort serial_number_word1; /* 18 Board serial number word 1 */
1243 ushort serial_number_word2; /* 19 Board serial number word 2 */
1244 ushort serial_number_word3; /* 20 Board serial number word 3 */
1245 ushort check_sum; /* 21 EEP check sum */
1246 uchar oem_name[16]; /* 22 OEM name */
1247 ushort dvc_err_code; /* 30 last device driver error code */
1248 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1249 ushort adv_err_addr; /* 32 last uc error address */
1250 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1251 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1252 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1253 ushort reserved36; /* 36 reserved */
1254 ushort reserved37; /* 37 reserved */
1255 ushort reserved38; /* 38 reserved */
1256 ushort reserved39; /* 39 reserved */
1257 ushort reserved40; /* 40 reserved */
1258 ushort reserved41; /* 41 reserved */
1259 ushort reserved42; /* 42 reserved */
1260 ushort reserved43; /* 43 reserved */
1261 ushort reserved44; /* 44 reserved */
1262 ushort reserved45; /* 45 reserved */
1263 ushort reserved46; /* 46 reserved */
1264 ushort reserved47; /* 47 reserved */
1265 ushort reserved48; /* 48 reserved */
1266 ushort reserved49; /* 49 reserved */
1267 ushort reserved50; /* 50 reserved */
1268 ushort reserved51; /* 51 reserved */
1269 ushort reserved52; /* 52 reserved */
1270 ushort reserved53; /* 53 reserved */
1271 ushort reserved54; /* 54 reserved */
1272 ushort reserved55; /* 55 reserved */
1273 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1274 ushort cisprt_msw; /* 57 CIS PTR MSW */
1275 ushort subsysvid; /* 58 SubSystem Vendor ID */
1276 ushort subsysid; /* 59 SubSystem ID */
1277 ushort reserved60; /* 60 reserved */
1278 ushort reserved61; /* 61 reserved */
1279 ushort reserved62; /* 62 reserved */
1280 ushort reserved63; /* 63 reserved */
1281 } ADVEEP_38C1600_CONFIG;
1286 #define ASC_EEP_CMD_DONE 0x0200
1289 #define BIOS_CTRL_BIOS 0x0001
1290 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1291 #define BIOS_CTRL_GT_2_DISK 0x0004
1292 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1293 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1294 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1295 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1296 #define BIOS_CTRL_NO_SCAM 0x0100
1297 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1298 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1299 #define BIOS_CTRL_SCSI_PARITY 0x1000
1300 #define BIOS_CTRL_AIPP_DIS 0x2000
1302 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1304 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1307 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1308 * a special 16K Adv Library and Microcode version. After the issue is
1309 * resolved, should restore 32K support.
1311 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1313 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1316 * Byte I/O register address from base of 'iop_base'.
1318 #define IOPB_INTR_STATUS_REG 0x00
1319 #define IOPB_CHIP_ID_1 0x01
1320 #define IOPB_INTR_ENABLES 0x02
1321 #define IOPB_CHIP_TYPE_REV 0x03
1322 #define IOPB_RES_ADDR_4 0x04
1323 #define IOPB_RES_ADDR_5 0x05
1324 #define IOPB_RAM_DATA 0x06
1325 #define IOPB_RES_ADDR_7 0x07
1326 #define IOPB_FLAG_REG 0x08
1327 #define IOPB_RES_ADDR_9 0x09
1328 #define IOPB_RISC_CSR 0x0A
1329 #define IOPB_RES_ADDR_B 0x0B
1330 #define IOPB_RES_ADDR_C 0x0C
1331 #define IOPB_RES_ADDR_D 0x0D
1332 #define IOPB_SOFT_OVER_WR 0x0E
1333 #define IOPB_RES_ADDR_F 0x0F
1334 #define IOPB_MEM_CFG 0x10
1335 #define IOPB_RES_ADDR_11 0x11
1336 #define IOPB_GPIO_DATA 0x12
1337 #define IOPB_RES_ADDR_13 0x13
1338 #define IOPB_FLASH_PAGE 0x14
1339 #define IOPB_RES_ADDR_15 0x15
1340 #define IOPB_GPIO_CNTL 0x16
1341 #define IOPB_RES_ADDR_17 0x17
1342 #define IOPB_FLASH_DATA 0x18
1343 #define IOPB_RES_ADDR_19 0x19
1344 #define IOPB_RES_ADDR_1A 0x1A
1345 #define IOPB_RES_ADDR_1B 0x1B
1346 #define IOPB_RES_ADDR_1C 0x1C
1347 #define IOPB_RES_ADDR_1D 0x1D
1348 #define IOPB_RES_ADDR_1E 0x1E
1349 #define IOPB_RES_ADDR_1F 0x1F
1350 #define IOPB_DMA_CFG0 0x20
1351 #define IOPB_DMA_CFG1 0x21
1352 #define IOPB_TICKLE 0x22
1353 #define IOPB_DMA_REG_WR 0x23
1354 #define IOPB_SDMA_STATUS 0x24
1355 #define IOPB_SCSI_BYTE_CNT 0x25
1356 #define IOPB_HOST_BYTE_CNT 0x26
1357 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1358 #define IOPB_BYTE_TO_XFER_0 0x28
1359 #define IOPB_BYTE_TO_XFER_1 0x29
1360 #define IOPB_BYTE_TO_XFER_2 0x2A
1361 #define IOPB_BYTE_TO_XFER_3 0x2B
1362 #define IOPB_ACC_GRP 0x2C
1363 #define IOPB_RES_ADDR_2D 0x2D
1364 #define IOPB_DEV_ID 0x2E
1365 #define IOPB_RES_ADDR_2F 0x2F
1366 #define IOPB_SCSI_DATA 0x30
1367 #define IOPB_RES_ADDR_31 0x31
1368 #define IOPB_RES_ADDR_32 0x32
1369 #define IOPB_SCSI_DATA_HSHK 0x33
1370 #define IOPB_SCSI_CTRL 0x34
1371 #define IOPB_RES_ADDR_35 0x35
1372 #define IOPB_RES_ADDR_36 0x36
1373 #define IOPB_RES_ADDR_37 0x37
1374 #define IOPB_RAM_BIST 0x38
1375 #define IOPB_PLL_TEST 0x39
1376 #define IOPB_PCI_INT_CFG 0x3A
1377 #define IOPB_RES_ADDR_3B 0x3B
1378 #define IOPB_RFIFO_CNT 0x3C
1379 #define IOPB_RES_ADDR_3D 0x3D
1380 #define IOPB_RES_ADDR_3E 0x3E
1381 #define IOPB_RES_ADDR_3F 0x3F
1384 * Word I/O register address from base of 'iop_base'.
1386 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1387 #define IOPW_CTRL_REG 0x02 /* CC */
1388 #define IOPW_RAM_ADDR 0x04 /* LA */
1389 #define IOPW_RAM_DATA 0x06 /* LD */
1390 #define IOPW_RES_ADDR_08 0x08
1391 #define IOPW_RISC_CSR 0x0A /* CSR */
1392 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1393 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1394 #define IOPW_RES_ADDR_10 0x10
1395 #define IOPW_SEL_MASK 0x12 /* SM */
1396 #define IOPW_RES_ADDR_14 0x14
1397 #define IOPW_FLASH_ADDR 0x16 /* FA */
1398 #define IOPW_RES_ADDR_18 0x18
1399 #define IOPW_EE_CMD 0x1A /* EC */
1400 #define IOPW_EE_DATA 0x1C /* ED */
1401 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1402 #define IOPW_RES_ADDR_20 0x20
1403 #define IOPW_Q_BASE 0x22 /* QB */
1404 #define IOPW_QP 0x24 /* QP */
1405 #define IOPW_IX 0x26 /* IX */
1406 #define IOPW_SP 0x28 /* SP */
1407 #define IOPW_PC 0x2A /* PC */
1408 #define IOPW_RES_ADDR_2C 0x2C
1409 #define IOPW_RES_ADDR_2E 0x2E
1410 #define IOPW_SCSI_DATA 0x30 /* SD */
1411 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1412 #define IOPW_SCSI_CTRL 0x34 /* SC */
1413 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1414 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1415 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1416 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1417 #define IOPW_RES_ADDR_3C 0x3C
1418 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1421 * Doubleword I/O register address from base of 'iop_base'.
1423 #define IOPDW_RES_ADDR_0 0x00
1424 #define IOPDW_RAM_DATA 0x04
1425 #define IOPDW_RES_ADDR_8 0x08
1426 #define IOPDW_RES_ADDR_C 0x0C
1427 #define IOPDW_RES_ADDR_10 0x10
1428 #define IOPDW_COMMA 0x14
1429 #define IOPDW_COMMB 0x18
1430 #define IOPDW_RES_ADDR_1C 0x1C
1431 #define IOPDW_SDMA_ADDR0 0x20
1432 #define IOPDW_SDMA_ADDR1 0x24
1433 #define IOPDW_SDMA_COUNT 0x28
1434 #define IOPDW_SDMA_ERROR 0x2C
1435 #define IOPDW_RDMA_ADDR0 0x30
1436 #define IOPDW_RDMA_ADDR1 0x34
1437 #define IOPDW_RDMA_COUNT 0x38
1438 #define IOPDW_RDMA_ERROR 0x3C
1440 #define ADV_CHIP_ID_BYTE 0x25
1441 #define ADV_CHIP_ID_WORD 0x04C1
1443 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1444 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1445 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1446 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1447 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1448 #define ADV_INTR_ENABLE_RST_INTR 0x20
1449 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1450 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1452 #define ADV_INTR_STATUS_INTRA 0x01
1453 #define ADV_INTR_STATUS_INTRB 0x02
1454 #define ADV_INTR_STATUS_INTRC 0x04
1456 #define ADV_RISC_CSR_STOP (0x0000)
1457 #define ADV_RISC_TEST_COND (0x2000)
1458 #define ADV_RISC_CSR_RUN (0x4000)
1459 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1461 #define ADV_CTRL_REG_HOST_INTR 0x0100
1462 #define ADV_CTRL_REG_SEL_INTR 0x0200
1463 #define ADV_CTRL_REG_DPR_INTR 0x0400
1464 #define ADV_CTRL_REG_RTA_INTR 0x0800
1465 #define ADV_CTRL_REG_RMA_INTR 0x1000
1466 #define ADV_CTRL_REG_RES_BIT14 0x2000
1467 #define ADV_CTRL_REG_DPE_INTR 0x4000
1468 #define ADV_CTRL_REG_POWER_DONE 0x8000
1469 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1471 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1472 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1473 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1474 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1475 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1477 #define ADV_TICKLE_NOP 0x00
1478 #define ADV_TICKLE_A 0x01
1479 #define ADV_TICKLE_B 0x02
1480 #define ADV_TICKLE_C 0x03
1482 #define AdvIsIntPending(port) \
1483 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1486 * SCSI_CFG0 Register bit definitions
1488 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1489 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1490 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1491 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1492 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1493 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1494 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1495 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1496 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1497 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1498 #define OUR_ID 0x000F /* SCSI ID */
1501 * SCSI_CFG1 Register bit definitions
1503 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1504 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1505 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1506 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1507 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1508 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1509 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1510 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1511 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1512 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1513 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1514 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1515 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1516 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1517 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1520 * Addendum for ASC-38C0800 Chip
1522 * The ASC-38C1600 Chip uses the same definitions except that the
1523 * bus mode override bits [12:10] have been moved to byte register
1524 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1525 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1526 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1527 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1528 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1530 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1531 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1532 #define HVD 0x1000 /* HVD Device Detect */
1533 #define LVD 0x0800 /* LVD Device Detect */
1534 #define SE 0x0400 /* SE Device Detect */
1535 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1536 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1537 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1538 #define TERM_SE 0x0030 /* SE Termination Bits */
1539 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1540 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1541 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1542 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1543 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1544 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1545 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1546 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1548 #define CABLE_ILLEGAL_A 0x7
1549 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1551 #define CABLE_ILLEGAL_B 0xB
1552 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1555 * MEM_CFG Register bit definitions
1557 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1558 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1559 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1560 #define RAM_SZ_2KB 0x00 /* 2 KB */
1561 #define RAM_SZ_4KB 0x04 /* 4 KB */
1562 #define RAM_SZ_8KB 0x08 /* 8 KB */
1563 #define RAM_SZ_16KB 0x0C /* 16 KB */
1564 #define RAM_SZ_32KB 0x10 /* 32 KB */
1565 #define RAM_SZ_64KB 0x14 /* 64 KB */
1568 * DMA_CFG0 Register bit definitions
1570 * This register is only accessible to the host.
1572 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1573 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1574 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1575 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1576 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1577 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1578 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1579 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1580 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1581 #define START_CTL 0x0C /* DMA start conditions */
1582 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1583 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1584 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1585 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1586 #define READ_CMD 0x03 /* Memory Read Method */
1587 #define READ_CMD_MR 0x00 /* Memory Read */
1588 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1589 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1592 * ASC-38C0800 RAM BIST Register bit definitions
1594 #define RAM_TEST_MODE 0x80
1595 #define PRE_TEST_MODE 0x40
1596 #define NORMAL_MODE 0x00
1597 #define RAM_TEST_DONE 0x10
1598 #define RAM_TEST_STATUS 0x0F
1599 #define RAM_TEST_HOST_ERROR 0x08
1600 #define RAM_TEST_INTRAM_ERROR 0x04
1601 #define RAM_TEST_RISC_ERROR 0x02
1602 #define RAM_TEST_SCSI_ERROR 0x01
1603 #define RAM_TEST_SUCCESS 0x00
1604 #define PRE_TEST_VALUE 0x05
1605 #define NORMAL_VALUE 0x00
1608 * ASC38C1600 Definitions
1610 * IOPB_PCI_INT_CFG Bit Field Definitions
1613 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1616 * Bit 1 can be set to change the interrupt for the Function to operate in
1617 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1618 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1619 * mode, otherwise the operating mode is undefined.
1621 #define TOTEMPOLE 0x02
1624 * Bit 0 can be used to change the Int Pin for the Function. The value is
1625 * 0 by default for both Functions with Function 0 using INT A and Function
1626 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1629 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1630 * value specified in the PCI Configuration Space.
1635 * Adv Library Status Definitions
1639 #define ADV_SUCCESS 1
1641 #define ADV_ERROR (-1)
1644 * ADV_DVC_VAR 'warn_code' values
1646 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1647 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1648 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1649 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1651 #define ADV_MAX_TID 15 /* max. target identifier */
1652 #define ADV_MAX_LUN 7 /* max. logical unit number */
1655 * Fixed locations of microcode operating variables.
1657 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1658 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1659 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1660 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1661 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1662 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1663 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1664 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1665 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1666 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1667 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1668 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1669 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1670 #define ASC_MC_CHIP_TYPE 0x009A
1671 #define ASC_MC_INTRB_CODE 0x009B
1672 #define ASC_MC_WDTR_ABLE 0x009C
1673 #define ASC_MC_SDTR_ABLE 0x009E
1674 #define ASC_MC_TAGQNG_ABLE 0x00A0
1675 #define ASC_MC_DISC_ENABLE 0x00A2
1676 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1677 #define ASC_MC_IDLE_CMD 0x00A6
1678 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1679 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1680 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1681 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1682 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1683 #define ASC_MC_SDTR_DONE 0x00B6
1684 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1685 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1686 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1687 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1688 #define ASC_MC_WDTR_DONE 0x0124
1689 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1690 #define ASC_MC_ICQ 0x0160
1691 #define ASC_MC_IRQ 0x0164
1692 #define ASC_MC_PPR_ABLE 0x017A
1695 * BIOS LRAM variable absolute offsets.
1697 #define BIOS_CODESEG 0x54
1698 #define BIOS_CODELEN 0x56
1699 #define BIOS_SIGNATURE 0x58
1700 #define BIOS_VERSION 0x5A
1703 * Microcode Control Flags
1705 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1706 * and handled by the microcode.
1708 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1709 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1712 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1714 #define HSHK_CFG_WIDE_XFR 0x8000
1715 #define HSHK_CFG_RATE 0x0F00
1716 #define HSHK_CFG_OFFSET 0x001F
1718 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1719 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1720 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1721 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1723 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1724 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1725 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1726 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1727 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1729 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1730 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1731 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1732 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1733 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1735 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1736 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1738 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1739 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1742 * All fields here are accessed by the board microcode and need to be
1745 typedef struct adv_carr_t {
1746 __le32 carr_va; /* Carrier Virtual Address */
1747 __le32 carr_pa; /* Carrier Physical Address */
1748 __le32 areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1750 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1752 * next_vpa [3:1] Reserved Bits
1753 * next_vpa [0] Done Flag set in Response Queue.
1759 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1761 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1763 #define ASC_RQ_DONE 0x00000001
1764 #define ASC_RQ_GOOD 0x00000002
1765 #define ASC_CQ_STOPPER 0x00000000
1767 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1770 * Each carrier is 64 bytes, and we need three additional
1771 * carrier for icq, irq, and the termination carrier.
1773 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1775 #define ADV_CARRIER_BUFSIZE \
1776 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1779 * ASC_SCSI_REQ_Q 'a_flag' definitions
1781 * The Adv Library should limit use to the lower nibble (4 bits) of
1782 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1784 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1785 #define ADV_SCSIQ_DONE 0x02 /* request done */
1786 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1788 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1789 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1790 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1793 * Adapter temporary configuration structure
1795 * This structure can be discarded after initialization. Don't add
1796 * fields here needed after initialization.
1798 * Field naming convention:
1800 * *_enable indicates the field enables or disables a feature. The
1801 * value of the field is never reset.
1803 typedef struct adv_dvc_cfg {
1804 ushort disc_enable; /* enable disconnection */
1805 uchar chip_version; /* chip version */
1806 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1807 ushort control_flag; /* Microcode Control Flag */
1808 ushort mcode_date; /* Microcode date */
1809 ushort mcode_version; /* Microcode version */
1810 ushort serial1; /* EEPROM serial number word 1 */
1811 ushort serial2; /* EEPROM serial number word 2 */
1812 ushort serial3; /* EEPROM serial number word 3 */
1816 struct adv_scsi_req_q;
1818 typedef struct asc_sg_block {
1822 uchar sg_cnt; /* Valid entries in block. */
1823 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1825 ADV_PADDR sg_addr; /* SG element address. */
1826 ADV_DCNT sg_count; /* SG element count. */
1827 } sg_list[NO_OF_SG_PER_BLOCK];
1831 * ADV_SCSI_REQ_Q - microcode request structure
1833 * All fields in this structure up to byte 60 are used by the microcode.
1834 * The microcode makes assumptions about the size and ordering of fields
1835 * in this structure. Do not change the structure definition here without
1836 * coordinating the change with the microcode.
1838 * All fields accessed by microcode must be maintained in little_endian
1841 typedef struct adv_scsi_req_q {
1842 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1844 uchar target_id; /* Device target identifier. */
1845 uchar target_lun; /* Device target logical unit number. */
1846 ADV_PADDR data_addr; /* Data buffer physical address. */
1847 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1852 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1854 uchar done_status; /* Completion status. */
1855 uchar scsi_status; /* SCSI status byte. */
1856 uchar host_status; /* Ucode host status. */
1857 uchar sg_working_ix;
1858 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1859 ADV_PADDR sg_real_addr; /* SG list physical address. */
1861 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1865 * End of microcode structure - 60 bytes. The rest of the structure
1866 * is used by the Adv Library and ignored by the microcode.
1870 uchar pad[3]; /* Pad out to a word boundary. */
1871 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1875 * The following two structures are used to process Wide Board requests.
1877 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1878 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1879 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1880 * to the Mid-Level SCSI request structure.
1882 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1883 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1884 * up to 255 scatter-gather elements may be used per request or
1887 * Both structures must be 32 byte aligned.
1889 typedef struct adv_sgblk {
1890 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1891 uchar align[32]; /* Sgblock structure padding. */
1892 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1895 typedef struct adv_req {
1896 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1897 uchar align[24]; /* Request structure padding. */
1898 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1899 dma_addr_t req_addr;
1900 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1901 } adv_req_t __aligned(32);
1904 * Adapter operation variable structure.
1906 * One structure is required per host adapter.
1908 * Field naming convention:
1910 * *_able indicates both whether a feature should be enabled or disabled
1911 * and whether a device isi capable of the feature. At initialization
1912 * this field may be set, but later if a device is found to be incapable
1913 * of the feature, the field is cleared.
1915 typedef struct adv_dvc_var {
1916 AdvPortAddr iop_base; /* I/O port address */
1917 ushort err_code; /* fatal error code */
1918 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1919 ushort wdtr_able; /* try WDTR for a device */
1920 ushort sdtr_able; /* try SDTR for a device */
1921 ushort ultra_able; /* try SDTR Ultra speed for a device */
1922 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1923 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1924 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1925 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1926 ushort tagqng_able; /* try tagged queuing with a device */
1927 ushort ppr_able; /* PPR message capable per TID bitmask. */
1928 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1929 ushort start_motor; /* start motor command allowed */
1930 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1931 uchar chip_no; /* should be assigned by caller */
1932 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1933 ushort no_scam; /* scam_tolerant of EEPROM */
1934 struct asc_board *drv_ptr; /* driver pointer to private structure */
1935 uchar chip_scsi_id; /* chip SCSI target ID */
1937 uchar bist_err_code;
1938 ADV_CARR_T *carrier;
1939 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1940 dma_addr_t carrier_addr;
1941 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1942 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1943 ushort carr_pending_cnt; /* Count of pending carriers. */
1945 * Note: The following fields will not be used after initialization. The
1946 * driver may discard the buffer after initialization is done.
1948 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1952 * Microcode idle loop commands
1954 #define IDLE_CMD_COMPLETED 0
1955 #define IDLE_CMD_STOP_CHIP 0x0001
1956 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1957 #define IDLE_CMD_SEND_INT 0x0004
1958 #define IDLE_CMD_ABORT 0x0008
1959 #define IDLE_CMD_DEVICE_RESET 0x0010
1960 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1961 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1962 #define IDLE_CMD_SCSIREQ 0x0080
1964 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1965 #define IDLE_CMD_STATUS_FAILURE 0x0002
1968 * AdvSendIdleCmd() flag definitions.
1970 #define ADV_NOWAIT 0x01
1973 * Wait loop time out values.
1975 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1976 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1977 #define SCSI_MAX_RETRY 10 /* retry count */
1979 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1980 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1981 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1982 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1984 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1986 /* Read byte from a register. */
1987 #define AdvReadByteRegister(iop_base, reg_off) \
1988 (ADV_MEM_READB((iop_base) + (reg_off)))
1990 /* Write byte to a register. */
1991 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1992 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1994 /* Read word (2 bytes) from a register. */
1995 #define AdvReadWordRegister(iop_base, reg_off) \
1996 (ADV_MEM_READW((iop_base) + (reg_off)))
1998 /* Write word (2 bytes) to a register. */
1999 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2000 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2002 /* Write dword (4 bytes) to a register. */
2003 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2004 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2006 /* Read byte from LRAM. */
2007 #define AdvReadByteLram(iop_base, addr, byte) \
2009 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2010 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2013 /* Write byte to LRAM. */
2014 #define AdvWriteByteLram(iop_base, addr, byte) \
2015 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2016 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2018 /* Read word (2 bytes) from LRAM. */
2019 #define AdvReadWordLram(iop_base, addr, word) \
2021 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2022 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2025 /* Write word (2 bytes) to LRAM. */
2026 #define AdvWriteWordLram(iop_base, addr, word) \
2027 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2028 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2030 /* Write little-endian double word (4 bytes) to LRAM */
2031 /* Because of unspecified C language ordering don't use auto-increment. */
2032 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2033 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2034 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2035 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2036 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2037 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2038 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2040 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2041 #define AdvReadWordAutoIncLram(iop_base) \
2042 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2044 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2045 #define AdvWriteWordAutoIncLram(iop_base, word) \
2046 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2049 * Define macro to check for Condor signature.
2051 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2052 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2054 #define AdvFindSignature(iop_base) \
2055 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2056 ADV_CHIP_ID_BYTE) && \
2057 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2058 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2061 * Define macro to Return the version number of the chip at 'iop_base'.
2063 * The second parameter 'bus_type' is currently unused.
2065 #define AdvGetChipVersion(iop_base, bus_type) \
2066 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2069 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
2070 * match the ASC_SCSI_REQ_Q 'srb_tag' field.
2072 * If the request has not yet been sent to the device it will simply be
2073 * aborted from RISC memory. If the request is disconnected it will be
2074 * aborted on reselection by sending an Abort Message to the target ID.
2077 * ADV_TRUE(1) - Queue was successfully aborted.
2078 * ADV_FALSE(0) - Queue was not found on the active queue list.
2080 #define AdvAbortQueue(asc_dvc, srb_tag) \
2081 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2082 (ADV_DCNT) (srb_tag))
2085 * Send a Bus Device Reset Message to the specified target ID.
2087 * All outstanding commands will be purged if sending the
2088 * Bus Device Reset Message is successful.
2091 * ADV_TRUE(1) - All requests on the target are purged.
2092 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2095 #define AdvResetDevice(asc_dvc, target_id) \
2096 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2097 (ADV_DCNT) (target_id))
2100 * SCSI Wide Type definition.
2102 #define ADV_SCSI_BIT_ID_TYPE ushort
2105 * AdvInitScsiTarget() 'cntl_flag' options.
2107 #define ADV_SCAN_LUN 0x01
2108 #define ADV_CAPINFO_NOLUN 0x02
2111 * Convert target id to target id bit mask.
2113 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2116 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2119 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2120 #define QD_NO_ERROR 0x01
2121 #define QD_ABORTED_BY_HOST 0x02
2122 #define QD_WITH_ERROR 0x04
2124 #define QHSTA_NO_ERROR 0x00
2125 #define QHSTA_M_SEL_TIMEOUT 0x11
2126 #define QHSTA_M_DATA_OVER_RUN 0x12
2127 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2128 #define QHSTA_M_QUEUE_ABORTED 0x15
2129 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2130 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2131 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2132 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2133 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2134 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2135 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2136 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2137 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2138 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2139 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2140 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2141 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2142 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2143 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2144 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2145 #define QHSTA_M_WTM_TIMEOUT 0x41
2146 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2147 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2148 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2149 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2150 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2151 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2153 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2154 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2155 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2156 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2159 * Total contiguous memory needed for driver SG blocks.
2161 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2162 * number of scatter-gather elements the driver supports in a
2166 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2167 (sizeof(ADV_SG_BLOCK) * \
2168 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2170 /* struct asc_board flags */
2171 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2173 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2175 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2177 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2179 /* Asc Library return codes */
2182 #define ASC_NOERROR 1
2184 #define ASC_ERROR (-1)
2186 /* struct scsi_cmnd function return codes */
2187 #define STATUS_BYTE(byte) (byte)
2188 #define MSG_BYTE(byte) ((byte) << 8)
2189 #define HOST_BYTE(byte) ((byte) << 16)
2190 #define DRIVER_BYTE(byte) ((byte) << 24)
2192 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2193 #ifndef ADVANSYS_STATS
2194 #define ASC_STATS_ADD(shost, counter, count)
2195 #else /* ADVANSYS_STATS */
2196 #define ASC_STATS_ADD(shost, counter, count) \
2197 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2198 #endif /* ADVANSYS_STATS */
2200 /* If the result wraps when calculating tenths, return 0. */
2201 #define ASC_TENTHS(num, den) \
2202 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2203 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2206 * Display a message to the console.
2208 #define ASC_PRINT(s) \
2210 printk("advansys: "); \
2214 #define ASC_PRINT1(s, a1) \
2216 printk("advansys: "); \
2217 printk((s), (a1)); \
2220 #define ASC_PRINT2(s, a1, a2) \
2222 printk("advansys: "); \
2223 printk((s), (a1), (a2)); \
2226 #define ASC_PRINT3(s, a1, a2, a3) \
2228 printk("advansys: "); \
2229 printk((s), (a1), (a2), (a3)); \
2232 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2234 printk("advansys: "); \
2235 printk((s), (a1), (a2), (a3), (a4)); \
2238 #ifndef ADVANSYS_DEBUG
2240 #define ASC_DBG(lvl, s...)
2241 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2242 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2243 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2244 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2245 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2246 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2247 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2248 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2249 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2251 #else /* ADVANSYS_DEBUG */
2254 * Debugging Message Levels:
2256 * 1: High-Level Tracing
2257 * 2-N: Verbose Tracing
2260 #define ASC_DBG(lvl, format, arg...) { \
2261 if (asc_dbglvl >= (lvl)) \
2262 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2263 __func__ , ## arg); \
2266 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2268 if (asc_dbglvl >= (lvl)) { \
2269 asc_prt_scsi_host(s); \
2273 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2275 if (asc_dbglvl >= (lvl)) { \
2276 asc_prt_asc_scsi_q(scsiqp); \
2280 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2282 if (asc_dbglvl >= (lvl)) { \
2283 asc_prt_asc_qdone_info(qdone); \
2287 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2289 if (asc_dbglvl >= (lvl)) { \
2290 asc_prt_adv_scsi_req_q(scsiqp); \
2294 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2296 if (asc_dbglvl >= (lvl)) { \
2297 asc_prt_hex((name), (start), (length)); \
2301 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2302 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2304 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2305 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2307 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2308 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2309 #endif /* ADVANSYS_DEBUG */
2311 #ifdef ADVANSYS_STATS
2313 /* Per board statistics structure */
2315 /* Driver Entrypoint Statistics */
2316 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2317 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2318 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2319 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2320 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2321 ADV_DCNT done; /* # calls to request's scsi_done function */
2322 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2323 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2324 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2325 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2326 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2327 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2328 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2329 ADV_DCNT exe_unknown; /* # unknown returns. */
2330 /* Data Transfer Statistics */
2331 ADV_DCNT xfer_cnt; /* # I/O requests received */
2332 ADV_DCNT xfer_elem; /* # scatter-gather elements */
2333 ADV_DCNT xfer_sect; /* # 512-byte blocks */
2335 #endif /* ADVANSYS_STATS */
2338 * Structure allocated for each board.
2340 * This structure is allocated by scsi_host_alloc() at the end
2341 * of the 'Scsi_Host' structure starting at the 'hostdata'
2342 * field. It is guaranteed to be allocated from DMA-able memory.
2346 struct Scsi_Host *shost;
2347 uint flags; /* Board flags */
2350 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2351 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2354 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2355 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2357 ushort asc_n_io_port; /* Number I/O ports. */
2358 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2359 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2360 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2361 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2363 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2364 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2365 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2366 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2368 /* /proc/scsi/advansys/[0...] */
2369 #ifdef ADVANSYS_STATS
2370 struct asc_stats asc_stats; /* Board statistics */
2371 #endif /* ADVANSYS_STATS */
2373 * The following fields are used only for Narrow Boards.
2375 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2377 * The following fields are used only for Wide Boards.
2379 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2380 ushort ioport; /* I/O Port address. */
2381 adv_req_t *adv_reqp; /* Request structures. */
2382 dma_addr_t adv_reqp_addr;
2383 size_t adv_reqp_size;
2384 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2385 ushort bios_signature; /* BIOS Signature. */
2386 ushort bios_version; /* BIOS Version. */
2387 ushort bios_codeseg; /* BIOS Code Segment. */
2388 ushort bios_codelen; /* BIOS Code Segment Length. */
2391 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2392 dvc_var.asc_dvc_var)
2393 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2394 dvc_var.adv_dvc_var)
2395 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2397 #ifdef ADVANSYS_DEBUG
2398 static int asc_dbglvl = 3;
2401 * asc_prt_asc_dvc_var()
2403 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2405 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2407 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2408 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2410 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2411 (unsigned)h->init_sdtr);
2413 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2414 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2415 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2416 (unsigned)h->chip_no);
2418 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2419 "%u,\n", (unsigned)h->queue_full_or_busy,
2420 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2422 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2423 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2424 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2425 (unsigned)h->in_critical_cnt);
2427 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2428 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2429 (unsigned)h->init_state, (unsigned)h->no_scam,
2430 (unsigned)h->pci_fix_asyn_xfer);
2432 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2436 * asc_prt_asc_dvc_cfg()
2438 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2440 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2442 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2443 h->can_tagged_qng, h->cmd_qng_enabled);
2444 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2445 h->disc_enable, h->sdtr_enable);
2447 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2448 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2449 h->isa_dma_channel, h->chip_version);
2451 printk(" mcode_date 0x%x, mcode_version %d\n",
2452 h->mcode_date, h->mcode_version);
2456 * asc_prt_adv_dvc_var()
2458 * Display an ADV_DVC_VAR structure.
2460 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2462 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2464 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2465 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2467 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2468 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2470 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2471 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2473 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2474 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2477 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2479 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2480 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2482 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2483 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2487 * asc_prt_adv_dvc_cfg()
2489 * Display an ADV_DVC_CFG structure.
2491 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2493 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2495 printk(" disc_enable 0x%x, termination 0x%x\n",
2496 h->disc_enable, h->termination);
2498 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2499 h->chip_version, h->mcode_date);
2501 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2502 h->mcode_version, h->control_flag);
2506 * asc_prt_scsi_host()
2508 static void asc_prt_scsi_host(struct Scsi_Host *s)
2510 struct asc_board *boardp = shost_priv(s);
2512 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2513 printk(" host_busy %u, host_no %d,\n",
2514 atomic_read(&s->host_busy), s->host_no);
2516 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2517 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2519 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2520 s->dma_channel, s->this_id, s->can_queue);
2522 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2523 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2525 if (ASC_NARROW_BOARD(boardp)) {
2526 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2527 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2529 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2530 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2537 * Print hexadecimal output in 4 byte groupings 32 bytes
2538 * or 8 double-words per line.
2540 static void asc_prt_hex(char *f, uchar *s, int l)
2547 printk("%s: (%d bytes)\n", f, l);
2549 for (i = 0; i < l; i += 32) {
2551 /* Display a maximum of 8 double-words per line. */
2552 if ((k = (l - i) / 4) >= 8) {
2559 for (j = 0; j < k; j++) {
2560 printk(" %2.2X%2.2X%2.2X%2.2X",
2561 (unsigned)s[i + (j * 4)],
2562 (unsigned)s[i + (j * 4) + 1],
2563 (unsigned)s[i + (j * 4) + 2],
2564 (unsigned)s[i + (j * 4) + 3]);
2572 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2575 printk(" %2.2X%2.2X",
2576 (unsigned)s[i + (j * 4)],
2577 (unsigned)s[i + (j * 4) + 1]);
2580 printk(" %2.2X%2.2X%2.2X",
2581 (unsigned)s[i + (j * 4) + 1],
2582 (unsigned)s[i + (j * 4) + 2],
2583 (unsigned)s[i + (j * 4) + 3]);
2592 * asc_prt_asc_scsi_q()
2594 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2599 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2602 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2603 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2607 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2608 (ulong)le32_to_cpu(q->q1.data_addr),
2609 (ulong)le32_to_cpu(q->q1.data_cnt),
2610 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2612 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2613 (ulong)q->cdbptr, q->q2.cdb_len,
2614 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2618 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2619 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2621 for (i = 0; i < sgp->entry_cnt; i++) {
2622 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2623 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2624 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2631 * asc_prt_asc_qdone_info()
2633 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2635 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2636 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2637 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2640 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2641 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2645 * asc_prt_adv_sgblock()
2647 * Display an ADV_SG_BLOCK structure.
2649 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2653 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2654 (ulong)b, sgblockno);
2655 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2656 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2657 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2659 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2660 for (i = 0; i < b->sg_cnt; i++) {
2661 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2662 i, (ulong)b->sg_list[i].sg_addr,
2663 (ulong)b->sg_list[i].sg_count);
2668 * asc_prt_adv_scsi_req_q()
2670 * Display an ADV_SCSI_REQ_Q structure.
2672 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2675 struct asc_sg_block *sg_ptr;
2677 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2679 printk(" target_id %u, target_lun %u, srb_tag 0x%x, a_flag 0x%x\n",
2680 q->target_id, q->target_lun, q->srb_tag, q->a_flag);
2682 printk(" cntl 0x%x, data_addr 0x%lx\n",
2683 q->cntl, (ulong)le32_to_cpu(q->data_addr));
2685 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2686 (ulong)le32_to_cpu(q->data_cnt),
2687 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2690 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2691 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2693 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2694 q->sg_working_ix, q->target_cmd);
2696 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2697 (ulong)le32_to_cpu(q->scsiq_rptr),
2698 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2700 /* Display the request's ADV_SG_BLOCK structures. */
2701 if (q->sg_list_ptr != NULL) {
2705 * 'sg_ptr' is a physical address. Convert it to a virtual
2706 * address by indexing 'sg_blk_cnt' into the virtual address
2707 * array 'sg_list_ptr'.
2709 * XXX - Assumes all SG physical blocks are virtually contiguous.
2712 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2713 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2714 if (sg_ptr->sg_ptr == 0) {
2721 #endif /* ADVANSYS_DEBUG */
2726 * Return suitable for printing on the console with the argument
2727 * adapter's configuration information.
2729 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2730 * otherwise the static 'info' array will be overrun.
2732 static const char *advansys_info(struct Scsi_Host *shost)
2734 static char info[ASC_INFO_SIZE];
2735 struct asc_board *boardp = shost_priv(shost);
2736 ASC_DVC_VAR *asc_dvc_varp;
2737 ADV_DVC_VAR *adv_dvc_varp;
2739 char *widename = NULL;
2741 if (ASC_NARROW_BOARD(boardp)) {
2742 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2743 ASC_DBG(1, "begin\n");
2744 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2745 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2747 busname = "ISA PnP";
2752 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2753 ASC_VERSION, busname,
2754 (ulong)shost->io_port,
2755 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2756 boardp->irq, shost->dma_channel);
2758 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2760 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2762 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2763 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2764 == ASC_IS_PCI_ULTRA) {
2765 busname = "PCI Ultra";
2771 shost_printk(KERN_ERR, shost, "unknown bus "
2772 "type %d\n", asc_dvc_varp->bus_type);
2775 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2776 ASC_VERSION, busname, (ulong)shost->io_port,
2777 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2782 * Wide Adapter Information
2784 * Memory-mapped I/O is used instead of I/O space to access
2785 * the adapter, but display the I/O Port range. The Memory
2786 * I/O address is displayed through the driver /proc file.
2788 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2789 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2790 widename = "Ultra-Wide";
2791 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2792 widename = "Ultra2-Wide";
2794 widename = "Ultra3-Wide";
2797 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2798 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2799 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2801 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2802 ASC_DBG(1, "end\n");
2806 #ifdef CONFIG_PROC_FS
2809 * asc_prt_board_devices()
2811 * Print driver information for devices attached to the board.
2813 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2815 struct asc_board *boardp = shost_priv(shost);
2820 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2823 if (ASC_NARROW_BOARD(boardp)) {
2824 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2826 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2829 seq_puts(m, "Target IDs Detected:");
2830 for (i = 0; i <= ADV_MAX_TID; i++) {
2831 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2832 seq_printf(m, " %X,", i);
2834 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2838 * Display Wide Board BIOS Information.
2840 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2842 struct asc_board *boardp = shost_priv(shost);
2843 ushort major, minor, letter;
2845 seq_puts(m, "\nROM BIOS Version: ");
2848 * If the BIOS saved a valid signature, then fill in
2849 * the BIOS code segment base address.
2851 if (boardp->bios_signature != 0x55AA) {
2852 seq_puts(m, "Disabled or Pre-3.1\n"
2853 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2854 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2856 major = (boardp->bios_version >> 12) & 0xF;
2857 minor = (boardp->bios_version >> 8) & 0xF;
2858 letter = (boardp->bios_version & 0xFF);
2860 seq_printf(m, "%d.%d%c\n",
2862 letter >= 26 ? '?' : letter + 'A');
2864 * Current available ROM BIOS release is 3.1I for UW
2865 * and 3.2I for U2W. This code doesn't differentiate
2866 * UW and U2W boards.
2868 if (major < 3 || (major <= 3 && minor < 1) ||
2869 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2870 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2871 "ftp://ftp.connectcom.net/pub\n");
2877 * Add serial number to information bar if signature AAh
2878 * is found in at bit 15-9 (7 bits) of word 1.
2880 * Serial Number consists fo 12 alpha-numeric digits.
2882 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2883 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2884 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2885 * 5 - Product revision (A-J) Word0: " "
2887 * Signature Word1: 15-9 (7 bits)
2888 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2889 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2891 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2893 * Note 1: Only production cards will have a serial number.
2895 * Note 2: Signature is most significant 7 bits (0xFE).
2897 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2899 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2903 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2907 * First word - 6 digits.
2911 /* Product type - 1st digit. */
2912 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2913 /* Product type is P=Prototype */
2918 /* Manufacturing location - 2nd digit. */
2919 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2921 /* Product ID - 3rd, 4th digits. */
2923 *cp++ = '0' + (num / 100);
2925 *cp++ = '0' + (num / 10);
2927 /* Product revision - 5th digit. */
2928 *cp++ = 'A' + (num % 10);
2938 * If bit 15 of third word is set, then the
2939 * last digit of the year is greater than 7.
2941 if (serialnum[2] & 0x8000) {
2942 *cp++ = '8' + ((w & 0x1C0) >> 6);
2944 *cp++ = '0' + ((w & 0x1C0) >> 6);
2947 /* Week of year - 7th, 8th digits. */
2949 *cp++ = '0' + num / 10;
2956 w = serialnum[2] & 0x7FFF;
2958 /* Serial number - 9th digit. */
2959 *cp++ = 'A' + (w / 1000);
2961 /* 10th, 11th, 12th digits. */
2963 *cp++ = '0' + num / 100;
2965 *cp++ = '0' + num / 10;
2969 *cp = '\0'; /* Null Terminate the string. */
2975 * asc_prt_asc_board_eeprom()
2977 * Print board EEPROM configuration.
2979 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2981 struct asc_board *boardp = shost_priv(shost);
2982 ASC_DVC_VAR *asc_dvc_varp;
2986 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2987 #endif /* CONFIG_ISA */
2988 uchar serialstr[13];
2990 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2991 ep = &boardp->eep_config.asc_eep;
2994 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2997 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2999 seq_printf(m, " Serial Number: %s\n", serialstr);
3000 else if (ep->adapter_info[5] == 0xBB)
3002 " Default Settings Used for EEPROM-less Adapter.\n");
3004 seq_puts(m, " Serial Number Signature Not Present.\n");
3007 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3008 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3012 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3014 seq_puts(m, " Target ID: ");
3015 for (i = 0; i <= ASC_MAX_TID; i++)
3016 seq_printf(m, " %d", i);
3018 seq_puts(m, "\n Disconnects: ");
3019 for (i = 0; i <= ASC_MAX_TID; i++)
3020 seq_printf(m, " %c",
3021 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3023 seq_puts(m, "\n Command Queuing: ");
3024 for (i = 0; i <= ASC_MAX_TID; i++)
3025 seq_printf(m, " %c",
3026 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3028 seq_puts(m, "\n Start Motor: ");
3029 for (i = 0; i <= ASC_MAX_TID; i++)
3030 seq_printf(m, " %c",
3031 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3033 seq_puts(m, "\n Synchronous Transfer:");
3034 for (i = 0; i <= ASC_MAX_TID; i++)
3035 seq_printf(m, " %c",
3036 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3040 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3042 " Host ISA DMA speed: %d MB/S\n",
3043 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3045 #endif /* CONFIG_ISA */
3049 * asc_prt_adv_board_eeprom()
3051 * Print board EEPROM configuration.
3053 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3055 struct asc_board *boardp = shost_priv(shost);
3056 ADV_DVC_VAR *adv_dvc_varp;
3059 uchar serialstr[13];
3060 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3061 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3062 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3065 ushort sdtr_speed = 0;
3067 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3068 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3069 ep_3550 = &boardp->eep_config.adv_3550_eep;
3070 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3071 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3073 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3077 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3080 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3081 wordp = &ep_3550->serial_number_word1;
3082 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3083 wordp = &ep_38C0800->serial_number_word1;
3085 wordp = &ep_38C1600->serial_number_word1;
3088 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3089 seq_printf(m, " Serial Number: %s\n", serialstr);
3091 seq_puts(m, " Serial Number Signature Not Present.\n");
3093 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3095 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3096 ep_3550->adapter_scsi_id,
3097 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3098 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3100 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3101 ep_38C0800->adapter_scsi_id,
3102 ep_38C0800->max_host_qng,
3103 ep_38C0800->max_dvc_qng);
3106 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3107 ep_38C1600->adapter_scsi_id,
3108 ep_38C1600->max_host_qng,
3109 ep_38C1600->max_dvc_qng);
3110 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3111 word = ep_3550->termination;
3112 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3113 word = ep_38C0800->termination_lvd;
3115 word = ep_38C1600->termination_lvd;
3119 termstr = "Low Off/High Off";
3122 termstr = "Low Off/High On";
3125 termstr = "Low On/High On";
3129 termstr = "Automatic";
3133 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3135 " termination: %u (%s), bios_ctrl: 0x%x\n",
3136 ep_3550->termination, termstr,
3137 ep_3550->bios_ctrl);
3138 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3140 " termination: %u (%s), bios_ctrl: 0x%x\n",
3141 ep_38C0800->termination_lvd, termstr,
3142 ep_38C0800->bios_ctrl);
3145 " termination: %u (%s), bios_ctrl: 0x%x\n",
3146 ep_38C1600->termination_lvd, termstr,
3147 ep_38C1600->bios_ctrl);
3149 seq_puts(m, " Target ID: ");
3150 for (i = 0; i <= ADV_MAX_TID; i++)
3151 seq_printf(m, " %X", i);
3154 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3155 word = ep_3550->disc_enable;
3156 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3157 word = ep_38C0800->disc_enable;
3159 word = ep_38C1600->disc_enable;
3161 seq_puts(m, " Disconnects: ");
3162 for (i = 0; i <= ADV_MAX_TID; i++)
3163 seq_printf(m, " %c",
3164 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3167 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3168 word = ep_3550->tagqng_able;
3169 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3170 word = ep_38C0800->tagqng_able;
3172 word = ep_38C1600->tagqng_able;
3174 seq_puts(m, " Command Queuing: ");
3175 for (i = 0; i <= ADV_MAX_TID; i++)
3176 seq_printf(m, " %c",
3177 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3180 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3181 word = ep_3550->start_motor;
3182 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3183 word = ep_38C0800->start_motor;
3185 word = ep_38C1600->start_motor;
3187 seq_puts(m, " Start Motor: ");
3188 for (i = 0; i <= ADV_MAX_TID; i++)
3189 seq_printf(m, " %c",
3190 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3193 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3194 seq_puts(m, " Synchronous Transfer:");
3195 for (i = 0; i <= ADV_MAX_TID; i++)
3196 seq_printf(m, " %c",
3197 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3202 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3203 seq_puts(m, " Ultra Transfer: ");
3204 for (i = 0; i <= ADV_MAX_TID; i++)
3205 seq_printf(m, " %c",
3206 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3211 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3212 word = ep_3550->wdtr_able;
3213 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3214 word = ep_38C0800->wdtr_able;
3216 word = ep_38C1600->wdtr_able;
3218 seq_puts(m, " Wide Transfer: ");
3219 for (i = 0; i <= ADV_MAX_TID; i++)
3220 seq_printf(m, " %c",
3221 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3224 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3225 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3226 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
3227 for (i = 0; i <= ADV_MAX_TID; i++) {
3231 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3232 } else if (i == 4) {
3233 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3234 } else if (i == 8) {
3235 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3236 } else if (i == 12) {
3237 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3239 switch (sdtr_speed & ADV_MAX_TID) {
3262 seq_printf(m, "%X:%s ", i, speed_str);
3272 * asc_prt_driver_conf()
3274 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3276 struct asc_board *boardp = shost_priv(shost);
3280 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3284 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3285 atomic_read(&shost->host_busy), shost->max_id,
3286 shost->max_lun, shost->max_channel);
3289 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3290 shost->unique_id, shost->can_queue, shost->this_id,
3291 shost->sg_tablesize, shost->cmd_per_lun);
3294 " unchecked_isa_dma %d, use_clustering %d\n",
3295 shost->unchecked_isa_dma, shost->use_clustering);
3298 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3299 boardp->flags, shost->last_reset, jiffies,
3300 boardp->asc_n_io_port);
3302 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3304 if (ASC_NARROW_BOARD(boardp)) {
3305 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3307 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3312 * asc_prt_asc_board_info()
3314 * Print dynamic board configuration information.
3316 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3318 struct asc_board *boardp = shost_priv(shost);
3323 int renegotiate = 0;
3325 v = &boardp->dvc_var.asc_dvc_var;
3326 c = &boardp->dvc_cfg.asc_dvc_cfg;
3327 chip_scsi_id = c->chip_scsi_id;
3330 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3333 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3334 "mcode_version 0x%x, err_code %u\n",
3335 c->chip_version, c->mcode_date, c->mcode_version,
3338 /* Current number of commands waiting for the host. */
3340 " Total Command Pending: %d\n", v->cur_total_qng);
3342 seq_puts(m, " Command Queuing:");
3343 for (i = 0; i <= ASC_MAX_TID; i++) {
3344 if ((chip_scsi_id == i) ||
3345 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3348 seq_printf(m, " %X:%c",
3350 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3353 /* Current number of commands waiting for a device. */
3354 seq_puts(m, "\n Command Queue Pending:");
3355 for (i = 0; i <= ASC_MAX_TID; i++) {
3356 if ((chip_scsi_id == i) ||
3357 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3360 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3363 /* Current limit on number of commands that can be sent to a device. */
3364 seq_puts(m, "\n Command Queue Limit:");
3365 for (i = 0; i <= ASC_MAX_TID; i++) {
3366 if ((chip_scsi_id == i) ||
3367 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3370 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3373 /* Indicate whether the device has returned queue full status. */
3374 seq_puts(m, "\n Command Queue Full:");
3375 for (i = 0; i <= ASC_MAX_TID; i++) {
3376 if ((chip_scsi_id == i) ||
3377 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3380 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3381 seq_printf(m, " %X:Y-%d",
3382 i, boardp->queue_full_cnt[i]);
3384 seq_printf(m, " %X:N", i);
3387 seq_puts(m, "\n Synchronous Transfer:");
3388 for (i = 0; i <= ASC_MAX_TID; i++) {
3389 if ((chip_scsi_id == i) ||
3390 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3393 seq_printf(m, " %X:%c",
3395 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3399 for (i = 0; i <= ASC_MAX_TID; i++) {
3400 uchar syn_period_ix;
3402 if ((chip_scsi_id == i) ||
3403 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3404 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3408 seq_printf(m, " %X:", i);
3410 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3411 seq_puts(m, " Asynchronous");
3414 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3418 " Transfer Period Factor: %d (%d.%d Mhz),",
3419 v->sdtr_period_tbl[syn_period_ix],
3420 250 / v->sdtr_period_tbl[syn_period_ix],
3422 v->sdtr_period_tbl[syn_period_ix]));
3424 seq_printf(m, " REQ/ACK Offset: %d",
3425 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3428 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3437 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3442 * asc_prt_adv_board_info()
3444 * Print dynamic board configuration information.
3446 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3448 struct asc_board *boardp = shost_priv(shost);
3452 AdvPortAddr iop_base;
3453 ushort chip_scsi_id;
3457 ushort sdtr_able, wdtr_able;
3458 ushort wdtr_done, sdtr_done;
3460 int renegotiate = 0;
3462 v = &boardp->dvc_var.adv_dvc_var;
3463 c = &boardp->dvc_cfg.adv_dvc_cfg;
3464 iop_base = v->iop_base;
3465 chip_scsi_id = v->chip_scsi_id;
3468 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3472 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3473 (unsigned long)v->iop_base,
3474 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3477 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3478 "mcode_version 0x%x\n", c->chip_version,
3479 c->mcode_date, c->mcode_version);
3481 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3482 seq_puts(m, " Queuing Enabled:");
3483 for (i = 0; i <= ADV_MAX_TID; i++) {
3484 if ((chip_scsi_id == i) ||
3485 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3489 seq_printf(m, " %X:%c",
3491 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3494 seq_puts(m, "\n Queue Limit:");
3495 for (i = 0; i <= ADV_MAX_TID; i++) {
3496 if ((chip_scsi_id == i) ||
3497 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3501 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3504 seq_printf(m, " %X:%d", i, lrambyte);
3507 seq_puts(m, "\n Command Pending:");
3508 for (i = 0; i <= ADV_MAX_TID; i++) {
3509 if ((chip_scsi_id == i) ||
3510 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3514 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3517 seq_printf(m, " %X:%d", i, lrambyte);
3521 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3522 seq_puts(m, " Wide Enabled:");
3523 for (i = 0; i <= ADV_MAX_TID; i++) {
3524 if ((chip_scsi_id == i) ||
3525 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3529 seq_printf(m, " %X:%c",
3531 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3535 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3536 seq_puts(m, " Transfer Bit Width:");
3537 for (i = 0; i <= ADV_MAX_TID; i++) {
3538 if ((chip_scsi_id == i) ||
3539 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3543 AdvReadWordLram(iop_base,
3544 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3547 seq_printf(m, " %X:%d",
3548 i, (lramword & 0x8000) ? 16 : 8);
3550 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3551 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3558 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3559 seq_puts(m, " Synchronous Enabled:");
3560 for (i = 0; i <= ADV_MAX_TID; i++) {
3561 if ((chip_scsi_id == i) ||
3562 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3566 seq_printf(m, " %X:%c",
3568 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3572 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3573 for (i = 0; i <= ADV_MAX_TID; i++) {
3575 AdvReadWordLram(iop_base,
3576 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3578 lramword &= ~0x8000;
3580 if ((chip_scsi_id == i) ||
3581 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3582 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3586 seq_printf(m, " %X:", i);
3588 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3589 seq_puts(m, " Asynchronous");
3591 seq_puts(m, " Transfer Period Factor: ");
3593 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3594 seq_puts(m, "9 (80.0 Mhz),");
3595 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3596 seq_puts(m, "10 (40.0 Mhz),");
3597 } else { /* 20 Mhz or below. */
3599 period = (((lramword >> 8) * 25) + 50) / 4;
3601 if (period == 0) { /* Should never happen. */
3602 seq_printf(m, "%d (? Mhz), ", period);
3606 period, 250 / period,
3607 ASC_TENTHS(250, period));
3611 seq_printf(m, " REQ/ACK Offset: %d",
3615 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3624 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3628 #ifdef ADVANSYS_STATS
3630 * asc_prt_board_stats()
3632 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3634 struct asc_board *boardp = shost_priv(shost);
3635 struct asc_stats *s = &boardp->asc_stats;
3638 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3642 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3643 s->queuecommand, s->reset, s->biosparam,
3647 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3648 s->callback, s->done, s->build_error,
3649 s->adv_build_noreq, s->adv_build_nosg);
3652 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3653 s->exe_noerror, s->exe_busy, s->exe_error,
3657 * Display data transfer statistics.
3659 if (s->xfer_cnt > 0) {
3660 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3661 s->xfer_cnt, s->xfer_elem);
3663 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3664 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3666 /* Scatter gather transfer statistics */
3667 seq_printf(m, " avg_num_elem %u.%01u, ",
3668 s->xfer_elem / s->xfer_cnt,
3669 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3671 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3672 (s->xfer_sect / 2) / s->xfer_elem,
3673 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3675 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3676 (s->xfer_sect / 2) / s->xfer_cnt,
3677 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3680 #endif /* ADVANSYS_STATS */
3683 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3685 * m: seq_file to print into
3688 * Return the number of bytes read from or written to a
3689 * /proc/scsi/advansys/[0...] file.
3692 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3694 struct asc_board *boardp = shost_priv(shost);
3696 ASC_DBG(1, "begin\n");
3699 * User read of /proc/scsi/advansys/[0...] file.
3703 * Get board configuration information.
3705 * advansys_info() returns the board string from its own static buffer.
3707 /* Copy board information. */
3708 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3710 * Display Wide Board BIOS Information.
3712 if (!ASC_NARROW_BOARD(boardp))
3713 asc_prt_adv_bios(m, shost);
3716 * Display driver information for each device attached to the board.
3718 asc_prt_board_devices(m, shost);
3721 * Display EEPROM configuration for the board.
3723 if (ASC_NARROW_BOARD(boardp))
3724 asc_prt_asc_board_eeprom(m, shost);
3726 asc_prt_adv_board_eeprom(m, shost);
3729 * Display driver configuration and information for the board.
3731 asc_prt_driver_conf(m, shost);
3733 #ifdef ADVANSYS_STATS
3735 * Display driver statistics for the board.
3737 asc_prt_board_stats(m, shost);
3738 #endif /* ADVANSYS_STATS */
3741 * Display Asc Library dynamic configuration information
3744 if (ASC_NARROW_BOARD(boardp))
3745 asc_prt_asc_board_info(m, shost);
3747 asc_prt_adv_board_info(m, shost);
3750 #endif /* CONFIG_PROC_FS */
3752 static void asc_scsi_done(struct scsi_cmnd *scp)
3754 scsi_dma_unmap(scp);
3755 ASC_STATS(scp->device->host, done);
3756 scp->scsi_done(scp);
3759 static void AscSetBank(PortAddr iop_base, uchar bank)
3763 val = AscGetChipControl(iop_base) &
3765 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3769 } else if (bank == 2) {
3770 val |= CC_DIAG | CC_BANK_ONE;
3772 val &= ~CC_BANK_ONE;
3774 AscSetChipControl(iop_base, val);
3777 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3779 AscSetBank(iop_base, 1);
3780 AscWriteChipIH(iop_base, ins_code);
3781 AscSetBank(iop_base, 0);
3784 static int AscStartChip(PortAddr iop_base)
3786 AscSetChipControl(iop_base, 0);
3787 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3793 static int AscStopChip(PortAddr iop_base)
3798 AscGetChipControl(iop_base) &
3799 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3800 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3801 AscSetChipIH(iop_base, INS_HALT);
3802 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3803 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3809 static int AscIsChipHalted(PortAddr iop_base)
3811 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3812 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3819 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3824 iop_base = asc_dvc->iop_base;
3825 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3829 AscStopChip(iop_base);
3830 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3832 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3833 AscSetChipIH(iop_base, INS_HALT);
3834 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3835 AscSetChipControl(iop_base, CC_HALT);
3837 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3838 AscSetChipStatus(iop_base, 0);
3839 return (AscIsChipHalted(iop_base));
3842 static int AscFindSignature(PortAddr iop_base)
3846 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3847 iop_base, AscGetChipSignatureByte(iop_base));
3848 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3849 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3850 iop_base, AscGetChipSignatureWord(iop_base));
3851 sig_word = AscGetChipSignatureWord(iop_base);
3852 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3853 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3860 static void AscEnableInterrupt(PortAddr iop_base)
3864 cfg = AscGetChipCfgLsw(iop_base);
3865 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3868 static void AscDisableInterrupt(PortAddr iop_base)
3872 cfg = AscGetChipCfgLsw(iop_base);
3873 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3876 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3878 unsigned char byte_data;
3879 unsigned short word_data;
3881 if (isodd_word(addr)) {
3882 AscSetChipLramAddr(iop_base, addr - 1);
3883 word_data = AscGetChipLramData(iop_base);
3884 byte_data = (word_data >> 8) & 0xFF;
3886 AscSetChipLramAddr(iop_base, addr);
3887 word_data = AscGetChipLramData(iop_base);
3888 byte_data = word_data & 0xFF;
3893 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3897 AscSetChipLramAddr(iop_base, addr);
3898 word_data = AscGetChipLramData(iop_base);
3902 #if CC_VERY_LONG_SG_LIST
3903 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
3905 ushort val_low, val_high;
3906 ASC_DCNT dword_data;
3908 AscSetChipLramAddr(iop_base, addr);
3909 val_low = AscGetChipLramData(iop_base);
3910 val_high = AscGetChipLramData(iop_base);
3911 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
3912 return (dword_data);
3914 #endif /* CC_VERY_LONG_SG_LIST */
3917 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3921 AscSetChipLramAddr(iop_base, s_addr);
3922 for (i = 0; i < words; i++) {
3923 AscSetChipLramData(iop_base, set_wval);
3927 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3929 AscSetChipLramAddr(iop_base, addr);
3930 AscSetChipLramData(iop_base, word_val);
3933 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3937 if (isodd_word(addr)) {
3939 word_data = AscReadLramWord(iop_base, addr);
3940 word_data &= 0x00FF;
3941 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3943 word_data = AscReadLramWord(iop_base, addr);
3944 word_data &= 0xFF00;
3945 word_data |= ((ushort)byte_val & 0x00FF);
3947 AscWriteLramWord(iop_base, addr, word_data);
3951 * Copy 2 bytes to LRAM.
3953 * The source data is assumed to be in little-endian order in memory
3954 * and is maintained in little-endian order when written to LRAM.
3957 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3958 const uchar *s_buffer, int words)
3962 AscSetChipLramAddr(iop_base, s_addr);
3963 for (i = 0; i < 2 * words; i += 2) {
3965 * On a little-endian system the second argument below
3966 * produces a little-endian ushort which is written to
3967 * LRAM in little-endian order. On a big-endian system
3968 * the second argument produces a big-endian ushort which
3969 * is "transparently" byte-swapped by outpw() and written
3970 * in little-endian order to LRAM.
3972 outpw(iop_base + IOP_RAM_DATA,
3973 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3978 * Copy 4 bytes to LRAM.
3980 * The source data is assumed to be in little-endian order in memory
3981 * and is maintained in little-endian order when written to LRAM.
3984 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3985 ushort s_addr, uchar *s_buffer, int dwords)
3989 AscSetChipLramAddr(iop_base, s_addr);
3990 for (i = 0; i < 4 * dwords; i += 4) {
3991 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3992 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3997 * Copy 2 bytes from LRAM.
3999 * The source data is assumed to be in little-endian order in LRAM
4000 * and is maintained in little-endian order when written to memory.
4003 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4004 ushort s_addr, uchar *d_buffer, int words)
4009 AscSetChipLramAddr(iop_base, s_addr);
4010 for (i = 0; i < 2 * words; i += 2) {
4011 word = inpw(iop_base + IOP_RAM_DATA);
4012 d_buffer[i] = word & 0xff;
4013 d_buffer[i + 1] = (word >> 8) & 0xff;
4017 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4023 for (i = 0; i < words; i++, s_addr += 2) {
4024 sum += AscReadLramWord(iop_base, s_addr);
4029 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4036 iop_base = asc_dvc->iop_base;
4038 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4039 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4041 i = ASC_MIN_ACTIVE_QNO;
4042 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4043 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4045 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4046 (uchar)(asc_dvc->max_total_qng));
4047 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4050 s_addr += ASC_QBLK_SIZE;
4051 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4052 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4054 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4056 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4059 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4060 (uchar)ASC_QLINK_END);
4061 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4062 (uchar)(asc_dvc->max_total_qng - 1));
4063 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4064 (uchar)asc_dvc->max_total_qng);
4066 s_addr += ASC_QBLK_SIZE;
4067 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4068 i++, s_addr += ASC_QBLK_SIZE) {
4069 AscWriteLramByte(iop_base,
4070 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4071 AscWriteLramByte(iop_base,
4072 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4073 AscWriteLramByte(iop_base,
4074 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4080 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4081 const uchar *mcode_buf, ushort mcode_size)
4084 ushort mcode_word_size;
4085 ushort mcode_chksum;
4087 /* Write the microcode buffer starting at LRAM address 0. */
4088 mcode_word_size = (ushort)(mcode_size >> 1);
4089 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4090 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4092 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4093 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4094 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4095 (ushort)ASC_CODE_SEC_BEG,
4096 (ushort)((mcode_size -
4100 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4101 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4102 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4106 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4112 iop_base = asc_dvc->iop_base;
4113 AscPutRiscVarFreeQHead(iop_base, 1);
4114 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4115 AscPutVarFreeQHead(iop_base, 1);
4116 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4117 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4118 (uchar)((int)asc_dvc->max_total_qng + 1));
4119 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4120 (uchar)((int)asc_dvc->max_total_qng + 2));
4121 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4122 asc_dvc->max_total_qng);
4123 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4124 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4125 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4126 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4127 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4128 AscPutQDoneInProgress(iop_base, 0);
4129 lram_addr = ASC_QADR_BEG;
4130 for (i = 0; i < 32; i++, lram_addr += 2) {
4131 AscWriteLramWord(iop_base, lram_addr, 0);
4135 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4142 struct asc_board *board = asc_dvc_to_board(asc_dvc);
4144 iop_base = asc_dvc->iop_base;
4146 for (i = 0; i <= ASC_MAX_TID; i++) {
4147 AscPutMCodeInitSDTRAtID(iop_base, i,
4148 asc_dvc->cfg->sdtr_period_offset[i]);
4151 AscInitQLinkVar(asc_dvc);
4152 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4153 asc_dvc->cfg->disc_enable);
4154 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4155 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4157 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4158 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4159 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4160 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4161 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4162 warn_code = -ENOMEM;
4165 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4166 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4167 (uchar *)&phy_addr, 1);
4168 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4169 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4170 (uchar *)&phy_size, 1);
4172 asc_dvc->cfg->mcode_date =
4173 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4174 asc_dvc->cfg->mcode_version =
4175 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4177 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4178 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4179 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4181 goto err_mcode_start;
4183 if (AscStartChip(iop_base) != 1) {
4184 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4186 goto err_mcode_start;
4192 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4193 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4195 asc_dvc->overrun_dma = 0;
4199 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4201 const struct firmware *fw;
4202 const char fwname[] = "advansys/mcode.bin";
4204 unsigned long chksum;
4208 iop_base = asc_dvc->iop_base;
4210 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4211 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4212 AscResetChipAndScsiBus(asc_dvc);
4213 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4215 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4216 if (asc_dvc->err_code != 0)
4218 if (!AscFindSignature(asc_dvc->iop_base)) {
4219 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4222 AscDisableInterrupt(iop_base);
4223 warn_code |= AscInitLram(asc_dvc);
4224 if (asc_dvc->err_code != 0)
4227 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4229 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4231 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4235 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4237 release_firmware(fw);
4238 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4241 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4242 (fw->data[1] << 8) | fw->data[0];
4243 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4244 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4245 fw->size - 4) != chksum) {
4246 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4247 release_firmware(fw);
4250 release_firmware(fw);
4251 warn_code |= AscInitMicroCodeVar(asc_dvc);
4252 if (!asc_dvc->overrun_dma)
4254 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4255 AscEnableInterrupt(iop_base);
4260 * Load the Microcode
4262 * Write the microcode image to RISC memory starting at address 0.
4264 * The microcode is stored compressed in the following format:
4266 * 254 word (508 byte) table indexed by byte code followed
4267 * by the following byte codes:
4270 * 00: Emit word 0 in table.
4271 * 01: Emit word 1 in table.
4273 * FD: Emit word 253 in table.
4276 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4277 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4279 * Returns 0 or an error if the checksum doesn't match
4281 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4282 int size, int memsize, int chksum)
4284 int i, j, end, len = 0;
4287 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4289 for (i = 253 * 2; i < size; i++) {
4290 if (buf[i] == 0xff) {
4291 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4292 for (j = 0; j < buf[i + 1]; j++) {
4293 AdvWriteWordAutoIncLram(iop_base, word);
4297 } else if (buf[i] == 0xfe) {
4298 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4299 AdvWriteWordAutoIncLram(iop_base, word);
4303 unsigned int off = buf[i] * 2;
4304 unsigned short word = (buf[off + 1] << 8) | buf[off];
4305 AdvWriteWordAutoIncLram(iop_base, word);
4312 while (len < memsize) {
4313 AdvWriteWordAutoIncLram(iop_base, 0);
4317 /* Verify the microcode checksum. */
4319 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4321 for (len = 0; len < end; len += 2) {
4322 sum += AdvReadWordAutoIncLram(iop_base);
4326 return ASC_IERR_MCODE_CHKSUM;
4331 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4333 off_t carr_offset = 0, next_offset;
4334 dma_addr_t carr_paddr;
4335 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4337 for (i = 0; i < carr_num; i++) {
4338 carr_offset = i * sizeof(ADV_CARR_T);
4339 /* Get physical address of the carrier 'carrp'. */
4340 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4342 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4343 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4344 adv_dvc->carrier[i].areq_vpa = 0;
4345 next_offset = carr_offset + sizeof(ADV_CARR_T);
4348 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4351 * We cannot have a carrier with 'carr_va' of '0', as
4352 * a reference to this carrier would be interpreted as
4354 * So start at carrier 1 with the freelist.
4356 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4359 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4363 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4365 index = offset / sizeof(ADV_CARR_T);
4366 return &adv_dvc->carrier[index];
4369 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4371 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4372 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4374 if (next_vpa == 0 || next_vpa == ~0) {
4375 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4379 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4381 * insert stopper carrier to terminate list
4383 carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4389 * 'offset' is the index in the request pointer array
4391 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4393 struct asc_board *boardp = adv_dvc->drv_ptr;
4395 BUG_ON(offset > adv_dvc->max_host_qng);
4396 return &boardp->adv_reqp[offset];
4400 * Send an idle command to the chip and wait for completion.
4402 * Command completion is polled for once per microsecond.
4404 * The function can be called from anywhere including an interrupt handler.
4405 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4406 * functions to prevent reentrancy.
4409 * ADV_TRUE - command completed successfully
4410 * ADV_FALSE - command failed
4411 * ADV_ERROR - command timed out
4414 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4415 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4419 AdvPortAddr iop_base;
4421 iop_base = asc_dvc->iop_base;
4424 * Clear the idle command status which is set by the microcode
4425 * to a non-zero value to indicate when the command is completed.
4426 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4428 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4431 * Write the idle command value after the idle command parameter
4432 * has been written to avoid a race condition. If the order is not
4433 * followed, the microcode may process the idle command before the
4434 * parameters have been written to LRAM.
4436 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4437 cpu_to_le32(idle_cmd_parameter));
4438 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4441 * Tickle the RISC to tell it to process the idle command.
4443 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4444 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4446 * Clear the tickle value. In the ASC-3550 the RISC flag
4447 * command 'clr_tickle_b' does not work unless the host
4450 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4453 /* Wait for up to 100 millisecond for the idle command to timeout. */
4454 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4455 /* Poll once each microsecond for command completion. */
4456 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4457 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4465 BUG(); /* The idle command should never timeout. */
4470 * Reset SCSI Bus and purge all outstanding requests.
4473 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4474 * ADV_FALSE(0) - Microcode command failed.
4475 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4476 * may be hung which requires driver recovery.
4478 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4483 * Send the SCSI Bus Reset idle start idle command which asserts
4484 * the SCSI Bus Reset signal.
4486 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4487 if (status != ADV_TRUE) {
4492 * Delay for the specified SCSI Bus Reset hold time.
4494 * The hold time delay is done on the host because the RISC has no
4495 * microsecond accurate timer.
4497 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4500 * Send the SCSI Bus Reset end idle command which de-asserts
4501 * the SCSI Bus Reset signal and purges any pending requests.
4503 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4504 if (status != ADV_TRUE) {
4508 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4514 * Initialize the ASC-3550.
4516 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4518 * For a non-fatal error return a warning code. If there are no warnings
4519 * then 0 is returned.
4521 * Needed after initialization for error recovery.
4523 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4525 const struct firmware *fw;
4526 const char fwname[] = "advansys/3550.bin";
4527 AdvPortAddr iop_base;
4535 unsigned long chksum;
4538 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4539 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4540 uchar max_cmd[ADV_MAX_TID + 1];
4542 /* If there is already an error, don't continue. */
4543 if (asc_dvc->err_code != 0)
4547 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4549 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4550 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4555 iop_base = asc_dvc->iop_base;
4558 * Save the RISC memory BIOS region before writing the microcode.
4559 * The BIOS may already be loaded and using its RISC LRAM region
4560 * so its region must be saved and restored.
4562 * Note: This code makes the assumption, which is currently true,
4563 * that a chip reset does not clear RISC LRAM.
4565 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4566 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4571 * Save current per TID negotiated values.
4573 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4574 ushort bios_version, major, minor;
4577 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4578 major = (bios_version >> 12) & 0xF;
4579 minor = (bios_version >> 8) & 0xF;
4580 if (major < 3 || (major == 3 && minor == 1)) {
4581 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4582 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4584 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4587 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4588 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4589 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4590 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4594 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4596 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4598 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4602 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4604 release_firmware(fw);
4605 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4608 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4609 (fw->data[1] << 8) | fw->data[0];
4610 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4611 fw->size - 4, ADV_3550_MEMSIZE,
4613 release_firmware(fw);
4614 if (asc_dvc->err_code)
4618 * Restore the RISC memory BIOS region.
4620 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4621 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4626 * Calculate and write the microcode code checksum to the microcode
4627 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4629 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4630 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4632 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4633 for (word = begin_addr; word < end_addr; word += 2) {
4634 code_sum += AdvReadWordAutoIncLram(iop_base);
4636 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4639 * Read and save microcode version and date.
4641 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4642 asc_dvc->cfg->mcode_date);
4643 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4644 asc_dvc->cfg->mcode_version);
4647 * Set the chip type to indicate the ASC3550.
4649 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4652 * If the PCI Configuration Command Register "Parity Error Response
4653 * Control" Bit was clear (0), then set the microcode variable
4654 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4655 * to ignore DMA parity errors.
4657 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4658 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4659 word |= CONTROL_FLAG_IGNORE_PERR;
4660 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4664 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4665 * threshold of 128 bytes. This register is only accessible to the host.
4667 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4668 START_CTL_EMFU | READ_CMD_MRM);
4671 * Microcode operating variables for WDTR, SDTR, and command tag
4672 * queuing will be set in slave_configure() based on what a
4673 * device reports it is capable of in Inquiry byte 7.
4675 * If SCSI Bus Resets have been disabled, then directly set
4676 * SDTR and WDTR from the EEPROM configuration. This will allow
4677 * the BIOS and warm boot to work without a SCSI bus hang on
4678 * the Inquiry caused by host and target mismatched DTR values.
4679 * Without the SCSI Bus Reset, before an Inquiry a device can't
4680 * be assumed to be in Asynchronous, Narrow mode.
4682 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4683 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4684 asc_dvc->wdtr_able);
4685 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4686 asc_dvc->sdtr_able);
4690 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4691 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4692 * bitmask. These values determine the maximum SDTR speed negotiated
4695 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4696 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4697 * without determining here whether the device supports SDTR.
4699 * 4-bit speed SDTR speed name
4700 * =========== ===============
4701 * 0000b (0x0) SDTR disabled
4703 * 0010b (0x2) 10 Mhz
4704 * 0011b (0x3) 20 Mhz (Ultra)
4705 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4706 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4707 * 0110b (0x6) Undefined
4709 * 1111b (0xF) Undefined
4712 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4713 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4714 /* Set Ultra speed for TID 'tid'. */
4715 word |= (0x3 << (4 * (tid % 4)));
4717 /* Set Fast speed for TID 'tid'. */
4718 word |= (0x2 << (4 * (tid % 4)));
4720 if (tid == 3) { /* Check if done with sdtr_speed1. */
4721 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4723 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4724 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4726 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4727 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4729 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4730 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4736 * Set microcode operating variable for the disconnect per TID bitmask.
4738 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4739 asc_dvc->cfg->disc_enable);
4742 * Set SCSI_CFG0 Microcode Default Value.
4744 * The microcode will set the SCSI_CFG0 register using this value
4745 * after it is started below.
4747 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4748 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4749 asc_dvc->chip_scsi_id);
4752 * Determine SCSI_CFG1 Microcode Default Value.
4754 * The microcode will set the SCSI_CFG1 register using this value
4755 * after it is started below.
4758 /* Read current SCSI_CFG1 Register value. */
4759 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4762 * If all three connectors are in use, return an error.
4764 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4765 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4766 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4771 * If the internal narrow cable is reversed all of the SCSI_CTRL
4772 * register signals will be set. Check for and return an error if
4773 * this condition is found.
4775 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4776 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4781 * If this is a differential board and a single-ended device
4782 * is attached to one of the connectors, return an error.
4784 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4785 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4790 * If automatic termination control is enabled, then set the
4791 * termination value based on a table listed in a_condor.h.
4793 * If manual termination was specified with an EEPROM setting
4794 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4795 * is ready to be 'ored' into SCSI_CFG1.
4797 if (asc_dvc->cfg->termination == 0) {
4799 * The software always controls termination by setting TERM_CTL_SEL.
4800 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4802 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4804 switch (scsi_cfg1 & CABLE_DETECT) {
4805 /* TERM_CTL_H: on, TERM_CTL_L: on */
4812 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4815 /* TERM_CTL_H: on, TERM_CTL_L: off */
4821 asc_dvc->cfg->termination |= TERM_CTL_H;
4824 /* TERM_CTL_H: off, TERM_CTL_L: off */
4832 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4834 scsi_cfg1 &= ~TERM_CTL;
4837 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4838 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4839 * referenced, because the hardware internally inverts
4840 * the Termination High and Low bits if TERM_POL is set.
4842 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4845 * Set SCSI_CFG1 Microcode Default Value
4847 * Set filter value and possibly modified termination control
4848 * bits in the Microcode SCSI_CFG1 Register Value.
4850 * The microcode will set the SCSI_CFG1 register using this value
4851 * after it is started below.
4853 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4854 FLTR_DISABLE | scsi_cfg1);
4857 * Set MEM_CFG Microcode Default Value
4859 * The microcode will set the MEM_CFG register using this value
4860 * after it is started below.
4862 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4865 * ASC-3550 has 8KB internal memory.
4867 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4868 BIOS_EN | RAM_SZ_8KB);
4871 * Set SEL_MASK Microcode Default Value
4873 * The microcode will set the SEL_MASK register using this value
4874 * after it is started below.
4876 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4877 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4879 AdvBuildCarrierFreelist(asc_dvc);
4882 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4885 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4886 if (!asc_dvc->icq_sp) {
4887 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4892 * Set RISC ICQ physical address start value.
4894 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4897 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4899 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4900 if (!asc_dvc->irq_sp) {
4901 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4906 * Set RISC IRQ physical address start value.
4908 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4909 asc_dvc->carr_pending_cnt = 0;
4911 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4912 (ADV_INTR_ENABLE_HOST_INTR |
4913 ADV_INTR_ENABLE_GLOBAL_INTR));
4915 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4916 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4918 /* finally, finally, gentlemen, start your engine */
4919 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4922 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4923 * Resets should be performed. The RISC has to be running
4924 * to issue a SCSI Bus Reset.
4926 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4928 * If the BIOS Signature is present in memory, restore the
4929 * BIOS Handshake Configuration Table and do not perform
4932 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4935 * Restore per TID negotiated values.
4937 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4938 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4939 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4941 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4942 AdvWriteByteLram(iop_base,
4943 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4947 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4948 warn_code = ASC_WARN_BUSRESET_ERROR;
4957 * Initialize the ASC-38C0800.
4959 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4961 * For a non-fatal error return a warning code. If there are no warnings
4962 * then 0 is returned.
4964 * Needed after initialization for error recovery.
4966 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4968 const struct firmware *fw;
4969 const char fwname[] = "advansys/38C0800.bin";
4970 AdvPortAddr iop_base;
4978 unsigned long chksum;
4982 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4983 ushort wdtr_able, sdtr_able, tagqng_able;
4984 uchar max_cmd[ADV_MAX_TID + 1];
4986 /* If there is already an error, don't continue. */
4987 if (asc_dvc->err_code != 0)
4991 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4993 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4994 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4999 iop_base = asc_dvc->iop_base;
5002 * Save the RISC memory BIOS region before writing the microcode.
5003 * The BIOS may already be loaded and using its RISC LRAM region
5004 * so its region must be saved and restored.
5006 * Note: This code makes the assumption, which is currently true,
5007 * that a chip reset does not clear RISC LRAM.
5009 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5010 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5015 * Save current per TID negotiated values.
5017 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5018 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5019 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5020 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5021 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5026 * RAM BIST (RAM Built-In Self Test)
5028 * Address : I/O base + offset 0x38h register (byte).
5029 * Function: Bit 7-6(RW) : RAM mode
5030 * Normal Mode : 0x00
5031 * Pre-test Mode : 0x40
5032 * RAM Test Mode : 0x80
5034 * Bit 4(RO) : Done bit
5035 * Bit 3-0(RO) : Status
5037 * Int_RAM Error : 0x04
5042 * Note: RAM BIST code should be put right here, before loading the
5043 * microcode and after saving the RISC memory BIOS region.
5049 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5050 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5051 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5052 * to NORMAL_MODE, return an error too.
5054 for (i = 0; i < 2; i++) {
5055 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5056 mdelay(10); /* Wait for 10ms before reading back. */
5057 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5058 if ((byte & RAM_TEST_DONE) == 0
5059 || (byte & 0x0F) != PRE_TEST_VALUE) {
5060 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5064 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5065 mdelay(10); /* Wait for 10ms before reading back. */
5066 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5068 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5074 * LRAM Test - It takes about 1.5 ms to run through the test.
5076 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5077 * If Done bit not set or Status not 0, save register byte, set the
5078 * err_code, and return an error.
5080 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5081 mdelay(10); /* Wait for 10ms before checking status. */
5083 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5084 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5085 /* Get here if Done bit not set or Status not 0. */
5086 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5087 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5091 /* We need to reset back to normal mode after LRAM test passes. */
5092 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5094 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5096 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5098 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5102 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5104 release_firmware(fw);
5105 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5108 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5109 (fw->data[1] << 8) | fw->data[0];
5110 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5111 fw->size - 4, ADV_38C0800_MEMSIZE,
5113 release_firmware(fw);
5114 if (asc_dvc->err_code)
5118 * Restore the RISC memory BIOS region.
5120 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5121 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5126 * Calculate and write the microcode code checksum to the microcode
5127 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5129 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5130 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5132 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5133 for (word = begin_addr; word < end_addr; word += 2) {
5134 code_sum += AdvReadWordAutoIncLram(iop_base);
5136 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5139 * Read microcode version and date.
5141 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5142 asc_dvc->cfg->mcode_date);
5143 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5144 asc_dvc->cfg->mcode_version);
5147 * Set the chip type to indicate the ASC38C0800.
5149 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5152 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5153 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5154 * cable detection and then we are able to read C_DET[3:0].
5156 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5157 * Microcode Default Value' section below.
5159 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5160 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5161 scsi_cfg1 | DIS_TERM_DRV);
5164 * If the PCI Configuration Command Register "Parity Error Response
5165 * Control" Bit was clear (0), then set the microcode variable
5166 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5167 * to ignore DMA parity errors.
5169 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5170 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5171 word |= CONTROL_FLAG_IGNORE_PERR;
5172 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5176 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5177 * bits for the default FIFO threshold.
5179 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5181 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5183 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5184 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5188 * Microcode operating variables for WDTR, SDTR, and command tag
5189 * queuing will be set in slave_configure() based on what a
5190 * device reports it is capable of in Inquiry byte 7.
5192 * If SCSI Bus Resets have been disabled, then directly set
5193 * SDTR and WDTR from the EEPROM configuration. This will allow
5194 * the BIOS and warm boot to work without a SCSI bus hang on
5195 * the Inquiry caused by host and target mismatched DTR values.
5196 * Without the SCSI Bus Reset, before an Inquiry a device can't
5197 * be assumed to be in Asynchronous, Narrow mode.
5199 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5200 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5201 asc_dvc->wdtr_able);
5202 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5203 asc_dvc->sdtr_able);
5207 * Set microcode operating variables for DISC and SDTR_SPEED1,
5208 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5209 * configuration values.
5211 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5212 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5213 * without determining here whether the device supports SDTR.
5215 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5216 asc_dvc->cfg->disc_enable);
5217 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5218 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5219 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5220 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5223 * Set SCSI_CFG0 Microcode Default Value.
5225 * The microcode will set the SCSI_CFG0 register using this value
5226 * after it is started below.
5228 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5229 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5230 asc_dvc->chip_scsi_id);
5233 * Determine SCSI_CFG1 Microcode Default Value.
5235 * The microcode will set the SCSI_CFG1 register using this value
5236 * after it is started below.
5239 /* Read current SCSI_CFG1 Register value. */
5240 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5243 * If the internal narrow cable is reversed all of the SCSI_CTRL
5244 * register signals will be set. Check for and return an error if
5245 * this condition is found.
5247 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5248 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5253 * All kind of combinations of devices attached to one of four
5254 * connectors are acceptable except HVD device attached. For example,
5255 * LVD device can be attached to SE connector while SE device attached
5256 * to LVD connector. If LVD device attached to SE connector, it only
5257 * runs up to Ultra speed.
5259 * If an HVD device is attached to one of LVD connectors, return an
5260 * error. However, there is no way to detect HVD device attached to
5263 if (scsi_cfg1 & HVD) {
5264 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5269 * If either SE or LVD automatic termination control is enabled, then
5270 * set the termination value based on a table listed in a_condor.h.
5272 * If manual termination was specified with an EEPROM setting then
5273 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5274 * to be 'ored' into SCSI_CFG1.
5276 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5277 /* SE automatic termination control is enabled. */
5278 switch (scsi_cfg1 & C_DET_SE) {
5279 /* TERM_SE_HI: on, TERM_SE_LO: on */
5283 asc_dvc->cfg->termination |= TERM_SE;
5286 /* TERM_SE_HI: on, TERM_SE_LO: off */
5288 asc_dvc->cfg->termination |= TERM_SE_HI;
5293 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5294 /* LVD automatic termination control is enabled. */
5295 switch (scsi_cfg1 & C_DET_LVD) {
5296 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5300 asc_dvc->cfg->termination |= TERM_LVD;
5303 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5310 * Clear any set TERM_SE and TERM_LVD bits.
5312 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5315 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5317 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5320 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5321 * bits and set possibly modified termination control bits in the
5322 * Microcode SCSI_CFG1 Register Value.
5324 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5327 * Set SCSI_CFG1 Microcode Default Value
5329 * Set possibly modified termination control and reset DIS_TERM_DRV
5330 * bits in the Microcode SCSI_CFG1 Register Value.
5332 * The microcode will set the SCSI_CFG1 register using this value
5333 * after it is started below.
5335 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5338 * Set MEM_CFG Microcode Default Value
5340 * The microcode will set the MEM_CFG register using this value
5341 * after it is started below.
5343 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5346 * ASC-38C0800 has 16KB internal memory.
5348 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5349 BIOS_EN | RAM_SZ_16KB);
5352 * Set SEL_MASK Microcode Default Value
5354 * The microcode will set the SEL_MASK register using this value
5355 * after it is started below.
5357 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5358 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5360 AdvBuildCarrierFreelist(asc_dvc);
5363 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5366 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5367 if (!asc_dvc->icq_sp) {
5368 ASC_DBG(0, "Failed to get ICQ carrier\n");
5369 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5374 * Set RISC ICQ physical address start value.
5375 * carr_pa is LE, must be native before write
5377 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5380 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5382 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5383 if (!asc_dvc->irq_sp) {
5384 ASC_DBG(0, "Failed to get IRQ carrier\n");
5385 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5390 * Set RISC IRQ physical address start value.
5392 * carr_pa is LE, must be native before write *
5394 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5395 asc_dvc->carr_pending_cnt = 0;
5397 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5398 (ADV_INTR_ENABLE_HOST_INTR |
5399 ADV_INTR_ENABLE_GLOBAL_INTR));
5401 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5402 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5404 /* finally, finally, gentlemen, start your engine */
5405 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5408 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5409 * Resets should be performed. The RISC has to be running
5410 * to issue a SCSI Bus Reset.
5412 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5414 * If the BIOS Signature is present in memory, restore the
5415 * BIOS Handshake Configuration Table and do not perform
5418 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5421 * Restore per TID negotiated values.
5423 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5424 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5425 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5427 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5428 AdvWriteByteLram(iop_base,
5429 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5433 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5434 warn_code = ASC_WARN_BUSRESET_ERROR;
5443 * Initialize the ASC-38C1600.
5445 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5447 * For a non-fatal error return a warning code. If there are no warnings
5448 * then 0 is returned.
5450 * Needed after initialization for error recovery.
5452 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5454 const struct firmware *fw;
5455 const char fwname[] = "advansys/38C1600.bin";
5456 AdvPortAddr iop_base;
5464 unsigned long chksum;
5468 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5469 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5470 uchar max_cmd[ASC_MAX_TID + 1];
5472 /* If there is already an error, don't continue. */
5473 if (asc_dvc->err_code != 0) {
5478 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5480 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5481 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5486 iop_base = asc_dvc->iop_base;
5489 * Save the RISC memory BIOS region before writing the microcode.
5490 * The BIOS may already be loaded and using its RISC LRAM region
5491 * so its region must be saved and restored.
5493 * Note: This code makes the assumption, which is currently true,
5494 * that a chip reset does not clear RISC LRAM.
5496 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5497 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5502 * Save current per TID negotiated values.
5504 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5505 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5506 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5507 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5508 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5509 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5514 * RAM BIST (Built-In Self Test)
5516 * Address : I/O base + offset 0x38h register (byte).
5517 * Function: Bit 7-6(RW) : RAM mode
5518 * Normal Mode : 0x00
5519 * Pre-test Mode : 0x40
5520 * RAM Test Mode : 0x80
5522 * Bit 4(RO) : Done bit
5523 * Bit 3-0(RO) : Status
5525 * Int_RAM Error : 0x04
5530 * Note: RAM BIST code should be put right here, before loading the
5531 * microcode and after saving the RISC memory BIOS region.
5537 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5538 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5539 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5540 * to NORMAL_MODE, return an error too.
5542 for (i = 0; i < 2; i++) {
5543 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5544 mdelay(10); /* Wait for 10ms before reading back. */
5545 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5546 if ((byte & RAM_TEST_DONE) == 0
5547 || (byte & 0x0F) != PRE_TEST_VALUE) {
5548 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5552 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5553 mdelay(10); /* Wait for 10ms before reading back. */
5554 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5556 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5562 * LRAM Test - It takes about 1.5 ms to run through the test.
5564 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5565 * If Done bit not set or Status not 0, save register byte, set the
5566 * err_code, and return an error.
5568 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5569 mdelay(10); /* Wait for 10ms before checking status. */
5571 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5572 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5573 /* Get here if Done bit not set or Status not 0. */
5574 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5575 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5579 /* We need to reset back to normal mode after LRAM test passes. */
5580 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5582 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5584 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5586 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5590 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5592 release_firmware(fw);
5593 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5596 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5597 (fw->data[1] << 8) | fw->data[0];
5598 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5599 fw->size - 4, ADV_38C1600_MEMSIZE,
5601 release_firmware(fw);
5602 if (asc_dvc->err_code)
5606 * Restore the RISC memory BIOS region.
5608 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5609 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5614 * Calculate and write the microcode code checksum to the microcode
5615 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5617 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5618 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5620 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5621 for (word = begin_addr; word < end_addr; word += 2) {
5622 code_sum += AdvReadWordAutoIncLram(iop_base);
5624 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5627 * Read microcode version and date.
5629 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5630 asc_dvc->cfg->mcode_date);
5631 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5632 asc_dvc->cfg->mcode_version);
5635 * Set the chip type to indicate the ASC38C1600.
5637 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5640 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5641 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5642 * cable detection and then we are able to read C_DET[3:0].
5644 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5645 * Microcode Default Value' section below.
5647 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5648 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5649 scsi_cfg1 | DIS_TERM_DRV);
5652 * If the PCI Configuration Command Register "Parity Error Response
5653 * Control" Bit was clear (0), then set the microcode variable
5654 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5655 * to ignore DMA parity errors.
5657 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5658 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5659 word |= CONTROL_FLAG_IGNORE_PERR;
5660 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5664 * If the BIOS control flag AIPP (Asynchronous Information
5665 * Phase Protection) disable bit is not set, then set the firmware
5666 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5667 * AIPP checking and encoding.
5669 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5670 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5671 word |= CONTROL_FLAG_ENABLE_AIPP;
5672 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5676 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5677 * and START_CTL_TH [3:2].
5679 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5680 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5683 * Microcode operating variables for WDTR, SDTR, and command tag
5684 * queuing will be set in slave_configure() based on what a
5685 * device reports it is capable of in Inquiry byte 7.
5687 * If SCSI Bus Resets have been disabled, then directly set
5688 * SDTR and WDTR from the EEPROM configuration. This will allow
5689 * the BIOS and warm boot to work without a SCSI bus hang on
5690 * the Inquiry caused by host and target mismatched DTR values.
5691 * Without the SCSI Bus Reset, before an Inquiry a device can't
5692 * be assumed to be in Asynchronous, Narrow mode.
5694 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5695 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5696 asc_dvc->wdtr_able);
5697 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5698 asc_dvc->sdtr_able);
5702 * Set microcode operating variables for DISC and SDTR_SPEED1,
5703 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5704 * configuration values.
5706 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5707 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5708 * without determining here whether the device supports SDTR.
5710 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5711 asc_dvc->cfg->disc_enable);
5712 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5713 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5714 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5715 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5718 * Set SCSI_CFG0 Microcode Default Value.
5720 * The microcode will set the SCSI_CFG0 register using this value
5721 * after it is started below.
5723 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5724 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5725 asc_dvc->chip_scsi_id);
5728 * Calculate SCSI_CFG1 Microcode Default Value.
5730 * The microcode will set the SCSI_CFG1 register using this value
5731 * after it is started below.
5733 * Each ASC-38C1600 function has only two cable detect bits.
5734 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5736 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5739 * If the cable is reversed all of the SCSI_CTRL register signals
5740 * will be set. Check for and return an error if this condition is
5743 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5744 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5749 * Each ASC-38C1600 function has two connectors. Only an HVD device
5750 * can not be connected to either connector. An LVD device or SE device
5751 * may be connected to either connecor. If an SE device is connected,
5752 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5754 * If an HVD device is attached, return an error.
5756 if (scsi_cfg1 & HVD) {
5757 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5762 * Each function in the ASC-38C1600 uses only the SE cable detect and
5763 * termination because there are two connectors for each function. Each
5764 * function may use either LVD or SE mode. Corresponding the SE automatic
5765 * termination control EEPROM bits are used for each function. Each
5766 * function has its own EEPROM. If SE automatic control is enabled for
5767 * the function, then set the termination value based on a table listed
5770 * If manual termination is specified in the EEPROM for the function,
5771 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5772 * ready to be 'ored' into SCSI_CFG1.
5774 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5775 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5776 /* SE automatic termination control is enabled. */
5777 switch (scsi_cfg1 & C_DET_SE) {
5778 /* TERM_SE_HI: on, TERM_SE_LO: on */
5782 asc_dvc->cfg->termination |= TERM_SE;
5786 if (PCI_FUNC(pdev->devfn) == 0) {
5787 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5789 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5790 asc_dvc->cfg->termination |= TERM_SE_HI;
5797 * Clear any set TERM_SE bits.
5799 scsi_cfg1 &= ~TERM_SE;
5802 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5804 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5807 * Clear Big Endian and Terminator Polarity bits and set possibly
5808 * modified termination control bits in the Microcode SCSI_CFG1
5811 * Big Endian bit is not used even on big endian machines.
5813 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5816 * Set SCSI_CFG1 Microcode Default Value
5818 * Set possibly modified termination control bits in the Microcode
5819 * SCSI_CFG1 Register Value.
5821 * The microcode will set the SCSI_CFG1 register using this value
5822 * after it is started below.
5824 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5827 * Set MEM_CFG Microcode Default Value
5829 * The microcode will set the MEM_CFG register using this value
5830 * after it is started below.
5832 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5835 * ASC-38C1600 has 32KB internal memory.
5837 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5838 * out a special 16K Adv Library and Microcode version. After the issue
5839 * resolved, we should turn back to the 32K support. Both a_condor.h and
5840 * mcode.sas files also need to be updated.
5842 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5843 * BIOS_EN | RAM_SZ_32KB);
5845 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5846 BIOS_EN | RAM_SZ_16KB);
5849 * Set SEL_MASK Microcode Default Value
5851 * The microcode will set the SEL_MASK register using this value
5852 * after it is started below.
5854 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5855 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5857 AdvBuildCarrierFreelist(asc_dvc);
5860 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5862 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5863 if (!asc_dvc->icq_sp) {
5864 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5869 * Set RISC ICQ physical address start value. Initialize the
5870 * COMMA register to the same value otherwise the RISC will
5871 * prematurely detect a command is available.
5873 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5874 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5875 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5878 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5880 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5881 if (!asc_dvc->irq_sp) {
5882 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5887 * Set RISC IRQ physical address start value.
5889 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5890 asc_dvc->carr_pending_cnt = 0;
5892 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5893 (ADV_INTR_ENABLE_HOST_INTR |
5894 ADV_INTR_ENABLE_GLOBAL_INTR));
5895 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5896 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5898 /* finally, finally, gentlemen, start your engine */
5899 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5902 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5903 * Resets should be performed. The RISC has to be running
5904 * to issue a SCSI Bus Reset.
5906 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5908 * If the BIOS Signature is present in memory, restore the
5909 * per TID microcode operating variables.
5911 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5914 * Restore per TID negotiated values.
5916 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5917 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5918 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5919 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5921 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5922 AdvWriteByteLram(iop_base,
5923 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5927 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5928 warn_code = ASC_WARN_BUSRESET_ERROR;
5937 * Reset chip and SCSI Bus.
5940 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5941 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5943 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5946 ushort wdtr_able, sdtr_able, tagqng_able;
5947 ushort ppr_able = 0;
5948 uchar tid, max_cmd[ADV_MAX_TID + 1];
5949 AdvPortAddr iop_base;
5952 iop_base = asc_dvc->iop_base;
5955 * Save current per TID negotiated values.
5957 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5958 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5959 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5960 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5962 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5963 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5964 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5969 * Force the AdvInitAsc3550/38C0800Driver() function to
5970 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5971 * The initialization functions assumes a SCSI Bus Reset is not
5972 * needed if the BIOS signature word is present.
5974 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5975 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5978 * Stop chip and reset it.
5980 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5981 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5983 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5984 ADV_CTRL_REG_CMD_WR_IO_REG);
5987 * Reset Adv Library error code, if any, and try
5988 * re-initializing the chip.
5990 asc_dvc->err_code = 0;
5991 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5992 status = AdvInitAsc38C1600Driver(asc_dvc);
5993 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5994 status = AdvInitAsc38C0800Driver(asc_dvc);
5996 status = AdvInitAsc3550Driver(asc_dvc);
5999 /* Translate initialization return value to status value. */
6007 * Restore the BIOS signature word.
6009 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6012 * Restore per TID negotiated values.
6014 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6015 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6016 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6017 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6019 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6020 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6021 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6029 * adv_async_callback() - Adv Library asynchronous event callback function.
6031 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
6034 case ADV_ASYNC_SCSI_BUS_RESET_DET:
6036 * The firmware detected a SCSI Bus reset.
6038 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
6041 case ADV_ASYNC_RDMA_FAILURE:
6043 * Handle RDMA failure by resetting the SCSI Bus and
6044 * possibly the chip if it is unresponsive. Log the error
6045 * with a unique code.
6047 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
6048 AdvResetChipAndSB(adv_dvc_varp);
6051 case ADV_HOST_SCSI_BUS_RESET:
6053 * Host generated SCSI bus reset occurred.
6055 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6059 ASC_DBG(0, "unknown code 0x%x\n", code);
6065 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6067 * Callback function for the Wide SCSI Adv Library.
6069 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6071 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
6074 adv_sgblk_t *sgblkp;
6075 struct scsi_cmnd *scp;
6077 dma_addr_t sense_addr;
6079 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
6080 adv_dvc_varp, scsiqp);
6081 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6084 * Get the adv_req_t structure for the command that has been
6085 * completed. The adv_req_t structure actually contains the
6086 * completed ADV_SCSI_REQ_Q structure.
6088 srb_tag = le32_to_cpu(scsiqp->srb_tag);
6089 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
6091 ASC_DBG(1, "scp 0x%p\n", scp);
6094 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6097 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6099 reqp = (adv_req_t *)scp->host_scribble;
6100 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6102 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6106 * Remove backreferences to avoid duplicate
6107 * command completions.
6109 scp->host_scribble = NULL;
6112 ASC_STATS(boardp->shost, callback);
6113 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
6115 sense_addr = le32_to_cpu(scsiqp->sense_addr);
6116 dma_unmap_single(boardp->dev, sense_addr,
6117 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6120 * 'done_status' contains the command's ending status.
6122 switch (scsiqp->done_status) {
6124 ASC_DBG(2, "QD_NO_ERROR\n");
6128 * Check for an underrun condition.
6130 * If there was no error and an underrun condition, then
6131 * then return the number of underrun bytes.
6133 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6134 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6135 resid_cnt <= scsi_bufflen(scp)) {
6136 ASC_DBG(1, "underrun condition %lu bytes\n",
6138 scsi_set_resid(scp, resid_cnt);
6143 ASC_DBG(2, "QD_WITH_ERROR\n");
6144 switch (scsiqp->host_status) {
6145 case QHSTA_NO_ERROR:
6146 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6147 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6148 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6149 SCSI_SENSE_BUFFERSIZE);
6151 * Note: The 'status_byte()' macro used by
6152 * target drivers defined in scsi.h shifts the
6153 * status byte returned by host drivers right
6154 * by 1 bit. This is why target drivers also
6155 * use right shifted status byte definitions.
6156 * For instance target drivers use
6157 * CHECK_CONDITION, defined to 0x1, instead of
6158 * the SCSI defined check condition value of
6159 * 0x2. Host drivers are supposed to return
6160 * the status byte as it is defined by SCSI.
6162 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6163 STATUS_BYTE(scsiqp->scsi_status);
6165 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6170 /* Some other QHSTA error occurred. */
6171 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6172 scp->result = HOST_BYTE(DID_BAD_TARGET);
6177 case QD_ABORTED_BY_HOST:
6178 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6180 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6184 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6186 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6191 * If the 'init_tidmask' bit isn't already set for the target and the
6192 * current request finished normally, then set the bit for the target
6193 * to indicate that a device is present.
6195 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6196 scsiqp->done_status == QD_NO_ERROR &&
6197 scsiqp->host_status == QHSTA_NO_ERROR) {
6198 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6204 * Free all 'adv_sgblk_t' structures allocated for the request.
6206 while ((sgblkp = reqp->sgblkp) != NULL) {
6207 /* Remove 'sgblkp' from the request list. */
6208 reqp->sgblkp = sgblkp->next_sgblkp;
6210 /* Add 'sgblkp' to the board free list. */
6211 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6212 boardp->adv_sgblkp = sgblkp;
6215 ASC_DBG(1, "done\n");
6219 * Adv Library Interrupt Service Routine
6221 * This function is called by a driver's interrupt service routine.
6222 * The function disables and re-enables interrupts.
6224 * When a microcode idle command is completed, the ADV_DVC_VAR
6225 * 'idle_cmd_done' field is set to ADV_TRUE.
6227 * Note: AdvISR() can be called when interrupts are disabled or even
6228 * when there is no hardware interrupt condition present. It will
6229 * always check for completed idle commands and microcode requests.
6230 * This is an important feature that shouldn't be changed because it
6231 * allows commands to be completed from polling mode loops.
6234 * ADV_TRUE(1) - interrupt was pending
6235 * ADV_FALSE(0) - no interrupt was pending
6237 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6239 AdvPortAddr iop_base;
6242 ADV_CARR_T *free_carrp;
6243 ADV_VADDR irq_next_vpa;
6244 ADV_SCSI_REQ_Q *scsiq;
6247 iop_base = asc_dvc->iop_base;
6249 /* Reading the register clears the interrupt. */
6250 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6252 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6253 ADV_INTR_STATUS_INTRC)) == 0) {
6258 * Notify the driver of an asynchronous microcode condition by
6259 * calling the adv_async_callback function. The function
6260 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6262 if (int_stat & ADV_INTR_STATUS_INTRB) {
6265 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6267 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6268 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6269 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6270 asc_dvc->carr_pending_cnt != 0) {
6271 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6273 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6274 AdvWriteByteRegister(iop_base,
6281 adv_async_callback(asc_dvc, intrb_code);
6285 * Check if the IRQ stopper carrier contains a completed request.
6287 while (((irq_next_vpa =
6288 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6290 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6291 * The RISC will have set 'areq_vpa' to a virtual address.
6293 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6294 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6295 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6296 * in AdvExeScsiQueue().
6298 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6299 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6300 asc_dvc->irq_sp, pa_offset);
6301 reqp = adv_get_reqp(asc_dvc, pa_offset);
6302 scsiq = &reqp->scsi_req_q;
6305 * Request finished with good status and the queue was not
6306 * DMAed to host memory by the firmware. Set all status fields
6307 * to indicate good status.
6309 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6310 scsiq->done_status = QD_NO_ERROR;
6311 scsiq->host_status = scsiq->scsi_status = 0;
6312 scsiq->data_cnt = 0L;
6316 * Advance the stopper pointer to the next carrier
6317 * ignoring the lower four bits. Free the previous
6320 free_carrp = asc_dvc->irq_sp;
6321 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6322 ASC_GET_CARRP(irq_next_vpa));
6324 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6325 asc_dvc->carr_freelist = free_carrp;
6326 asc_dvc->carr_pending_cnt--;
6328 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6331 * Clear request microcode control flag.
6336 * Notify the driver of the completed request by passing
6337 * the ADV_SCSI_REQ_Q pointer to its callback function.
6339 scsiq->a_flag |= ADV_SCSIQ_DONE;
6340 adv_isr_callback(asc_dvc, scsiq);
6342 * Note: After the driver callback function is called, 'scsiq'
6343 * can no longer be referenced.
6345 * Fall through and continue processing other completed
6352 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6354 if (asc_dvc->err_code == 0) {
6355 asc_dvc->err_code = err_code;
6356 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6362 static void AscAckInterrupt(PortAddr iop_base)
6370 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6371 if (loop++ > 0x7FFF) {
6374 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6376 AscReadLramByte(iop_base,
6377 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6378 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6379 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6380 AscSetChipStatus(iop_base, CIW_INT_ACK);
6382 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6383 AscSetChipStatus(iop_base, CIW_INT_ACK);
6388 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6391 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6393 const uchar *period_table;
6398 period_table = asc_dvc->sdtr_period_tbl;
6399 max_index = (int)asc_dvc->max_sdtr_index;
6400 min_index = (int)asc_dvc->min_sdtr_index;
6401 if ((syn_time <= period_table[max_index])) {
6402 for (i = min_index; i < (max_index - 1); i++) {
6403 if (syn_time <= period_table[i]) {
6407 return (uchar)max_index;
6409 return (uchar)(max_index + 1);
6414 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6417 uchar sdtr_period_index;
6420 iop_base = asc_dvc->iop_base;
6421 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6422 sdtr_buf.msg_len = MS_SDTR_LEN;
6423 sdtr_buf.msg_req = EXTENDED_SDTR;
6424 sdtr_buf.xfer_period = sdtr_period;
6425 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6426 sdtr_buf.req_ack_offset = sdtr_offset;
6427 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6428 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6429 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6431 sizeof(EXT_MSG) >> 1);
6432 return ((sdtr_period_index << 4) | sdtr_offset);
6434 sdtr_buf.req_ack_offset = 0;
6435 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6437 sizeof(EXT_MSG) >> 1);
6443 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6446 uchar sdtr_period_ix;
6448 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6449 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6451 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6455 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6457 ASC_SCSI_BIT_ID_TYPE org_id;
6461 AscSetBank(iop_base, 1);
6462 org_id = AscReadChipDvcID(iop_base);
6463 for (i = 0; i <= ASC_MAX_TID; i++) {
6464 if (org_id == (0x01 << i))
6467 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6468 AscWriteChipDvcID(iop_base, id);
6469 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6470 AscSetBank(iop_base, 0);
6471 AscSetChipSyn(iop_base, sdtr_data);
6472 if (AscGetChipSyn(iop_base) != sdtr_data) {
6478 AscSetBank(iop_base, 1);
6479 AscWriteChipDvcID(iop_base, org_id);
6480 AscSetBank(iop_base, 0);
6484 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6486 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6487 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6490 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6496 ushort int_halt_code;
6497 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6498 ASC_SCSI_BIT_ID_TYPE target_id;
6505 uchar q_cntl, tid_no;
6509 struct asc_board *boardp;
6511 BUG_ON(!asc_dvc->drv_ptr);
6512 boardp = asc_dvc->drv_ptr;
6514 iop_base = asc_dvc->iop_base;
6515 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6517 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6518 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6519 target_ix = AscReadLramByte(iop_base,
6520 (ushort)(halt_q_addr +
6521 (ushort)ASC_SCSIQ_B_TARGET_IX));
6522 q_cntl = AscReadLramByte(iop_base,
6523 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6524 tid_no = ASC_TIX_TO_TID(target_ix);
6525 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6526 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6527 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6531 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6532 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6533 AscSetChipSDTR(iop_base, 0, tid_no);
6534 boardp->sdtr_data[tid_no] = 0;
6536 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6538 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6539 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6540 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6541 boardp->sdtr_data[tid_no] = asyn_sdtr;
6543 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6545 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6546 AscMemWordCopyPtrFromLram(iop_base,
6549 sizeof(EXT_MSG) >> 1);
6551 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6552 ext_msg.msg_req == EXTENDED_SDTR &&
6553 ext_msg.msg_len == MS_SDTR_LEN) {
6555 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6557 sdtr_accept = FALSE;
6558 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6560 if ((ext_msg.xfer_period <
6561 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6562 || (ext_msg.xfer_period >
6563 asc_dvc->sdtr_period_tbl[asc_dvc->
6565 sdtr_accept = FALSE;
6566 ext_msg.xfer_period =
6567 asc_dvc->sdtr_period_tbl[asc_dvc->
6572 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6573 ext_msg.req_ack_offset);
6574 if ((sdtr_data == 0xFF)) {
6576 q_cntl |= QC_MSG_OUT;
6577 asc_dvc->init_sdtr &= ~target_id;
6578 asc_dvc->sdtr_done &= ~target_id;
6579 AscSetChipSDTR(iop_base, asyn_sdtr,
6581 boardp->sdtr_data[tid_no] = asyn_sdtr;
6584 if (ext_msg.req_ack_offset == 0) {
6586 q_cntl &= ~QC_MSG_OUT;
6587 asc_dvc->init_sdtr &= ~target_id;
6588 asc_dvc->sdtr_done &= ~target_id;
6589 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6591 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6592 q_cntl &= ~QC_MSG_OUT;
6593 asc_dvc->sdtr_done |= target_id;
6594 asc_dvc->init_sdtr |= target_id;
6595 asc_dvc->pci_fix_asyn_xfer &=
6598 AscCalSDTRData(asc_dvc,
6599 ext_msg.xfer_period,
6602 AscSetChipSDTR(iop_base, sdtr_data,
6604 boardp->sdtr_data[tid_no] = sdtr_data;
6606 q_cntl |= QC_MSG_OUT;
6607 AscMsgOutSDTR(asc_dvc,
6608 ext_msg.xfer_period,
6609 ext_msg.req_ack_offset);
6610 asc_dvc->pci_fix_asyn_xfer &=
6613 AscCalSDTRData(asc_dvc,
6614 ext_msg.xfer_period,
6617 AscSetChipSDTR(iop_base, sdtr_data,
6619 boardp->sdtr_data[tid_no] = sdtr_data;
6620 asc_dvc->sdtr_done |= target_id;
6621 asc_dvc->init_sdtr |= target_id;
6625 AscWriteLramByte(iop_base,
6626 (ushort)(halt_q_addr +
6627 (ushort)ASC_SCSIQ_B_CNTL),
6629 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6631 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6632 ext_msg.msg_req == EXTENDED_WDTR &&
6633 ext_msg.msg_len == MS_WDTR_LEN) {
6635 ext_msg.wdtr_width = 0;
6636 AscMemWordCopyPtrToLram(iop_base,
6639 sizeof(EXT_MSG) >> 1);
6640 q_cntl |= QC_MSG_OUT;
6641 AscWriteLramByte(iop_base,
6642 (ushort)(halt_q_addr +
6643 (ushort)ASC_SCSIQ_B_CNTL),
6645 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6649 ext_msg.msg_type = MESSAGE_REJECT;
6650 AscMemWordCopyPtrToLram(iop_base,
6653 sizeof(EXT_MSG) >> 1);
6654 q_cntl |= QC_MSG_OUT;
6655 AscWriteLramByte(iop_base,
6656 (ushort)(halt_q_addr +
6657 (ushort)ASC_SCSIQ_B_CNTL),
6659 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6662 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6664 q_cntl |= QC_REQ_SENSE;
6666 if ((asc_dvc->init_sdtr & target_id) != 0) {
6668 asc_dvc->sdtr_done &= ~target_id;
6670 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6671 q_cntl |= QC_MSG_OUT;
6672 AscMsgOutSDTR(asc_dvc,
6674 sdtr_period_tbl[(sdtr_data >> 4) &
6678 (uchar)(sdtr_data & (uchar)
6679 ASC_SYN_MAX_OFFSET));
6682 AscWriteLramByte(iop_base,
6683 (ushort)(halt_q_addr +
6684 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6686 tag_code = AscReadLramByte(iop_base,
6687 (ushort)(halt_q_addr + (ushort)
6688 ASC_SCSIQ_B_TAG_CODE));
6690 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6691 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6694 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6695 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6698 AscWriteLramByte(iop_base,
6699 (ushort)(halt_q_addr +
6700 (ushort)ASC_SCSIQ_B_TAG_CODE),
6703 q_status = AscReadLramByte(iop_base,
6704 (ushort)(halt_q_addr + (ushort)
6705 ASC_SCSIQ_B_STATUS));
6706 q_status |= (QS_READY | QS_BUSY);
6707 AscWriteLramByte(iop_base,
6708 (ushort)(halt_q_addr +
6709 (ushort)ASC_SCSIQ_B_STATUS),
6712 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6713 scsi_busy &= ~target_id;
6714 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6716 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6718 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6720 AscMemWordCopyPtrFromLram(iop_base,
6723 sizeof(EXT_MSG) >> 1);
6725 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6726 (out_msg.msg_len == MS_SDTR_LEN) &&
6727 (out_msg.msg_req == EXTENDED_SDTR)) {
6729 asc_dvc->init_sdtr &= ~target_id;
6730 asc_dvc->sdtr_done &= ~target_id;
6731 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6732 boardp->sdtr_data[tid_no] = asyn_sdtr;
6734 q_cntl &= ~QC_MSG_OUT;
6735 AscWriteLramByte(iop_base,
6736 (ushort)(halt_q_addr +
6737 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6738 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6740 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6742 scsi_status = AscReadLramByte(iop_base,
6743 (ushort)((ushort)halt_q_addr +
6745 ASC_SCSIQ_SCSI_STATUS));
6747 AscReadLramByte(iop_base,
6748 (ushort)((ushort)ASC_QADR_BEG +
6749 (ushort)target_ix));
6750 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6752 scsi_busy = AscReadLramByte(iop_base,
6753 (ushort)ASCV_SCSIBUSY_B);
6754 scsi_busy |= target_id;
6755 AscWriteLramByte(iop_base,
6756 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6757 asc_dvc->queue_full_or_busy |= target_id;
6759 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6760 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6762 asc_dvc->max_dvc_qng[tid_no] =
6765 AscWriteLramByte(iop_base,
6767 ASCV_MAX_DVC_QNG_BEG
6773 * Set the device queue depth to the
6774 * number of active requests when the
6775 * QUEUE FULL condition was encountered.
6777 boardp->queue_full |= target_id;
6778 boardp->queue_full_cnt[tid_no] =
6783 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6786 #if CC_VERY_LONG_SG_LIST
6787 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6791 uchar first_sg_wk_q_no;
6792 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6793 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6794 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6795 ushort sg_list_dwords;
6796 ushort sg_entry_cnt;
6800 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6801 if (q_no == ASC_QLINK_END)
6804 q_addr = ASC_QNO_TO_QADDR(q_no);
6807 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6808 * structure pointer using a macro provided by the driver.
6809 * The ASC_SCSI_REQ pointer provides a pointer to the
6810 * host ASC_SG_HEAD structure.
6812 /* Read request's SRB pointer. */
6813 scsiq = (ASC_SCSI_Q *)
6814 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6817 ASC_SCSIQ_D_SRBPTR))));
6820 * Get request's first and working SG queue.
6822 sg_wk_q_no = AscReadLramByte(iop_base,
6824 ASC_SCSIQ_B_SG_WK_QP));
6826 first_sg_wk_q_no = AscReadLramByte(iop_base,
6828 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6831 * Reset request's working SG queue back to the
6834 AscWriteLramByte(iop_base,
6836 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6839 sg_head = scsiq->sg_head;
6842 * Set sg_entry_cnt to the number of SG elements
6843 * that will be completed on this interrupt.
6845 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6846 * SG elements. The data_cnt and data_addr fields which
6847 * add 1 to the SG element capacity are not used when
6848 * restarting SG handling after a halt.
6850 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6851 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6854 * Keep track of remaining number of SG elements that
6855 * will need to be handled on the next interrupt.
6857 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6859 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6860 scsiq->remain_sg_entry_cnt = 0;
6864 * Copy SG elements into the list of allocated SG queues.
6866 * Last index completed is saved in scsiq->next_sg_index.
6868 next_qp = first_sg_wk_q_no;
6869 q_addr = ASC_QNO_TO_QADDR(next_qp);
6870 scsi_sg_q.sg_head_qp = q_no;
6871 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6872 for (i = 0; i < sg_head->queue_cnt; i++) {
6873 scsi_sg_q.seq_no = i + 1;
6874 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6875 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6876 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6878 * After very first SG queue RISC FW uses next
6879 * SG queue first element then checks sg_list_cnt
6880 * against zero and then decrements, so set
6881 * sg_list_cnt 1 less than number of SG elements
6884 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6885 scsi_sg_q.sg_cur_list_cnt =
6886 ASC_SG_LIST_PER_Q - 1;
6889 * This is the last SG queue in the list of
6890 * allocated SG queues. If there are more
6891 * SG elements than will fit in the allocated
6892 * queues, then set the QCSG_SG_XFER_MORE flag.
6894 if (scsiq->remain_sg_entry_cnt != 0) {
6895 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6897 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6899 /* equals sg_entry_cnt * 2 */
6900 sg_list_dwords = sg_entry_cnt << 1;
6901 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6902 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6906 scsi_sg_q.q_no = next_qp;
6907 AscMemWordCopyPtrToLram(iop_base,
6908 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6909 (uchar *)&scsi_sg_q,
6910 sizeof(ASC_SG_LIST_Q) >> 1);
6912 AscMemDWordCopyPtrToLram(iop_base,
6913 q_addr + ASC_SGQ_LIST_BEG,
6915 sg_list[scsiq->next_sg_index],
6918 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6921 * If the just completed SG queue contained the
6922 * last SG element, then no more SG queues need
6925 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6929 next_qp = AscReadLramByte(iop_base,
6932 q_addr = ASC_QNO_TO_QADDR(next_qp);
6936 * Clear the halt condition so the RISC will be restarted
6939 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6942 #endif /* CC_VERY_LONG_SG_LIST */
6948 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6950 * Calling/Exit State:
6954 * Input an ASC_QDONE_INFO structure from the chip
6957 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6962 AscSetChipLramAddr(iop_base, s_addr);
6963 for (i = 0; i < 2 * words; i += 2) {
6967 word = inpw(iop_base + IOP_RAM_DATA);
6968 inbuf[i] = word & 0xff;
6969 inbuf[i + 1] = (word >> 8) & 0xff;
6971 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6975 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6977 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
6982 DvcGetQinfo(iop_base,
6983 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6985 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6987 _val = AscReadLramWord(iop_base,
6988 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6989 scsiq->q_status = (uchar)_val;
6990 scsiq->q_no = (uchar)(_val >> 8);
6991 _val = AscReadLramWord(iop_base,
6992 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6993 scsiq->cntl = (uchar)_val;
6994 sg_queue_cnt = (uchar)(_val >> 8);
6995 _val = AscReadLramWord(iop_base,
6997 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6998 scsiq->sense_len = (uchar)_val;
6999 scsiq->extra_bytes = (uchar)(_val >> 8);
7002 * Read high word of remain bytes from alternate location.
7004 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7007 ASC_SCSIQ_W_ALT_DC1)))
7010 * Read low word of remain bytes from original location.
7012 scsiq->remain_bytes += AscReadLramWord(iop_base,
7013 (ushort)(q_addr + (ushort)
7014 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7016 scsiq->remain_bytes &= max_dma_count;
7017 return sg_queue_cnt;
7021 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
7023 * Interrupt callback function for the Narrow SCSI Asc Library.
7025 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
7027 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
7029 struct scsi_cmnd *scp;
7031 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
7032 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
7035 * Decrease the srb_tag by 1 to find the SCSI command
7037 srb_tag = qdonep->d2.srb_tag - 1;
7038 scp = scsi_host_find_tag(boardp->shost, srb_tag);
7042 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7044 ASC_STATS(boardp->shost, callback);
7046 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
7047 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7049 * 'qdonep' contains the command's ending status.
7051 switch (qdonep->d3.done_stat) {
7053 ASC_DBG(2, "QD_NO_ERROR\n");
7057 * Check for an underrun condition.
7059 * If there was no error and an underrun condition, then
7060 * return the number of underrun bytes.
7062 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7063 qdonep->remain_bytes <= scsi_bufflen(scp)) {
7064 ASC_DBG(1, "underrun condition %u bytes\n",
7065 (unsigned)qdonep->remain_bytes);
7066 scsi_set_resid(scp, qdonep->remain_bytes);
7071 ASC_DBG(2, "QD_WITH_ERROR\n");
7072 switch (qdonep->d3.host_stat) {
7073 case QHSTA_NO_ERROR:
7074 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7075 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7076 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7077 SCSI_SENSE_BUFFERSIZE);
7079 * Note: The 'status_byte()' macro used by
7080 * target drivers defined in scsi.h shifts the
7081 * status byte returned by host drivers right
7082 * by 1 bit. This is why target drivers also
7083 * use right shifted status byte definitions.
7084 * For instance target drivers use
7085 * CHECK_CONDITION, defined to 0x1, instead of
7086 * the SCSI defined check condition value of
7087 * 0x2. Host drivers are supposed to return
7088 * the status byte as it is defined by SCSI.
7090 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7091 STATUS_BYTE(qdonep->d3.scsi_stat);
7093 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7098 /* QHSTA error occurred */
7099 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7100 scp->result = HOST_BYTE(DID_BAD_TARGET);
7105 case QD_ABORTED_BY_HOST:
7106 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7108 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7110 STATUS_BYTE(qdonep->d3.scsi_stat);
7114 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7116 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7118 STATUS_BYTE(qdonep->d3.scsi_stat);
7123 * If the 'init_tidmask' bit isn't already set for the target and the
7124 * current request finished normally, then set the bit for the target
7125 * to indicate that a device is present.
7127 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7128 qdonep->d3.done_stat == QD_NO_ERROR &&
7129 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7130 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7136 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7145 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7146 ASC_SCSI_BIT_ID_TYPE target_id;
7150 uchar cur_target_qng;
7151 ASC_QDONE_INFO scsiq_buf;
7152 ASC_QDONE_INFO *scsiq;
7155 iop_base = asc_dvc->iop_base;
7157 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7158 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7159 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7160 next_qp = AscReadLramByte(iop_base,
7161 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7162 if (next_qp != ASC_QLINK_END) {
7163 AscPutVarDoneQTail(iop_base, next_qp);
7164 q_addr = ASC_QNO_TO_QADDR(next_qp);
7165 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7166 asc_dvc->max_dma_count);
7167 AscWriteLramByte(iop_base,
7169 (ushort)ASC_SCSIQ_B_STATUS),
7171 q_status & (uchar)~(QS_READY |
7173 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7174 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7175 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7177 sg_list_qp = next_qp;
7178 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7179 sg_list_qp = AscReadLramByte(iop_base,
7183 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7184 if (sg_list_qp == ASC_QLINK_END) {
7185 AscSetLibErrorCode(asc_dvc,
7186 ASCQ_ERR_SG_Q_LINKS);
7187 scsiq->d3.done_stat = QD_WITH_ERROR;
7188 scsiq->d3.host_stat =
7189 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7190 goto FATAL_ERR_QDONE;
7192 AscWriteLramByte(iop_base,
7193 (ushort)(sg_q_addr + (ushort)
7194 ASC_SCSIQ_B_STATUS),
7197 n_q_used = sg_queue_cnt + 1;
7198 AscPutVarDoneQTail(iop_base, sg_list_qp);
7200 if (asc_dvc->queue_full_or_busy & target_id) {
7201 cur_target_qng = AscReadLramByte(iop_base,
7207 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7208 scsi_busy = AscReadLramByte(iop_base, (ushort)
7210 scsi_busy &= ~target_id;
7211 AscWriteLramByte(iop_base,
7212 (ushort)ASCV_SCSIBUSY_B,
7214 asc_dvc->queue_full_or_busy &= ~target_id;
7217 if (asc_dvc->cur_total_qng >= n_q_used) {
7218 asc_dvc->cur_total_qng -= n_q_used;
7219 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7220 asc_dvc->cur_dvc_qng[tid_no]--;
7223 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7224 scsiq->d3.done_stat = QD_WITH_ERROR;
7225 goto FATAL_ERR_QDONE;
7227 if ((scsiq->d2.srb_tag == 0UL) ||
7228 ((scsiq->q_status & QS_ABORTED) != 0)) {
7230 } else if (scsiq->q_status == QS_DONE) {
7231 false_overrun = FALSE;
7232 if (scsiq->extra_bytes != 0) {
7233 scsiq->remain_bytes +=
7234 (ADV_DCNT)scsiq->extra_bytes;
7236 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7237 if (scsiq->d3.host_stat ==
7238 QHSTA_M_DATA_OVER_RUN) {
7240 cntl & (QC_DATA_IN | QC_DATA_OUT))
7242 scsiq->d3.done_stat =
7244 scsiq->d3.host_stat =
7246 } else if (false_overrun) {
7247 scsiq->d3.done_stat =
7249 scsiq->d3.host_stat =
7252 } else if (scsiq->d3.host_stat ==
7253 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7254 AscStopChip(iop_base);
7255 AscSetChipControl(iop_base,
7256 (uchar)(CC_SCSI_RESET
7259 AscSetChipControl(iop_base, CC_HALT);
7260 AscSetChipStatus(iop_base,
7261 CIW_CLR_SCSI_RESET_INT);
7262 AscSetChipStatus(iop_base, 0);
7263 AscSetChipControl(iop_base, 0);
7266 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7267 asc_isr_callback(asc_dvc, scsiq);
7269 if ((AscReadLramByte(iop_base,
7270 (ushort)(q_addr + (ushort)
7273 asc_dvc->unit_not_ready &= ~target_id;
7274 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7275 asc_dvc->start_motor &=
7282 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7284 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7285 asc_isr_callback(asc_dvc, scsiq);
7293 static int AscISR(ASC_DVC_VAR *asc_dvc)
7295 ASC_CS_TYPE chipstat;
7297 ushort saved_ram_addr;
7299 uchar saved_ctrl_reg;
7304 iop_base = asc_dvc->iop_base;
7305 int_pending = FALSE;
7307 if (AscIsIntPending(iop_base) == 0)
7310 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7313 if (asc_dvc->in_critical_cnt != 0) {
7314 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7317 if (asc_dvc->is_in_int) {
7318 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7321 asc_dvc->is_in_int = TRUE;
7322 ctrl_reg = AscGetChipControl(iop_base);
7323 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7324 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7325 chipstat = AscGetChipStatus(iop_base);
7326 if (chipstat & CSW_SCSI_RESET_LATCH) {
7327 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7330 asc_dvc->sdtr_done = 0;
7331 saved_ctrl_reg &= (uchar)(~CC_HALT);
7332 while ((AscGetChipStatus(iop_base) &
7333 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7336 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7337 AscSetChipControl(iop_base, CC_HALT);
7338 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7339 AscSetChipStatus(iop_base, 0);
7340 chipstat = AscGetChipStatus(iop_base);
7343 saved_ram_addr = AscGetChipLramAddr(iop_base);
7344 host_flag = AscReadLramByte(iop_base,
7346 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7347 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7348 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7349 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7350 AscAckInterrupt(iop_base);
7352 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7353 if (AscIsrChipHalted(asc_dvc) == ERR) {
7354 goto ISR_REPORT_QDONE_FATAL_ERROR;
7356 saved_ctrl_reg &= (uchar)(~CC_HALT);
7359 ISR_REPORT_QDONE_FATAL_ERROR:
7360 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7362 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7367 AscIsrQDone(asc_dvc)) == 1) {
7370 } while (status == 0x11);
7372 if ((status & 0x80) != 0)
7376 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7377 AscSetChipLramAddr(iop_base, saved_ram_addr);
7378 AscSetChipControl(iop_base, saved_ctrl_reg);
7379 asc_dvc->is_in_int = FALSE;
7386 * Reset the host associated with the command 'scp'.
7388 * This function runs its own thread. Interrupts must be blocked but
7389 * sleeping is allowed and no locking other than for host structures is
7390 * required. Returns SUCCESS or FAILED.
7392 static int advansys_reset(struct scsi_cmnd *scp)
7394 struct Scsi_Host *shost = scp->device->host;
7395 struct asc_board *boardp = shost_priv(shost);
7396 unsigned long flags;
7400 ASC_DBG(1, "0x%p\n", scp);
7402 ASC_STATS(shost, reset);
7404 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7406 if (ASC_NARROW_BOARD(boardp)) {
7407 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7409 /* Reset the chip and SCSI bus. */
7410 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7411 status = AscInitAsc1000Driver(asc_dvc);
7413 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7414 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7415 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7416 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7419 } else if (status) {
7420 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7423 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7427 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7430 * If the suggest reset bus flags are set, then reset the bus.
7431 * Otherwise only reset the device.
7433 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7436 * Reset the chip and SCSI bus.
7438 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7439 switch (AdvResetChipAndSB(adv_dvc)) {
7441 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7446 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7450 spin_lock_irqsave(shost->host_lock, flags);
7452 spin_unlock_irqrestore(shost->host_lock, flags);
7455 ASC_DBG(1, "ret %d\n", ret);
7461 * advansys_biosparam()
7463 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7464 * support is enabled for a drive.
7466 * ip (information pointer) is an int array with the following definition:
7472 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7473 sector_t capacity, int ip[])
7475 struct asc_board *boardp = shost_priv(sdev->host);
7477 ASC_DBG(1, "begin\n");
7478 ASC_STATS(sdev->host, biosparam);
7479 if (ASC_NARROW_BOARD(boardp)) {
7480 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7481 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7489 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7490 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7498 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7499 ASC_DBG(1, "end\n");
7504 * First-level interrupt handler.
7506 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7508 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7510 struct Scsi_Host *shost = dev_id;
7511 struct asc_board *boardp = shost_priv(shost);
7512 irqreturn_t result = IRQ_NONE;
7514 ASC_DBG(2, "boardp 0x%p\n", boardp);
7515 spin_lock(shost->host_lock);
7516 if (ASC_NARROW_BOARD(boardp)) {
7517 if (AscIsIntPending(shost->io_port)) {
7518 result = IRQ_HANDLED;
7519 ASC_STATS(shost, interrupt);
7520 ASC_DBG(1, "before AscISR()\n");
7521 AscISR(&boardp->dvc_var.asc_dvc_var);
7524 ASC_DBG(1, "before AdvISR()\n");
7525 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7526 result = IRQ_HANDLED;
7527 ASC_STATS(shost, interrupt);
7530 spin_unlock(shost->host_lock);
7532 ASC_DBG(1, "end\n");
7536 static int AscHostReqRiscHalt(PortAddr iop_base)
7540 uchar saved_stop_code;
7542 if (AscIsChipHalted(iop_base))
7544 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7545 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7546 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7548 if (AscIsChipHalted(iop_base)) {
7553 } while (count++ < 20);
7554 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7559 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7563 if (AscHostReqRiscHalt(iop_base)) {
7564 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7565 AscStartChip(iop_base);
7570 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7572 char type = sdev->type;
7573 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7575 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7577 if (asc_dvc->init_sdtr & tid_bits)
7580 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7581 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7583 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7584 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7585 (type == TYPE_ROM) || (type == TYPE_TAPE))
7586 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7588 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7589 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7590 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7594 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7596 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7597 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7599 if (sdev->lun == 0) {
7600 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7601 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7602 asc_dvc->init_sdtr |= tid_bit;
7604 asc_dvc->init_sdtr &= ~tid_bit;
7607 if (orig_init_sdtr != asc_dvc->init_sdtr)
7608 AscAsyncFix(asc_dvc, sdev);
7611 if (sdev->tagged_supported) {
7612 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7613 if (sdev->lun == 0) {
7614 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7615 asc_dvc->use_tagged_qng |= tid_bit;
7617 scsi_change_queue_depth(sdev,
7618 asc_dvc->max_dvc_qng[sdev->id]);
7621 if (sdev->lun == 0) {
7622 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7623 asc_dvc->use_tagged_qng &= ~tid_bit;
7627 if ((sdev->lun == 0) &&
7628 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7629 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7630 asc_dvc->cfg->disc_enable);
7631 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7632 asc_dvc->use_tagged_qng);
7633 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7634 asc_dvc->cfg->can_tagged_qng);
7636 asc_dvc->max_dvc_qng[sdev->id] =
7637 asc_dvc->cfg->max_tag_qng[sdev->id];
7638 AscWriteLramByte(asc_dvc->iop_base,
7639 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7640 asc_dvc->max_dvc_qng[sdev->id]);
7647 * If the EEPROM enabled WDTR for the device and the device supports wide
7648 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7649 * write the new value to the microcode.
7652 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7654 unsigned short cfg_word;
7655 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7656 if ((cfg_word & tidmask) != 0)
7659 cfg_word |= tidmask;
7660 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7663 * Clear the microcode SDTR and WDTR negotiation done indicators for
7664 * the target to cause it to negotiate with the new setting set above.
7665 * WDTR when accepted causes the target to enter asynchronous mode, so
7666 * SDTR must be negotiated.
7668 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7669 cfg_word &= ~tidmask;
7670 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7671 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7672 cfg_word &= ~tidmask;
7673 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7677 * Synchronous Transfers
7679 * If the EEPROM enabled SDTR for the device and the device
7680 * supports synchronous transfers, then turn on the device's
7681 * 'sdtr_able' bit. Write the new value to the microcode.
7684 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7686 unsigned short cfg_word;
7687 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7688 if ((cfg_word & tidmask) != 0)
7691 cfg_word |= tidmask;
7692 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7695 * Clear the microcode "SDTR negotiation" done indicator for the
7696 * target to cause it to negotiate with the new setting set above.
7698 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7699 cfg_word &= ~tidmask;
7700 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7704 * PPR (Parallel Protocol Request) Capable
7706 * If the device supports DT mode, then it must be PPR capable.
7707 * The PPR message will be used in place of the SDTR and WDTR
7708 * messages to negotiate synchronous speed and offset, transfer
7709 * width, and protocol options.
7711 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7712 AdvPortAddr iop_base, unsigned short tidmask)
7714 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7715 adv_dvc->ppr_able |= tidmask;
7716 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7720 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7722 AdvPortAddr iop_base = adv_dvc->iop_base;
7723 unsigned short tidmask = 1 << sdev->id;
7725 if (sdev->lun == 0) {
7727 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7728 * is enabled in the EEPROM and the device supports the
7729 * feature, then enable it in the microcode.
7732 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7733 advansys_wide_enable_wdtr(iop_base, tidmask);
7734 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7735 advansys_wide_enable_sdtr(iop_base, tidmask);
7736 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7737 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7740 * Tag Queuing is disabled for the BIOS which runs in polled
7741 * mode and would see no benefit from Tag Queuing. Also by
7742 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7743 * bugs will at least work with the BIOS.
7745 if ((adv_dvc->tagqng_able & tidmask) &&
7746 sdev->tagged_supported) {
7747 unsigned short cfg_word;
7748 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7749 cfg_word |= tidmask;
7750 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7752 AdvWriteByteLram(iop_base,
7753 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7754 adv_dvc->max_dvc_qng);
7758 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7759 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
7763 * Set the number of commands to queue per device for the
7764 * specified host adapter.
7766 static int advansys_slave_configure(struct scsi_device *sdev)
7768 struct asc_board *boardp = shost_priv(sdev->host);
7770 if (ASC_NARROW_BOARD(boardp))
7771 advansys_narrow_slave_configure(sdev,
7772 &boardp->dvc_var.asc_dvc_var);
7774 advansys_wide_slave_configure(sdev,
7775 &boardp->dvc_var.adv_dvc_var);
7780 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7782 struct asc_board *board = shost_priv(scp->device->host);
7783 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7784 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7785 dma_cache_sync(board->dev, scp->sense_buffer,
7786 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7787 return cpu_to_le32(scp->SCp.dma_handle);
7790 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7791 struct asc_scsi_q *asc_scsi_q)
7793 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7797 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7800 * Set the srb_tag to the command tag + 1, as
7801 * srb_tag '0' is used internally by the chip.
7803 srb_tag = scp->request->tag + 1;
7804 asc_scsi_q->q2.srb_tag = srb_tag;
7807 * Build the ASC_SCSI_Q request.
7809 asc_scsi_q->cdbptr = &scp->cmnd[0];
7810 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7811 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7812 asc_scsi_q->q1.target_lun = scp->device->lun;
7813 asc_scsi_q->q2.target_ix =
7814 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7815 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
7816 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7819 * If there are any outstanding requests for the current target,
7820 * then every 255th request send an ORDERED request. This heuristic
7821 * tries to retain the benefit of request sorting while preventing
7822 * request starvation. 255 is the max number of tags or pending commands
7823 * a device may have outstanding.
7825 * The request count is incremented below for every successfully
7829 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7830 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7831 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
7833 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
7836 /* Build ASC_SCSI_Q */
7837 use_sg = scsi_dma_map(scp);
7840 struct scatterlist *slp;
7841 struct asc_sg_head *asc_sg_head;
7843 if (use_sg > scp->device->host->sg_tablesize) {
7844 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7845 "sg_tablesize %d\n", use_sg,
7846 scp->device->host->sg_tablesize);
7847 scsi_dma_unmap(scp);
7848 scp->result = HOST_BYTE(DID_ERROR);
7852 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7853 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7855 scsi_dma_unmap(scp);
7856 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7860 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7861 asc_scsi_q->sg_head = asc_sg_head;
7862 asc_scsi_q->q1.data_cnt = 0;
7863 asc_scsi_q->q1.data_addr = 0;
7864 /* This is a byte value, otherwise it would need to be swapped. */
7865 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7866 ASC_STATS_ADD(scp->device->host, xfer_elem,
7867 asc_sg_head->entry_cnt);
7870 * Convert scatter-gather list into ASC_SG_HEAD list.
7872 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7873 asc_sg_head->sg_list[sgcnt].addr =
7874 cpu_to_le32(sg_dma_address(slp));
7875 asc_sg_head->sg_list[sgcnt].bytes =
7876 cpu_to_le32(sg_dma_len(slp));
7877 ASC_STATS_ADD(scp->device->host, xfer_sect,
7878 DIV_ROUND_UP(sg_dma_len(slp), 512));
7882 ASC_STATS(scp->device->host, xfer_cnt);
7884 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7885 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7891 * Build scatter-gather list for Adv Library (Wide Board).
7893 * Additional ADV_SG_BLOCK structures will need to be allocated
7894 * if the total number of scatter-gather elements exceeds
7895 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7896 * assumed to be physically contiguous.
7899 * ADV_SUCCESS(1) - SG List successfully created
7900 * ADV_ERROR(-1) - SG List creation failed
7903 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7904 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
7906 adv_sgblk_t *sgblkp;
7907 struct scatterlist *slp;
7909 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7910 ADV_PADDR sg_block_paddr;
7913 slp = scsi_sglist(scp);
7914 sg_elem_cnt = use_sg;
7915 prev_sg_block = NULL;
7916 reqp->sgblkp = NULL;
7920 * Allocate a 'adv_sgblk_t' structure from the board free
7921 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7922 * (15) scatter-gather elements.
7924 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
7925 ASC_DBG(1, "no free adv_sgblk_t\n");
7926 ASC_STATS(scp->device->host, adv_build_nosg);
7929 * Allocation failed. Free 'adv_sgblk_t' structures
7930 * already allocated for the request.
7932 while ((sgblkp = reqp->sgblkp) != NULL) {
7933 /* Remove 'sgblkp' from the request list. */
7934 reqp->sgblkp = sgblkp->next_sgblkp;
7936 /* Add 'sgblkp' to the board free list. */
7937 sgblkp->next_sgblkp = boardp->adv_sgblkp;
7938 boardp->adv_sgblkp = sgblkp;
7943 /* Complete 'adv_sgblk_t' board allocation. */
7944 boardp->adv_sgblkp = sgblkp->next_sgblkp;
7945 sgblkp->next_sgblkp = NULL;
7948 * Get 8 byte aligned virtual and physical addresses
7949 * for the allocated ADV_SG_BLOCK structure.
7951 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
7952 sg_block_paddr = virt_to_bus(sg_block);
7955 * Check if this is the first 'adv_sgblk_t' for the
7958 if (reqp->sgblkp == NULL) {
7959 /* Request's first scatter-gather block. */
7960 reqp->sgblkp = sgblkp;
7963 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7966 scsiqp->sg_list_ptr = sg_block;
7967 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
7969 /* Request's second or later scatter-gather block. */
7970 sgblkp->next_sgblkp = reqp->sgblkp;
7971 reqp->sgblkp = sgblkp;
7974 * Point the previous ADV_SG_BLOCK structure to
7975 * the newly allocated ADV_SG_BLOCK structure.
7977 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
7980 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7981 sg_block->sg_list[i].sg_addr =
7982 cpu_to_le32(sg_dma_address(slp));
7983 sg_block->sg_list[i].sg_count =
7984 cpu_to_le32(sg_dma_len(slp));
7985 ASC_STATS_ADD(scp->device->host, xfer_sect,
7986 DIV_ROUND_UP(sg_dma_len(slp), 512));
7988 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
7989 sg_block->sg_cnt = i + 1;
7990 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7995 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7996 prev_sg_block = sg_block;
8001 * Build a request structure for the Adv Library (Wide Board).
8003 * If an adv_req_t can not be allocated to issue the request,
8004 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
8006 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
8007 * microcode for DMA addresses or math operations are byte swapped
8008 * to little-endian order.
8011 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
8012 adv_req_t **adv_reqpp)
8014 u32 srb_tag = scp->request->tag;
8016 ADV_SCSI_REQ_Q *scsiqp;
8019 dma_addr_t sense_addr;
8022 * Allocate an adv_req_t structure from the board to execute
8025 reqp = &boardp->adv_reqp[srb_tag];
8026 if (reqp->cmndp && reqp->cmndp != scp ) {
8027 ASC_DBG(1, "no free adv_req_t\n");
8028 ASC_STATS(scp->device->host, adv_build_noreq);
8032 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
8034 scsiqp = &reqp->scsi_req_q;
8037 * Initialize the structure.
8039 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
8042 * Set the srb_tag to the command tag.
8044 scsiqp->srb_tag = srb_tag;
8047 * Set 'host_scribble' to point to the adv_req_t structure.
8050 scp->host_scribble = (void *)reqp;
8053 * Build the ADV_SCSI_REQ_Q request.
8056 /* Set CDB length and copy it to the request structure. */
8057 scsiqp->cdb_len = scp->cmd_len;
8058 /* Copy first 12 CDB bytes to cdb[]. */
8059 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
8060 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8061 if (scp->cmd_len > 12) {
8062 int cdb16_len = scp->cmd_len - 12;
8064 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
8067 scsiqp->target_id = scp->device->id;
8068 scsiqp->target_lun = scp->device->lun;
8070 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
8071 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
8072 scsiqp->sense_addr = cpu_to_le32(sense_addr);
8073 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
8075 /* Build ADV_SCSI_REQ_Q */
8077 use_sg = scsi_dma_map(scp);
8079 /* Zero-length transfer */
8080 reqp->sgblkp = NULL;
8081 scsiqp->data_cnt = 0;
8083 scsiqp->data_addr = 0;
8084 scsiqp->sg_list_ptr = NULL;
8085 scsiqp->sg_real_addr = 0;
8087 if (use_sg > ADV_MAX_SG_LIST) {
8088 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8089 "ADV_MAX_SG_LIST %d\n", use_sg,
8090 scp->device->host->sg_tablesize);
8091 scsi_dma_unmap(scp);
8092 scp->result = HOST_BYTE(DID_ERROR);
8094 scp->host_scribble = NULL;
8099 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8101 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
8102 if (ret != ADV_SUCCESS) {
8103 scsi_dma_unmap(scp);
8104 scp->result = HOST_BYTE(DID_ERROR);
8106 scp->host_scribble = NULL;
8111 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
8114 ASC_STATS(scp->device->host, xfer_cnt);
8116 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8117 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8124 static int AscSgListToQueue(int sg_list)
8128 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8129 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8131 return n_sg_list_qs + 1;
8135 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8139 ASC_SCSI_BIT_ID_TYPE target_id;
8142 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8143 tid_no = ASC_TIX_TO_TID(target_ix);
8144 if ((asc_dvc->unit_not_ready & target_id) ||
8145 (asc_dvc->queue_full_or_busy & target_id)) {
8149 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8150 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8152 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8153 (uint) ASC_MIN_FREE_Q;
8155 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8156 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8157 if (asc_dvc->cur_dvc_qng[tid_no] >=
8158 asc_dvc->max_dvc_qng[tid_no]) {
8164 if ((n_qs > asc_dvc->last_q_shortage)
8165 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8166 asc_dvc->last_q_shortage = n_qs;
8172 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8178 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8179 q_status = (uchar)AscReadLramByte(iop_base,
8181 ASC_SCSIQ_B_STATUS));
8182 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8183 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8185 return ASC_QLINK_END;
8189 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8193 for (i = 0; i < n_free_q; i++) {
8194 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8195 if (free_q_head == ASC_QLINK_END)
8203 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8205 * Calling/Exit State:
8209 * Output an ASC_SCSI_Q structure to the chip
8212 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8216 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8217 AscSetChipLramAddr(iop_base, s_addr);
8218 for (i = 0; i < 2 * words; i += 2) {
8219 if (i == 4 || i == 20) {
8222 outpw(iop_base + IOP_RAM_DATA,
8223 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
8227 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8232 uchar syn_period_ix;
8236 iop_base = asc_dvc->iop_base;
8237 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8238 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8239 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8240 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8242 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8243 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8244 AscMsgOutSDTR(asc_dvc,
8245 asc_dvc->sdtr_period_tbl[syn_period_ix],
8247 scsiq->q1.cntl |= QC_MSG_OUT;
8249 q_addr = ASC_QNO_TO_QADDR(q_no);
8250 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
8251 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8253 scsiq->q1.status = QS_FREE;
8254 AscMemWordCopyPtrToLram(iop_base,
8255 q_addr + ASC_SCSIQ_CDB_BEG,
8256 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8258 DvcPutScsiQ(iop_base,
8259 q_addr + ASC_SCSIQ_CPY_BEG,
8260 (uchar *)&scsiq->q1.cntl,
8261 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8262 AscWriteLramWord(iop_base,
8263 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8264 (ushort)(((ushort)scsiq->q1.
8265 q_no << 8) | (ushort)QS_READY));
8270 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8274 ASC_SG_HEAD *sg_head;
8275 ASC_SG_LIST_Q scsi_sg_q;
8276 ASC_DCNT saved_data_addr;
8277 ASC_DCNT saved_data_cnt;
8279 ushort sg_list_dwords;
8281 ushort sg_entry_cnt;
8285 iop_base = asc_dvc->iop_base;
8286 sg_head = scsiq->sg_head;
8287 saved_data_addr = scsiq->q1.data_addr;
8288 saved_data_cnt = scsiq->q1.data_cnt;
8289 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
8290 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
8291 #if CC_VERY_LONG_SG_LIST
8293 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8294 * then not all SG elements will fit in the allocated queues.
8295 * The rest of the SG elements will be copied when the RISC
8296 * completes the SG elements that fit and halts.
8298 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8300 * Set sg_entry_cnt to be the number of SG elements that
8301 * will fit in the allocated SG queues. It is minus 1, because
8302 * the first SG element is handled above. ASC_MAX_SG_LIST is
8303 * already inflated by 1 to account for this. For example it
8304 * may be 50 which is 1 + 7 queues * 7 SG elements.
8306 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8309 * Keep track of remaining number of SG elements that will
8310 * need to be handled from a_isr.c.
8312 scsiq->remain_sg_entry_cnt =
8313 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8315 #endif /* CC_VERY_LONG_SG_LIST */
8317 * Set sg_entry_cnt to be the number of SG elements that
8318 * will fit in the allocated SG queues. It is minus 1, because
8319 * the first SG element is handled above.
8321 sg_entry_cnt = sg_head->entry_cnt - 1;
8322 #if CC_VERY_LONG_SG_LIST
8324 #endif /* CC_VERY_LONG_SG_LIST */
8325 if (sg_entry_cnt != 0) {
8326 scsiq->q1.cntl |= QC_SG_HEAD;
8327 q_addr = ASC_QNO_TO_QADDR(q_no);
8329 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8330 scsi_sg_q.sg_head_qp = q_no;
8331 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8332 for (i = 0; i < sg_head->queue_cnt; i++) {
8333 scsi_sg_q.seq_no = i + 1;
8334 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8335 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8336 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8338 scsi_sg_q.sg_list_cnt =
8340 scsi_sg_q.sg_cur_list_cnt =
8343 scsi_sg_q.sg_list_cnt =
8344 ASC_SG_LIST_PER_Q - 1;
8345 scsi_sg_q.sg_cur_list_cnt =
8346 ASC_SG_LIST_PER_Q - 1;
8349 #if CC_VERY_LONG_SG_LIST
8351 * This is the last SG queue in the list of
8352 * allocated SG queues. If there are more
8353 * SG elements than will fit in the allocated
8354 * queues, then set the QCSG_SG_XFER_MORE flag.
8356 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8357 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8359 #endif /* CC_VERY_LONG_SG_LIST */
8360 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8361 #if CC_VERY_LONG_SG_LIST
8363 #endif /* CC_VERY_LONG_SG_LIST */
8364 sg_list_dwords = sg_entry_cnt << 1;
8366 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8367 scsi_sg_q.sg_cur_list_cnt =
8370 scsi_sg_q.sg_list_cnt =
8372 scsi_sg_q.sg_cur_list_cnt =
8377 next_qp = AscReadLramByte(iop_base,
8380 scsi_sg_q.q_no = next_qp;
8381 q_addr = ASC_QNO_TO_QADDR(next_qp);
8382 AscMemWordCopyPtrToLram(iop_base,
8383 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8384 (uchar *)&scsi_sg_q,
8385 sizeof(ASC_SG_LIST_Q) >> 1);
8386 AscMemDWordCopyPtrToLram(iop_base,
8387 q_addr + ASC_SGQ_LIST_BEG,
8391 sg_index += ASC_SG_LIST_PER_Q;
8392 scsiq->next_sg_index = sg_index;
8395 scsiq->q1.cntl &= ~QC_SG_HEAD;
8397 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8398 scsiq->q1.data_addr = saved_data_addr;
8399 scsiq->q1.data_cnt = saved_data_cnt;
8404 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8413 iop_base = asc_dvc->iop_base;
8414 target_ix = scsiq->q2.target_ix;
8415 tid_no = ASC_TIX_TO_TID(target_ix);
8417 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8418 if (n_q_required > 1) {
8419 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8420 (uchar)n_q_required);
8421 if (next_qp != ASC_QLINK_END) {
8422 asc_dvc->last_q_shortage = 0;
8423 scsiq->sg_head->queue_cnt = n_q_required - 1;
8424 scsiq->q1.q_no = free_q_head;
8425 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8428 } else if (n_q_required == 1) {
8429 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8430 if (next_qp != ASC_QLINK_END) {
8431 scsiq->q1.q_no = free_q_head;
8432 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8436 AscPutVarFreeQHead(iop_base, next_qp);
8437 asc_dvc->cur_total_qng += n_q_required;
8438 asc_dvc->cur_dvc_qng[tid_no]++;
8443 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8444 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8463 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8468 int disable_syn_offset_one_fix;
8471 ushort sg_entry_cnt = 0;
8472 ushort sg_entry_cnt_minus_one = 0;
8479 ASC_SG_HEAD *sg_head;
8482 iop_base = asc_dvc->iop_base;
8483 sg_head = scsiq->sg_head;
8484 if (asc_dvc->err_code != 0)
8487 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8488 scsiq->q1.extra_bytes = 0;
8491 target_ix = scsiq->q2.target_ix;
8492 tid_no = ASC_TIX_TO_TID(target_ix);
8494 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8495 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8496 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8497 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8498 AscMsgOutSDTR(asc_dvc,
8500 sdtr_period_tbl[(sdtr_data >> 4) &
8504 (uchar)(sdtr_data & (uchar)
8505 ASC_SYN_MAX_OFFSET));
8506 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8509 if (asc_dvc->in_critical_cnt != 0) {
8510 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8513 asc_dvc->in_critical_cnt++;
8514 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8515 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8516 asc_dvc->in_critical_cnt--;
8519 #if !CC_VERY_LONG_SG_LIST
8520 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8521 asc_dvc->in_critical_cnt--;
8524 #endif /* !CC_VERY_LONG_SG_LIST */
8525 if (sg_entry_cnt == 1) {
8526 scsiq->q1.data_addr =
8527 (ADV_PADDR)sg_head->sg_list[0].addr;
8528 scsiq->q1.data_cnt =
8529 (ADV_DCNT)sg_head->sg_list[0].bytes;
8530 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8532 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8534 scsi_cmd = scsiq->cdbptr[0];
8535 disable_syn_offset_one_fix = FALSE;
8536 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8537 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8538 if (scsiq->q1.cntl & QC_SG_HEAD) {
8540 for (i = 0; i < sg_entry_cnt; i++) {
8542 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
8546 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8548 if (data_cnt != 0UL) {
8549 if (data_cnt < 512UL) {
8550 disable_syn_offset_one_fix = TRUE;
8552 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8555 _syn_offset_one_disable_cmd[i];
8556 if (disable_cmd == 0xFF) {
8559 if (scsi_cmd == disable_cmd) {
8560 disable_syn_offset_one_fix =
8568 if (disable_syn_offset_one_fix) {
8569 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8570 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8571 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8573 scsiq->q2.tag_code &= 0x27;
8575 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8576 if (asc_dvc->bug_fix_cntl) {
8577 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8578 if ((scsi_cmd == READ_6) ||
8579 (scsi_cmd == READ_10)) {
8581 (ADV_PADDR)le32_to_cpu(sg_head->
8583 [sg_entry_cnt_minus_one].
8585 (ADV_DCNT)le32_to_cpu(sg_head->
8587 [sg_entry_cnt_minus_one].
8590 (uchar)((ushort)addr & 0x0003);
8591 if ((extra_bytes != 0)
8595 ASC_TAG_FLAG_EXTRA_BYTES)
8597 scsiq->q2.tag_code |=
8598 ASC_TAG_FLAG_EXTRA_BYTES;
8599 scsiq->q1.extra_bytes =
8602 le32_to_cpu(sg_head->
8604 [sg_entry_cnt_minus_one].
8607 (ASC_DCNT) extra_bytes;
8610 [sg_entry_cnt_minus_one].
8612 cpu_to_le32(data_cnt);
8617 sg_head->entry_to_copy = sg_head->entry_cnt;
8618 #if CC_VERY_LONG_SG_LIST
8620 * Set the sg_entry_cnt to the maximum possible. The rest of
8621 * the SG elements will be copied when the RISC completes the
8622 * SG elements that fit and halts.
8624 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8625 sg_entry_cnt = ASC_MAX_SG_LIST;
8627 #endif /* CC_VERY_LONG_SG_LIST */
8628 n_q_required = AscSgListToQueue(sg_entry_cnt);
8629 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8630 (uint) n_q_required)
8631 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8633 AscSendScsiQueue(asc_dvc, scsiq,
8634 n_q_required)) == 1) {
8635 asc_dvc->in_critical_cnt--;
8640 if (asc_dvc->bug_fix_cntl) {
8641 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8642 if ((scsi_cmd == READ_6) ||
8643 (scsi_cmd == READ_10)) {
8645 le32_to_cpu(scsiq->q1.data_addr) +
8646 le32_to_cpu(scsiq->q1.data_cnt);
8648 (uchar)((ushort)addr & 0x0003);
8649 if ((extra_bytes != 0)
8653 ASC_TAG_FLAG_EXTRA_BYTES)
8656 le32_to_cpu(scsiq->q1.
8658 if (((ushort)data_cnt & 0x01FF)
8660 scsiq->q2.tag_code |=
8661 ASC_TAG_FLAG_EXTRA_BYTES;
8662 data_cnt -= (ASC_DCNT)
8664 scsiq->q1.data_cnt =
8667 scsiq->q1.extra_bytes =
8675 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8676 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8677 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8678 n_q_required)) == 1) {
8679 asc_dvc->in_critical_cnt--;
8684 asc_dvc->in_critical_cnt--;
8689 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8691 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8692 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8693 * RISC to notify it a new command is ready to be executed.
8695 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8696 * set to SCSI_MAX_RETRY.
8698 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8699 * for DMA addresses or math operations are byte swapped to little-endian
8703 * ADV_SUCCESS(1) - The request was successfully queued.
8704 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8705 * request completes.
8706 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8709 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
8711 AdvPortAddr iop_base;
8712 ADV_CARR_T *new_carrp;
8713 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
8716 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8718 if (scsiq->target_id > ADV_MAX_TID) {
8719 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8720 scsiq->done_status = QD_WITH_ERROR;
8724 iop_base = asc_dvc->iop_base;
8727 * Allocate a carrier ensuring at least one carrier always
8728 * remains on the freelist and initialize fields.
8730 new_carrp = adv_get_next_carrier(asc_dvc);
8732 ASC_DBG(1, "No free carriers\n");
8736 asc_dvc->carr_pending_cnt++;
8739 * Clear the ADV_SCSI_REQ_Q done flag.
8741 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
8743 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8744 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8745 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
8747 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
8748 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8751 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8752 * the microcode. The newly allocated stopper will become the new
8755 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
8758 * Set the 'next_vpa' pointer for the old stopper to be the
8759 * physical address of the new stopper. The RISC can only
8760 * follow physical addresses.
8762 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8765 * Set the host adapter stopper pointer to point to the new carrier.
8767 asc_dvc->icq_sp = new_carrp;
8769 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8770 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8772 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8774 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8775 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8777 * Clear the tickle value. In the ASC-3550 the RISC flag
8778 * command 'clr_tickle_a' does not work unless the host
8781 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8784 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8786 * Notify the RISC a carrier is ready by writing the physical
8787 * address of the new carrier stopper to the COMMA register.
8789 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8790 le32_to_cpu(new_carrp->carr_pa));
8797 * Execute a single 'Scsi_Cmnd'.
8799 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8802 struct asc_board *boardp = shost_priv(scp->device->host);
8804 ASC_DBG(1, "scp 0x%p\n", scp);
8806 if (ASC_NARROW_BOARD(boardp)) {
8807 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8808 struct asc_scsi_q asc_scsi_q;
8810 /* asc_build_req() can not return ASC_BUSY. */
8811 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8812 if (ret == ASC_ERROR) {
8813 ASC_STATS(scp->device->host, build_error);
8817 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8818 kfree(asc_scsi_q.sg_head);
8819 err_code = asc_dvc->err_code;
8821 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8822 adv_req_t *adv_reqp;
8824 switch (adv_build_req(boardp, scp, &adv_reqp)) {
8826 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8829 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8831 * The asc_stats fields 'adv_build_noreq' and
8832 * 'adv_build_nosg' count wide board busy conditions.
8833 * They are updated in adv_build_req and
8834 * adv_get_sglist, respectively.
8839 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8840 ASC_STATS(scp->device->host, build_error);
8844 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
8845 err_code = adv_dvc->err_code;
8850 ASC_STATS(scp->device->host, exe_noerror);
8852 * Increment monotonically increasing per device
8853 * successful request counter. Wrapping doesn't matter.
8855 boardp->reqcnt[scp->device->id]++;
8856 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8859 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
8860 ASC_STATS(scp->device->host, exe_busy);
8863 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8864 "err_code 0x%x\n", err_code);
8865 ASC_STATS(scp->device->host, exe_error);
8866 scp->result = HOST_BYTE(DID_ERROR);
8869 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8870 "err_code 0x%x\n", err_code);
8871 ASC_STATS(scp->device->host, exe_unknown);
8872 scp->result = HOST_BYTE(DID_ERROR);
8876 ASC_DBG(1, "end\n");
8881 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8883 * This function always returns 0. Command return status is saved
8884 * in the 'scp' result field.
8887 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
8889 struct Scsi_Host *shost = scp->device->host;
8890 int asc_res, result = 0;
8892 ASC_STATS(shost, queuecommand);
8893 scp->scsi_done = done;
8895 asc_res = asc_execute_scsi_cmnd(scp);
8901 result = SCSI_MLQUEUE_HOST_BUSY;
8912 static DEF_SCSI_QCMD(advansys_queuecommand)
8914 static ushort AscGetEisaChipCfg(PortAddr iop_base)
8916 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8917 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8918 return inpw(eisa_cfg_iop);
8922 * Return the BIOS address of the adapter at the specified
8923 * I/O port and with the specified bus type.
8925 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8926 unsigned short bus_type)
8928 unsigned short cfg_lsw;
8929 unsigned short bios_addr;
8932 * The PCI BIOS is re-located by the motherboard BIOS. Because
8933 * of this the driver can not determine where a PCI BIOS is
8934 * loaded and executes.
8936 if (bus_type & ASC_IS_PCI)
8939 if ((bus_type & ASC_IS_EISA) != 0) {
8940 cfg_lsw = AscGetEisaChipCfg(iop_base);
8942 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8946 cfg_lsw = AscGetChipCfgLsw(iop_base);
8949 * ISA PnP uses the top bit as the 32K BIOS flag
8951 if (bus_type == ASC_IS_ISAPNP)
8953 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8957 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8961 if (AscGetChipScsiID(iop_base) == new_host_id) {
8962 return (new_host_id);
8964 cfg_lsw = AscGetChipCfgLsw(iop_base);
8966 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8967 AscSetChipCfgLsw(iop_base, cfg_lsw);
8968 return (AscGetChipScsiID(iop_base));
8971 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
8975 AscSetBank(iop_base, 1);
8976 sc = inp(iop_base + IOP_REG_SC);
8977 AscSetBank(iop_base, 0);
8981 static unsigned char AscGetChipVersion(PortAddr iop_base,
8982 unsigned short bus_type)
8984 if (bus_type & ASC_IS_EISA) {
8986 unsigned char revision;
8987 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8988 (PortAddr) ASC_EISA_REV_IOP_MASK;
8989 revision = inp(eisa_iop);
8990 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
8992 return AscGetChipVerNo(iop_base);
8996 static void AscEnableIsaDma(uchar dma_channel)
8998 if (dma_channel < 4) {
8999 outp(0x000B, (ushort)(0xC0 | dma_channel));
9000 outp(0x000A, dma_channel);
9001 } else if (dma_channel < 8) {
9002 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
9003 outp(0x00D4, (ushort)(dma_channel - 4));
9006 #endif /* CONFIG_ISA */
9008 static int AscStopQueueExe(PortAddr iop_base)
9012 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
9013 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9014 ASC_STOP_REQ_RISC_STOP);
9016 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
9017 ASC_STOP_ACK_RISC_STOP) {
9021 } while (count++ < 20);
9026 static ASC_DCNT AscGetMaxDmaCount(ushort bus_type)
9028 if (bus_type & ASC_IS_ISA)
9029 return ASC_MAX_ISA_DMA_COUNT;
9030 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
9031 return ASC_MAX_VL_DMA_COUNT;
9032 return ASC_MAX_PCI_DMA_COUNT;
9036 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
9040 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
9041 if (channel == 0x03)
9043 else if (channel == 0x00)
9045 return (channel + 4);
9048 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
9053 if ((dma_channel >= 5) && (dma_channel <= 7)) {
9054 if (dma_channel == 7)
9057 value = dma_channel - 4;
9058 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9060 AscSetChipCfgLsw(iop_base, cfg_lsw);
9061 return (AscGetIsaDmaChannel(iop_base));
9066 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
9070 AscSetBank(iop_base, 1);
9071 speed_value = AscReadChipDmaSpeed(iop_base);
9072 speed_value &= 0x07;
9073 AscSetBank(iop_base, 0);
9077 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
9079 speed_value &= 0x07;
9080 AscSetBank(iop_base, 1);
9081 AscWriteChipDmaSpeed(iop_base, speed_value);
9082 AscSetBank(iop_base, 0);
9083 return AscGetIsaDmaSpeed(iop_base);
9085 #endif /* CONFIG_ISA */
9087 static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
9094 iop_base = asc_dvc->iop_base;
9096 asc_dvc->err_code = 0;
9097 if ((asc_dvc->bus_type &
9098 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9099 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
9101 AscSetChipControl(iop_base, CC_HALT);
9102 AscSetChipStatus(iop_base, 0);
9103 asc_dvc->bug_fix_cntl = 0;
9104 asc_dvc->pci_fix_asyn_xfer = 0;
9105 asc_dvc->pci_fix_asyn_xfer_always = 0;
9106 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
9107 asc_dvc->sdtr_done = 0;
9108 asc_dvc->cur_total_qng = 0;
9109 asc_dvc->is_in_int = 0;
9110 asc_dvc->in_critical_cnt = 0;
9111 asc_dvc->last_q_shortage = 0;
9112 asc_dvc->use_tagged_qng = 0;
9113 asc_dvc->no_scam = 0;
9114 asc_dvc->unit_not_ready = 0;
9115 asc_dvc->queue_full_or_busy = 0;
9116 asc_dvc->redo_scam = 0;
9118 asc_dvc->min_sdtr_index = 0;
9119 asc_dvc->cfg->can_tagged_qng = 0;
9120 asc_dvc->cfg->cmd_qng_enabled = 0;
9121 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9122 asc_dvc->init_sdtr = 0;
9123 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9124 asc_dvc->scsi_reset_wait = 3;
9125 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9126 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9127 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9128 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9129 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
9130 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9131 asc_dvc->cfg->chip_version = chip_version;
9132 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
9133 asc_dvc->max_sdtr_index = 7;
9134 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9135 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9136 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
9137 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
9138 asc_dvc->max_sdtr_index = 15;
9139 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9140 AscSetExtraControl(iop_base,
9141 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9142 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9143 AscSetExtraControl(iop_base,
9144 (SEC_ACTIVE_NEGATE |
9145 SEC_ENABLE_FILTER));
9148 if (asc_dvc->bus_type == ASC_IS_PCI) {
9149 AscSetExtraControl(iop_base,
9150 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9153 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9155 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9156 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9157 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9158 asc_dvc->bus_type = ASC_IS_ISAPNP;
9160 asc_dvc->cfg->isa_dma_channel =
9161 (uchar)AscGetIsaDmaChannel(iop_base);
9163 #endif /* CONFIG_ISA */
9164 for (i = 0; i <= ASC_MAX_TID; i++) {
9165 asc_dvc->cur_dvc_qng[i] = 0;
9166 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9167 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9168 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9169 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
9174 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9178 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9179 unsigned char read_back;
9180 AscSetChipEEPCmd(iop_base, cmd_reg);
9182 read_back = AscGetChipEEPCmd(iop_base);
9183 if (read_back == cmd_reg)
9189 static void AscWaitEEPRead(void)
9194 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
9199 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9201 cmd_reg = addr | ASC_EEP_CMD_READ;
9202 AscWriteEEPCmdReg(iop_base, cmd_reg);
9204 read_wval = AscGetChipEEPData(iop_base);
9209 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9217 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9220 wbuf = (ushort *)cfg_buf;
9222 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9223 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9224 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9227 if (bus_type & ASC_IS_VL) {
9228 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9229 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9231 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9232 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9234 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9235 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9236 if (s_addr <= uchar_end_in_config) {
9238 * Swap all char fields - must unswap bytes already swapped
9239 * by AscReadEEPWord().
9241 *wbuf = le16_to_cpu(wval);
9243 /* Don't swap word field at the end - cntl field. */
9246 sum += wval; /* Checksum treats all EEPROM data as words. */
9249 * Read the checksum word which will be compared against 'sum'
9250 * by the caller. Word field already swapped.
9252 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9256 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
9263 iop_base = asc_dvc->iop_base;
9265 q_addr = ASC_QNO_TO_QADDR(241);
9266 saved_word = AscReadLramWord(iop_base, q_addr);
9267 AscSetChipLramAddr(iop_base, q_addr);
9268 AscSetChipLramData(iop_base, 0x55AA);
9270 AscSetChipLramAddr(iop_base, q_addr);
9271 if (AscGetChipLramData(iop_base) == 0x55AA) {
9273 AscWriteLramWord(iop_base, q_addr, saved_word);
9278 static void AscWaitEEPWrite(void)
9283 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9290 AscSetChipEEPData(iop_base, data_reg);
9292 read_back = AscGetChipEEPData(iop_base);
9293 if (read_back == data_reg) {
9296 if (retry++ > ASC_EEP_MAX_RETRY) {
9302 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9306 read_wval = AscReadEEPWord(iop_base, addr);
9307 if (read_wval != word_val) {
9308 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9310 AscWriteEEPDataReg(iop_base, word_val);
9312 AscWriteEEPCmdReg(iop_base,
9313 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9315 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9317 return (AscReadEEPWord(iop_base, addr));
9322 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9332 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9334 wbuf = (ushort *)cfg_buf;
9337 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9338 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9340 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9344 if (bus_type & ASC_IS_VL) {
9345 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9346 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9348 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9349 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9351 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9352 if (s_addr <= uchar_end_in_config) {
9354 * This is a char field. Swap char fields before they are
9355 * swapped again by AscWriteEEPWord().
9357 word = cpu_to_le16(*wbuf);
9359 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9363 /* Don't swap word field at the end - cntl field. */
9365 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9369 sum += *wbuf; /* Checksum calculated from word values. */
9371 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9373 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9377 /* Read EEPROM back again. */
9378 wbuf = (ushort *)cfg_buf;
9380 * Read two config words; Byte-swapping done by AscReadEEPWord().
9382 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9383 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9387 if (bus_type & ASC_IS_VL) {
9388 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9389 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9391 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9392 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9394 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9395 if (s_addr <= uchar_end_in_config) {
9397 * Swap all char fields. Must unswap bytes already swapped
9398 * by AscReadEEPWord().
9401 le16_to_cpu(AscReadEEPWord
9402 (iop_base, (uchar)s_addr));
9404 /* Don't swap word field at the end - cntl field. */
9405 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9407 if (*wbuf != word) {
9411 /* Read checksum; Byte swapping not needed. */
9412 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9418 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9426 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9430 if (++retry > ASC_EEP_MAX_RETRY) {
9437 static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9439 ASCEEP_CONFIG eep_config_buf;
9440 ASCEEP_CONFIG *eep_config;
9444 ushort cfg_msw, cfg_lsw;
9448 iop_base = asc_dvc->iop_base;
9450 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9451 AscStopQueueExe(iop_base);
9452 if ((AscStopChip(iop_base) == FALSE) ||
9453 (AscGetChipScsiCtrl(iop_base) != 0)) {
9454 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9455 AscResetChipAndScsiBus(asc_dvc);
9456 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9458 if (AscIsChipHalted(iop_base) == FALSE) {
9459 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9462 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9463 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9464 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9467 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9468 cfg_msw = AscGetChipCfgMsw(iop_base);
9469 cfg_lsw = AscGetChipCfgLsw(iop_base);
9470 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9471 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9472 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9473 AscSetChipCfgMsw(iop_base, cfg_msw);
9475 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9476 ASC_DBG(1, "chksum 0x%x\n", chksum);
9480 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9481 warn_code |= ASC_WARN_AUTO_CONFIG;
9482 if (asc_dvc->cfg->chip_version == 3) {
9483 if (eep_config->cfg_lsw != cfg_lsw) {
9484 warn_code |= ASC_WARN_EEPROM_RECOVER;
9485 eep_config->cfg_lsw =
9486 AscGetChipCfgLsw(iop_base);
9488 if (eep_config->cfg_msw != cfg_msw) {
9489 warn_code |= ASC_WARN_EEPROM_RECOVER;
9490 eep_config->cfg_msw =
9491 AscGetChipCfgMsw(iop_base);
9495 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9496 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9497 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9498 if (chksum != eep_config->chksum) {
9499 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9500 ASC_CHIP_VER_PCI_ULTRA_3050) {
9501 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9502 eep_config->init_sdtr = 0xFF;
9503 eep_config->disc_enable = 0xFF;
9504 eep_config->start_motor = 0xFF;
9505 eep_config->use_cmd_qng = 0;
9506 eep_config->max_total_qng = 0xF0;
9507 eep_config->max_tag_qng = 0x20;
9508 eep_config->cntl = 0xBFFF;
9509 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9510 eep_config->no_scam = 0;
9511 eep_config->adapter_info[0] = 0;
9512 eep_config->adapter_info[1] = 0;
9513 eep_config->adapter_info[2] = 0;
9514 eep_config->adapter_info[3] = 0;
9515 eep_config->adapter_info[4] = 0;
9516 /* Indicate EEPROM-less board. */
9517 eep_config->adapter_info[5] = 0xBB;
9520 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9522 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9525 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9526 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9527 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9528 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9529 asc_dvc->start_motor = eep_config->start_motor;
9530 asc_dvc->dvc_cntl = eep_config->cntl;
9531 asc_dvc->no_scam = eep_config->no_scam;
9532 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9533 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9534 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9535 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9536 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9537 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9538 if (!AscTestExternalLram(asc_dvc)) {
9539 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9540 ASC_IS_PCI_ULTRA)) {
9541 eep_config->max_total_qng =
9542 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9543 eep_config->max_tag_qng =
9544 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9546 eep_config->cfg_msw |= 0x0800;
9548 AscSetChipCfgMsw(iop_base, cfg_msw);
9549 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9550 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9554 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9555 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9557 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9558 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9560 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9561 eep_config->max_tag_qng = eep_config->max_total_qng;
9563 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9564 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9566 asc_dvc->max_total_qng = eep_config->max_total_qng;
9567 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9568 eep_config->use_cmd_qng) {
9569 eep_config->disc_enable = eep_config->use_cmd_qng;
9570 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9572 ASC_EEP_SET_CHIP_ID(eep_config,
9573 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9574 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9575 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9576 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9577 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9580 for (i = 0; i <= ASC_MAX_TID; i++) {
9581 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9582 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9583 asc_dvc->cfg->sdtr_period_offset[i] =
9584 (uchar)(ASC_DEF_SDTR_OFFSET |
9585 (asc_dvc->min_sdtr_index << 4));
9587 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9589 if ((i = AscSetEEPConfig(iop_base, eep_config,
9590 asc_dvc->bus_type)) != 0) {
9592 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9596 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9602 static int AscInitGetConfig(struct Scsi_Host *shost)
9604 struct asc_board *board = shost_priv(shost);
9605 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9606 unsigned short warn_code = 0;
9608 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9609 if (asc_dvc->err_code != 0)
9610 return asc_dvc->err_code;
9612 if (AscFindSignature(asc_dvc->iop_base)) {
9613 warn_code |= AscInitAscDvcVar(asc_dvc);
9614 warn_code |= AscInitFromEEP(asc_dvc);
9615 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9616 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9617 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9619 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9622 switch (warn_code) {
9623 case 0: /* No error */
9625 case ASC_WARN_IO_PORT_ROTATE:
9626 shost_printk(KERN_WARNING, shost, "I/O port address "
9629 case ASC_WARN_AUTO_CONFIG:
9630 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9633 case ASC_WARN_EEPROM_CHKSUM:
9634 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9636 case ASC_WARN_IRQ_MODIFIED:
9637 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9639 case ASC_WARN_CMD_QNG_CONFLICT:
9640 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9644 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9649 if (asc_dvc->err_code != 0)
9650 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9651 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9653 return asc_dvc->err_code;
9656 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9658 struct asc_board *board = shost_priv(shost);
9659 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9660 PortAddr iop_base = asc_dvc->iop_base;
9661 unsigned short cfg_msw;
9662 unsigned short warn_code = 0;
9664 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9665 if (asc_dvc->err_code != 0)
9666 return asc_dvc->err_code;
9667 if (!AscFindSignature(asc_dvc->iop_base)) {
9668 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9669 return asc_dvc->err_code;
9672 cfg_msw = AscGetChipCfgMsw(iop_base);
9673 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9674 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9675 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9676 AscSetChipCfgMsw(iop_base, cfg_msw);
9678 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9679 asc_dvc->cfg->cmd_qng_enabled) {
9680 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9681 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9683 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9684 warn_code |= ASC_WARN_AUTO_CONFIG;
9687 if (asc_dvc->bus_type & ASC_IS_PCI) {
9689 AscSetChipCfgMsw(iop_base, cfg_msw);
9690 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9692 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9693 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9694 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9695 asc_dvc->bug_fix_cntl |=
9696 ASC_BUG_FIX_ASYN_USE_SYN;
9700 #endif /* CONFIG_PCI */
9701 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9702 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9703 == ASC_CHIP_VER_ASYN_BUG) {
9704 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9707 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9708 asc_dvc->cfg->chip_scsi_id) {
9709 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9712 if (asc_dvc->bus_type & ASC_IS_ISA) {
9713 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9714 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9716 #endif /* CONFIG_ISA */
9718 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9720 switch (warn_code) {
9721 case 0: /* No error. */
9723 case ASC_WARN_IO_PORT_ROTATE:
9724 shost_printk(KERN_WARNING, shost, "I/O port address "
9727 case ASC_WARN_AUTO_CONFIG:
9728 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9731 case ASC_WARN_EEPROM_CHKSUM:
9732 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9734 case ASC_WARN_IRQ_MODIFIED:
9735 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9737 case ASC_WARN_CMD_QNG_CONFLICT:
9738 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9742 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9747 if (asc_dvc->err_code != 0)
9748 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9749 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9751 return asc_dvc->err_code;
9755 * EEPROM Configuration.
9757 * All drivers should use this structure to set the default EEPROM
9758 * configuration. The BIOS now uses this structure when it is built.
9759 * Additional structure information can be found in a_condor.h where
9760 * the structure is defined.
9762 * The *_Field_IsChar structs are needed to correct for endianness.
9763 * These values are read from the board 16 bits at a time directly
9764 * into the structs. Because some fields are char, the values will be
9765 * in the wrong order. The *_Field_IsChar tells when to flip the
9766 * bytes. Data read and written to PCI memory is automatically swapped
9767 * on big-endian platforms so char fields read as words are actually being
9768 * unswapped on big-endian platforms.
9770 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9771 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9772 0x0000, /* cfg_msw */
9773 0xFFFF, /* disc_enable */
9774 0xFFFF, /* wdtr_able */
9775 0xFFFF, /* sdtr_able */
9776 0xFFFF, /* start_motor */
9777 0xFFFF, /* tagqng_able */
9778 0xFFFF, /* bios_scan */
9779 0, /* scam_tolerant */
9780 7, /* adapter_scsi_id */
9781 0, /* bios_boot_delay */
9782 3, /* scsi_reset_delay */
9783 0, /* bios_id_lun */
9784 0, /* termination */
9786 0xFFE7, /* bios_ctrl */
9787 0xFFFF, /* ultra_able */
9789 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9790 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9793 0, /* serial_number_word1 */
9794 0, /* serial_number_word2 */
9795 0, /* serial_number_word3 */
9797 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9798 , /* oem_name[16] */
9799 0, /* dvc_err_code */
9800 0, /* adv_err_code */
9801 0, /* adv_err_addr */
9802 0, /* saved_dvc_err_code */
9803 0, /* saved_adv_err_code */
9804 0, /* saved_adv_err_addr */
9808 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9811 0, /* -disc_enable */
9814 0, /* start_motor */
9815 0, /* tagqng_able */
9817 0, /* scam_tolerant */
9818 1, /* adapter_scsi_id */
9819 1, /* bios_boot_delay */
9820 1, /* scsi_reset_delay */
9821 1, /* bios_id_lun */
9822 1, /* termination */
9827 1, /* max_host_qng */
9828 1, /* max_dvc_qng */
9831 0, /* serial_number_word1 */
9832 0, /* serial_number_word2 */
9833 0, /* serial_number_word3 */
9835 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9836 , /* oem_name[16] */
9837 0, /* dvc_err_code */
9838 0, /* adv_err_code */
9839 0, /* adv_err_addr */
9840 0, /* saved_dvc_err_code */
9841 0, /* saved_adv_err_code */
9842 0, /* saved_adv_err_addr */
9846 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9847 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9848 0x0000, /* 01 cfg_msw */
9849 0xFFFF, /* 02 disc_enable */
9850 0xFFFF, /* 03 wdtr_able */
9851 0x4444, /* 04 sdtr_speed1 */
9852 0xFFFF, /* 05 start_motor */
9853 0xFFFF, /* 06 tagqng_able */
9854 0xFFFF, /* 07 bios_scan */
9855 0, /* 08 scam_tolerant */
9856 7, /* 09 adapter_scsi_id */
9857 0, /* bios_boot_delay */
9858 3, /* 10 scsi_reset_delay */
9859 0, /* bios_id_lun */
9860 0, /* 11 termination_se */
9861 0, /* termination_lvd */
9862 0xFFE7, /* 12 bios_ctrl */
9863 0x4444, /* 13 sdtr_speed2 */
9864 0x4444, /* 14 sdtr_speed3 */
9865 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9866 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9867 0, /* 16 dvc_cntl */
9868 0x4444, /* 17 sdtr_speed4 */
9869 0, /* 18 serial_number_word1 */
9870 0, /* 19 serial_number_word2 */
9871 0, /* 20 serial_number_word3 */
9872 0, /* 21 check_sum */
9873 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9874 , /* 22-29 oem_name[16] */
9875 0, /* 30 dvc_err_code */
9876 0, /* 31 adv_err_code */
9877 0, /* 32 adv_err_addr */
9878 0, /* 33 saved_dvc_err_code */
9879 0, /* 34 saved_adv_err_code */
9880 0, /* 35 saved_adv_err_addr */
9881 0, /* 36 reserved */
9882 0, /* 37 reserved */
9883 0, /* 38 reserved */
9884 0, /* 39 reserved */
9885 0, /* 40 reserved */
9886 0, /* 41 reserved */
9887 0, /* 42 reserved */
9888 0, /* 43 reserved */
9889 0, /* 44 reserved */
9890 0, /* 45 reserved */
9891 0, /* 46 reserved */
9892 0, /* 47 reserved */
9893 0, /* 48 reserved */
9894 0, /* 49 reserved */
9895 0, /* 50 reserved */
9896 0, /* 51 reserved */
9897 0, /* 52 reserved */
9898 0, /* 53 reserved */
9899 0, /* 54 reserved */
9900 0, /* 55 reserved */
9901 0, /* 56 cisptr_lsw */
9902 0, /* 57 cisprt_msw */
9903 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9904 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9905 0, /* 60 reserved */
9906 0, /* 61 reserved */
9907 0, /* 62 reserved */
9911 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
9914 0, /* 02 disc_enable */
9915 0, /* 03 wdtr_able */
9916 0, /* 04 sdtr_speed1 */
9917 0, /* 05 start_motor */
9918 0, /* 06 tagqng_able */
9919 0, /* 07 bios_scan */
9920 0, /* 08 scam_tolerant */
9921 1, /* 09 adapter_scsi_id */
9922 1, /* bios_boot_delay */
9923 1, /* 10 scsi_reset_delay */
9924 1, /* bios_id_lun */
9925 1, /* 11 termination_se */
9926 1, /* termination_lvd */
9927 0, /* 12 bios_ctrl */
9928 0, /* 13 sdtr_speed2 */
9929 0, /* 14 sdtr_speed3 */
9930 1, /* 15 max_host_qng */
9931 1, /* max_dvc_qng */
9932 0, /* 16 dvc_cntl */
9933 0, /* 17 sdtr_speed4 */
9934 0, /* 18 serial_number_word1 */
9935 0, /* 19 serial_number_word2 */
9936 0, /* 20 serial_number_word3 */
9937 0, /* 21 check_sum */
9938 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9939 , /* 22-29 oem_name[16] */
9940 0, /* 30 dvc_err_code */
9941 0, /* 31 adv_err_code */
9942 0, /* 32 adv_err_addr */
9943 0, /* 33 saved_dvc_err_code */
9944 0, /* 34 saved_adv_err_code */
9945 0, /* 35 saved_adv_err_addr */
9946 0, /* 36 reserved */
9947 0, /* 37 reserved */
9948 0, /* 38 reserved */
9949 0, /* 39 reserved */
9950 0, /* 40 reserved */
9951 0, /* 41 reserved */
9952 0, /* 42 reserved */
9953 0, /* 43 reserved */
9954 0, /* 44 reserved */
9955 0, /* 45 reserved */
9956 0, /* 46 reserved */
9957 0, /* 47 reserved */
9958 0, /* 48 reserved */
9959 0, /* 49 reserved */
9960 0, /* 50 reserved */
9961 0, /* 51 reserved */
9962 0, /* 52 reserved */
9963 0, /* 53 reserved */
9964 0, /* 54 reserved */
9965 0, /* 55 reserved */
9966 0, /* 56 cisptr_lsw */
9967 0, /* 57 cisprt_msw */
9968 0, /* 58 subsysvid */
9969 0, /* 59 subsysid */
9970 0, /* 60 reserved */
9971 0, /* 61 reserved */
9972 0, /* 62 reserved */
9976 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
9977 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9978 0x0000, /* 01 cfg_msw */
9979 0xFFFF, /* 02 disc_enable */
9980 0xFFFF, /* 03 wdtr_able */
9981 0x5555, /* 04 sdtr_speed1 */
9982 0xFFFF, /* 05 start_motor */
9983 0xFFFF, /* 06 tagqng_able */
9984 0xFFFF, /* 07 bios_scan */
9985 0, /* 08 scam_tolerant */
9986 7, /* 09 adapter_scsi_id */
9987 0, /* bios_boot_delay */
9988 3, /* 10 scsi_reset_delay */
9989 0, /* bios_id_lun */
9990 0, /* 11 termination_se */
9991 0, /* termination_lvd */
9992 0xFFE7, /* 12 bios_ctrl */
9993 0x5555, /* 13 sdtr_speed2 */
9994 0x5555, /* 14 sdtr_speed3 */
9995 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9996 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9997 0, /* 16 dvc_cntl */
9998 0x5555, /* 17 sdtr_speed4 */
9999 0, /* 18 serial_number_word1 */
10000 0, /* 19 serial_number_word2 */
10001 0, /* 20 serial_number_word3 */
10002 0, /* 21 check_sum */
10003 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10004 , /* 22-29 oem_name[16] */
10005 0, /* 30 dvc_err_code */
10006 0, /* 31 adv_err_code */
10007 0, /* 32 adv_err_addr */
10008 0, /* 33 saved_dvc_err_code */
10009 0, /* 34 saved_adv_err_code */
10010 0, /* 35 saved_adv_err_addr */
10011 0, /* 36 reserved */
10012 0, /* 37 reserved */
10013 0, /* 38 reserved */
10014 0, /* 39 reserved */
10015 0, /* 40 reserved */
10016 0, /* 41 reserved */
10017 0, /* 42 reserved */
10018 0, /* 43 reserved */
10019 0, /* 44 reserved */
10020 0, /* 45 reserved */
10021 0, /* 46 reserved */
10022 0, /* 47 reserved */
10023 0, /* 48 reserved */
10024 0, /* 49 reserved */
10025 0, /* 50 reserved */
10026 0, /* 51 reserved */
10027 0, /* 52 reserved */
10028 0, /* 53 reserved */
10029 0, /* 54 reserved */
10030 0, /* 55 reserved */
10031 0, /* 56 cisptr_lsw */
10032 0, /* 57 cisprt_msw */
10033 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
10034 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
10035 0, /* 60 reserved */
10036 0, /* 61 reserved */
10037 0, /* 62 reserved */
10038 0 /* 63 reserved */
10041 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
10042 0, /* 00 cfg_lsw */
10043 0, /* 01 cfg_msw */
10044 0, /* 02 disc_enable */
10045 0, /* 03 wdtr_able */
10046 0, /* 04 sdtr_speed1 */
10047 0, /* 05 start_motor */
10048 0, /* 06 tagqng_able */
10049 0, /* 07 bios_scan */
10050 0, /* 08 scam_tolerant */
10051 1, /* 09 adapter_scsi_id */
10052 1, /* bios_boot_delay */
10053 1, /* 10 scsi_reset_delay */
10054 1, /* bios_id_lun */
10055 1, /* 11 termination_se */
10056 1, /* termination_lvd */
10057 0, /* 12 bios_ctrl */
10058 0, /* 13 sdtr_speed2 */
10059 0, /* 14 sdtr_speed3 */
10060 1, /* 15 max_host_qng */
10061 1, /* max_dvc_qng */
10062 0, /* 16 dvc_cntl */
10063 0, /* 17 sdtr_speed4 */
10064 0, /* 18 serial_number_word1 */
10065 0, /* 19 serial_number_word2 */
10066 0, /* 20 serial_number_word3 */
10067 0, /* 21 check_sum */
10068 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10069 , /* 22-29 oem_name[16] */
10070 0, /* 30 dvc_err_code */
10071 0, /* 31 adv_err_code */
10072 0, /* 32 adv_err_addr */
10073 0, /* 33 saved_dvc_err_code */
10074 0, /* 34 saved_adv_err_code */
10075 0, /* 35 saved_adv_err_addr */
10076 0, /* 36 reserved */
10077 0, /* 37 reserved */
10078 0, /* 38 reserved */
10079 0, /* 39 reserved */
10080 0, /* 40 reserved */
10081 0, /* 41 reserved */
10082 0, /* 42 reserved */
10083 0, /* 43 reserved */
10084 0, /* 44 reserved */
10085 0, /* 45 reserved */
10086 0, /* 46 reserved */
10087 0, /* 47 reserved */
10088 0, /* 48 reserved */
10089 0, /* 49 reserved */
10090 0, /* 50 reserved */
10091 0, /* 51 reserved */
10092 0, /* 52 reserved */
10093 0, /* 53 reserved */
10094 0, /* 54 reserved */
10095 0, /* 55 reserved */
10096 0, /* 56 cisptr_lsw */
10097 0, /* 57 cisprt_msw */
10098 0, /* 58 subsysvid */
10099 0, /* 59 subsysid */
10100 0, /* 60 reserved */
10101 0, /* 61 reserved */
10102 0, /* 62 reserved */
10103 0 /* 63 reserved */
10108 * Wait for EEPROM command to complete
10110 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
10114 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10115 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10116 ASC_EEP_CMD_DONE) {
10121 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10127 * Read the EEPROM from specified location
10129 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
10131 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10132 ASC_EEP_CMD_READ | eep_word_addr);
10133 AdvWaitEEPCmd(iop_base);
10134 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10138 * Write the EEPROM from 'cfg_buf'.
10140 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10141 ADVEEP_3550_CONFIG *cfg_buf)
10144 ushort addr, chksum;
10145 ushort *charfields;
10147 wbuf = (ushort *)cfg_buf;
10148 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10151 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10152 AdvWaitEEPCmd(iop_base);
10155 * Write EEPROM from word 0 to word 20.
10157 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10158 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10161 if (*charfields++) {
10162 word = cpu_to_le16(*wbuf);
10166 chksum += *wbuf; /* Checksum is calculated from word values. */
10167 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10168 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10169 ASC_EEP_CMD_WRITE | addr);
10170 AdvWaitEEPCmd(iop_base);
10171 mdelay(ADV_EEP_DELAY_MS);
10175 * Write EEPROM checksum at word 21.
10177 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10178 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10179 AdvWaitEEPCmd(iop_base);
10184 * Write EEPROM OEM name at words 22 to 29.
10186 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10187 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10190 if (*charfields++) {
10191 word = cpu_to_le16(*wbuf);
10195 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10196 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10197 ASC_EEP_CMD_WRITE | addr);
10198 AdvWaitEEPCmd(iop_base);
10200 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10201 AdvWaitEEPCmd(iop_base);
10205 * Write the EEPROM from 'cfg_buf'.
10207 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10208 ADVEEP_38C0800_CONFIG *cfg_buf)
10211 ushort *charfields;
10212 ushort addr, chksum;
10214 wbuf = (ushort *)cfg_buf;
10215 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10218 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10219 AdvWaitEEPCmd(iop_base);
10222 * Write EEPROM from word 0 to word 20.
10224 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10225 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10228 if (*charfields++) {
10229 word = cpu_to_le16(*wbuf);
10233 chksum += *wbuf; /* Checksum is calculated from word values. */
10234 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10235 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10236 ASC_EEP_CMD_WRITE | addr);
10237 AdvWaitEEPCmd(iop_base);
10238 mdelay(ADV_EEP_DELAY_MS);
10242 * Write EEPROM checksum at word 21.
10244 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10245 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10246 AdvWaitEEPCmd(iop_base);
10251 * Write EEPROM OEM name at words 22 to 29.
10253 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10254 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10257 if (*charfields++) {
10258 word = cpu_to_le16(*wbuf);
10262 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10263 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10264 ASC_EEP_CMD_WRITE | addr);
10265 AdvWaitEEPCmd(iop_base);
10267 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10268 AdvWaitEEPCmd(iop_base);
10272 * Write the EEPROM from 'cfg_buf'.
10274 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10275 ADVEEP_38C1600_CONFIG *cfg_buf)
10278 ushort *charfields;
10279 ushort addr, chksum;
10281 wbuf = (ushort *)cfg_buf;
10282 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10285 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10286 AdvWaitEEPCmd(iop_base);
10289 * Write EEPROM from word 0 to word 20.
10291 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10292 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10295 if (*charfields++) {
10296 word = cpu_to_le16(*wbuf);
10300 chksum += *wbuf; /* Checksum is calculated from word values. */
10301 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10302 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10303 ASC_EEP_CMD_WRITE | addr);
10304 AdvWaitEEPCmd(iop_base);
10305 mdelay(ADV_EEP_DELAY_MS);
10309 * Write EEPROM checksum at word 21.
10311 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10312 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10313 AdvWaitEEPCmd(iop_base);
10318 * Write EEPROM OEM name at words 22 to 29.
10320 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10321 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10324 if (*charfields++) {
10325 word = cpu_to_le16(*wbuf);
10329 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10330 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10331 ASC_EEP_CMD_WRITE | addr);
10332 AdvWaitEEPCmd(iop_base);
10334 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10335 AdvWaitEEPCmd(iop_base);
10339 * Read EEPROM configuration into the specified buffer.
10341 * Return a checksum based on the EEPROM configuration read.
10343 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10344 ADVEEP_3550_CONFIG *cfg_buf)
10346 ushort wval, chksum;
10349 ushort *charfields;
10351 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10352 wbuf = (ushort *)cfg_buf;
10355 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10356 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10357 wval = AdvReadEEPWord(iop_base, eep_addr);
10358 chksum += wval; /* Checksum is calculated from word values. */
10359 if (*charfields++) {
10360 *wbuf = le16_to_cpu(wval);
10365 /* Read checksum word. */
10366 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10370 /* Read rest of EEPROM not covered by the checksum. */
10371 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10372 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10373 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10374 if (*charfields++) {
10375 *wbuf = le16_to_cpu(*wbuf);
10382 * Read EEPROM configuration into the specified buffer.
10384 * Return a checksum based on the EEPROM configuration read.
10386 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10387 ADVEEP_38C0800_CONFIG *cfg_buf)
10389 ushort wval, chksum;
10392 ushort *charfields;
10394 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10395 wbuf = (ushort *)cfg_buf;
10398 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10399 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10400 wval = AdvReadEEPWord(iop_base, eep_addr);
10401 chksum += wval; /* Checksum is calculated from word values. */
10402 if (*charfields++) {
10403 *wbuf = le16_to_cpu(wval);
10408 /* Read checksum word. */
10409 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10413 /* Read rest of EEPROM not covered by the checksum. */
10414 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10415 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10416 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10417 if (*charfields++) {
10418 *wbuf = le16_to_cpu(*wbuf);
10425 * Read EEPROM configuration into the specified buffer.
10427 * Return a checksum based on the EEPROM configuration read.
10429 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10430 ADVEEP_38C1600_CONFIG *cfg_buf)
10432 ushort wval, chksum;
10435 ushort *charfields;
10437 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10438 wbuf = (ushort *)cfg_buf;
10441 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10442 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10443 wval = AdvReadEEPWord(iop_base, eep_addr);
10444 chksum += wval; /* Checksum is calculated from word values. */
10445 if (*charfields++) {
10446 *wbuf = le16_to_cpu(wval);
10451 /* Read checksum word. */
10452 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10456 /* Read rest of EEPROM not covered by the checksum. */
10457 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10458 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10459 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10460 if (*charfields++) {
10461 *wbuf = le16_to_cpu(*wbuf);
10468 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10469 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10470 * all of this is done.
10472 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10474 * For a non-fatal error return a warning code. If there are no warnings
10475 * then 0 is returned.
10477 * Note: Chip is stopped on entry.
10479 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10481 AdvPortAddr iop_base;
10483 ADVEEP_3550_CONFIG eep_config;
10485 iop_base = asc_dvc->iop_base;
10490 * Read the board's EEPROM configuration.
10492 * Set default values if a bad checksum is found.
10494 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10495 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10498 * Set EEPROM default values.
10500 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10501 sizeof(ADVEEP_3550_CONFIG));
10504 * Assume the 6 byte board serial number that was read from
10505 * EEPROM is correct even if the EEPROM checksum failed.
10507 eep_config.serial_number_word3 =
10508 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10510 eep_config.serial_number_word2 =
10511 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10513 eep_config.serial_number_word1 =
10514 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10516 AdvSet3550EEPConfig(iop_base, &eep_config);
10519 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10520 * EEPROM configuration that was read.
10522 * This is the mapping of EEPROM fields to Adv Library fields.
10524 asc_dvc->wdtr_able = eep_config.wdtr_able;
10525 asc_dvc->sdtr_able = eep_config.sdtr_able;
10526 asc_dvc->ultra_able = eep_config.ultra_able;
10527 asc_dvc->tagqng_able = eep_config.tagqng_able;
10528 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10529 asc_dvc->max_host_qng = eep_config.max_host_qng;
10530 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10531 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10532 asc_dvc->start_motor = eep_config.start_motor;
10533 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10534 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10535 asc_dvc->no_scam = eep_config.scam_tolerant;
10536 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10537 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10538 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10541 * Set the host maximum queuing (max. 253, min. 16) and the per device
10542 * maximum queuing (max. 63, min. 4).
10544 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10545 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10546 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10547 /* If the value is zero, assume it is uninitialized. */
10548 if (eep_config.max_host_qng == 0) {
10549 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10551 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10555 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10556 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10557 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10558 /* If the value is zero, assume it is uninitialized. */
10559 if (eep_config.max_dvc_qng == 0) {
10560 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10562 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10567 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10568 * set 'max_dvc_qng' to 'max_host_qng'.
10570 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10571 eep_config.max_dvc_qng = eep_config.max_host_qng;
10575 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10576 * values based on possibly adjusted EEPROM values.
10578 asc_dvc->max_host_qng = eep_config.max_host_qng;
10579 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10582 * If the EEPROM 'termination' field is set to automatic (0), then set
10583 * the ADV_DVC_CFG 'termination' field to automatic also.
10585 * If the termination is specified with a non-zero 'termination'
10586 * value check that a legal value is set and set the ADV_DVC_CFG
10587 * 'termination' field appropriately.
10589 if (eep_config.termination == 0) {
10590 asc_dvc->cfg->termination = 0; /* auto termination */
10592 /* Enable manual control with low off / high off. */
10593 if (eep_config.termination == 1) {
10594 asc_dvc->cfg->termination = TERM_CTL_SEL;
10596 /* Enable manual control with low off / high on. */
10597 } else if (eep_config.termination == 2) {
10598 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10600 /* Enable manual control with low on / high on. */
10601 } else if (eep_config.termination == 3) {
10602 asc_dvc->cfg->termination =
10603 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10606 * The EEPROM 'termination' field contains a bad value. Use
10607 * automatic termination instead.
10609 asc_dvc->cfg->termination = 0;
10610 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10618 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10619 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10620 * all of this is done.
10622 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10624 * For a non-fatal error return a warning code. If there are no warnings
10625 * then 0 is returned.
10627 * Note: Chip is stopped on entry.
10629 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10631 AdvPortAddr iop_base;
10633 ADVEEP_38C0800_CONFIG eep_config;
10634 uchar tid, termination;
10635 ushort sdtr_speed = 0;
10637 iop_base = asc_dvc->iop_base;
10642 * Read the board's EEPROM configuration.
10644 * Set default values if a bad checksum is found.
10646 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10647 eep_config.check_sum) {
10648 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10651 * Set EEPROM default values.
10653 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10654 sizeof(ADVEEP_38C0800_CONFIG));
10657 * Assume the 6 byte board serial number that was read from
10658 * EEPROM is correct even if the EEPROM checksum failed.
10660 eep_config.serial_number_word3 =
10661 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10663 eep_config.serial_number_word2 =
10664 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10666 eep_config.serial_number_word1 =
10667 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10669 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10672 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10673 * EEPROM configuration that was read.
10675 * This is the mapping of EEPROM fields to Adv Library fields.
10677 asc_dvc->wdtr_able = eep_config.wdtr_able;
10678 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10679 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10680 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10681 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10682 asc_dvc->tagqng_able = eep_config.tagqng_able;
10683 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10684 asc_dvc->max_host_qng = eep_config.max_host_qng;
10685 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10686 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10687 asc_dvc->start_motor = eep_config.start_motor;
10688 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10689 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10690 asc_dvc->no_scam = eep_config.scam_tolerant;
10691 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10692 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10693 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10696 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10697 * are set, then set an 'sdtr_able' bit for it.
10699 asc_dvc->sdtr_able = 0;
10700 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10702 sdtr_speed = asc_dvc->sdtr_speed1;
10703 } else if (tid == 4) {
10704 sdtr_speed = asc_dvc->sdtr_speed2;
10705 } else if (tid == 8) {
10706 sdtr_speed = asc_dvc->sdtr_speed3;
10707 } else if (tid == 12) {
10708 sdtr_speed = asc_dvc->sdtr_speed4;
10710 if (sdtr_speed & ADV_MAX_TID) {
10711 asc_dvc->sdtr_able |= (1 << tid);
10717 * Set the host maximum queuing (max. 253, min. 16) and the per device
10718 * maximum queuing (max. 63, min. 4).
10720 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10721 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10722 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10723 /* If the value is zero, assume it is uninitialized. */
10724 if (eep_config.max_host_qng == 0) {
10725 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10727 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10731 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10732 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10733 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10734 /* If the value is zero, assume it is uninitialized. */
10735 if (eep_config.max_dvc_qng == 0) {
10736 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10738 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10743 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10744 * set 'max_dvc_qng' to 'max_host_qng'.
10746 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10747 eep_config.max_dvc_qng = eep_config.max_host_qng;
10751 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10752 * values based on possibly adjusted EEPROM values.
10754 asc_dvc->max_host_qng = eep_config.max_host_qng;
10755 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10758 * If the EEPROM 'termination' field is set to automatic (0), then set
10759 * the ADV_DVC_CFG 'termination' field to automatic also.
10761 * If the termination is specified with a non-zero 'termination'
10762 * value check that a legal value is set and set the ADV_DVC_CFG
10763 * 'termination' field appropriately.
10765 if (eep_config.termination_se == 0) {
10766 termination = 0; /* auto termination for SE */
10768 /* Enable manual control with low off / high off. */
10769 if (eep_config.termination_se == 1) {
10772 /* Enable manual control with low off / high on. */
10773 } else if (eep_config.termination_se == 2) {
10774 termination = TERM_SE_HI;
10776 /* Enable manual control with low on / high on. */
10777 } else if (eep_config.termination_se == 3) {
10778 termination = TERM_SE;
10781 * The EEPROM 'termination_se' field contains a bad value.
10782 * Use automatic termination instead.
10785 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10789 if (eep_config.termination_lvd == 0) {
10790 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10792 /* Enable manual control with low off / high off. */
10793 if (eep_config.termination_lvd == 1) {
10794 asc_dvc->cfg->termination = termination;
10796 /* Enable manual control with low off / high on. */
10797 } else if (eep_config.termination_lvd == 2) {
10798 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10800 /* Enable manual control with low on / high on. */
10801 } else if (eep_config.termination_lvd == 3) {
10802 asc_dvc->cfg->termination = termination | TERM_LVD;
10805 * The EEPROM 'termination_lvd' field contains a bad value.
10806 * Use automatic termination instead.
10808 asc_dvc->cfg->termination = termination;
10809 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10817 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10818 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10819 * all of this is done.
10821 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10823 * For a non-fatal error return a warning code. If there are no warnings
10824 * then 0 is returned.
10826 * Note: Chip is stopped on entry.
10828 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10830 AdvPortAddr iop_base;
10832 ADVEEP_38C1600_CONFIG eep_config;
10833 uchar tid, termination;
10834 ushort sdtr_speed = 0;
10836 iop_base = asc_dvc->iop_base;
10841 * Read the board's EEPROM configuration.
10843 * Set default values if a bad checksum is found.
10845 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10846 eep_config.check_sum) {
10847 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10848 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10851 * Set EEPROM default values.
10853 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10854 sizeof(ADVEEP_38C1600_CONFIG));
10856 if (PCI_FUNC(pdev->devfn) != 0) {
10859 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10860 * and old Mac system booting problem. The Expansion
10861 * ROM must be disabled in Function 1 for these systems
10863 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10865 * Clear the INTAB (bit 11) if the GPIO 0 input
10866 * indicates the Function 1 interrupt line is wired
10869 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10870 * 1 - Function 1 interrupt line wired to INT A.
10871 * 0 - Function 1 interrupt line wired to INT B.
10873 * Note: Function 0 is always wired to INTA.
10874 * Put all 5 GPIO bits in input mode and then read
10875 * their input values.
10877 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10878 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10879 if ((ints & 0x01) == 0)
10880 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10884 * Assume the 6 byte board serial number that was read from
10885 * EEPROM is correct even if the EEPROM checksum failed.
10887 eep_config.serial_number_word3 =
10888 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10889 eep_config.serial_number_word2 =
10890 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10891 eep_config.serial_number_word1 =
10892 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10894 AdvSet38C1600EEPConfig(iop_base, &eep_config);
10898 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10899 * EEPROM configuration that was read.
10901 * This is the mapping of EEPROM fields to Adv Library fields.
10903 asc_dvc->wdtr_able = eep_config.wdtr_able;
10904 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10905 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10906 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10907 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10908 asc_dvc->ppr_able = 0;
10909 asc_dvc->tagqng_able = eep_config.tagqng_able;
10910 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10911 asc_dvc->max_host_qng = eep_config.max_host_qng;
10912 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10913 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10914 asc_dvc->start_motor = eep_config.start_motor;
10915 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10916 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10917 asc_dvc->no_scam = eep_config.scam_tolerant;
10920 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10921 * are set, then set an 'sdtr_able' bit for it.
10923 asc_dvc->sdtr_able = 0;
10924 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10926 sdtr_speed = asc_dvc->sdtr_speed1;
10927 } else if (tid == 4) {
10928 sdtr_speed = asc_dvc->sdtr_speed2;
10929 } else if (tid == 8) {
10930 sdtr_speed = asc_dvc->sdtr_speed3;
10931 } else if (tid == 12) {
10932 sdtr_speed = asc_dvc->sdtr_speed4;
10934 if (sdtr_speed & ASC_MAX_TID) {
10935 asc_dvc->sdtr_able |= (1 << tid);
10941 * Set the host maximum queuing (max. 253, min. 16) and the per device
10942 * maximum queuing (max. 63, min. 4).
10944 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10945 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10946 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10947 /* If the value is zero, assume it is uninitialized. */
10948 if (eep_config.max_host_qng == 0) {
10949 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10951 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10955 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10956 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10957 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10958 /* If the value is zero, assume it is uninitialized. */
10959 if (eep_config.max_dvc_qng == 0) {
10960 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10962 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10967 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10968 * set 'max_dvc_qng' to 'max_host_qng'.
10970 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10971 eep_config.max_dvc_qng = eep_config.max_host_qng;
10975 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10976 * values based on possibly adjusted EEPROM values.
10978 asc_dvc->max_host_qng = eep_config.max_host_qng;
10979 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10982 * If the EEPROM 'termination' field is set to automatic (0), then set
10983 * the ASC_DVC_CFG 'termination' field to automatic also.
10985 * If the termination is specified with a non-zero 'termination'
10986 * value check that a legal value is set and set the ASC_DVC_CFG
10987 * 'termination' field appropriately.
10989 if (eep_config.termination_se == 0) {
10990 termination = 0; /* auto termination for SE */
10992 /* Enable manual control with low off / high off. */
10993 if (eep_config.termination_se == 1) {
10996 /* Enable manual control with low off / high on. */
10997 } else if (eep_config.termination_se == 2) {
10998 termination = TERM_SE_HI;
11000 /* Enable manual control with low on / high on. */
11001 } else if (eep_config.termination_se == 3) {
11002 termination = TERM_SE;
11005 * The EEPROM 'termination_se' field contains a bad value.
11006 * Use automatic termination instead.
11009 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11013 if (eep_config.termination_lvd == 0) {
11014 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
11016 /* Enable manual control with low off / high off. */
11017 if (eep_config.termination_lvd == 1) {
11018 asc_dvc->cfg->termination = termination;
11020 /* Enable manual control with low off / high on. */
11021 } else if (eep_config.termination_lvd == 2) {
11022 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
11024 /* Enable manual control with low on / high on. */
11025 } else if (eep_config.termination_lvd == 3) {
11026 asc_dvc->cfg->termination = termination | TERM_LVD;
11029 * The EEPROM 'termination_lvd' field contains a bad value.
11030 * Use automatic termination instead.
11032 asc_dvc->cfg->termination = termination;
11033 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11041 * Initialize the ADV_DVC_VAR structure.
11043 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11045 * For a non-fatal error return a warning code. If there are no warnings
11046 * then 0 is returned.
11048 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11050 struct asc_board *board = shost_priv(shost);
11051 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
11052 unsigned short warn_code = 0;
11053 AdvPortAddr iop_base = asc_dvc->iop_base;
11057 asc_dvc->err_code = 0;
11060 * Save the state of the PCI Configuration Command Register
11061 * "Parity Error Response Control" Bit. If the bit is clear (0),
11062 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11063 * DMA parity errors.
11065 asc_dvc->cfg->control_flag = 0;
11066 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11067 if ((cmd & PCI_COMMAND_PARITY) == 0)
11068 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11070 asc_dvc->cfg->chip_version =
11071 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11073 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
11074 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11075 (ushort)ADV_CHIP_ID_BYTE);
11077 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
11078 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11079 (ushort)ADV_CHIP_ID_WORD);
11082 * Reset the chip to start and allow register writes.
11084 if (AdvFindSignature(iop_base) == 0) {
11085 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11089 * The caller must set 'chip_type' to a valid setting.
11091 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11092 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11093 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11094 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11101 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11102 ADV_CTRL_REG_CMD_RESET);
11104 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11105 ADV_CTRL_REG_CMD_WR_IO_REG);
11107 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11108 status = AdvInitFrom38C1600EEP(asc_dvc);
11109 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11110 status = AdvInitFrom38C0800EEP(asc_dvc);
11112 status = AdvInitFrom3550EEP(asc_dvc);
11114 warn_code |= status;
11117 if (warn_code != 0)
11118 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
11120 if (asc_dvc->err_code)
11121 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11122 asc_dvc->err_code);
11124 return asc_dvc->err_code;
11128 static struct scsi_host_template advansys_template = {
11129 .proc_name = DRV_NAME,
11130 #ifdef CONFIG_PROC_FS
11131 .show_info = advansys_show_info,
11134 .info = advansys_info,
11135 .queuecommand = advansys_queuecommand,
11136 .eh_host_reset_handler = advansys_reset,
11137 .bios_param = advansys_biosparam,
11138 .slave_configure = advansys_slave_configure,
11140 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11141 * must be set. The flag will be cleared in advansys_board_found
11142 * for non-ISA adapters.
11144 .unchecked_isa_dma = 1,
11146 * All adapters controlled by this driver are capable of large
11147 * scatter-gather lists. According to the mid-level SCSI documentation
11148 * this obviates any performance gain provided by setting
11149 * 'use_clustering'. But empirically while CPU utilization is increased
11150 * by enabling clustering, I/O throughput increases as well.
11152 .use_clustering = ENABLE_CLUSTERING,
11156 static int advansys_wide_init_chip(struct Scsi_Host *shost)
11158 struct asc_board *board = shost_priv(shost);
11159 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11162 int warn_code, err_code;
11165 * Allocate buffer carrier structures. The total size
11166 * is about 8 KB, so allocate all at once.
11168 adv_dvc->carrier = dma_alloc_coherent(board->dev,
11169 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
11170 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
11172 if (!adv_dvc->carrier)
11173 goto kmalloc_failed;
11176 * Allocate up to 'max_host_qng' request structures for the Wide
11177 * board. The total size is about 16 KB, so allocate all at once.
11178 * If the allocation fails decrement and try again.
11180 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
11181 if (board->adv_reqp_size & 0x1f) {
11182 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
11183 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
11185 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
11186 &board->adv_reqp_addr, GFP_KERNEL);
11188 if (!board->adv_reqp)
11189 goto kmalloc_failed;
11191 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
11192 adv_dvc->max_host_qng, board->adv_reqp_size);
11195 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11196 * the Wide board. Each structure is about 136 bytes.
11198 board->adv_sgblkp = NULL;
11199 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
11200 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
11205 sgp->next_sgblkp = board->adv_sgblkp;
11206 board->adv_sgblkp = sgp;
11210 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", sg_cnt, sizeof(adv_sgblk_t),
11211 sizeof(adv_sgblk_t) * sg_cnt);
11213 if (!board->adv_sgblkp)
11214 goto kmalloc_failed;
11216 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
11217 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
11218 warn_code = AdvInitAsc3550Driver(adv_dvc);
11219 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11220 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
11221 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
11223 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
11224 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
11226 err_code = adv_dvc->err_code;
11228 if (warn_code || err_code) {
11229 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11230 "0x%x\n", warn_code, err_code);
11236 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
11237 err_code = ADV_ERROR;
11242 static void advansys_wide_free_mem(struct asc_board *board)
11244 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11246 if (adv_dvc->carrier) {
11247 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
11248 adv_dvc->carrier, adv_dvc->carrier_addr);
11249 adv_dvc->carrier = NULL;
11251 if (board->adv_reqp) {
11252 dma_free_coherent(board->dev, board->adv_reqp_size,
11253 board->adv_reqp, board->adv_reqp_addr);
11254 board->adv_reqp = NULL;
11256 while (board->adv_sgblkp) {
11257 adv_sgblk_t *sgp = board->adv_sgblkp;
11258 board->adv_sgblkp = sgp->next_sgblkp;
11263 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11266 struct pci_dev *pdev;
11267 struct asc_board *boardp = shost_priv(shost);
11268 ASC_DVC_VAR *asc_dvc_varp = NULL;
11269 ADV_DVC_VAR *adv_dvc_varp = NULL;
11270 int share_irq, warn_code, ret;
11272 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
11274 if (ASC_NARROW_BOARD(boardp)) {
11275 ASC_DBG(1, "narrow board\n");
11276 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11277 asc_dvc_varp->bus_type = bus_type;
11278 asc_dvc_varp->drv_ptr = boardp;
11279 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
11280 asc_dvc_varp->iop_base = iop;
11283 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11284 adv_dvc_varp->drv_ptr = boardp;
11285 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
11286 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
11287 ASC_DBG(1, "wide board ASC-3550\n");
11288 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11289 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
11290 ASC_DBG(1, "wide board ASC-38C0800\n");
11291 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11293 ASC_DBG(1, "wide board ASC-38C1600\n");
11294 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11297 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
11298 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
11299 if (!boardp->ioremap_addr) {
11300 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
11302 (long)pci_resource_start(pdev, 1),
11303 boardp->asc_n_io_port);
11307 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11308 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
11311 * Even though it isn't used to access wide boards, other
11312 * than for the debug line below, save I/O Port address so
11313 * that it can be reported.
11315 boardp->ioport = iop;
11317 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11318 (ushort)inp(iop + 1), (ushort)inpw(iop));
11319 #endif /* CONFIG_PCI */
11322 if (ASC_NARROW_BOARD(boardp)) {
11324 * Set the board bus type and PCI IRQ before
11325 * calling AscInitGetConfig().
11327 switch (asc_dvc_varp->bus_type) {
11330 shost->unchecked_isa_dma = TRUE;
11334 shost->unchecked_isa_dma = FALSE;
11338 shost->unchecked_isa_dma = FALSE;
11339 share_irq = IRQF_SHARED;
11341 #endif /* CONFIG_ISA */
11344 shost->unchecked_isa_dma = FALSE;
11345 share_irq = IRQF_SHARED;
11347 #endif /* CONFIG_PCI */
11349 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11350 "%d\n", asc_dvc_varp->bus_type);
11351 shost->unchecked_isa_dma = TRUE;
11357 * NOTE: AscInitGetConfig() may change the board's
11358 * bus_type value. The bus_type value should no
11359 * longer be used. If the bus_type field must be
11360 * referenced only use the bit-wise AND operator "&".
11362 ASC_DBG(2, "AscInitGetConfig()\n");
11363 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11367 * For Wide boards set PCI information before calling
11368 * AdvInitGetConfig().
11370 shost->unchecked_isa_dma = FALSE;
11371 share_irq = IRQF_SHARED;
11372 ASC_DBG(2, "AdvInitGetConfig()\n");
11374 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11375 #endif /* CONFIG_PCI */
11382 * Save the EEPROM configuration so that it can be displayed
11383 * from /proc/scsi/advansys/[0...].
11385 if (ASC_NARROW_BOARD(boardp)) {
11390 * Set the adapter's target id bit in the 'init_tidmask' field.
11392 boardp->init_tidmask |=
11393 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11396 * Save EEPROM settings for the board.
11398 ep = &boardp->eep_config.asc_eep;
11400 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11401 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11402 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11403 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11404 ep->start_motor = asc_dvc_varp->start_motor;
11405 ep->cntl = asc_dvc_varp->dvc_cntl;
11406 ep->no_scam = asc_dvc_varp->no_scam;
11407 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11408 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11409 /* 'max_tag_qng' is set to the same value for every device. */
11410 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11411 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11412 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11413 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11414 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11415 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11416 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11419 * Modify board configuration.
11421 ASC_DBG(2, "AscInitSetConfig()\n");
11422 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11426 ADVEEP_3550_CONFIG *ep_3550;
11427 ADVEEP_38C0800_CONFIG *ep_38C0800;
11428 ADVEEP_38C1600_CONFIG *ep_38C1600;
11431 * Save Wide EEP Configuration Information.
11433 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11434 ep_3550 = &boardp->eep_config.adv_3550_eep;
11436 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11437 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11438 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11439 ep_3550->termination = adv_dvc_varp->cfg->termination;
11440 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11441 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11442 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11443 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11444 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11445 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11446 ep_3550->start_motor = adv_dvc_varp->start_motor;
11447 ep_3550->scsi_reset_delay =
11448 adv_dvc_varp->scsi_reset_wait;
11449 ep_3550->serial_number_word1 =
11450 adv_dvc_varp->cfg->serial1;
11451 ep_3550->serial_number_word2 =
11452 adv_dvc_varp->cfg->serial2;
11453 ep_3550->serial_number_word3 =
11454 adv_dvc_varp->cfg->serial3;
11455 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11456 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11458 ep_38C0800->adapter_scsi_id =
11459 adv_dvc_varp->chip_scsi_id;
11460 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11461 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11462 ep_38C0800->termination_lvd =
11463 adv_dvc_varp->cfg->termination;
11464 ep_38C0800->disc_enable =
11465 adv_dvc_varp->cfg->disc_enable;
11466 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11467 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11468 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11469 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11470 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11471 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11472 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11473 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11474 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11475 ep_38C0800->scsi_reset_delay =
11476 adv_dvc_varp->scsi_reset_wait;
11477 ep_38C0800->serial_number_word1 =
11478 adv_dvc_varp->cfg->serial1;
11479 ep_38C0800->serial_number_word2 =
11480 adv_dvc_varp->cfg->serial2;
11481 ep_38C0800->serial_number_word3 =
11482 adv_dvc_varp->cfg->serial3;
11484 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11486 ep_38C1600->adapter_scsi_id =
11487 adv_dvc_varp->chip_scsi_id;
11488 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11489 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11490 ep_38C1600->termination_lvd =
11491 adv_dvc_varp->cfg->termination;
11492 ep_38C1600->disc_enable =
11493 adv_dvc_varp->cfg->disc_enable;
11494 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11495 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11496 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11497 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11498 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11499 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11500 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11501 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11502 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11503 ep_38C1600->scsi_reset_delay =
11504 adv_dvc_varp->scsi_reset_wait;
11505 ep_38C1600->serial_number_word1 =
11506 adv_dvc_varp->cfg->serial1;
11507 ep_38C1600->serial_number_word2 =
11508 adv_dvc_varp->cfg->serial2;
11509 ep_38C1600->serial_number_word3 =
11510 adv_dvc_varp->cfg->serial3;
11514 * Set the adapter's target id bit in the 'init_tidmask' field.
11516 boardp->init_tidmask |=
11517 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11521 * Channels are numbered beginning with 0. For AdvanSys one host
11522 * structure supports one channel. Multi-channel boards have a
11523 * separate host structure for each channel.
11525 shost->max_channel = 0;
11526 if (ASC_NARROW_BOARD(boardp)) {
11527 shost->max_id = ASC_MAX_TID + 1;
11528 shost->max_lun = ASC_MAX_LUN + 1;
11529 shost->max_cmd_len = ASC_MAX_CDB_LEN;
11531 shost->io_port = asc_dvc_varp->iop_base;
11532 boardp->asc_n_io_port = ASC_IOADR_GAP;
11533 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11535 /* Set maximum number of queues the adapter can handle. */
11536 shost->can_queue = asc_dvc_varp->max_total_qng;
11538 shost->max_id = ADV_MAX_TID + 1;
11539 shost->max_lun = ADV_MAX_LUN + 1;
11540 shost->max_cmd_len = ADV_MAX_CDB_LEN;
11543 * Save the I/O Port address and length even though
11544 * I/O ports are not used to access Wide boards.
11545 * Instead the Wide boards are accessed with
11546 * PCI Memory Mapped I/O.
11548 shost->io_port = iop;
11550 shost->this_id = adv_dvc_varp->chip_scsi_id;
11552 /* Set maximum number of queues the adapter can handle. */
11553 shost->can_queue = adv_dvc_varp->max_host_qng;
11555 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11557 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11562 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11563 * and should be set to zero.
11565 * But because of a bug introduced in v1.3.89 if the driver is
11566 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11567 * SCSI function 'allocate_device' will panic. To allow the driver
11568 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11570 * Note: This is wrong. cmd_per_lun should be set to the depth
11571 * you want on untagged devices always.
11574 shost->cmd_per_lun = 1;
11576 shost->cmd_per_lun = 0;
11580 * Set the maximum number of scatter-gather elements the
11581 * adapter can handle.
11583 if (ASC_NARROW_BOARD(boardp)) {
11585 * Allow two commands with 'sg_tablesize' scatter-gather
11586 * elements to be executed simultaneously. This value is
11587 * the theoretical hardware limit. It may be decreased
11590 shost->sg_tablesize =
11591 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11592 ASC_SG_LIST_PER_Q) + 1;
11594 shost->sg_tablesize = ADV_MAX_SG_LIST;
11598 * The value of 'sg_tablesize' can not exceed the SCSI
11599 * mid-level driver definition of SG_ALL. SG_ALL also
11600 * must not be exceeded, because it is used to define the
11601 * size of the scatter-gather table in 'struct asc_sg_head'.
11603 if (shost->sg_tablesize > SG_ALL) {
11604 shost->sg_tablesize = SG_ALL;
11607 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11609 /* BIOS start address. */
11610 if (ASC_NARROW_BOARD(boardp)) {
11611 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11612 asc_dvc_varp->bus_type);
11615 * Fill-in BIOS board variables. The Wide BIOS saves
11616 * information in LRAM that is used by the driver.
11618 AdvReadWordLram(adv_dvc_varp->iop_base,
11619 BIOS_SIGNATURE, boardp->bios_signature);
11620 AdvReadWordLram(adv_dvc_varp->iop_base,
11621 BIOS_VERSION, boardp->bios_version);
11622 AdvReadWordLram(adv_dvc_varp->iop_base,
11623 BIOS_CODESEG, boardp->bios_codeseg);
11624 AdvReadWordLram(adv_dvc_varp->iop_base,
11625 BIOS_CODELEN, boardp->bios_codelen);
11627 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11628 boardp->bios_signature, boardp->bios_version);
11630 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11631 boardp->bios_codeseg, boardp->bios_codelen);
11634 * If the BIOS saved a valid signature, then fill in
11635 * the BIOS code segment base address.
11637 if (boardp->bios_signature == 0x55AA) {
11639 * Convert x86 realmode code segment to a linear
11640 * address by shifting left 4.
11642 shost->base = ((ulong)boardp->bios_codeseg << 4);
11649 * Register Board Resources - I/O Port, DMA, IRQ
11652 /* Register DMA Channel for Narrow boards. */
11653 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11655 if (ASC_NARROW_BOARD(boardp)) {
11656 /* Register DMA channel for ISA bus. */
11657 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11658 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11659 ret = request_dma(shost->dma_channel, DRV_NAME);
11661 shost_printk(KERN_ERR, shost, "request_dma() "
11663 shost->dma_channel, ret);
11666 AscEnableIsaDma(shost->dma_channel);
11669 #endif /* CONFIG_ISA */
11671 /* Register IRQ Number. */
11672 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11674 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11678 if (ret == -EBUSY) {
11679 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11680 "already in use\n", boardp->irq);
11681 } else if (ret == -EINVAL) {
11682 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11683 "not valid\n", boardp->irq);
11685 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11686 "failed with %d\n", boardp->irq, ret);
11692 * Initialize board RISC chip and enable interrupts.
11694 if (ASC_NARROW_BOARD(boardp)) {
11695 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11697 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11698 if (!asc_dvc_varp->overrun_buf) {
11702 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11704 if (warn_code || asc_dvc_varp->err_code) {
11705 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11706 "warn 0x%x, error 0x%x\n",
11707 asc_dvc_varp->init_state, warn_code,
11708 asc_dvc_varp->err_code);
11709 if (!asc_dvc_varp->overrun_dma) {
11715 if (advansys_wide_init_chip(shost)) {
11721 ASC_DBG_PRT_SCSI_HOST(2, shost);
11723 ret = scsi_add_host(shost, boardp->dev);
11727 scsi_scan_host(shost);
11731 if (ASC_NARROW_BOARD(boardp)) {
11732 if (asc_dvc_varp->overrun_dma)
11733 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11734 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11735 kfree(asc_dvc_varp->overrun_buf);
11737 advansys_wide_free_mem(boardp);
11739 free_irq(boardp->irq, shost);
11742 if (shost->dma_channel != NO_ISA_DMA)
11743 free_dma(shost->dma_channel);
11746 if (boardp->ioremap_addr)
11747 iounmap(boardp->ioremap_addr);
11753 * advansys_release()
11755 * Release resources allocated for a single AdvanSys adapter.
11757 static int advansys_release(struct Scsi_Host *shost)
11759 struct asc_board *board = shost_priv(shost);
11760 ASC_DBG(1, "begin\n");
11761 scsi_remove_host(shost);
11762 free_irq(board->irq, shost);
11764 if (shost->dma_channel != NO_ISA_DMA) {
11765 ASC_DBG(1, "free_dma()\n");
11766 free_dma(shost->dma_channel);
11769 if (ASC_NARROW_BOARD(board)) {
11770 dma_unmap_single(board->dev,
11771 board->dvc_var.asc_dvc_var.overrun_dma,
11772 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11773 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11775 iounmap(board->ioremap_addr);
11776 advansys_wide_free_mem(board);
11778 scsi_host_put(shost);
11779 ASC_DBG(1, "end\n");
11783 #define ASC_IOADR_TABLE_MAX_IX 11
11785 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11786 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11787 0x0210, 0x0230, 0x0250, 0x0330
11791 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11797 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11799 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11800 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11801 if (chip_irq == 13)
11806 static int advansys_isa_probe(struct device *dev, unsigned int id)
11809 PortAddr iop_base = _asc_def_iop_base[id];
11810 struct Scsi_Host *shost;
11811 struct asc_board *board;
11813 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11814 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11817 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11818 if (!AscFindSignature(iop_base))
11819 goto release_region;
11820 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11821 goto release_region;
11824 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11826 goto release_region;
11828 board = shost_priv(shost);
11829 board->irq = advansys_isa_irq_no(iop_base);
11831 board->shost = shost;
11833 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11837 dev_set_drvdata(dev, shost);
11841 scsi_host_put(shost);
11843 release_region(iop_base, ASC_IOADR_GAP);
11847 static int advansys_isa_remove(struct device *dev, unsigned int id)
11849 int ioport = _asc_def_iop_base[id];
11850 advansys_release(dev_get_drvdata(dev));
11851 release_region(ioport, ASC_IOADR_GAP);
11855 static struct isa_driver advansys_isa_driver = {
11856 .probe = advansys_isa_probe,
11857 .remove = advansys_isa_remove,
11859 .owner = THIS_MODULE,
11865 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11875 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11877 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11878 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11879 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11884 static int advansys_vlb_probe(struct device *dev, unsigned int id)
11887 PortAddr iop_base = _asc_def_iop_base[id];
11888 struct Scsi_Host *shost;
11889 struct asc_board *board;
11891 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11892 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11895 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11896 if (!AscFindSignature(iop_base))
11897 goto release_region;
11899 * I don't think this condition can actually happen, but the old
11900 * driver did it, and the chances of finding a VLB setup in 2007
11901 * to do testing with is slight to none.
11903 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
11904 goto release_region;
11907 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11909 goto release_region;
11911 board = shost_priv(shost);
11912 board->irq = advansys_vlb_irq_no(iop_base);
11914 board->shost = shost;
11916 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11920 dev_set_drvdata(dev, shost);
11924 scsi_host_put(shost);
11926 release_region(iop_base, ASC_IOADR_GAP);
11930 static struct isa_driver advansys_vlb_driver = {
11931 .probe = advansys_vlb_probe,
11932 .remove = advansys_isa_remove,
11934 .owner = THIS_MODULE,
11935 .name = "advansys_vlb",
11939 static struct eisa_device_id advansys_eisa_table[] = {
11945 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11948 * EISA is a little more tricky than PCI; each EISA device may have two
11949 * channels, and this driver is written to make each channel its own Scsi_Host
11951 struct eisa_scsi_data {
11952 struct Scsi_Host *host[2];
11956 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11966 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
11968 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11969 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11970 if ((chip_irq == 13) || (chip_irq > 15))
11975 static int advansys_eisa_probe(struct device *dev)
11977 int i, ioport, irq = 0;
11979 struct eisa_device *edev = to_eisa_device(dev);
11980 struct eisa_scsi_data *data;
11983 data = kzalloc(sizeof(*data), GFP_KERNEL);
11986 ioport = edev->base_addr + 0xc30;
11989 for (i = 0; i < 2; i++, ioport += 0x20) {
11990 struct asc_board *board;
11991 struct Scsi_Host *shost;
11992 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
11993 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11994 ioport + ASC_IOADR_GAP - 1);
11997 if (!AscFindSignature(ioport)) {
11998 release_region(ioport, ASC_IOADR_GAP);
12003 * I don't know why we need to do this for EISA chips, but
12004 * not for any others. It looks to be equivalent to
12005 * AscGetChipCfgMsw, but I may have overlooked something,
12006 * so I'm not converting it until I get an EISA board to
12012 irq = advansys_eisa_irq_no(edev);
12015 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12017 goto release_region;
12019 board = shost_priv(shost);
12022 board->shost = shost;
12024 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
12026 data->host[i] = shost;
12030 scsi_host_put(shost);
12032 release_region(ioport, ASC_IOADR_GAP);
12038 dev_set_drvdata(dev, data);
12042 kfree(data->host[0]);
12043 kfree(data->host[1]);
12049 static int advansys_eisa_remove(struct device *dev)
12052 struct eisa_scsi_data *data = dev_get_drvdata(dev);
12054 for (i = 0; i < 2; i++) {
12056 struct Scsi_Host *shost = data->host[i];
12059 ioport = shost->io_port;
12060 advansys_release(shost);
12061 release_region(ioport, ASC_IOADR_GAP);
12068 static struct eisa_driver advansys_eisa_driver = {
12069 .id_table = advansys_eisa_table,
12072 .probe = advansys_eisa_probe,
12073 .remove = advansys_eisa_remove,
12077 /* PCI Devices supported by this driver */
12078 static struct pci_device_id advansys_pci_tbl[] = {
12079 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12080 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12081 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12082 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12083 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12084 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12085 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12086 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12087 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12088 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12089 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12090 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12094 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
12096 static void advansys_set_latency(struct pci_dev *pdev)
12098 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12099 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12100 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12103 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12104 if (latency < 0x20)
12105 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12109 static int advansys_pci_probe(struct pci_dev *pdev,
12110 const struct pci_device_id *ent)
12113 struct Scsi_Host *shost;
12114 struct asc_board *board;
12116 err = pci_enable_device(pdev);
12119 err = pci_request_regions(pdev, DRV_NAME);
12121 goto disable_device;
12122 pci_set_master(pdev);
12123 advansys_set_latency(pdev);
12126 if (pci_resource_len(pdev, 0) == 0)
12127 goto release_region;
12129 ioport = pci_resource_start(pdev, 0);
12132 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12134 goto release_region;
12136 board = shost_priv(shost);
12137 board->irq = pdev->irq;
12138 board->dev = &pdev->dev;
12139 board->shost = shost;
12141 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12142 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12143 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12144 board->flags |= ASC_IS_WIDE_BOARD;
12147 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12151 pci_set_drvdata(pdev, shost);
12155 scsi_host_put(shost);
12157 pci_release_regions(pdev);
12159 pci_disable_device(pdev);
12164 static void advansys_pci_remove(struct pci_dev *pdev)
12166 advansys_release(pci_get_drvdata(pdev));
12167 pci_release_regions(pdev);
12168 pci_disable_device(pdev);
12171 static struct pci_driver advansys_pci_driver = {
12173 .id_table = advansys_pci_tbl,
12174 .probe = advansys_pci_probe,
12175 .remove = advansys_pci_remove,
12178 static int __init advansys_init(void)
12182 error = isa_register_driver(&advansys_isa_driver,
12183 ASC_IOADR_TABLE_MAX_IX);
12187 error = isa_register_driver(&advansys_vlb_driver,
12188 ASC_IOADR_TABLE_MAX_IX);
12190 goto unregister_isa;
12192 error = eisa_driver_register(&advansys_eisa_driver);
12194 goto unregister_vlb;
12196 error = pci_register_driver(&advansys_pci_driver);
12198 goto unregister_eisa;
12203 eisa_driver_unregister(&advansys_eisa_driver);
12205 isa_unregister_driver(&advansys_vlb_driver);
12207 isa_unregister_driver(&advansys_isa_driver);
12212 static void __exit advansys_exit(void)
12214 pci_unregister_driver(&advansys_pci_driver);
12215 eisa_driver_unregister(&advansys_eisa_driver);
12216 isa_unregister_driver(&advansys_vlb_driver);
12217 isa_unregister_driver(&advansys_isa_driver);
12220 module_init(advansys_init);
12221 module_exit(advansys_exit);
12223 MODULE_LICENSE("GPL");
12224 MODULE_FIRMWARE("advansys/mcode.bin");
12225 MODULE_FIRMWARE("advansys/3550.bin");
12226 MODULE_FIRMWARE("advansys/38C0800.bin");
12227 MODULE_FIRMWARE("advansys/38C1600.bin");