drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of.h>
  32 #include <linux/of_gpio.h>
  33
  34 #include <mach/dma.h>
  35 #include <plat/s3c64xx-spi.h>
  36
  37 #define MAX_SPI_PORTS           3
  38
  39 /* Registers and bit-fields */
  40
  41 #define S3C64XX_SPI_CH_CFG              0x00
  42 #define S3C64XX_SPI_CLK_CFG             0x04
  43 #define S3C64XX_SPI_MODE_CFG    0x08
  44 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  45 #define S3C64XX_SPI_INT_EN              0x10
  46 #define S3C64XX_SPI_STATUS              0x14
  47 #define S3C64XX_SPI_TX_DATA             0x18
  48 #define S3C64XX_SPI_RX_DATA             0x1C
  49 #define S3C64XX_SPI_PACKET_CNT  0x20
  50 #define S3C64XX_SPI_PENDING_CLR 0x24
  51 #define S3C64XX_SPI_SWAP_CFG    0x28
  52 #define S3C64XX_SPI_FB_CLK              0x2C
  53
  54 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  55 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  56 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  57 #define S3C64XX_SPI_CPOL_L              (1<<3)
  58 #define S3C64XX_SPI_CPHA_B              (1<<2)
  59 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  60 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  61
  62 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  63 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  64 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  65 #define S3C64XX_SPI_PSR_MASK            0xff
  66
  67 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  68 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  69 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  70 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  71 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  72 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  73 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  74 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  75 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  76 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  77 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  78
  79 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  80 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  81
  82 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  83 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  84 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  85 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  86 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  87 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  88 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  89
  90 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  91 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  92 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  93 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  94 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  95 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  96
  97 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  98
  99 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 100 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 101 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 102 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 103 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 104
 105 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 106 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 107 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 108 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 109 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 110 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 111 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 112 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 113
 114 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 115
 116 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 117 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 118                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 121                                         FIFO_LVL_MASK(i))
 122
 123 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 124 #define S3C64XX_SPI_TRAILCNT_OFF        19
 125
 126 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 127
 128 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 129
 130 #define RXBUSY    (1<<2)
 131 #define TXBUSY    (1<<3)
 132
 133 struct s3c64xx_spi_dma_data {
 134         unsigned                ch;
 135         enum dma_transfer_direction direction;
 136         enum dma_ch     dmach;
 137         struct property         *dma_prop;
 138 };
 139
 140 /**
 141  * struct s3c64xx_spi_info - SPI Controller hardware info
 142  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 143  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 144  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 145  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 146  * @clk_from_cmu: True, if the controller does not include a clock mux and
 147  *      prescaler unit.
 148  *
 149  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 150  * differ in some aspects such as the size of the fifo and spi bus clock
 151  * setup. Such differences are specified to the driver using this structure
 152  * which is provided as driver data to the driver.
 153  */
 154 struct s3c64xx_spi_port_config {
 155         int     fifo_lvl_mask[MAX_SPI_PORTS];
 156         int     rx_lvl_offset;
 157         int     tx_st_done;
 158         bool    high_speed;
 159         bool    clk_from_cmu;
 160 };
 161
 162 /**
 163  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 164  * @clk: Pointer to the spi clock.
 165  * @src_clk: Pointer to the clock used to generate SPI signals.
 166  * @master: Pointer to the SPI Protocol master.
 167  * @cntrlr_info: Platform specific data for the controller this driver manages.
 168  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 169  * @queue: To log SPI xfer requests.
 170  * @lock: Controller specific lock.
 171  * @state: Set of FLAGS to indicate status.
 172  * @rx_dmach: Controller's DMA channel for Rx.
 173  * @tx_dmach: Controller's DMA channel for Tx.
 174  * @sfr_start: BUS address of SPI controller regs.
 175  * @regs: Pointer to ioremap'ed controller registers.
 176  * @irq: interrupt
 177  * @xfer_completion: To indicate completion of xfer task.
 178  * @cur_mode: Stores the active configuration of the controller.
 179  * @cur_bpw: Stores the active bits per word settings.
 180  * @cur_speed: Stores the active xfer clock speed.
 181  */
 182 struct s3c64xx_spi_driver_data {
 183         void __iomem                    *regs;
 184         struct clk                      *clk;
 185         struct clk                      *src_clk;
 186         struct platform_device          *pdev;
 187         struct spi_master               *master;
 188         struct s3c64xx_spi_info  *cntrlr_info;
 189         struct spi_device               *tgl_spi;
 190         struct list_head                queue;
 191         spinlock_t                      lock;
 192         unsigned long                   sfr_start;
 193         struct completion               xfer_completion;
 194         unsigned                        state;
 195         unsigned                        cur_mode, cur_bpw;
 196         unsigned                        cur_speed;
 197         struct s3c64xx_spi_dma_data     rx_dma;
 198         struct s3c64xx_spi_dma_data     tx_dma;
 199         struct samsung_dma_ops          *ops;
 200         struct s3c64xx_spi_port_config  *port_conf;
 201         unsigned int                    port_id;
 202         unsigned long                   gpios[4];
 203 };
 204
 205 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 206         .name = "samsung-spi-dma",
 207 };
 208
 209 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 210 {
 211         void __iomem *regs = sdd->regs;
 212         unsigned long loops;
 213         u32 val;
 214
 215         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 216
 217         val = readl(regs + S3C64XX_SPI_CH_CFG);
 218         val |= S3C64XX_SPI_CH_SW_RST;
 219         val &= ~S3C64XX_SPI_CH_HS_EN;
 220         writel(val, regs + S3C64XX_SPI_CH_CFG);
 221
 222         /* Flush TxFIFO*/
 223         loops = msecs_to_loops(1);
 224         do {
 225                 val = readl(regs + S3C64XX_SPI_STATUS);
 226         } while (TX_FIFO_LVL(val, sdd) && loops--);
 227
 228         if (loops == 0)
 229                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 230
 231         /* Flush RxFIFO*/
 232         loops = msecs_to_loops(1);
 233         do {
 234                 val = readl(regs + S3C64XX_SPI_STATUS);
 235                 if (RX_FIFO_LVL(val, sdd))
 236                         readl(regs + S3C64XX_SPI_RX_DATA);
 237                 else
 238                         break;
 239         } while (loops--);
 240
 241         if (loops == 0)
 242                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 243
 244         val = readl(regs + S3C64XX_SPI_CH_CFG);
 245         val &= ~S3C64XX_SPI_CH_SW_RST;
 246         writel(val, regs + S3C64XX_SPI_CH_CFG);
 247
 248         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 249         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 250         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 251
 252         val = readl(regs + S3C64XX_SPI_CH_CFG);
 253         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 254         writel(val, regs + S3C64XX_SPI_CH_CFG);
 255 }
 256
 257 static void s3c64xx_spi_dmacb(void *data)
 258 {
 259         struct s3c64xx_spi_driver_data *sdd;
 260         struct s3c64xx_spi_dma_data *dma = data;
 261         unsigned long flags;
 262
 263         if (dma->direction == DMA_DEV_TO_MEM)
 264                 sdd = container_of(data,
 265                         struct s3c64xx_spi_driver_data, rx_dma);
 266         else
 267                 sdd = container_of(data,
 268                         struct s3c64xx_spi_driver_data, tx_dma);
 269
 270         spin_lock_irqsave(&sdd->lock, flags);
 271
 272         if (dma->direction == DMA_DEV_TO_MEM) {
 273                 sdd->state &= ~RXBUSY;
 274                 if (!(sdd->state & TXBUSY))
 275                         complete(&sdd->xfer_completion);
 276         } else {
 277                 sdd->state &= ~TXBUSY;
 278                 if (!(sdd->state & RXBUSY))
 279                         complete(&sdd->xfer_completion);
 280         }
 281
 282         spin_unlock_irqrestore(&sdd->lock, flags);
 283 }
 284
 285 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 286                                         unsigned len, dma_addr_t buf)
 287 {
 288         struct s3c64xx_spi_driver_data *sdd;
 289         struct samsung_dma_prep info;
 290         struct samsung_dma_config config;
 291
 292         if (dma->direction == DMA_DEV_TO_MEM) {
 293                 sdd = container_of((void *)dma,
 294                         struct s3c64xx_spi_driver_data, rx_dma);
 295                 config.direction = sdd->rx_dma.direction;
 296                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 297                 config.width = sdd->cur_bpw / 8;
 298                 sdd->ops->config(sdd->rx_dma.ch, &config);
 299         } else {
 300                 sdd = container_of((void *)dma,
 301                         struct s3c64xx_spi_driver_data, tx_dma);
 302                 config.direction =  sdd->tx_dma.direction;
 303                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 304                 config.width = sdd->cur_bpw / 8;
 305                 sdd->ops->config(sdd->tx_dma.ch, &config);
 306         }
 307
 308         info.cap = DMA_SLAVE;
 309         info.len = len;
 310         info.fp = s3c64xx_spi_dmacb;
 311         info.fp_param = dma;
 312         info.direction = dma->direction;
 313         info.buf = buf;
 314
 315         sdd->ops->prepare(dma->ch, &info);
 316         sdd->ops->trigger(dma->ch);
 317 }
 318
 319 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 320 {
 321         struct samsung_dma_req req;
 322
 323         sdd->ops = samsung_dma_get_ops();
 324
 325         req.cap = DMA_SLAVE;
 326         req.client = &s3c64xx_spi_dma_client;
 327
 328         req.dt_dmach_prop = sdd->rx_dma.dma_prop;
 329         sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req);
 330         req.dt_dmach_prop = sdd->tx_dma.dma_prop;
 331         sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req);
 332
 333         return 1;
 334 }
 335
 336 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 337                                 struct spi_device *spi,
 338                                 struct spi_transfer *xfer, int dma_mode)
 339 {
 340         void __iomem *regs = sdd->regs;
 341         u32 modecfg, chcfg;
 342
 343         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 344         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 345
 346         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 347         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 348
 349         if (dma_mode) {
 350                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 351         } else {
 352                 /* Always shift in data in FIFO, even if xfer is Tx only,
 353                  * this helps setting PCKT_CNT value for generating clocks
 354                  * as exactly needed.
 355                  */
 356                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 357                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 358                                         | S3C64XX_SPI_PACKET_CNT_EN,
 359                                         regs + S3C64XX_SPI_PACKET_CNT);
 360         }
 361
 362         if (xfer->tx_buf != NULL) {
 363                 sdd->state |= TXBUSY;
 364                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 365                 if (dma_mode) {
 366                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 367                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 368                 } else {
 369                         switch (sdd->cur_bpw) {
 370                         case 32:
 371                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 372                                         xfer->tx_buf, xfer->len / 4);
 373                                 break;
 374                         case 16:
 375                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 376                                         xfer->tx_buf, xfer->len / 2);
 377                                 break;
 378                         default:
 379                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 380                                         xfer->tx_buf, xfer->len);
 381                                 break;
 382                         }
 383                 }
 384         }
 385
 386         if (xfer->rx_buf != NULL) {
 387                 sdd->state |= RXBUSY;
 388
 389                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 390                                         && !(sdd->cur_mode & SPI_CPHA))
 391                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 392
 393                 if (dma_mode) {
 394                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 395                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 396                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 397                                         | S3C64XX_SPI_PACKET_CNT_EN,
 398                                         regs + S3C64XX_SPI_PACKET_CNT);
 399                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 400                 }
 401         }
 402
 403         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 404         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 405 }
 406
 407 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 408                                                 struct spi_device *spi)
 409 {
 410         struct s3c64xx_spi_csinfo *cs;
 411
 412         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 413                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 414                         /* Deselect the last toggled device */
 415                         cs = sdd->tgl_spi->controller_data;
 416                         gpio_set_value(cs->line,
 417                                 spi->mode & SPI_CS_HIGH ? 0 : 1);
 418                 }
 419                 sdd->tgl_spi = NULL;
 420         }
 421
 422         cs = spi->controller_data;
 423         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 424 }
 425
 426 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 427                                 struct spi_transfer *xfer, int dma_mode)
 428 {
 429         void __iomem *regs = sdd->regs;
 430         unsigned long val;
 431         int ms;
 432
 433         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 434         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 435         ms += 10; /* some tolerance */
 436
 437         if (dma_mode) {
 438                 val = msecs_to_jiffies(ms) + 10;
 439                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 440         } else {
 441                 u32 status;
 442                 val = msecs_to_loops(ms);
 443                 do {
 444                         status = readl(regs + S3C64XX_SPI_STATUS);
 445                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 446         }
 447
 448         if (!val)
 449                 return -EIO;
 450
 451         if (dma_mode) {
 452                 u32 status;
 453
 454                 /*
 455                  * DmaTx returns after simply writing data in the FIFO,
 456                  * w/o waiting for real transmission on the bus to finish.
 457                  * DmaRx returns only after Dma read data from FIFO which
 458                  * needs bus transmission to finish, so we don't worry if
 459                  * Xfer involved Rx(with or without Tx).
 460                  */
 461                 if (xfer->rx_buf == NULL) {
 462                         val = msecs_to_loops(10);
 463                         status = readl(regs + S3C64XX_SPI_STATUS);
 464                         while ((TX_FIFO_LVL(status, sdd)
 465                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 466                                         && --val) {
 467                                 cpu_relax();
 468                                 status = readl(regs + S3C64XX_SPI_STATUS);
 469                         }
 470
 471                         if (!val)
 472                                 return -EIO;
 473                 }
 474         } else {
 475                 /* If it was only Tx */
 476                 if (xfer->rx_buf == NULL) {
 477                         sdd->state &= ~TXBUSY;
 478                         return 0;
 479                 }
 480
 481                 switch (sdd->cur_bpw) {
 482                 case 32:
 483                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 484                                 xfer->rx_buf, xfer->len / 4);
 485                         break;
 486                 case 16:
 487                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 488                                 xfer->rx_buf, xfer->len / 2);
 489                         break;
 490                 default:
 491                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 492                                 xfer->rx_buf, xfer->len);
 493                         break;
 494                 }
 495                 sdd->state &= ~RXBUSY;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 502                                                 struct spi_device *spi)
 503 {
 504         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 505
 506         if (sdd->tgl_spi == spi)
 507                 sdd->tgl_spi = NULL;
 508
 509         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 510 }
 511
 512 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 513 {
 514         void __iomem *regs = sdd->regs;
 515         u32 val;
 516
 517         /* Disable Clock */
 518         if (sdd->port_conf->clk_from_cmu) {
 519                 clk_disable(sdd->src_clk);
 520         } else {
 521                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 522                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 523                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 524         }
 525
 526         /* Set Polarity and Phase */
 527         val = readl(regs + S3C64XX_SPI_CH_CFG);
 528         val &= ~(S3C64XX_SPI_CH_SLAVE |
 529                         S3C64XX_SPI_CPOL_L |
 530                         S3C64XX_SPI_CPHA_B);
 531
 532         if (sdd->cur_mode & SPI_CPOL)
 533                 val |= S3C64XX_SPI_CPOL_L;
 534
 535         if (sdd->cur_mode & SPI_CPHA)
 536                 val |= S3C64XX_SPI_CPHA_B;
 537
 538         writel(val, regs + S3C64XX_SPI_CH_CFG);
 539
 540         /* Set Channel & DMA Mode */
 541         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 542         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 543                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 544
 545         switch (sdd->cur_bpw) {
 546         case 32:
 547                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 548                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 549                 break;
 550         case 16:
 551                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 552                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 553                 break;
 554         default:
 555                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 556                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 557                 break;
 558         }
 559
 560         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 561
 562         if (sdd->port_conf->clk_from_cmu) {
 563                 /* Configure Clock */
 564                 /* There is half-multiplier before the SPI */
 565                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 566                 /* Enable Clock */
 567                 clk_enable(sdd->src_clk);
 568         } else {
 569                 /* Configure Clock */
 570                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 571                 val &= ~S3C64XX_SPI_PSR_MASK;
 572                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 573                                 & S3C64XX_SPI_PSR_MASK);
 574                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 575
 576                 /* Enable Clock */
 577                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 578                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 579                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 580         }
 581 }
 582
 583 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 584
 585 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 586                                                 struct spi_message *msg)
 587 {
 588         struct device *dev = &sdd->pdev->dev;
 589         struct spi_transfer *xfer;
 590
 591         if (msg->is_dma_mapped)
 592                 return 0;
 593
 594         /* First mark all xfer unmapped */
 595         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 596                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 597                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 598         }
 599
 600         /* Map until end or first fail */
 601         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 602
 603                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 604                         continue;
 605
 606                 if (xfer->tx_buf != NULL) {
 607                         xfer->tx_dma = dma_map_single(dev,
 608                                         (void *)xfer->tx_buf, xfer->len,
 609                                         DMA_TO_DEVICE);
 610                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 611                                 dev_err(dev, "dma_map_single Tx failed\n");
 612                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 613                                 return -ENOMEM;
 614                         }
 615                 }
 616
 617                 if (xfer->rx_buf != NULL) {
 618                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 619                                                 xfer->len, DMA_FROM_DEVICE);
 620                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 621                                 dev_err(dev, "dma_map_single Rx failed\n");
 622                                 dma_unmap_single(dev, xfer->tx_dma,
 623                                                 xfer->len, DMA_TO_DEVICE);
 624                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 625                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 626                                 return -ENOMEM;
 627                         }
 628                 }
 629         }
 630
 631         return 0;
 632 }
 633
 634 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 635                                                 struct spi_message *msg)
 636 {
 637         struct device *dev = &sdd->pdev->dev;
 638         struct spi_transfer *xfer;
 639
 640         if (msg->is_dma_mapped)
 641                 return;
 642
 643         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 644
 645                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 646                         continue;
 647
 648                 if (xfer->rx_buf != NULL
 649                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 650                         dma_unmap_single(dev, xfer->rx_dma,
 651                                                 xfer->len, DMA_FROM_DEVICE);
 652
 653                 if (xfer->tx_buf != NULL
 654                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 655                         dma_unmap_single(dev, xfer->tx_dma,
 656                                                 xfer->len, DMA_TO_DEVICE);
 657         }
 658 }
 659
 660 static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 661                                             struct spi_message *msg)
 662 {
 663         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 664         struct spi_device *spi = msg->spi;
 665         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 666         struct spi_transfer *xfer;
 667         int status = 0, cs_toggle = 0;
 668         u32 speed;
 669         u8 bpw;
 670
 671         /* If Master's(controller) state differs from that needed by Slave */
 672         if (sdd->cur_speed != spi->max_speed_hz
 673                         || sdd->cur_mode != spi->mode
 674                         || sdd->cur_bpw != spi->bits_per_word) {
 675                 sdd->cur_bpw = spi->bits_per_word;
 676                 sdd->cur_speed = spi->max_speed_hz;
 677                 sdd->cur_mode = spi->mode;
 678                 s3c64xx_spi_config(sdd);
 679         }
 680
 681         /* Map all the transfers if needed */
 682         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 683                 dev_err(&spi->dev,
 684                         "Xfer: Unable to map message buffers!\n");
 685                 status = -ENOMEM;
 686                 goto out;
 687         }
 688
 689         /* Configure feedback delay */
 690         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 691
 692         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 693
 694                 unsigned long flags;
 695                 int use_dma;
 696
 697                 INIT_COMPLETION(sdd->xfer_completion);
 698
 699                 /* Only BPW and Speed may change across transfers */
 700                 bpw = xfer->bits_per_word ? : spi->bits_per_word;
 701                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 702
 703                 if (xfer->len % (bpw / 8)) {
 704                         dev_err(&spi->dev,
 705                                 "Xfer length(%u) not a multiple of word size(%u)\n",
 706                                 xfer->len, bpw / 8);
 707                         status = -EIO;
 708                         goto out;
 709                 }
 710
 711                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 712                         sdd->cur_bpw = bpw;
 713                         sdd->cur_speed = speed;
 714                         s3c64xx_spi_config(sdd);
 715                 }
 716
 717                 /* Polling method for xfers not bigger than FIFO capacity */
 718                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 719                         use_dma = 0;
 720                 else
 721                         use_dma = 1;
 722
 723                 spin_lock_irqsave(&sdd->lock, flags);
 724
 725                 /* Pending only which is to be done */
 726                 sdd->state &= ~RXBUSY;
 727                 sdd->state &= ~TXBUSY;
 728
 729                 enable_datapath(sdd, spi, xfer, use_dma);
 730
 731                 /* Slave Select */
 732                 enable_cs(sdd, spi);
 733
 734                 /* Start the signals */
 735                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 736
 737                 spin_unlock_irqrestore(&sdd->lock, flags);
 738
 739                 status = wait_for_xfer(sdd, xfer, use_dma);
 740
 741                 /* Quiese the signals */
 742                 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 743                        sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 744
 745                 if (status) {
 746                         dev_err(&spi->dev, "I/O Error: "
 747                                 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 748                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 749                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 750                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 751                                 xfer->len);
 752
 753                         if (use_dma) {
 754                                 if (xfer->tx_buf != NULL
 755                                                 && (sdd->state & TXBUSY))
 756                                         sdd->ops->stop(sdd->tx_dma.ch);
 757                                 if (xfer->rx_buf != NULL
 758                                                 && (sdd->state & RXBUSY))
 759                                         sdd->ops->stop(sdd->rx_dma.ch);
 760                         }
 761
 762                         goto out;
 763                 }
 764
 765                 if (xfer->delay_usecs)
 766                         udelay(xfer->delay_usecs);
 767
 768                 if (xfer->cs_change) {
 769                         /* Hint that the next mssg is gonna be
 770                            for the same device */
 771                         if (list_is_last(&xfer->transfer_list,
 772                                                 &msg->transfers))
 773                                 cs_toggle = 1;
 774                         else
 775                                 disable_cs(sdd, spi);
 776                 }
 777
 778                 msg->actual_length += xfer->len;
 779
 780                 flush_fifo(sdd);
 781         }
 782
 783 out:
 784         if (!cs_toggle || status)
 785                 disable_cs(sdd, spi);
 786         else
 787                 sdd->tgl_spi = spi;
 788
 789         s3c64xx_spi_unmap_mssg(sdd, msg);
 790
 791         msg->status = status;
 792
 793         spi_finalize_current_message(master);
 794
 795         return 0;
 796 }
 797
 798 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 799 {
 800         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 801
 802         /* Acquire DMA channels */
 803         while (!acquire_dma(sdd))
 804                 msleep(10);
 805
 806         pm_runtime_get_sync(&sdd->pdev->dev);
 807
 808         return 0;
 809 }
 810
 811 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 812 {
 813         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 814
 815         /* Free DMA channels */
 816         sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
 817         sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
 818
 819         pm_runtime_put(&sdd->pdev->dev);
 820
 821         return 0;
 822 }
 823
 824 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 825                                 struct s3c64xx_spi_driver_data *sdd,
 826                                 struct spi_device *spi)
 827 {
 828         struct s3c64xx_spi_csinfo *cs;
 829         struct device_node *slave_np, *data_np = NULL;
 830         u32 fb_delay = 0;
 831
 832         slave_np = spi->dev.of_node;
 833         if (!slave_np) {
 834                 dev_err(&spi->dev, "device node not found\n");
 835                 return ERR_PTR(-EINVAL);
 836         }
 837
 838         for_each_child_of_node(slave_np, data_np)
 839                 if (!strcmp(data_np->name, "controller-data"))
 840                         break;
 841         if (!data_np) {
 842                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 843                 return ERR_PTR(-EINVAL);
 844         }
 845
 846         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 847         if (!cs) {
 848                 dev_err(&spi->dev, "could not allocate memory for controller"
 849                                         " data\n");
 850                 return ERR_PTR(-ENOMEM);
 851         }
 852
 853         cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
 854         if (!gpio_is_valid(cs->line)) {
 855                 dev_err(&spi->dev, "chip select gpio is not specified or "
 856                                         "invalid\n");
 857                 kfree(cs);
 858                 return ERR_PTR(-EINVAL);
 859         }
 860
 861         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 862         cs->fb_delay = fb_delay;
 863         return cs;
 864 }
 865
 866 /*
 867  * Here we only check the validity of requested configuration
 868  * and save the configuration in a local data-structure.
 869  * The controller is actually configured only just before we
 870  * get a message to transfer.
 871  */
 872 static int s3c64xx_spi_setup(struct spi_device *spi)
 873 {
 874         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 875         struct s3c64xx_spi_driver_data *sdd;
 876         struct s3c64xx_spi_info *sci;
 877         struct spi_message *msg;
 878         unsigned long flags;
 879         int err;
 880
 881         sdd = spi_master_get_devdata(spi->master);
 882         if (!cs && spi->dev.of_node) {
 883                 cs = s3c64xx_get_slave_ctrldata(sdd, spi);
 884                 spi->controller_data = cs;
 885         }
 886
 887         if (IS_ERR_OR_NULL(cs)) {
 888                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 889                 return -ENODEV;
 890         }
 891
 892         if (!spi_get_ctldata(spi)) {
 893                 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
 894                                        dev_name(&spi->dev));
 895                 if (err) {
 896                         dev_err(&spi->dev,
 897                                 "Failed to get /CS gpio [%d]: %d\n",
 898                                 cs->line, err);
 899                         goto err_gpio_req;
 900                 }
 901                 spi_set_ctldata(spi, cs);
 902         }
 903
 904         sci = sdd->cntrlr_info;
 905
 906         spin_lock_irqsave(&sdd->lock, flags);
 907
 908         list_for_each_entry(msg, &sdd->queue, queue) {
 909                 /* Is some mssg is already queued for this device */
 910                 if (msg->spi == spi) {
 911                         dev_err(&spi->dev,
 912                                 "setup: attempt while mssg in queue!\n");
 913                         spin_unlock_irqrestore(&sdd->lock, flags);
 914                         err = -EBUSY;
 915                         goto err_msgq;
 916                 }
 917         }
 918
 919         spin_unlock_irqrestore(&sdd->lock, flags);
 920
 921         if (spi->bits_per_word != 8
 922                         && spi->bits_per_word != 16
 923                         && spi->bits_per_word != 32) {
 924                 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
 925                                                         spi->bits_per_word);
 926                 err = -EINVAL;
 927                 goto setup_exit;
 928         }
 929
 930         pm_runtime_get_sync(&sdd->pdev->dev);
 931
 932         /* Check if we can provide the requested rate */
 933         if (!sdd->port_conf->clk_from_cmu) {
 934                 u32 psr, speed;
 935
 936                 /* Max possible */
 937                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 938
 939                 if (spi->max_speed_hz > speed)
 940                         spi->max_speed_hz = speed;
 941
 942                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 943                 psr &= S3C64XX_SPI_PSR_MASK;
 944                 if (psr == S3C64XX_SPI_PSR_MASK)
 945                         psr--;
 946
 947                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 948                 if (spi->max_speed_hz < speed) {
 949                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 950                                 psr++;
 951                         } else {
 952                                 err = -EINVAL;
 953                                 goto setup_exit;
 954                         }
 955                 }
 956
 957                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 958                 if (spi->max_speed_hz >= speed) {
 959                         spi->max_speed_hz = speed;
 960                 } else {
 961                         err = -EINVAL;
 962                         goto setup_exit;
 963                 }
 964         }
 965
 966         pm_runtime_put(&sdd->pdev->dev);
 967         disable_cs(sdd, spi);
 968         return 0;
 969
 970 setup_exit:
 971         /* setup() returns with device de-selected */
 972         disable_cs(sdd, spi);
 973
 974 err_msgq:
 975         gpio_free(cs->line);
 976         spi_set_ctldata(spi, NULL);
 977
 978 err_gpio_req:
 979         kfree(cs);
 980
 981         return err;
 982 }
 983
 984 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 985 {
 986         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 987
 988         if (cs) {
 989                 gpio_free(cs->line);
 990                 if (spi->dev.of_node)
 991                         kfree(cs);
 992         }
 993         spi_set_ctldata(spi, NULL);
 994 }
 995
 996 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 997 {
 998         struct s3c64xx_spi_driver_data *sdd = data;
 999         struct spi_master *spi = sdd->master;
1000         unsigned int val;
1001
1002         val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
1003
1004         val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1005                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1006                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1007                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1008
1009         writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1010
1011         if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
1012                 dev_err(&spi->dev, "RX overrun\n");
1013         if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
1014                 dev_err(&spi->dev, "RX underrun\n");
1015         if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
1016                 dev_err(&spi->dev, "TX overrun\n");
1017         if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
1018                 dev_err(&spi->dev, "TX underrun\n");
1019
1020         return IRQ_HANDLED;
1021 }
1022
1023 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1024 {
1025         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1026         void __iomem *regs = sdd->regs;
1027         unsigned int val;
1028
1029         sdd->cur_speed = 0;
1030
1031         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1032
1033         /* Disable Interrupts - we use Polling if not DMA mode */
1034         writel(0, regs + S3C64XX_SPI_INT_EN);
1035
1036         if (!sdd->port_conf->clk_from_cmu)
1037                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1038                                 regs + S3C64XX_SPI_CLK_CFG);
1039         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1040         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1041
1042         /* Clear any irq pending bits */
1043         writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
1044                                 regs + S3C64XX_SPI_PENDING_CLR);
1045
1046         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1047
1048         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1049         val &= ~S3C64XX_SPI_MODE_4BURST;
1050         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1051         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1052         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1053
1054         flush_fifo(sdd);
1055 }
1056
1057 static int __devinit s3c64xx_spi_get_dmares(
1058                         struct s3c64xx_spi_driver_data *sdd, bool tx)
1059 {
1060         struct platform_device *pdev = sdd->pdev;
1061         struct s3c64xx_spi_dma_data *dma_data;
1062         struct property *prop;
1063         struct resource *res;
1064         char prop_name[15], *chan_str;
1065
1066         if (tx) {
1067                 dma_data = &sdd->tx_dma;
1068                 dma_data->direction = DMA_MEM_TO_DEV;
1069                 chan_str = "tx";
1070         } else {
1071                 dma_data = &sdd->rx_dma;
1072                 dma_data->direction = DMA_DEV_TO_MEM;
1073                 chan_str = "rx";
1074         }
1075
1076         if (!sdd->pdev->dev.of_node) {
1077                 res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
1078                 if (!res) {
1079                         dev_err(&pdev->dev, "Unable to get SPI-%s dma "
1080                                         "resource\n", chan_str);
1081                         return -ENXIO;
1082                 }
1083                 dma_data->dmach = res->start;
1084                 return 0;
1085         }
1086
1087         sprintf(prop_name, "%s-dma-channel", chan_str);
1088         prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
1089         if (!prop) {
1090                 dev_err(&pdev->dev, "%s dma channel property not specified\n",
1091                                         chan_str);
1092                 return -ENXIO;
1093         }
1094
1095         dma_data->dmach = DMACH_DT_PROP;
1096         dma_data->dma_prop = prop;
1097         return 0;
1098 }
1099
1100 #ifdef CONFIG_OF
1101 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1102 {
1103         struct device *dev = &sdd->pdev->dev;
1104         int idx, gpio, ret;
1105
1106         /* find gpios for mosi, miso and clock lines */
1107         for (idx = 0; idx < 3; idx++) {
1108                 gpio = of_get_gpio(dev->of_node, idx);
1109                 if (!gpio_is_valid(gpio)) {
1110                         dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1111                         goto free_gpio;
1112                 }
1113
1114                 ret = gpio_request(gpio, "spi-bus");
1115                 if (ret) {
1116                         dev_err(dev, "gpio [%d] request failed: %d\n",
1117                                 gpio, ret);
1118                         goto free_gpio;
1119                 }
1120         }
1121         return 0;
1122
1123 free_gpio:
1124         while (--idx >= 0)
1125                 gpio_free(sdd->gpios[idx]);
1126         return -EINVAL;
1127 }
1128
1129 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1130 {
1131         unsigned int idx;
1132         for (idx = 0; idx < 3; idx++)
1133                 gpio_free(sdd->gpios[idx]);
1134 }
1135
1136 static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt(
1137                                                 struct device *dev)
1138 {
1139         struct s3c64xx_spi_info *sci;
1140         u32 temp;
1141
1142         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1143         if (!sci) {
1144                 dev_err(dev, "memory allocation for spi_info failed\n");
1145                 return ERR_PTR(-ENOMEM);
1146         }
1147
1148         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1149                 dev_warn(dev, "spi bus clock parent not specified, using "
1150                                 "clock at index 0 as parent\n");
1151                 sci->src_clk_nr = 0;
1152         } else {
1153                 sci->src_clk_nr = temp;
1154         }
1155
1156         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1157                 dev_warn(dev, "number of chip select lines not specified, "
1158                                 "assuming 1 chip select line\n");
1159                 sci->num_cs = 1;
1160         } else {
1161                 sci->num_cs = temp;
1162         }
1163
1164         return sci;
1165 }
1166 #else
1167 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1168 {
1169         return dev->platform_data;
1170 }
1171
1172 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1173 {
1174         return -EINVAL;
1175 }
1176
1177 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1178 {
1179 }
1180 #endif
1181
1182 static const struct of_device_id s3c64xx_spi_dt_match[];
1183
1184 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1185                                                 struct platform_device *pdev)
1186 {
1187 #ifdef CONFIG_OF
1188         if (pdev->dev.of_node) {
1189                 const struct of_device_id *match;
1190                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1191                 return (struct s3c64xx_spi_port_config *)match->data;
1192         }
1193 #endif
1194         return (struct s3c64xx_spi_port_config *)
1195                          platform_get_device_id(pdev)->driver_data;
1196 }
1197
1198 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1199 {
1200         struct resource *mem_res;
1201         struct s3c64xx_spi_driver_data *sdd;
1202         struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
1203         struct spi_master *master;
1204         int ret, irq;
1205         char clk_name[16];
1206
1207         if (!sci && pdev->dev.of_node) {
1208                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1209                 if (IS_ERR(sci))
1210                         return PTR_ERR(sci);
1211         }
1212
1213         if (!sci) {
1214                 dev_err(&pdev->dev, "platform_data missing!\n");
1215                 return -ENODEV;
1216         }
1217
1218         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1219         if (mem_res == NULL) {
1220                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1221                 return -ENXIO;
1222         }
1223
1224         irq = platform_get_irq(pdev, 0);
1225         if (irq < 0) {
1226                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1227                 return irq;
1228         }
1229
1230         master = spi_alloc_master(&pdev->dev,
1231                                 sizeof(struct s3c64xx_spi_driver_data));
1232         if (master == NULL) {
1233                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1234                 return -ENOMEM;
1235         }
1236
1237         platform_set_drvdata(pdev, master);
1238
1239         sdd = spi_master_get_devdata(master);
1240         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1241         sdd->master = master;
1242         sdd->cntrlr_info = sci;
1243         sdd->pdev = pdev;
1244         sdd->sfr_start = mem_res->start;
1245         if (pdev->dev.of_node) {
1246                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1247                 if (ret < 0) {
1248                         dev_err(&pdev->dev, "failed to get alias id, "
1249                                                 "errno %d\n", ret);
1250                         goto err0;
1251                 }
1252                 sdd->port_id = ret;
1253         } else {
1254                 sdd->port_id = pdev->id;
1255         }
1256
1257         sdd->cur_bpw = 8;
1258
1259         ret = s3c64xx_spi_get_dmares(sdd, true);
1260         if (ret)
1261                 goto err0;
1262
1263         ret = s3c64xx_spi_get_dmares(sdd, false);
1264         if (ret)
1265                 goto err0;
1266
1267         master->dev.of_node = pdev->dev.of_node;
1268         master->bus_num = sdd->port_id;
1269         master->setup = s3c64xx_spi_setup;
1270         master->cleanup = s3c64xx_spi_cleanup;
1271         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1272         master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1273         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1274         master->num_chipselect = sci->num_cs;
1275         master->dma_alignment = 8;
1276         /* the spi->mode bits understood by this driver: */
1277         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1278
1279         sdd->regs = devm_request_and_ioremap(&pdev->dev, mem_res);
1280         if (sdd->regs == NULL) {
1281                 dev_err(&pdev->dev, "Unable to remap IO\n");
1282                 ret = -ENXIO;
1283                 goto err1;
1284         }
1285
1286         if (!sci->cfg_gpio && pdev->dev.of_node) {
1287                 if (s3c64xx_spi_parse_dt_gpio(sdd))
1288                         return -EBUSY;
1289         } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
1290                 dev_err(&pdev->dev, "Unable to config gpio\n");
1291                 ret = -EBUSY;
1292                 goto err2;
1293         }
1294
1295         /* Setup clocks */
1296         sdd->clk = clk_get(&pdev->dev, "spi");
1297         if (IS_ERR(sdd->clk)) {
1298                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1299                 ret = PTR_ERR(sdd->clk);
1300                 goto err3;
1301         }
1302
1303         if (clk_enable(sdd->clk)) {
1304                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1305                 ret = -EBUSY;
1306                 goto err4;
1307         }
1308
1309         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1310         sdd->src_clk = clk_get(&pdev->dev, clk_name);
1311         if (IS_ERR(sdd->src_clk)) {
1312                 dev_err(&pdev->dev,
1313                         "Unable to acquire clock '%s'\n", clk_name);
1314                 ret = PTR_ERR(sdd->src_clk);
1315                 goto err5;
1316         }
1317
1318         if (clk_enable(sdd->src_clk)) {
1319                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1320                 ret = -EBUSY;
1321                 goto err6;
1322         }
1323
1324         /* Setup Deufult Mode */
1325         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1326
1327         spin_lock_init(&sdd->lock);
1328         init_completion(&sdd->xfer_completion);
1329         INIT_LIST_HEAD(&sdd->queue);
1330
1331         ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd);
1332         if (ret != 0) {
1333                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1334                         irq, ret);
1335                 goto err7;
1336         }
1337
1338         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1339                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1340                sdd->regs + S3C64XX_SPI_INT_EN);
1341
1342         if (spi_register_master(master)) {
1343                 dev_err(&pdev->dev, "cannot register SPI master\n");
1344                 ret = -EBUSY;
1345                 goto err8;
1346         }
1347
1348         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1349                                         "with %d Slaves attached\n",
1350                                         sdd->port_id, master->num_chipselect);
1351         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1352                                         mem_res->end, mem_res->start,
1353                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1354
1355         pm_runtime_enable(&pdev->dev);
1356
1357         return 0;
1358
1359 err8:
1360         free_irq(irq, sdd);
1361 err7:
1362         clk_disable(sdd->src_clk);
1363 err6:
1364         clk_put(sdd->src_clk);
1365 err5:
1366         clk_disable(sdd->clk);
1367 err4:
1368         clk_put(sdd->clk);
1369 err3:
1370         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1371                 s3c64xx_spi_dt_gpio_free(sdd);
1372 err2:
1373 err1:
1374 err0:
1375         platform_set_drvdata(pdev, NULL);
1376         spi_master_put(master);
1377
1378         return ret;
1379 }
1380
1381 static int s3c64xx_spi_remove(struct platform_device *pdev)
1382 {
1383         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1384         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1385
1386         pm_runtime_disable(&pdev->dev);
1387
1388         spi_unregister_master(master);
1389
1390         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1391
1392         free_irq(platform_get_irq(pdev, 0), sdd);
1393
1394         clk_disable(sdd->src_clk);
1395         clk_put(sdd->src_clk);
1396
1397         clk_disable(sdd->clk);
1398         clk_put(sdd->clk);
1399
1400         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1401                 s3c64xx_spi_dt_gpio_free(sdd);
1402
1403         platform_set_drvdata(pdev, NULL);
1404         spi_master_put(master);
1405
1406         return 0;
1407 }
1408
1409 #ifdef CONFIG_PM
1410 static int s3c64xx_spi_suspend(struct device *dev)
1411 {
1412         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1413         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1414
1415         spi_master_suspend(master);
1416
1417         /* Disable the clock */
1418         clk_disable(sdd->src_clk);
1419         clk_disable(sdd->clk);
1420
1421         if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1422                 s3c64xx_spi_dt_gpio_free(sdd);
1423
1424         sdd->cur_speed = 0; /* Output Clock is stopped */
1425
1426         return 0;
1427 }
1428
1429 static int s3c64xx_spi_resume(struct device *dev)
1430 {
1431         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1432         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1433         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1434
1435         if (!sci->cfg_gpio && dev->of_node)
1436                 s3c64xx_spi_parse_dt_gpio(sdd);
1437         else
1438                 sci->cfg_gpio();
1439
1440         /* Enable the clock */
1441         clk_enable(sdd->src_clk);
1442         clk_enable(sdd->clk);
1443
1444         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1445
1446         spi_master_resume(master);
1447
1448         return 0;
1449 }
1450 #endif /* CONFIG_PM */
1451
1452 #ifdef CONFIG_PM_RUNTIME
1453 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1454 {
1455         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1456         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1457
1458         clk_disable(sdd->clk);
1459         clk_disable(sdd->src_clk);
1460
1461         return 0;
1462 }
1463
1464 static int s3c64xx_spi_runtime_resume(struct device *dev)
1465 {
1466         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1467         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1468
1469         clk_enable(sdd->src_clk);
1470         clk_enable(sdd->clk);
1471
1472         return 0;
1473 }
1474 #endif /* CONFIG_PM_RUNTIME */
1475
1476 static const struct dev_pm_ops s3c64xx_spi_pm = {
1477         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1478         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1479                            s3c64xx_spi_runtime_resume, NULL)
1480 };
1481
1482 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1483         .fifo_lvl_mask  = { 0x7f },
1484         .rx_lvl_offset  = 13,
1485         .tx_st_done     = 21,
1486         .high_speed     = true,
1487 };
1488
1489 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1490         .fifo_lvl_mask  = { 0x7f, 0x7F },
1491         .rx_lvl_offset  = 13,
1492         .tx_st_done     = 21,
1493 };
1494
1495 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1496         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1497         .rx_lvl_offset  = 15,
1498         .tx_st_done     = 25,
1499 };
1500
1501 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1502         .fifo_lvl_mask  = { 0x7f, 0x7F },
1503         .rx_lvl_offset  = 13,
1504         .tx_st_done     = 21,
1505         .high_speed     = true,
1506 };
1507
1508 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1509         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1510         .rx_lvl_offset  = 15,
1511         .tx_st_done     = 25,
1512         .high_speed     = true,
1513 };
1514
1515 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1516         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1517         .rx_lvl_offset  = 15,
1518         .tx_st_done     = 25,
1519         .high_speed     = true,
1520         .clk_from_cmu   = true,
1521 };
1522
1523 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1524         {
1525                 .name           = "s3c2443-spi",
1526                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1527         }, {
1528                 .name           = "s3c6410-spi",
1529                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1530         }, {
1531                 .name           = "s5p64x0-spi",
1532                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1533         }, {
1534                 .name           = "s5pc100-spi",
1535                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1536         }, {
1537                 .name           = "s5pv210-spi",
1538                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1539         }, {
1540                 .name           = "exynos4210-spi",
1541                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1542         },
1543         { },
1544 };
1545
1546 #ifdef CONFIG_OF
1547 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1548         { .compatible = "samsung,exynos4210-spi",
1549                         .data = (void *)&exynos4_spi_port_config,
1550         },
1551         { },
1552 };
1553 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1554 #endif /* CONFIG_OF */
1555
1556 static struct platform_driver s3c64xx_spi_driver = {
1557         .driver = {
1558                 .name   = "s3c64xx-spi",
1559                 .owner = THIS_MODULE,
1560                 .pm = &s3c64xx_spi_pm,
1561                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1562         },
1563         .remove = s3c64xx_spi_remove,
1564         .id_table = s3c64xx_spi_driver_ids,
1565 };
1566 MODULE_ALIAS("platform:s3c64xx-spi");
1567
1568 static int __init s3c64xx_spi_init(void)
1569 {
1570         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1571 }
1572 subsys_initcall(s3c64xx_spi_init);
1573
1574 static void __exit s3c64xx_spi_exit(void)
1575 {
1576         platform_driver_unregister(&s3c64xx_spi_driver);
1577 }
1578 module_exit(s3c64xx_spi_exit);
1579
1580 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1581 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1582 MODULE_LICENSE("GPL");