drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60 #include "comedi_fc.h"
  61
  62 /* A timeout count */
  63 #define NI_TIMEOUT 1000
  64 static const unsigned old_RTSI_clock_channel = 7;
  65
  66 /* Note: this table must match the ai_gain_* definitions */
  67 static const short ni_gainlkup[][16] = {
  68         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  69                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  70         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  71         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  72                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  73         [ai_gain_4] = {0, 1, 4, 7},
  74         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  75                           0x003, 0x004, 0x005, 0x006},
  76         [ai_gain_622x] = {0, 1, 4, 5},
  77         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  78         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  79 };
  80
  81 static const struct comedi_lrange range_ni_E_ai = {
  82         16, {
  83                 BIP_RANGE(10),
  84                 BIP_RANGE(5),
  85                 BIP_RANGE(2.5),
  86                 BIP_RANGE(1),
  87                 BIP_RANGE(0.5),
  88                 BIP_RANGE(0.25),
  89                 BIP_RANGE(0.1),
  90                 BIP_RANGE(0.05),
  91                 UNI_RANGE(20),
  92                 UNI_RANGE(10),
  93                 UNI_RANGE(5),
  94                 UNI_RANGE(2),
  95                 UNI_RANGE(1),
  96                 UNI_RANGE(0.5),
  97                 UNI_RANGE(0.2),
  98                 UNI_RANGE(0.1)
  99         }
 100 };
 101
 102 static const struct comedi_lrange range_ni_E_ai_limited = {
 103         8, {
 104                 BIP_RANGE(10),
 105                 BIP_RANGE(5),
 106                 BIP_RANGE(1),
 107                 BIP_RANGE(0.1),
 108                 UNI_RANGE(10),
 109                 UNI_RANGE(5),
 110                 UNI_RANGE(1),
 111                 UNI_RANGE(0.1)
 112         }
 113 };
 114
 115 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 116         14, {
 117                 BIP_RANGE(10),
 118                 BIP_RANGE(5),
 119                 BIP_RANGE(2),
 120                 BIP_RANGE(1),
 121                 BIP_RANGE(0.5),
 122                 BIP_RANGE(0.2),
 123                 BIP_RANGE(0.1),
 124                 UNI_RANGE(10),
 125                 UNI_RANGE(5),
 126                 UNI_RANGE(2),
 127                 UNI_RANGE(1),
 128                 UNI_RANGE(0.5),
 129                 UNI_RANGE(0.2),
 130                 UNI_RANGE(0.1)
 131         }
 132 };
 133
 134 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 135         4, {
 136                 BIP_RANGE(10),
 137                 BIP_RANGE(5),
 138                 BIP_RANGE(0.5),
 139                 BIP_RANGE(0.05)
 140         }
 141 };
 142
 143 static const struct comedi_lrange range_ni_E_ai_611x = {
 144         8, {
 145                 BIP_RANGE(50),
 146                 BIP_RANGE(20),
 147                 BIP_RANGE(10),
 148                 BIP_RANGE(5),
 149                 BIP_RANGE(2),
 150                 BIP_RANGE(1),
 151                 BIP_RANGE(0.5),
 152                 BIP_RANGE(0.2)
 153         }
 154 };
 155
 156 static const struct comedi_lrange range_ni_M_ai_622x = {
 157         4, {
 158                 BIP_RANGE(10),
 159                 BIP_RANGE(5),
 160                 BIP_RANGE(1),
 161                 BIP_RANGE(0.2)
 162         }
 163 };
 164
 165 static const struct comedi_lrange range_ni_M_ai_628x = {
 166         7, {
 167                 BIP_RANGE(10),
 168                 BIP_RANGE(5),
 169                 BIP_RANGE(2),
 170                 BIP_RANGE(1),
 171                 BIP_RANGE(0.5),
 172                 BIP_RANGE(0.2),
 173                 BIP_RANGE(0.1)
 174         }
 175 };
 176
 177 static const struct comedi_lrange range_ni_E_ao_ext = {
 178         4, {
 179                 BIP_RANGE(10),
 180                 UNI_RANGE(10),
 181                 RANGE_ext(-1, 1),
 182                 RANGE_ext(0, 1)
 183         }
 184 };
 185
 186 static const struct comedi_lrange *const ni_range_lkup[] = {
 187         [ai_gain_16] = &range_ni_E_ai,
 188         [ai_gain_8] = &range_ni_E_ai_limited,
 189         [ai_gain_14] = &range_ni_E_ai_limited14,
 190         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 191         [ai_gain_611x] = &range_ni_E_ai_611x,
 192         [ai_gain_622x] = &range_ni_M_ai_622x,
 193         [ai_gain_628x] = &range_ni_M_ai_628x,
 194         [ai_gain_6143] = &range_bipolar5
 195 };
 196
 197 static int ni_dio_insn_config(struct comedi_device *dev,
 198                               struct comedi_subdevice *s,
 199                               struct comedi_insn *insn, unsigned int *data);
 200 static int ni_dio_insn_bits(struct comedi_device *dev,
 201                             struct comedi_subdevice *s,
 202                             struct comedi_insn *insn, unsigned int *data);
 203 static int ni_cdio_cmdtest(struct comedi_device *dev,
 204                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 205 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 206 static int ni_cdio_cancel(struct comedi_device *dev,
 207                           struct comedi_subdevice *s);
 208 static void handle_cdio_interrupt(struct comedi_device *dev);
 209 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 210                           unsigned int trignum);
 211
 212 static int ni_serial_insn_config(struct comedi_device *dev,
 213                                  struct comedi_subdevice *s,
 214                                  struct comedi_insn *insn, unsigned int *data);
 215 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 216                                    struct comedi_subdevice *s,
 217                                    unsigned char data_out,
 218                                    unsigned char *data_in);
 219 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 220                                    struct comedi_subdevice *s,
 221                                    unsigned char data_out,
 222                                    unsigned char *data_in);
 223
 224 static int ni_calib_insn_read(struct comedi_device *dev,
 225                               struct comedi_subdevice *s,
 226                               struct comedi_insn *insn, unsigned int *data);
 227 static int ni_calib_insn_write(struct comedi_device *dev,
 228                                struct comedi_subdevice *s,
 229                                struct comedi_insn *insn, unsigned int *data);
 230
 231 static int ni_eeprom_insn_read(struct comedi_device *dev,
 232                                struct comedi_subdevice *s,
 233                                struct comedi_insn *insn, unsigned int *data);
 234 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 235                                         struct comedi_subdevice *s,
 236                                         struct comedi_insn *insn,
 237                                         unsigned int *data);
 238
 239 static int ni_pfi_insn_bits(struct comedi_device *dev,
 240                             struct comedi_subdevice *s,
 241                             struct comedi_insn *insn, unsigned int *data);
 242 static int ni_pfi_insn_config(struct comedi_device *dev,
 243                               struct comedi_subdevice *s,
 244                               struct comedi_insn *insn, unsigned int *data);
 245 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 246                                        unsigned chan);
 247
 248 static void ni_rtsi_init(struct comedi_device *dev);
 249 static int ni_rtsi_insn_bits(struct comedi_device *dev,
 250                              struct comedi_subdevice *s,
 251                              struct comedi_insn *insn, unsigned int *data);
 252 static int ni_rtsi_insn_config(struct comedi_device *dev,
 253                                struct comedi_subdevice *s,
 254                                struct comedi_insn *insn, unsigned int *data);
 255
 256 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 257 static int ni_read_eeprom(struct comedi_device *dev, int addr);
 258
 259 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 260 #ifndef PCIDMA
 261 static void ni_handle_fifo_half_full(struct comedi_device *dev);
 262 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 263                                  struct comedi_subdevice *s);
 264 #endif
 265 static void ni_handle_fifo_dregs(struct comedi_device *dev);
 266 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 267                          unsigned int trignum);
 268 static void ni_load_channelgain_list(struct comedi_device *dev,
 269                                      unsigned int n_chan, unsigned int *list);
 270 static void shutdown_ai_command(struct comedi_device *dev);
 271
 272 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 273                          unsigned int trignum);
 274
 275 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 276
 277 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 278
 279 #ifdef PCIDMA
 280 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 281 #endif
 282 static int ni_gpct_cancel(struct comedi_device *dev,
 283                           struct comedi_subdevice *s);
 284 static void handle_gpct_interrupt(struct comedi_device *dev,
 285                                   unsigned short counter_index);
 286
 287 static int init_cs5529(struct comedi_device *dev);
 288 static int cs5529_do_conversion(struct comedi_device *dev,
 289                                 unsigned short *data);
 290 static int cs5529_ai_insn_read(struct comedi_device *dev,
 291                                struct comedi_subdevice *s,
 292                                struct comedi_insn *insn, unsigned int *data);
 293 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 294                                 unsigned int reg_select_bits);
 295
 296 static int ni_m_series_pwm_config(struct comedi_device *dev,
 297                                   struct comedi_subdevice *s,
 298                                   struct comedi_insn *insn, unsigned int *data);
 299 static int ni_6143_pwm_config(struct comedi_device *dev,
 300                               struct comedi_subdevice *s,
 301                               struct comedi_insn *insn, unsigned int *data);
 302
 303 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 304                                unsigned period_ns);
 305 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 306 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 307
 308 enum aimodes {
 309         AIMODE_NONE = 0,
 310         AIMODE_HALF_FULL = 1,
 311         AIMODE_SCAN = 2,
 312         AIMODE_SAMPLE = 3,
 313 };
 314
 315 enum ni_common_subdevices {
 316         NI_AI_SUBDEV,
 317         NI_AO_SUBDEV,
 318         NI_DIO_SUBDEV,
 319         NI_8255_DIO_SUBDEV,
 320         NI_UNUSED_SUBDEV,
 321         NI_CALIBRATION_SUBDEV,
 322         NI_EEPROM_SUBDEV,
 323         NI_PFI_DIO_SUBDEV,
 324         NI_CS5529_CALIBRATION_SUBDEV,
 325         NI_SERIAL_SUBDEV,
 326         NI_RTSI_SUBDEV,
 327         NI_GPCT0_SUBDEV,
 328         NI_GPCT1_SUBDEV,
 329         NI_FREQ_OUT_SUBDEV,
 330         NI_NUM_SUBDEVICES
 331 };
 332 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 333 {
 334         switch (counter_index) {
 335         case 0:
 336                 return NI_GPCT0_SUBDEV;
 337                 break;
 338         case 1:
 339                 return NI_GPCT1_SUBDEV;
 340                 break;
 341         default:
 342                 break;
 343         }
 344         BUG();
 345         return NI_GPCT0_SUBDEV;
 346 }
 347
 348 enum timebase_nanoseconds {
 349         TIMEBASE_1_NS = 50,
 350         TIMEBASE_2_NS = 10000
 351 };
 352
 353 #define SERIAL_DISABLED         0
 354 #define SERIAL_600NS            600
 355 #define SERIAL_1_2US            1200
 356 #define SERIAL_10US                     10000
 357
 358 static const int num_adc_stages_611x = 3;
 359
 360 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 361                                unsigned ai_mite_status);
 362 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 363                                unsigned ao_mite_status);
 364 static void get_last_sample_611x(struct comedi_device *dev);
 365 static void get_last_sample_6143(struct comedi_device *dev);
 366
 367 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 368                                    unsigned bit_mask, unsigned bit_values)
 369 {
 370         struct ni_private *devpriv = dev->private;
 371         unsigned long flags;
 372
 373         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 374         switch (reg) {
 375         case Interrupt_A_Enable_Register:
 376                 devpriv->int_a_enable_reg &= ~bit_mask;
 377                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 378                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 379                                     Interrupt_A_Enable_Register);
 380                 break;
 381         case Interrupt_B_Enable_Register:
 382                 devpriv->int_b_enable_reg &= ~bit_mask;
 383                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 384                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 385                                     Interrupt_B_Enable_Register);
 386                 break;
 387         case IO_Bidirection_Pin_Register:
 388                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 389                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 390                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 391                                     IO_Bidirection_Pin_Register);
 392                 break;
 393         case AI_AO_Select:
 394                 devpriv->ai_ao_select_reg &= ~bit_mask;
 395                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 396                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 397                 break;
 398         case G0_G1_Select:
 399                 devpriv->g0_g1_select_reg &= ~bit_mask;
 400                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 401                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 402                 break;
 403         default:
 404                 printk("Warning %s() called with invalid register\n", __func__);
 405                 printk("reg is %d\n", reg);
 406                 break;
 407         }
 408         mmiowb();
 409         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 410 }
 411
 412 #ifdef PCIDMA
 413 static int ni_ai_drain_dma(struct comedi_device *dev);
 414
 415 /* DMA channel setup */
 416
 417 /* negative channel means no channel */
 418 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 419 {
 420         unsigned bitfield;
 421
 422         if (channel >= 0) {
 423                 bitfield =
 424                     (ni_stc_dma_channel_select_bitfield(channel) <<
 425                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 426         } else {
 427                 bitfield = 0;
 428         }
 429         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 430 }
 431
 432 /* negative channel means no channel */
 433 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 434 {
 435         unsigned bitfield;
 436
 437         if (channel >= 0) {
 438                 bitfield =
 439                     (ni_stc_dma_channel_select_bitfield(channel) <<
 440                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 441         } else {
 442                 bitfield = 0;
 443         }
 444         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 445 }
 446
 447 /* negative mite_channel means no channel */
 448 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 449                                            unsigned gpct_index,
 450                                            int mite_channel)
 451 {
 452         unsigned bitfield;
 453
 454         if (mite_channel >= 0)
 455                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 456         else
 457                 bitfield = 0;
 458         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 459                         bitfield);
 460 }
 461
 462 /* negative mite_channel means no channel */
 463 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 464                                           int mite_channel)
 465 {
 466         struct ni_private *devpriv = dev->private;
 467         unsigned long flags;
 468
 469         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 470         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 471         if (mite_channel >= 0) {
 472                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 473                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 474                    Definitely works for dma channels 0 and 1. */
 475                 devpriv->cdio_dma_select_reg |=
 476                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 477                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 478         }
 479         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 480         mmiowb();
 481         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 482 }
 483
 484 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 485 {
 486         struct ni_private *devpriv = dev->private;
 487         unsigned long flags;
 488
 489         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 490         BUG_ON(devpriv->ai_mite_chan);
 491         devpriv->ai_mite_chan =
 492             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 493         if (devpriv->ai_mite_chan == NULL) {
 494                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 495                 comedi_error(dev,
 496                              "failed to reserve mite dma channel for analog input.");
 497                 return -EBUSY;
 498         }
 499         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 500         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 501         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 502         return 0;
 503 }
 504
 505 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 506 {
 507         struct ni_private *devpriv = dev->private;
 508         unsigned long flags;
 509
 510         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 511         BUG_ON(devpriv->ao_mite_chan);
 512         devpriv->ao_mite_chan =
 513             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 514         if (devpriv->ao_mite_chan == NULL) {
 515                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 516                 comedi_error(dev,
 517                              "failed to reserve mite dma channel for analog outut.");
 518                 return -EBUSY;
 519         }
 520         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 521         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 522         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 523         return 0;
 524 }
 525
 526 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 527                                         unsigned gpct_index,
 528                                         enum comedi_io_direction direction)
 529 {
 530         struct ni_private *devpriv = dev->private;
 531         unsigned long flags;
 532         struct mite_channel *mite_chan;
 533
 534         BUG_ON(gpct_index >= NUM_GPCT);
 535         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 536         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 537         mite_chan =
 538             mite_request_channel(devpriv->mite,
 539                                  devpriv->gpct_mite_ring[gpct_index]);
 540         if (mite_chan == NULL) {
 541                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 542                 comedi_error(dev,
 543                              "failed to reserve mite dma channel for counter.");
 544                 return -EBUSY;
 545         }
 546         mite_chan->dir = direction;
 547         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 548                                 mite_chan);
 549         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 550         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 551         return 0;
 552 }
 553
 554 #endif /*  PCIDMA */
 555
 556 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 557 {
 558 #ifdef PCIDMA
 559         struct ni_private *devpriv = dev->private;
 560         unsigned long flags;
 561
 562         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 563         BUG_ON(devpriv->cdo_mite_chan);
 564         devpriv->cdo_mite_chan =
 565             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 566         if (devpriv->cdo_mite_chan == NULL) {
 567                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 568                 comedi_error(dev,
 569                              "failed to reserve mite dma channel for correlated digital outut.");
 570                 return -EBUSY;
 571         }
 572         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 573         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 574         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 575 #endif /*  PCIDMA */
 576         return 0;
 577 }
 578
 579 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 580 {
 581 #ifdef PCIDMA
 582         struct ni_private *devpriv = dev->private;
 583         unsigned long flags;
 584
 585         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 586         if (devpriv->ai_mite_chan) {
 587                 ni_set_ai_dma_channel(dev, -1);
 588                 mite_release_channel(devpriv->ai_mite_chan);
 589                 devpriv->ai_mite_chan = NULL;
 590         }
 591         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 592 #endif /*  PCIDMA */
 593 }
 594
 595 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 596 {
 597 #ifdef PCIDMA
 598         struct ni_private *devpriv = dev->private;
 599         unsigned long flags;
 600
 601         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 602         if (devpriv->ao_mite_chan) {
 603                 ni_set_ao_dma_channel(dev, -1);
 604                 mite_release_channel(devpriv->ao_mite_chan);
 605                 devpriv->ao_mite_chan = NULL;
 606         }
 607         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 608 #endif /*  PCIDMA */
 609 }
 610
 611 #ifdef PCIDMA
 612 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 613                                          unsigned gpct_index)
 614 {
 615         struct ni_private *devpriv = dev->private;
 616         unsigned long flags;
 617
 618         BUG_ON(gpct_index >= NUM_GPCT);
 619         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 620         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 621                 struct mite_channel *mite_chan =
 622                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 623
 624                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 625                 ni_tio_set_mite_channel(&devpriv->
 626                                         counter_dev->counters[gpct_index],
 627                                         NULL);
 628                 mite_release_channel(mite_chan);
 629         }
 630         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 631 }
 632 #endif /*  PCIDMA */
 633
 634 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 635 {
 636 #ifdef PCIDMA
 637         struct ni_private *devpriv = dev->private;
 638         unsigned long flags;
 639
 640         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 641         if (devpriv->cdo_mite_chan) {
 642                 ni_set_cdo_dma_channel(dev, -1);
 643                 mite_release_channel(devpriv->cdo_mite_chan);
 644                 devpriv->cdo_mite_chan = NULL;
 645         }
 646         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 647 #endif /*  PCIDMA */
 648 }
 649
 650 /* e-series boards use the second irq signals to generate dma requests for their counters */
 651 #ifdef PCIDMA
 652 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 653                                           unsigned gpct_index, short enable)
 654 {
 655         const struct ni_board_struct *board = comedi_board(dev);
 656         struct ni_private *devpriv = dev->private;
 657
 658         if (board->reg_type & ni_reg_m_series_mask)
 659                 return;
 660         switch (gpct_index) {
 661         case 0:
 662                 if (enable) {
 663                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 664                                             Second_IRQ_A_Enable_Register);
 665                 } else {
 666                         devpriv->stc_writew(dev, 0,
 667                                             Second_IRQ_A_Enable_Register);
 668                 }
 669                 break;
 670         case 1:
 671                 if (enable) {
 672                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 673                                             Second_IRQ_B_Enable_Register);
 674                 } else {
 675                         devpriv->stc_writew(dev, 0,
 676                                             Second_IRQ_B_Enable_Register);
 677                 }
 678                 break;
 679         default:
 680                 BUG();
 681                 break;
 682         }
 683 }
 684 #endif /*  PCIDMA */
 685
 686 static void ni_clear_ai_fifo(struct comedi_device *dev)
 687 {
 688         const struct ni_board_struct *board = comedi_board(dev);
 689         struct ni_private *devpriv = dev->private;
 690
 691         if (board->reg_type == ni_reg_6143) {
 692                 /*  Flush the 6143 data FIFO */
 693                 ni_writel(0x10, AIFIFO_Control_6143);   /*  Flush fifo */
 694                 ni_writel(0x00, AIFIFO_Control_6143);   /*  Flush fifo */
 695                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   /*  Wait for complete */
 696         } else {
 697                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 698                 if (board->reg_type == ni_reg_625x) {
 699                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 700                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 701 #if 0
 702                         /* the NI example code does 3 convert pulses for 625x boards,
 703                            but that appears to be wrong in practice. */
 704                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 705                                             AI_Command_1_Register);
 706                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 707                                             AI_Command_1_Register);
 708                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 709                                             AI_Command_1_Register);
 710 #endif
 711                 }
 712         }
 713 }
 714
 715 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 716 {
 717         struct ni_private *devpriv = dev->private;
 718
 719         devpriv->stc_writew(dev, data >> 16, reg);
 720         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 721 }
 722
 723 static uint32_t win_in2(struct comedi_device *dev, int reg)
 724 {
 725         struct ni_private *devpriv = dev->private;
 726         uint32_t bits;
 727
 728         bits = devpriv->stc_readw(dev, reg) << 16;
 729         bits |= devpriv->stc_readw(dev, reg + 1);
 730         return bits;
 731 }
 732
 733 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 734 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 735                                   int addr)
 736 {
 737         struct ni_private *devpriv = dev->private;
 738         unsigned long flags;
 739
 740         spin_lock_irqsave(&devpriv->window_lock, flags);
 741         ni_writew(addr, AO_Window_Address_611x);
 742         ni_writew(data, AO_Window_Data_611x);
 743         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 744 }
 745
 746 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 747                                   int addr)
 748 {
 749         struct ni_private *devpriv = dev->private;
 750         unsigned long flags;
 751
 752         spin_lock_irqsave(&devpriv->window_lock, flags);
 753         ni_writew(addr, AO_Window_Address_611x);
 754         ni_writel(data, AO_Window_Data_611x);
 755         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 756 }
 757
 758 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 759 {
 760         struct ni_private *devpriv = dev->private;
 761         unsigned long flags;
 762         unsigned short data;
 763
 764         spin_lock_irqsave(&devpriv->window_lock, flags);
 765         ni_writew(addr, AO_Window_Address_611x);
 766         data = ni_readw(AO_Window_Data_611x);
 767         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 768         return data;
 769 }
 770
 771 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 772 * share registers (such as Interrupt_A_Register) without interfering with
 773 * each other.
 774 *
 775 * NOTE: the switch/case statements are optimized out for a constant argument
 776 * so this is actually quite fast---  If you must wrap another function around this
 777 * make it inline to avoid a large speed penalty.
 778 *
 779 * value should only be 1 or 0.
 780 */
 781 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 782                                unsigned bits, unsigned value)
 783 {
 784         unsigned bit_values;
 785
 786         if (value)
 787                 bit_values = bits;
 788         else
 789                 bit_values = 0;
 790         ni_set_bitfield(dev, reg, bits, bit_values);
 791 }
 792
 793 static irqreturn_t ni_E_interrupt(int irq, void *d)
 794 {
 795         struct comedi_device *dev = d;
 796         struct ni_private *devpriv = dev->private;
 797         unsigned short a_status;
 798         unsigned short b_status;
 799         unsigned int ai_mite_status = 0;
 800         unsigned int ao_mite_status = 0;
 801         unsigned long flags;
 802 #ifdef PCIDMA
 803         struct mite_struct *mite = devpriv->mite;
 804 #endif
 805
 806         if (!dev->attached)
 807                 return IRQ_NONE;
 808         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
 809
 810         /*  lock to avoid race with comedi_poll */
 811         spin_lock_irqsave(&dev->spinlock, flags);
 812         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 813         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 814 #ifdef PCIDMA
 815         if (mite) {
 816                 unsigned long flags_too;
 817
 818                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 819                 if (devpriv->ai_mite_chan) {
 820                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 821                         if (ai_mite_status & CHSR_LINKC)
 822                                 writel(CHOR_CLRLC,
 823                                        devpriv->mite->mite_io_addr +
 824                                        MITE_CHOR(devpriv->
 825                                                  ai_mite_chan->channel));
 826                 }
 827                 if (devpriv->ao_mite_chan) {
 828                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 829                         if (ao_mite_status & CHSR_LINKC)
 830                                 writel(CHOR_CLRLC,
 831                                        mite->mite_io_addr +
 832                                        MITE_CHOR(devpriv->
 833                                                  ao_mite_chan->channel));
 834                 }
 835                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 836         }
 837 #endif
 838         ack_a_interrupt(dev, a_status);
 839         ack_b_interrupt(dev, b_status);
 840         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 841                 handle_a_interrupt(dev, a_status, ai_mite_status);
 842         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 843                 handle_b_interrupt(dev, b_status, ao_mite_status);
 844         handle_gpct_interrupt(dev, 0);
 845         handle_gpct_interrupt(dev, 1);
 846         handle_cdio_interrupt(dev);
 847
 848         spin_unlock_irqrestore(&dev->spinlock, flags);
 849         return IRQ_HANDLED;
 850 }
 851
 852 #ifdef PCIDMA
 853 static void ni_sync_ai_dma(struct comedi_device *dev)
 854 {
 855         struct ni_private *devpriv = dev->private;
 856         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 857         unsigned long flags;
 858
 859         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 860         if (devpriv->ai_mite_chan)
 861                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 862         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 863 }
 864
 865 static void mite_handle_b_linkc(struct mite_struct *mite,
 866                                 struct comedi_device *dev)
 867 {
 868         struct ni_private *devpriv = dev->private;
 869         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
 870         unsigned long flags;
 871
 872         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 873         if (devpriv->ao_mite_chan)
 874                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 875         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 876 }
 877
 878 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 879 {
 880         struct ni_private *devpriv = dev->private;
 881         static const int timeout = 10000;
 882         int i;
 883         for (i = 0; i < timeout; i++) {
 884                 unsigned short b_status;
 885
 886                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 887                 if (b_status & AO_FIFO_Half_Full_St)
 888                         break;
 889                 /* if we poll too often, the pci bus activity seems
 890                    to slow the dma transfer down */
 891                 udelay(10);
 892         }
 893         if (i == timeout) {
 894                 comedi_error(dev, "timed out waiting for dma load");
 895                 return -EPIPE;
 896         }
 897         return 0;
 898 }
 899
 900 #endif /* PCIDMA */
 901 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 902 {
 903         struct ni_private *devpriv = dev->private;
 904
 905         if (devpriv->aimode == AIMODE_SCAN) {
 906 #ifdef PCIDMA
 907                 static const int timeout = 10;
 908                 int i;
 909
 910                 for (i = 0; i < timeout; i++) {
 911                         ni_sync_ai_dma(dev);
 912                         if ((s->async->events & COMEDI_CB_EOS))
 913                                 break;
 914                         udelay(1);
 915                 }
 916 #else
 917                 ni_handle_fifo_dregs(dev);
 918                 s->async->events |= COMEDI_CB_EOS;
 919 #endif
 920         }
 921         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 922         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan))
 923                 shutdown_ai_command(dev);
 924 }
 925
 926 static void shutdown_ai_command(struct comedi_device *dev)
 927 {
 928         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 929
 930 #ifdef PCIDMA
 931         ni_ai_drain_dma(dev);
 932 #endif
 933         ni_handle_fifo_dregs(dev);
 934         get_last_sample_611x(dev);
 935         get_last_sample_6143(dev);
 936
 937         s->async->events |= COMEDI_CB_EOA;
 938 }
 939
 940 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
 941 {
 942         if (s->
 943             async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
 944                              COMEDI_CB_EOA)) {
 945                 switch (s->index) {
 946                 case NI_AI_SUBDEV:
 947                         ni_ai_reset(dev, s);
 948                         break;
 949                 case NI_AO_SUBDEV:
 950                         ni_ao_reset(dev, s);
 951                         break;
 952                 case NI_GPCT0_SUBDEV:
 953                 case NI_GPCT1_SUBDEV:
 954                         ni_gpct_cancel(dev, s);
 955                         break;
 956                 case NI_DIO_SUBDEV:
 957                         ni_cdio_cancel(dev, s);
 958                         break;
 959                 default:
 960                         break;
 961                 }
 962         }
 963         comedi_event(dev, s);
 964 }
 965
 966 static void handle_gpct_interrupt(struct comedi_device *dev,
 967                                   unsigned short counter_index)
 968 {
 969 #ifdef PCIDMA
 970         struct ni_private *devpriv = dev->private;
 971         struct comedi_subdevice *s;
 972
 973         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
 974
 975         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
 976                                 s);
 977         if (s->async->events)
 978                 ni_event(dev, s);
 979 #endif
 980 }
 981
 982 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
 983 {
 984         struct ni_private *devpriv = dev->private;
 985         unsigned short ack = 0;
 986
 987         if (a_status & AI_SC_TC_St)
 988                 ack |= AI_SC_TC_Interrupt_Ack;
 989         if (a_status & AI_START1_St)
 990                 ack |= AI_START1_Interrupt_Ack;
 991         if (a_status & AI_START_St)
 992                 ack |= AI_START_Interrupt_Ack;
 993         if (a_status & AI_STOP_St)
 994                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
 995                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */;
 996         if (ack)
 997                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
 998 }
 999
1000 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1001                                unsigned ai_mite_status)
1002 {
1003         struct ni_private *devpriv = dev->private;
1004         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1005
1006         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1007         if (s->type == COMEDI_SUBD_UNUSED)
1008                 return;
1009
1010 #ifdef PCIDMA
1011         if (ai_mite_status & CHSR_LINKC)
1012                 ni_sync_ai_dma(dev);
1013
1014         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1015                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1016                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1017                 printk
1018                     ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1019                      ai_mite_status);
1020                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1021                 /* disable_irq(dev->irq); */
1022         }
1023 #endif
1024
1025         /* test for all uncommon interrupt events at the same time */
1026         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1027                       AI_SC_TC_St | AI_START1_St)) {
1028                 if (status == 0xffff) {
1029                         printk
1030                             ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1031                         /* we probably aren't even running a command now,
1032                          * so it's a good idea to be careful. */
1033                         if (comedi_is_subdevice_running(s)) {
1034                                 s->async->events |=
1035                                     COMEDI_CB_ERROR | COMEDI_CB_EOA;
1036                                 ni_event(dev, s);
1037                         }
1038                         return;
1039                 }
1040                 if (status & (AI_Overrun_St | AI_Overflow_St |
1041                               AI_SC_TC_Error_St)) {
1042                         printk("ni_mio_common: ai error a_status=%04x\n",
1043                                status);
1044
1045                         shutdown_ai_command(dev);
1046
1047                         s->async->events |= COMEDI_CB_ERROR;
1048                         if (status & (AI_Overrun_St | AI_Overflow_St))
1049                                 s->async->events |= COMEDI_CB_OVERFLOW;
1050
1051                         ni_event(dev, s);
1052
1053                         return;
1054                 }
1055                 if (status & AI_SC_TC_St) {
1056                         if (!devpriv->ai_continuous)
1057                                 shutdown_ai_command(dev);
1058                 }
1059         }
1060 #ifndef PCIDMA
1061         if (status & AI_FIFO_Half_Full_St) {
1062                 int i;
1063                 static const int timeout = 10;
1064                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1065                  *fail to get the fifo less than half full, so loop to be sure.*/
1066                 for (i = 0; i < timeout; ++i) {
1067                         ni_handle_fifo_half_full(dev);
1068                         if ((devpriv->stc_readw(dev,
1069                                                 AI_Status_1_Register) &
1070                              AI_FIFO_Half_Full_St) == 0)
1071                                 break;
1072                 }
1073         }
1074 #endif /*  !PCIDMA */
1075
1076         if ((status & AI_STOP_St))
1077                 ni_handle_eos(dev, s);
1078
1079         ni_event(dev, s);
1080 }
1081
1082 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1083 {
1084         struct ni_private *devpriv = dev->private;
1085         unsigned short ack = 0;
1086
1087         if (b_status & AO_BC_TC_St)
1088                 ack |= AO_BC_TC_Interrupt_Ack;
1089         if (b_status & AO_Overrun_St)
1090                 ack |= AO_Error_Interrupt_Ack;
1091         if (b_status & AO_START_St)
1092                 ack |= AO_START_Interrupt_Ack;
1093         if (b_status & AO_START1_St)
1094                 ack |= AO_START1_Interrupt_Ack;
1095         if (b_status & AO_UC_TC_St)
1096                 ack |= AO_UC_TC_Interrupt_Ack;
1097         if (b_status & AO_UI2_TC_St)
1098                 ack |= AO_UI2_TC_Interrupt_Ack;
1099         if (b_status & AO_UPDATE_St)
1100                 ack |= AO_UPDATE_Interrupt_Ack;
1101         if (ack)
1102                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1103 }
1104
1105 static void handle_b_interrupt(struct comedi_device *dev,
1106                                unsigned short b_status, unsigned ao_mite_status)
1107 {
1108         struct ni_private *devpriv = dev->private;
1109         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1110         /* unsigned short ack=0; */
1111
1112 #ifdef PCIDMA
1113         /* Currently, mite.c requires us to handle LINKC */
1114         if (ao_mite_status & CHSR_LINKC)
1115                 mite_handle_b_linkc(devpriv->mite, dev);
1116
1117         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1118                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1119                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1120                 printk
1121                     ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1122                      ao_mite_status);
1123                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1124         }
1125 #endif
1126
1127         if (b_status == 0xffff)
1128                 return;
1129         if (b_status & AO_Overrun_St) {
1130                 printk
1131                     ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1132                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1133                 s->async->events |= COMEDI_CB_OVERFLOW;
1134         }
1135
1136         if (b_status & AO_BC_TC_St)
1137                 s->async->events |= COMEDI_CB_EOA;
1138
1139 #ifndef PCIDMA
1140         if (b_status & AO_FIFO_Request_St) {
1141                 int ret;
1142
1143                 ret = ni_ao_fifo_half_empty(dev, s);
1144                 if (!ret) {
1145                         printk("ni_mio_common: AO buffer underrun\n");
1146                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1147                                     AO_FIFO_Interrupt_Enable |
1148                                     AO_Error_Interrupt_Enable, 0);
1149                         s->async->events |= COMEDI_CB_OVERFLOW;
1150                 }
1151         }
1152 #endif
1153
1154         ni_event(dev, s);
1155 }
1156
1157 #ifndef PCIDMA
1158
1159 static void ni_ao_fifo_load(struct comedi_device *dev,
1160                             struct comedi_subdevice *s, int n)
1161 {
1162         const struct ni_board_struct *board = comedi_board(dev);
1163         struct comedi_async *async = s->async;
1164         struct comedi_cmd *cmd = &async->cmd;
1165         int chan;
1166         int i;
1167         unsigned short d;
1168         u32 packed_data;
1169         int range;
1170         int err = 1;
1171
1172         chan = async->cur_chan;
1173         for (i = 0; i < n; i++) {
1174                 err &= comedi_buf_get(async, &d);
1175                 if (err == 0)
1176                         break;
1177
1178                 range = CR_RANGE(cmd->chanlist[chan]);
1179
1180                 if (board->reg_type & ni_reg_6xxx_mask) {
1181                         packed_data = d & 0xffff;
1182                         /* 6711 only has 16 bit wide ao fifo */
1183                         if (board->reg_type != ni_reg_6711) {
1184                                 err &= comedi_buf_get(async, &d);
1185                                 if (err == 0)
1186                                         break;
1187                                 chan++;
1188                                 i++;
1189                                 packed_data |= (d << 16) & 0xffff0000;
1190                         }
1191                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1192                 } else {
1193                         ni_writew(d, DAC_FIFO_Data);
1194                 }
1195                 chan++;
1196                 chan %= cmd->chanlist_len;
1197         }
1198         async->cur_chan = chan;
1199         if (err == 0)
1200                 async->events |= COMEDI_CB_OVERFLOW;
1201 }
1202
1203 /*
1204  *  There's a small problem if the FIFO gets really low and we
1205  *  don't have the data to fill it.  Basically, if after we fill
1206  *  the FIFO with all the data available, the FIFO is _still_
1207  *  less than half full, we never clear the interrupt.  If the
1208  *  IRQ is in edge mode, we never get another interrupt, because
1209  *  this one wasn't cleared.  If in level mode, we get flooded
1210  *  with interrupts that we can't fulfill, because nothing ever
1211  *  gets put into the buffer.
1212  *
1213  *  This kind of situation is recoverable, but it is easier to
1214  *  just pretend we had a FIFO underrun, since there is a good
1215  *  chance it will happen anyway.  This is _not_ the case for
1216  *  RT code, as RT code might purposely be running close to the
1217  *  metal.  Needs to be fixed eventually.
1218  */
1219 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1220                                  struct comedi_subdevice *s)
1221 {
1222         const struct ni_board_struct *board = comedi_board(dev);
1223         int n;
1224
1225         n = comedi_buf_read_n_available(s->async);
1226         if (n == 0) {
1227                 s->async->events |= COMEDI_CB_OVERFLOW;
1228                 return 0;
1229         }
1230
1231         n /= sizeof(short);
1232         if (n > board->ao_fifo_depth / 2)
1233                 n = board->ao_fifo_depth / 2;
1234
1235         ni_ao_fifo_load(dev, s, n);
1236
1237         s->async->events |= COMEDI_CB_BLOCK;
1238
1239         return 1;
1240 }
1241
1242 static int ni_ao_prep_fifo(struct comedi_device *dev,
1243                            struct comedi_subdevice *s)
1244 {
1245         const struct ni_board_struct *board = comedi_board(dev);
1246         struct ni_private *devpriv = dev->private;
1247         int n;
1248
1249         /* reset fifo */
1250         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1251         if (board->reg_type & ni_reg_6xxx_mask)
1252                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1253
1254         /* load some data */
1255         n = comedi_buf_read_n_available(s->async);
1256         if (n == 0)
1257                 return 0;
1258
1259         n /= sizeof(short);
1260         if (n > board->ao_fifo_depth)
1261                 n = board->ao_fifo_depth;
1262
1263         ni_ao_fifo_load(dev, s, n);
1264
1265         return n;
1266 }
1267
1268 static void ni_ai_fifo_read(struct comedi_device *dev,
1269                             struct comedi_subdevice *s, int n)
1270 {
1271         const struct ni_board_struct *board = comedi_board(dev);
1272         struct ni_private *devpriv = dev->private;
1273         struct comedi_async *async = s->async;
1274         int i;
1275
1276         if (board->reg_type == ni_reg_611x) {
1277                 unsigned short data[2];
1278                 u32 dl;
1279
1280                 for (i = 0; i < n / 2; i++) {
1281                         dl = ni_readl(ADC_FIFO_Data_611x);
1282                         /* This may get the hi/lo data in the wrong order */
1283                         data[0] = (dl >> 16) & 0xffff;
1284                         data[1] = dl & 0xffff;
1285                         cfc_write_array_to_buffer(s, data, sizeof(data));
1286                 }
1287                 /* Check if there's a single sample stuck in the FIFO */
1288                 if (n % 2) {
1289                         dl = ni_readl(ADC_FIFO_Data_611x);
1290                         data[0] = dl & 0xffff;
1291                         cfc_write_to_buffer(s, data[0]);
1292                 }
1293         } else if (board->reg_type == ni_reg_6143) {
1294                 unsigned short data[2];
1295                 u32 dl;
1296
1297                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1298                 for (i = 0; i < n / 2; i++) {
1299                         dl = ni_readl(AIFIFO_Data_6143);
1300
1301                         data[0] = (dl >> 16) & 0xffff;
1302                         data[1] = dl & 0xffff;
1303                         cfc_write_array_to_buffer(s, data, sizeof(data));
1304                 }
1305                 if (n % 2) {
1306                         /* Assume there is a single sample stuck in the FIFO */
1307                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1308                         dl = ni_readl(AIFIFO_Data_6143);
1309                         data[0] = (dl >> 16) & 0xffff;
1310                         cfc_write_to_buffer(s, data[0]);
1311                 }
1312         } else {
1313                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1314                     sizeof(devpriv->ai_fifo_buffer[0])) {
1315                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1316                         async->events |= COMEDI_CB_ERROR;
1317                         return;
1318                 }
1319                 for (i = 0; i < n; i++) {
1320                         devpriv->ai_fifo_buffer[i] =
1321                             ni_readw(ADC_FIFO_Data_Register);
1322                 }
1323                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1324                                           n *
1325                                           sizeof(devpriv->ai_fifo_buffer[0]));
1326         }
1327 }
1328
1329 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1330 {
1331         const struct ni_board_struct *board = comedi_board(dev);
1332         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1333         int n;
1334
1335         n = board->ai_fifo_depth / 2;
1336
1337         ni_ai_fifo_read(dev, s, n);
1338 }
1339 #endif
1340
1341 #ifdef PCIDMA
1342 static int ni_ai_drain_dma(struct comedi_device *dev)
1343 {
1344         struct ni_private *devpriv = dev->private;
1345         int i;
1346         static const int timeout = 10000;
1347         unsigned long flags;
1348         int retval = 0;
1349
1350         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1351         if (devpriv->ai_mite_chan) {
1352                 for (i = 0; i < timeout; i++) {
1353                         if ((devpriv->stc_readw(dev,
1354                                                 AI_Status_1_Register) &
1355                              AI_FIFO_Empty_St)
1356                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1357                             0)
1358                                 break;
1359                         udelay(5);
1360                 }
1361                 if (i == timeout) {
1362                         printk("ni_mio_common: wait for dma drain timed out\n");
1363                         printk
1364                             ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1365                              mite_bytes_in_transit(devpriv->ai_mite_chan),
1366                              devpriv->stc_readw(dev, AI_Status_1_Register));
1367                         retval = -1;
1368                 }
1369         }
1370         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1371
1372         ni_sync_ai_dma(dev);
1373
1374         return retval;
1375 }
1376 #endif
1377 /*
1378    Empties the AI fifo
1379 */
1380 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1381 {
1382         const struct ni_board_struct *board = comedi_board(dev);
1383         struct ni_private *devpriv = dev->private;
1384         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1385         unsigned short data[2];
1386         u32 dl;
1387         unsigned short fifo_empty;
1388         int i;
1389
1390         if (board->reg_type == ni_reg_611x) {
1391                 while ((devpriv->stc_readw(dev,
1392                                            AI_Status_1_Register) &
1393                         AI_FIFO_Empty_St) == 0) {
1394                         dl = ni_readl(ADC_FIFO_Data_611x);
1395
1396                         /* This may get the hi/lo data in the wrong order */
1397                         data[0] = (dl >> 16);
1398                         data[1] = (dl & 0xffff);
1399                         cfc_write_array_to_buffer(s, data, sizeof(data));
1400                 }
1401         } else if (board->reg_type == ni_reg_6143) {
1402                 i = 0;
1403                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1404                         dl = ni_readl(AIFIFO_Data_6143);
1405
1406                         /* This may get the hi/lo data in the wrong order */
1407                         data[0] = (dl >> 16);
1408                         data[1] = (dl & 0xffff);
1409                         cfc_write_array_to_buffer(s, data, sizeof(data));
1410                         i += 2;
1411                 }
1412                 /*  Check if stranded sample is present */
1413                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1414                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1415                         dl = ni_readl(AIFIFO_Data_6143);
1416                         data[0] = (dl >> 16) & 0xffff;
1417                         cfc_write_to_buffer(s, data[0]);
1418                 }
1419
1420         } else {
1421                 fifo_empty =
1422                     devpriv->stc_readw(dev,
1423                                        AI_Status_1_Register) & AI_FIFO_Empty_St;
1424                 while (fifo_empty == 0) {
1425                         for (i = 0;
1426                              i <
1427                              sizeof(devpriv->ai_fifo_buffer) /
1428                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1429                                 fifo_empty =
1430                                     devpriv->stc_readw(dev,
1431                                                        AI_Status_1_Register) &
1432                                     AI_FIFO_Empty_St;
1433                                 if (fifo_empty)
1434                                         break;
1435                                 devpriv->ai_fifo_buffer[i] =
1436                                     ni_readw(ADC_FIFO_Data_Register);
1437                         }
1438                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1439                                                   i *
1440                                                   sizeof(devpriv->
1441                                                          ai_fifo_buffer[0]));
1442                 }
1443         }
1444 }
1445
1446 static void get_last_sample_611x(struct comedi_device *dev)
1447 {
1448         const struct ni_board_struct *board = comedi_board(dev);
1449         struct ni_private *devpriv __maybe_unused = dev->private;
1450         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1451         unsigned short data;
1452         u32 dl;
1453
1454         if (board->reg_type != ni_reg_611x)
1455                 return;
1456
1457         /* Check if there's a single sample stuck in the FIFO */
1458         if (ni_readb(XXX_Status) & 0x80) {
1459                 dl = ni_readl(ADC_FIFO_Data_611x);
1460                 data = (dl & 0xffff);
1461                 cfc_write_to_buffer(s, data);
1462         }
1463 }
1464
1465 static void get_last_sample_6143(struct comedi_device *dev)
1466 {
1467         const struct ni_board_struct *board = comedi_board(dev);
1468         struct ni_private *devpriv __maybe_unused = dev->private;
1469         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1470         unsigned short data;
1471         u32 dl;
1472
1473         if (board->reg_type != ni_reg_6143)
1474                 return;
1475
1476         /* Check if there's a single sample stuck in the FIFO */
1477         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1478                 ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1479                 dl = ni_readl(AIFIFO_Data_6143);
1480
1481                 /* This may get the hi/lo data in the wrong order */
1482                 data = (dl >> 16) & 0xffff;
1483                 cfc_write_to_buffer(s, data);
1484         }
1485 }
1486
1487 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1488                         void *data, unsigned int num_bytes,
1489                         unsigned int chan_index)
1490 {
1491         struct ni_private *devpriv = dev->private;
1492         struct comedi_async *async = s->async;
1493         unsigned int i;
1494         unsigned int length = num_bytes / bytes_per_sample(s);
1495         unsigned short *array = data;
1496         unsigned int *larray = data;
1497
1498         for (i = 0; i < length; i++) {
1499 #ifdef PCIDMA
1500                 if (s->subdev_flags & SDF_LSAMPL)
1501                         larray[i] = le32_to_cpu(larray[i]);
1502                 else
1503                         array[i] = le16_to_cpu(array[i]);
1504 #endif
1505                 if (s->subdev_flags & SDF_LSAMPL)
1506                         larray[i] += devpriv->ai_offset[chan_index];
1507                 else
1508                         array[i] += devpriv->ai_offset[chan_index];
1509                 chan_index++;
1510                 chan_index %= async->cmd.chanlist_len;
1511         }
1512 }
1513
1514 #ifdef PCIDMA
1515
1516 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1517 {
1518         const struct ni_board_struct *board = comedi_board(dev);
1519         struct ni_private *devpriv = dev->private;
1520         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1521         int retval;
1522         unsigned long flags;
1523
1524         retval = ni_request_ai_mite_channel(dev);
1525         if (retval)
1526                 return retval;
1527 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1528
1529         /* write alloc the entire buffer */
1530         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1531
1532         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1533         if (devpriv->ai_mite_chan == NULL) {
1534                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1535                 return -EIO;
1536         }
1537
1538         switch (board->reg_type) {
1539         case ni_reg_611x:
1540         case ni_reg_6143:
1541                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1542                 break;
1543         case ni_reg_628x:
1544                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1545                 break;
1546         default:
1547                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1548                 break;
1549         }
1550         /*start the MITE */
1551         mite_dma_arm(devpriv->ai_mite_chan);
1552         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1553
1554         return 0;
1555 }
1556
1557 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1558 {
1559         const struct ni_board_struct *board = comedi_board(dev);
1560         struct ni_private *devpriv = dev->private;
1561         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1562         int retval;
1563         unsigned long flags;
1564
1565         retval = ni_request_ao_mite_channel(dev);
1566         if (retval)
1567                 return retval;
1568
1569         /* read alloc the entire buffer */
1570         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1571
1572         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1573         if (devpriv->ao_mite_chan) {
1574                 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1575                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1576                 } else {
1577                         /* doing 32 instead of 16 bit wide transfers from memory
1578                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1579                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1580                 }
1581                 mite_dma_arm(devpriv->ao_mite_chan);
1582         } else
1583                 retval = -EIO;
1584         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1585
1586         return retval;
1587 }
1588
1589 #endif /*  PCIDMA */
1590
1591 /*
1592    used for both cancel ioctl and board initialization
1593
1594    this is pretty harsh for a cancel, but it works...
1595  */
1596
1597 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1598 {
1599         const struct ni_board_struct *board = comedi_board(dev);
1600         struct ni_private *devpriv = dev->private;
1601
1602         ni_release_ai_mite_channel(dev);
1603         /* ai configuration */
1604         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1605                             Joint_Reset_Register);
1606
1607         ni_set_bits(dev, Interrupt_A_Enable_Register,
1608                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1609                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1610                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1611                     AI_FIFO_Interrupt_Enable, 0);
1612
1613         ni_clear_ai_fifo(dev);
1614
1615         if (board->reg_type != ni_reg_6143)
1616                 ni_writeb(0, Misc_Command);
1617
1618         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1619         devpriv->stc_writew(dev,
1620                             AI_Start_Stop | AI_Mode_1_Reserved
1621                             /*| AI_Trigger_Once */ ,
1622                             AI_Mode_1_Register);
1623         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1624         /* generate FIFO interrupts on non-empty */
1625         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1626         if (board->reg_type == ni_reg_611x) {
1627                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1628                                     AI_SOC_Polarity |
1629                                     AI_LOCALMUX_CLK_Pulse_Width,
1630                                     AI_Personal_Register);
1631                 devpriv->stc_writew(dev,
1632                                     AI_SCAN_IN_PROG_Output_Select(3) |
1633                                     AI_EXTMUX_CLK_Output_Select(0) |
1634                                     AI_LOCALMUX_CLK_Output_Select(2) |
1635                                     AI_SC_TC_Output_Select(3) |
1636                                     AI_CONVERT_Output_Select
1637                                     (AI_CONVERT_Output_Enable_High),
1638                                     AI_Output_Control_Register);
1639         } else if (board->reg_type == ni_reg_6143) {
1640                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1641                                     AI_SOC_Polarity |
1642                                     AI_LOCALMUX_CLK_Pulse_Width,
1643                                     AI_Personal_Register);
1644                 devpriv->stc_writew(dev,
1645                                     AI_SCAN_IN_PROG_Output_Select(3) |
1646                                     AI_EXTMUX_CLK_Output_Select(0) |
1647                                     AI_LOCALMUX_CLK_Output_Select(2) |
1648                                     AI_SC_TC_Output_Select(3) |
1649                                     AI_CONVERT_Output_Select
1650                                     (AI_CONVERT_Output_Enable_Low),
1651                                     AI_Output_Control_Register);
1652         } else {
1653                 unsigned ai_output_control_bits;
1654                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1655                                     AI_SOC_Polarity |
1656                                     AI_CONVERT_Pulse_Width |
1657                                     AI_LOCALMUX_CLK_Pulse_Width,
1658                                     AI_Personal_Register);
1659                 ai_output_control_bits =
1660                     AI_SCAN_IN_PROG_Output_Select(3) |
1661                     AI_EXTMUX_CLK_Output_Select(0) |
1662                     AI_LOCALMUX_CLK_Output_Select(2) |
1663                     AI_SC_TC_Output_Select(3);
1664                 if (board->reg_type == ni_reg_622x)
1665                         ai_output_control_bits |=
1666                             AI_CONVERT_Output_Select
1667                             (AI_CONVERT_Output_Enable_High);
1668                 else
1669                         ai_output_control_bits |=
1670                             AI_CONVERT_Output_Select
1671                             (AI_CONVERT_Output_Enable_Low);
1672                 devpriv->stc_writew(dev, ai_output_control_bits,
1673                                     AI_Output_Control_Register);
1674         }
1675         /* the following registers should not be changed, because there
1676          * are no backup registers in devpriv.  If you want to change
1677          * any of these, add a backup register and other appropriate code:
1678          *      AI_Mode_1_Register
1679          *      AI_Mode_3_Register
1680          *      AI_Personal_Register
1681          *      AI_Output_Control_Register
1682          */
1683         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1684
1685         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1686
1687         return 0;
1688 }
1689
1690 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1691 {
1692         unsigned long flags;
1693         int count;
1694
1695         /*  lock to avoid race with interrupt handler */
1696         spin_lock_irqsave(&dev->spinlock, flags);
1697 #ifndef PCIDMA
1698         ni_handle_fifo_dregs(dev);
1699 #else
1700         ni_sync_ai_dma(dev);
1701 #endif
1702         count = s->async->buf_write_count - s->async->buf_read_count;
1703         spin_unlock_irqrestore(&dev->spinlock, flags);
1704
1705         return count;
1706 }
1707
1708 static int ni_ai_insn_read(struct comedi_device *dev,
1709                            struct comedi_subdevice *s, struct comedi_insn *insn,
1710                            unsigned int *data)
1711 {
1712         const struct ni_board_struct *board = comedi_board(dev);
1713         struct ni_private *devpriv = dev->private;
1714         int i, n;
1715         const unsigned int mask = (1 << board->adbits) - 1;
1716         unsigned signbits;
1717         unsigned short d;
1718         unsigned long dl;
1719
1720         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1721
1722         ni_clear_ai_fifo(dev);
1723
1724         signbits = devpriv->ai_offset[0];
1725         if (board->reg_type == ni_reg_611x) {
1726                 for (n = 0; n < num_adc_stages_611x; n++) {
1727                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1728                                             AI_Command_1_Register);
1729                         udelay(1);
1730                 }
1731                 for (n = 0; n < insn->n; n++) {
1732                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1733                                             AI_Command_1_Register);
1734                         /* The 611x has screwy 32-bit FIFOs. */
1735                         d = 0;
1736                         for (i = 0; i < NI_TIMEOUT; i++) {
1737                                 if (ni_readb(XXX_Status) & 0x80) {
1738                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1739                                             & 0xffff;
1740                                         break;
1741                                 }
1742                                 if (!(devpriv->stc_readw(dev,
1743                                                          AI_Status_1_Register) &
1744                                       AI_FIFO_Empty_St)) {
1745                                         d = ni_readl(ADC_FIFO_Data_611x) &
1746                                             0xffff;
1747                                         break;
1748                                 }
1749                         }
1750                         if (i == NI_TIMEOUT) {
1751                                 printk
1752                                     ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1753                                 return -ETIME;
1754                         }
1755                         d += signbits;
1756                         data[n] = d;
1757                 }
1758         } else if (board->reg_type == ni_reg_6143) {
1759                 for (n = 0; n < insn->n; n++) {
1760                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1761                                             AI_Command_1_Register);
1762
1763                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1764                         dl = 0;
1765                         for (i = 0; i < NI_TIMEOUT; i++) {
1766                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1767                                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1768                                         dl = ni_readl(AIFIFO_Data_6143);
1769                                         break;
1770                                 }
1771                         }
1772                         if (i == NI_TIMEOUT) {
1773                                 printk
1774                                     ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1775                                 return -ETIME;
1776                         }
1777                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1778                 }
1779         } else {
1780                 for (n = 0; n < insn->n; n++) {
1781                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1782                                             AI_Command_1_Register);
1783                         for (i = 0; i < NI_TIMEOUT; i++) {
1784                                 if (!(devpriv->stc_readw(dev,
1785                                                          AI_Status_1_Register) &
1786                                       AI_FIFO_Empty_St))
1787                                         break;
1788                         }
1789                         if (i == NI_TIMEOUT) {
1790                                 printk
1791                                     ("ni_mio_common: timeout in ni_ai_insn_read\n");
1792                                 return -ETIME;
1793                         }
1794                         if (board->reg_type & ni_reg_m_series_mask) {
1795                                 data[n] =
1796                                     ni_readl(M_Offset_AI_FIFO_Data) & mask;
1797                         } else {
1798                                 d = ni_readw(ADC_FIFO_Data_Register);
1799                                 d += signbits;  /* subtle: needs to be short addition */
1800                                 data[n] = d;
1801                         }
1802                 }
1803         }
1804         return insn->n;
1805 }
1806
1807 static void ni_prime_channelgain_list(struct comedi_device *dev)
1808 {
1809         struct ni_private *devpriv = dev->private;
1810         int i;
1811
1812         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1813         for (i = 0; i < NI_TIMEOUT; ++i) {
1814                 if (!(devpriv->stc_readw(dev,
1815                                          AI_Status_1_Register) &
1816                       AI_FIFO_Empty_St)) {
1817                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1818                         return;
1819                 }
1820                 udelay(1);
1821         }
1822         printk("ni_mio_common: timeout loading channel/gain list\n");
1823 }
1824
1825 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1826                                               unsigned int n_chan,
1827                                               unsigned int *list)
1828 {
1829         const struct ni_board_struct *board = comedi_board(dev);
1830         struct ni_private *devpriv = dev->private;
1831         unsigned int chan, range, aref;
1832         unsigned int i;
1833         unsigned offset;
1834         unsigned int dither;
1835         unsigned range_code;
1836
1837         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1838
1839 /* offset = 1 << (board->adbits - 1); */
1840         if ((list[0] & CR_ALT_SOURCE)) {
1841                 unsigned bypass_bits;
1842                 chan = CR_CHAN(list[0]);
1843                 range = CR_RANGE(list[0]);
1844                 range_code = ni_gainlkup[board->gainlkup][range];
1845                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1846                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1847                 bypass_bits |= chan;
1848                 bypass_bits |=
1849                     (devpriv->ai_calib_source) &
1850                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1851                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1852                      MSeries_AI_Bypass_Mode_Mux_Mask |
1853                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1854                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1855                 if (dither)
1856                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1857                 /*  don't use 2's complement encoding */
1858                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1859                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1860         } else {
1861                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1862         }
1863         offset = 0;
1864         for (i = 0; i < n_chan; i++) {
1865                 unsigned config_bits = 0;
1866                 chan = CR_CHAN(list[i]);
1867                 aref = CR_AREF(list[i]);
1868                 range = CR_RANGE(list[i]);
1869                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1870
1871                 range_code = ni_gainlkup[board->gainlkup][range];
1872                 devpriv->ai_offset[i] = offset;
1873                 switch (aref) {
1874                 case AREF_DIFF:
1875                         config_bits |=
1876                             MSeries_AI_Config_Channel_Type_Differential_Bits;
1877                         break;
1878                 case AREF_COMMON:
1879                         config_bits |=
1880                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1881                         break;
1882                 case AREF_GROUND:
1883                         config_bits |=
1884                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1885                         break;
1886                 case AREF_OTHER:
1887                         break;
1888                 }
1889                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1890                 config_bits |=
1891                     MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
1892                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1893                 if (i == n_chan - 1)
1894                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1895                 if (dither)
1896                         config_bits |= MSeries_AI_Config_Dither_Bit;
1897                 /*  don't use 2's complement encoding */
1898                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1899                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1900         }
1901         ni_prime_channelgain_list(dev);
1902 }
1903
1904 /*
1905  * Notes on the 6110 and 6111:
1906  * These boards a slightly different than the rest of the series, since
1907  * they have multiple A/D converters.
1908  * From the driver side, the configuration memory is a
1909  * little different.
1910  * Configuration Memory Low:
1911  *   bits 15-9: same
1912  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1913  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1914  *       1001 gain=0.1 (+/- 50)
1915  *       1010 0.2
1916  *       1011 0.1
1917  *       0001 1
1918  *       0010 2
1919  *       0011 5
1920  *       0100 10
1921  *       0101 20
1922  *       0110 50
1923  * Configuration Memory High:
1924  *   bits 12-14: Channel Type
1925  *       001 for differential
1926  *       000 for calibration
1927  *   bit 11: coupling  (this is not currently handled)
1928  *       1 AC coupling
1929  *       0 DC coupling
1930  *   bits 0-2: channel
1931  *       valid channels are 0-3
1932  */
1933 static void ni_load_channelgain_list(struct comedi_device *dev,
1934                                      unsigned int n_chan, unsigned int *list)
1935 {
1936         const struct ni_board_struct *board = comedi_board(dev);
1937         struct ni_private *devpriv = dev->private;
1938         unsigned int chan, range, aref;
1939         unsigned int i;
1940         unsigned int hi, lo;
1941         unsigned offset;
1942         unsigned int dither;
1943
1944         if (board->reg_type & ni_reg_m_series_mask) {
1945                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1946                 return;
1947         }
1948         if (n_chan == 1 && (board->reg_type != ni_reg_611x)
1949             && (board->reg_type != ni_reg_6143)) {
1950                 if (devpriv->changain_state
1951                     && devpriv->changain_spec == list[0]) {
1952                         /*  ready to go. */
1953                         return;
1954                 }
1955                 devpriv->changain_state = 1;
1956                 devpriv->changain_spec = list[0];
1957         } else {
1958                 devpriv->changain_state = 0;
1959         }
1960
1961         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1962
1963         /*  Set up Calibration mode if required */
1964         if (board->reg_type == ni_reg_6143) {
1965                 if ((list[0] & CR_ALT_SOURCE)
1966                     && !devpriv->ai_calib_source_enabled) {
1967                         /*  Strobe Relay enable bit */
1968                         ni_writew(devpriv->ai_calib_source |
1969                                   Calibration_Channel_6143_RelayOn,
1970                                   Calibration_Channel_6143);
1971                         ni_writew(devpriv->ai_calib_source,
1972                                   Calibration_Channel_6143);
1973                         devpriv->ai_calib_source_enabled = 1;
1974                         msleep_interruptible(100);      /*  Allow relays to change */
1975                 } else if (!(list[0] & CR_ALT_SOURCE)
1976                            && devpriv->ai_calib_source_enabled) {
1977                         /*  Strobe Relay disable bit */
1978                         ni_writew(devpriv->ai_calib_source |
1979                                   Calibration_Channel_6143_RelayOff,
1980                                   Calibration_Channel_6143);
1981                         ni_writew(devpriv->ai_calib_source,
1982                                   Calibration_Channel_6143);
1983                         devpriv->ai_calib_source_enabled = 0;
1984                         msleep_interruptible(100);      /*  Allow relays to change */
1985                 }
1986         }
1987
1988         offset = 1 << (board->adbits - 1);
1989         for (i = 0; i < n_chan; i++) {
1990                 if ((board->reg_type != ni_reg_6143)
1991                     && (list[i] & CR_ALT_SOURCE)) {
1992                         chan = devpriv->ai_calib_source;
1993                 } else {
1994                         chan = CR_CHAN(list[i]);
1995                 }
1996                 aref = CR_AREF(list[i]);
1997                 range = CR_RANGE(list[i]);
1998                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1999
2000                 /* fix the external/internal range differences */
2001                 range = ni_gainlkup[board->gainlkup][range];
2002                 if (board->reg_type == ni_reg_611x)
2003                         devpriv->ai_offset[i] = offset;
2004                 else
2005                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2006
2007                 hi = 0;
2008                 if ((list[i] & CR_ALT_SOURCE)) {
2009                         if (board->reg_type == ni_reg_611x)
2010                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2011                                           Calibration_Channel_Select_611x);
2012                 } else {
2013                         if (board->reg_type == ni_reg_611x)
2014                                 aref = AREF_DIFF;
2015                         else if (board->reg_type == ni_reg_6143)
2016                                 aref = AREF_OTHER;
2017                         switch (aref) {
2018                         case AREF_DIFF:
2019                                 hi |= AI_DIFFERENTIAL;
2020                                 break;
2021                         case AREF_COMMON:
2022                                 hi |= AI_COMMON;
2023                                 break;
2024                         case AREF_GROUND:
2025                                 hi |= AI_GROUND;
2026                                 break;
2027                         case AREF_OTHER:
2028                                 break;
2029                         }
2030                 }
2031                 hi |= AI_CONFIG_CHANNEL(chan);
2032
2033                 ni_writew(hi, Configuration_Memory_High);
2034
2035                 if (board->reg_type != ni_reg_6143) {
2036                         lo = range;
2037                         if (i == n_chan - 1)
2038                                 lo |= AI_LAST_CHANNEL;
2039                         if (dither)
2040                                 lo |= AI_DITHER;
2041
2042                         ni_writew(lo, Configuration_Memory_Low);
2043                 }
2044         }
2045
2046         /* prime the channel/gain list */
2047         if ((board->reg_type != ni_reg_611x)
2048             && (board->reg_type != ni_reg_6143)) {
2049                 ni_prime_channelgain_list(dev);
2050         }
2051 }
2052
2053 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2054                           int round_mode)
2055 {
2056         struct ni_private *devpriv = dev->private;
2057         int divider;
2058
2059         switch (round_mode) {
2060         case TRIG_ROUND_NEAREST:
2061         default:
2062                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2063                 break;
2064         case TRIG_ROUND_DOWN:
2065                 divider = (nanosec) / devpriv->clock_ns;
2066                 break;
2067         case TRIG_ROUND_UP:
2068                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2069                 break;
2070         }
2071         return divider - 1;
2072 }
2073
2074 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2075 {
2076         struct ni_private *devpriv = dev->private;
2077
2078         return devpriv->clock_ns * (timer + 1);
2079 }
2080
2081 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2082                                          unsigned num_channels)
2083 {
2084         const struct ni_board_struct *board = comedi_board(dev);
2085
2086         switch (board->reg_type) {
2087         case ni_reg_611x:
2088         case ni_reg_6143:
2089                 /*  simultaneously-sampled inputs */
2090                 return board->ai_speed;
2091                 break;
2092         default:
2093                 /*  multiplexed inputs */
2094                 break;
2095         }
2096         return board->ai_speed * num_channels;
2097 }
2098
2099 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2100                          struct comedi_cmd *cmd)
2101 {
2102         const struct ni_board_struct *board = comedi_board(dev);
2103         struct ni_private *devpriv = dev->private;
2104         int err = 0;
2105         int tmp;
2106         unsigned int sources;
2107
2108         /* Step 1 : check if triggers are trivially valid */
2109
2110         if ((cmd->flags & CMDF_WRITE))
2111                 cmd->flags &= ~CMDF_WRITE;
2112
2113         err |= cfc_check_trigger_src(&cmd->start_src,
2114                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2115         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2116                                         TRIG_TIMER | TRIG_EXT);
2117
2118         sources = TRIG_TIMER | TRIG_EXT;
2119         if (board->reg_type == ni_reg_611x ||
2120             board->reg_type == ni_reg_6143)
2121                 sources |= TRIG_NOW;
2122         err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2123
2124         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2125         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2126
2127         if (err)
2128                 return 1;
2129
2130         /* Step 2a : make sure trigger sources are unique */
2131
2132         err |= cfc_check_trigger_is_unique(cmd->start_src);
2133         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2134         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2135         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2136
2137         /* Step 2b : and mutually compatible */
2138
2139         if (err)
2140                 return 2;
2141
2142         /* Step 3: check if arguments are trivially valid */
2143
2144         if (cmd->start_src == TRIG_EXT) {
2145                 /* external trigger */
2146                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2147
2148                 if (tmp > 16)
2149                         tmp = 16;
2150                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2151                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2152         } else {
2153                 /* true for both TRIG_NOW and TRIG_INT */
2154                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2155         }
2156
2157         if (cmd->scan_begin_src == TRIG_TIMER) {
2158                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2159                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2160                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2161                                                  devpriv->clock_ns * 0xffffff);
2162         } else if (cmd->scan_begin_src == TRIG_EXT) {
2163                 /* external trigger */
2164                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2165
2166                 if (tmp > 16)
2167                         tmp = 16;
2168                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2169                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2170         } else {                /* TRIG_OTHER */
2171                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2172         }
2173
2174         if (cmd->convert_src == TRIG_TIMER) {
2175                 if ((board->reg_type == ni_reg_611x)
2176                     || (board->reg_type == ni_reg_6143)) {
2177                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2178                 } else {
2179                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2180                                                          board->ai_speed);
2181                         err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2182                                                 devpriv->clock_ns * 0xffff);
2183                 }
2184         } else if (cmd->convert_src == TRIG_EXT) {
2185                 /* external trigger */
2186                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2187
2188                 if (tmp > 16)
2189                         tmp = 16;
2190                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2191                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2192         } else if (cmd->convert_src == TRIG_NOW) {
2193                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2194         }
2195
2196         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2197
2198         if (cmd->stop_src == TRIG_COUNT) {
2199                 unsigned int max_count = 0x01000000;
2200
2201                 if (board->reg_type == ni_reg_611x)
2202                         max_count -= num_adc_stages_611x;
2203                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2204                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2205         } else {
2206                 /* TRIG_NONE */
2207                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2208         }
2209
2210         if (err)
2211                 return 3;
2212
2213         /* step 4: fix up any arguments */
2214
2215         if (cmd->scan_begin_src == TRIG_TIMER) {
2216                 tmp = cmd->scan_begin_arg;
2217                 cmd->scan_begin_arg =
2218                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2219                                                        cmd->scan_begin_arg,
2220                                                        cmd->
2221                                                        flags &
2222                                                        TRIG_ROUND_MASK));
2223                 if (tmp != cmd->scan_begin_arg)
2224                         err++;
2225         }
2226         if (cmd->convert_src == TRIG_TIMER) {
2227                 if ((board->reg_type != ni_reg_611x)
2228                     && (board->reg_type != ni_reg_6143)) {
2229                         tmp = cmd->convert_arg;
2230                         cmd->convert_arg =
2231                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2232                                                                cmd->convert_arg,
2233                                                                cmd->
2234                                                                flags &
2235                                                                TRIG_ROUND_MASK));
2236                         if (tmp != cmd->convert_arg)
2237                                 err++;
2238                         if (cmd->scan_begin_src == TRIG_TIMER &&
2239                             cmd->scan_begin_arg <
2240                             cmd->convert_arg * cmd->scan_end_arg) {
2241                                 cmd->scan_begin_arg =
2242                                     cmd->convert_arg * cmd->scan_end_arg;
2243                                 err++;
2244                         }
2245                 }
2246         }
2247
2248         if (err)
2249                 return 4;
2250
2251         return 0;
2252 }
2253
2254 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2255 {
2256         const struct ni_board_struct *board = comedi_board(dev);
2257         struct ni_private *devpriv = dev->private;
2258         const struct comedi_cmd *cmd = &s->async->cmd;
2259         int timer;
2260         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2261         int mode2 = 0;
2262         int start_stop_select = 0;
2263         unsigned int stop_count;
2264         int interrupt_a_enable = 0;
2265
2266         if (dev->irq == 0) {
2267                 comedi_error(dev, "cannot run command without an irq");
2268                 return -EIO;
2269         }
2270         ni_clear_ai_fifo(dev);
2271
2272         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2273
2274         /* start configuration */
2275         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2276
2277         /* disable analog triggering for now, since it
2278          * interferes with the use of pfi0 */
2279         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2280         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2281                             Analog_Trigger_Etc_Register);
2282
2283         switch (cmd->start_src) {
2284         case TRIG_INT:
2285         case TRIG_NOW:
2286                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2287                                     AI_START1_Sync | AI_START1_Edge |
2288                                     AI_START1_Select(0),
2289                                     AI_Trigger_Select_Register);
2290                 break;
2291         case TRIG_EXT:
2292                 {
2293                         int chan = CR_CHAN(cmd->start_arg);
2294                         unsigned int bits = AI_START2_Select(0) |
2295                             AI_START1_Sync | AI_START1_Select(chan + 1);
2296
2297                         if (cmd->start_arg & CR_INVERT)
2298                                 bits |= AI_START1_Polarity;
2299                         if (cmd->start_arg & CR_EDGE)
2300                                 bits |= AI_START1_Edge;
2301                         devpriv->stc_writew(dev, bits,
2302                                             AI_Trigger_Select_Register);
2303                         break;
2304                 }
2305         }
2306
2307         mode2 &= ~AI_Pre_Trigger;
2308         mode2 &= ~AI_SC_Initial_Load_Source;
2309         mode2 &= ~AI_SC_Reload_Mode;
2310         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2311
2312         if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2313             || (board->reg_type == ni_reg_6143)) {
2314                 start_stop_select |= AI_STOP_Polarity;
2315                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2316                 start_stop_select |= AI_STOP_Sync;
2317         } else {
2318                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2319         }
2320         devpriv->stc_writew(dev, start_stop_select,
2321                             AI_START_STOP_Select_Register);
2322
2323         devpriv->ai_cmd2 = 0;
2324         switch (cmd->stop_src) {
2325         case TRIG_COUNT:
2326                 stop_count = cmd->stop_arg - 1;
2327
2328                 if (board->reg_type == ni_reg_611x) {
2329                         /*  have to take 3 stage adc pipeline into account */
2330                         stop_count += num_adc_stages_611x;
2331                 }
2332                 /* stage number of scans */
2333                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2334
2335                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2336                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2337                 /* load SC (Scan Count) */
2338                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2339
2340                 devpriv->ai_continuous = 0;
2341                 if (stop_count == 0) {
2342                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2343                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2344                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2345                         if (cmd->chanlist_len > 1)
2346                                 start_stop_select |=
2347                                     AI_STOP_Polarity | AI_STOP_Edge;
2348                 }
2349                 break;
2350         case TRIG_NONE:
2351                 /* stage number of scans */
2352                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2353
2354                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2355                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2356
2357                 /* load SC (Scan Count) */
2358                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2359
2360                 devpriv->ai_continuous = 1;
2361
2362                 break;
2363         }
2364
2365         switch (cmd->scan_begin_src) {
2366         case TRIG_TIMER:
2367                 /*
2368                    stop bits for non 611x boards
2369                    AI_SI_Special_Trigger_Delay=0
2370                    AI_Pre_Trigger=0
2371                    AI_START_STOP_Select_Register:
2372                    AI_START_Polarity=0 (?)      rising edge
2373                    AI_START_Edge=1              edge triggered
2374                    AI_START_Sync=1 (?)
2375                    AI_START_Select=0            SI_TC
2376                    AI_STOP_Polarity=0           rising edge
2377                    AI_STOP_Edge=0               level
2378                    AI_STOP_Sync=1
2379                    AI_STOP_Select=19            external pin (configuration mem)
2380                  */
2381                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2382                 devpriv->stc_writew(dev, start_stop_select,
2383                                     AI_START_STOP_Select_Register);
2384
2385                 mode2 |= AI_SI_Reload_Mode(0);
2386                 /* AI_SI_Initial_Load_Source=A */
2387                 mode2 &= ~AI_SI_Initial_Load_Source;
2388                 /* mode2 |= AI_SC_Reload_Mode; */
2389                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2390
2391                 /* load SI */
2392                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2393                                        TRIG_ROUND_NEAREST);
2394                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2395                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2396                 break;
2397         case TRIG_EXT:
2398                 if (cmd->scan_begin_arg & CR_EDGE)
2399                         start_stop_select |= AI_START_Edge;
2400                 /* AI_START_Polarity==1 is falling edge */
2401                 if (cmd->scan_begin_arg & CR_INVERT)
2402                         start_stop_select |= AI_START_Polarity;
2403                 if (cmd->scan_begin_src != cmd->convert_src ||
2404                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2405                     (cmd->convert_arg & ~CR_EDGE))
2406                         start_stop_select |= AI_START_Sync;
2407                 start_stop_select |=
2408                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2409                 devpriv->stc_writew(dev, start_stop_select,
2410                                     AI_START_STOP_Select_Register);
2411                 break;
2412         }
2413
2414         switch (cmd->convert_src) {
2415         case TRIG_TIMER:
2416         case TRIG_NOW:
2417                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2418                         timer = 1;
2419                 else
2420                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2421                                                TRIG_ROUND_NEAREST);
2422                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2423                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2424
2425                 /* AI_SI2_Reload_Mode = alternate */
2426                 /* AI_SI2_Initial_Load_Source = A */
2427                 mode2 &= ~AI_SI2_Initial_Load_Source;
2428                 mode2 |= AI_SI2_Reload_Mode;
2429                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2430
2431                 /* AI_SI2_Load */
2432                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2433
2434                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2435                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2436
2437                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2438                 break;
2439         case TRIG_EXT:
2440                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2441                 if ((cmd->convert_arg & CR_INVERT) == 0)
2442                         mode1 |= AI_CONVERT_Source_Polarity;
2443                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2444
2445                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2446                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2447
2448                 break;
2449         }
2450
2451         if (dev->irq) {
2452
2453                 /* interrupt on FIFO, errors, SC_TC */
2454                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2455                     AI_SC_TC_Interrupt_Enable;
2456
2457 #ifndef PCIDMA
2458                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2459 #endif
2460
2461                 if (cmd->flags & TRIG_WAKE_EOS
2462                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2463                         /* wake on end-of-scan */
2464                         devpriv->aimode = AIMODE_SCAN;
2465                 } else {
2466                         devpriv->aimode = AIMODE_HALF_FULL;
2467                 }
2468
2469                 switch (devpriv->aimode) {
2470                 case AIMODE_HALF_FULL:
2471                         /*generate FIFO interrupts and DMA requests on half-full */
2472 #ifdef PCIDMA
2473                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2474                                             AI_Mode_3_Register);
2475 #else
2476                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2477                                             AI_Mode_3_Register);
2478 #endif
2479                         break;
2480                 case AIMODE_SAMPLE:
2481                         /*generate FIFO interrupts on non-empty */
2482                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2483                                             AI_Mode_3_Register);
2484                         break;
2485                 case AIMODE_SCAN:
2486 #ifdef PCIDMA
2487                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2488                                             AI_Mode_3_Register);
2489 #else
2490                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2491                                             AI_Mode_3_Register);
2492 #endif
2493                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2494                         break;
2495                 default:
2496                         break;
2497                 }
2498
2499                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2500
2501                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2502                             interrupt_a_enable, 1);
2503         } else {
2504                 /* interrupt on nothing */
2505                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2506
2507                 /* XXX start polling if necessary */
2508         }
2509
2510         /* end configuration */
2511         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2512
2513         switch (cmd->scan_begin_src) {
2514         case TRIG_TIMER:
2515                 devpriv->stc_writew(dev,
2516                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2517                                     AI_SC_Arm, AI_Command_1_Register);
2518                 break;
2519         case TRIG_EXT:
2520                 /* XXX AI_SI_Arm? */
2521                 devpriv->stc_writew(dev,
2522                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2523                                     AI_SC_Arm, AI_Command_1_Register);
2524                 break;
2525         }
2526
2527 #ifdef PCIDMA
2528         {
2529                 int retval = ni_ai_setup_MITE_dma(dev);
2530                 if (retval)
2531                         return retval;
2532         }
2533 #endif
2534
2535         switch (cmd->start_src) {
2536         case TRIG_NOW:
2537                 /* AI_START1_Pulse */
2538                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2539                                     AI_Command_2_Register);
2540                 s->async->inttrig = NULL;
2541                 break;
2542         case TRIG_EXT:
2543                 s->async->inttrig = NULL;
2544                 break;
2545         case TRIG_INT:
2546                 s->async->inttrig = &ni_ai_inttrig;
2547                 break;
2548         }
2549
2550         return 0;
2551 }
2552
2553 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2554                          unsigned int trignum)
2555 {
2556         struct ni_private *devpriv = dev->private;
2557
2558         if (trignum != 0)
2559                 return -EINVAL;
2560
2561         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2562                             AI_Command_2_Register);
2563         s->async->inttrig = NULL;
2564
2565         return 1;
2566 }
2567
2568 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2569                                     struct comedi_subdevice *s,
2570                                     struct comedi_insn *insn,
2571                                     unsigned int *data);
2572
2573 static int ni_ai_insn_config(struct comedi_device *dev,
2574                              struct comedi_subdevice *s,
2575                              struct comedi_insn *insn, unsigned int *data)
2576 {
2577         const struct ni_board_struct *board = comedi_board(dev);
2578         struct ni_private *devpriv = dev->private;
2579
2580         if (insn->n < 1)
2581                 return -EINVAL;
2582
2583         switch (data[0]) {
2584         case INSN_CONFIG_ANALOG_TRIG:
2585                 return ni_ai_config_analog_trig(dev, s, insn, data);
2586         case INSN_CONFIG_ALT_SOURCE:
2587                 if (board->reg_type & ni_reg_m_series_mask) {
2588                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2589                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2590                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2591                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2592                                 return -EINVAL;
2593                         }
2594                         devpriv->ai_calib_source = data[1];
2595                 } else if (board->reg_type == ni_reg_6143) {
2596                         unsigned int calib_source;
2597
2598                         calib_source = data[1] & 0xf;
2599
2600                         if (calib_source > 0xF)
2601                                 return -EINVAL;
2602
2603                         devpriv->ai_calib_source = calib_source;
2604                         ni_writew(calib_source, Calibration_Channel_6143);
2605                 } else {
2606                         unsigned int calib_source;
2607                         unsigned int calib_source_adjust;
2608
2609                         calib_source = data[1] & 0xf;
2610                         calib_source_adjust = (data[1] >> 4) & 0xff;
2611
2612                         if (calib_source >= 8)
2613                                 return -EINVAL;
2614                         devpriv->ai_calib_source = calib_source;
2615                         if (board->reg_type == ni_reg_611x) {
2616                                 ni_writeb(calib_source_adjust,
2617                                           Cal_Gain_Select_611x);
2618                         }
2619                 }
2620                 return 2;
2621         default:
2622                 break;
2623         }
2624
2625         return -EINVAL;
2626 }
2627
2628 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2629                                     struct comedi_subdevice *s,
2630                                     struct comedi_insn *insn,
2631                                     unsigned int *data)
2632 {
2633         const struct ni_board_struct *board = comedi_board(dev);
2634         struct ni_private *devpriv = dev->private;
2635         unsigned int a, b, modebits;
2636         int err = 0;
2637
2638         /* data[1] is flags
2639          * data[2] is analog line
2640          * data[3] is set level
2641          * data[4] is reset level */
2642         if (!board->has_analog_trig)
2643                 return -EINVAL;
2644         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2645                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2646                 err++;
2647         }
2648         if (data[2] >= board->n_adchan) {
2649                 data[2] = board->n_adchan - 1;
2650                 err++;
2651         }
2652         if (data[3] > 255) {    /* a */
2653                 data[3] = 255;
2654                 err++;
2655         }
2656         if (data[4] > 255) {    /* b */
2657                 data[4] = 255;
2658                 err++;
2659         }
2660         /*
2661          * 00 ignore
2662          * 01 set
2663          * 10 reset
2664          *
2665          * modes:
2666          *   1 level:                    +b-   +a-
2667          *     high mode                00 00 01 10
2668          *     low mode                 00 00 10 01
2669          *   2 level: (a<b)
2670          *     hysteresis low mode      10 00 00 01
2671          *     hysteresis high mode     01 00 00 10
2672          *     middle mode              10 01 01 10
2673          */
2674
2675         a = data[3];
2676         b = data[4];
2677         modebits = data[1] & 0xff;
2678         if (modebits & 0xf0) {
2679                 /* two level mode */
2680                 if (b < a) {
2681                         /* swap order */
2682                         a = data[4];
2683                         b = data[3];
2684                         modebits =
2685                             ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2686                 }
2687                 devpriv->atrig_low = a;
2688                 devpriv->atrig_high = b;
2689                 switch (modebits) {
2690                 case 0x81:      /* low hysteresis mode */
2691                         devpriv->atrig_mode = 6;
2692                         break;
2693                 case 0x42:      /* high hysteresis mode */
2694                         devpriv->atrig_mode = 3;
2695                         break;
2696                 case 0x96:      /* middle window mode */
2697                         devpriv->atrig_mode = 2;
2698                         break;
2699                 default:
2700                         data[1] &= ~0xff;
2701                         err++;
2702                 }
2703         } else {
2704                 /* one level mode */
2705                 if (b != 0) {
2706                         data[4] = 0;
2707                         err++;
2708                 }
2709                 switch (modebits) {
2710                 case 0x06:      /* high window mode */
2711                         devpriv->atrig_high = a;
2712                         devpriv->atrig_mode = 0;
2713                         break;
2714                 case 0x09:      /* low window mode */
2715                         devpriv->atrig_low = a;
2716                         devpriv->atrig_mode = 1;
2717                         break;
2718                 default:
2719                         data[1] &= ~0xff;
2720                         err++;
2721                 }
2722         }
2723         if (err)
2724                 return -EAGAIN;
2725         return 5;
2726 }
2727
2728 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2729 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2730                         void *data, unsigned int num_bytes,
2731                         unsigned int chan_index)
2732 {
2733         const struct ni_board_struct *board = comedi_board(dev);
2734         struct comedi_async *async = s->async;
2735         unsigned int range;
2736         unsigned int i;
2737         unsigned int offset;
2738         unsigned int length = num_bytes / sizeof(short);
2739         unsigned short *array = data;
2740
2741         offset = 1 << (board->aobits - 1);
2742         for (i = 0; i < length; i++) {
2743                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2744                 if (board->ao_unipolar == 0 || (range & 1) == 0)
2745                         array[i] -= offset;
2746 #ifdef PCIDMA
2747                 array[i] = cpu_to_le16(array[i]);
2748 #endif
2749                 chan_index++;
2750                 chan_index %= async->cmd.chanlist_len;
2751         }
2752 }
2753
2754 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2755                                           struct comedi_subdevice *s,
2756                                           unsigned int chanspec[],
2757                                           unsigned int n_chans, int timed)
2758 {
2759         const struct ni_board_struct *board = comedi_board(dev);
2760         struct ni_private *devpriv = dev->private;
2761         unsigned int range;
2762         unsigned int chan;
2763         unsigned int conf;
2764         int i;
2765         int invert = 0;
2766
2767         if (timed) {
2768                 for (i = 0; i < board->n_aochan; ++i) {
2769                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2770                         ni_writeb(devpriv->ao_conf[i],
2771                                   M_Offset_AO_Config_Bank(i));
2772                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2773                 }
2774         }
2775         for (i = 0; i < n_chans; i++) {
2776                 const struct comedi_krange *krange;
2777                 chan = CR_CHAN(chanspec[i]);
2778                 range = CR_RANGE(chanspec[i]);
2779                 krange = s->range_table->range + range;
2780                 invert = 0;
2781                 conf = 0;
2782                 switch (krange->max - krange->min) {
2783                 case 20000000:
2784                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2785                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2786                         break;
2787                 case 10000000:
2788                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2789                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2790                         break;
2791                 case 4000000:
2792                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2793                         ni_writeb(MSeries_Attenuate_x5_Bit,
2794                                   M_Offset_AO_Reference_Attenuation(chan));
2795                         break;
2796                 case 2000000:
2797                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2798                         ni_writeb(MSeries_Attenuate_x5_Bit,
2799                                   M_Offset_AO_Reference_Attenuation(chan));
2800                         break;
2801                 default:
2802                         printk("%s: bug! unhandled ao reference voltage\n",
2803                                __func__);
2804                         break;
2805                 }
2806                 switch (krange->max + krange->min) {
2807                 case 0:
2808                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2809                         break;
2810                 case 10000000:
2811                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2812                         break;
2813                 default:
2814                         printk("%s: bug! unhandled ao offset voltage\n",
2815                                __func__);
2816                         break;
2817                 }
2818                 if (timed)
2819                         conf |= MSeries_AO_Update_Timed_Bit;
2820                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2821                 devpriv->ao_conf[chan] = conf;
2822                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2823         }
2824         return invert;
2825 }
2826
2827 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2828                                      struct comedi_subdevice *s,
2829                                      unsigned int chanspec[],
2830                                      unsigned int n_chans)
2831 {
2832         const struct ni_board_struct *board = comedi_board(dev);
2833         struct ni_private *devpriv = dev->private;
2834         unsigned int range;
2835         unsigned int chan;
2836         unsigned int conf;
2837         int i;
2838         int invert = 0;
2839
2840         for (i = 0; i < n_chans; i++) {
2841                 chan = CR_CHAN(chanspec[i]);
2842                 range = CR_RANGE(chanspec[i]);
2843                 conf = AO_Channel(chan);
2844
2845                 if (board->ao_unipolar) {
2846                         if ((range & 1) == 0) {
2847                                 conf |= AO_Bipolar;
2848                                 invert = (1 << (board->aobits - 1));
2849                         } else {
2850                                 invert = 0;
2851                         }
2852                         if (range & 2)
2853                                 conf |= AO_Ext_Ref;
2854                 } else {
2855                         conf |= AO_Bipolar;
2856                         invert = (1 << (board->aobits - 1));
2857                 }
2858
2859                 /* not all boards can deglitch, but this shouldn't hurt */
2860                 if (chanspec[i] & CR_DEGLITCH)
2861                         conf |= AO_Deglitch;
2862
2863                 /* analog reference */
2864                 /* AREF_OTHER connects AO ground to AI ground, i think */
2865                 conf |= (CR_AREF(chanspec[i]) ==
2866                          AREF_OTHER) ? AO_Ground_Ref : 0;
2867
2868                 ni_writew(conf, AO_Configuration);
2869                 devpriv->ao_conf[chan] = conf;
2870         }
2871         return invert;
2872 }
2873
2874 static int ni_ao_config_chanlist(struct comedi_device *dev,
2875                                  struct comedi_subdevice *s,
2876                                  unsigned int chanspec[], unsigned int n_chans,
2877                                  int timed)
2878 {
2879         const struct ni_board_struct *board = comedi_board(dev);
2880
2881         if (board->reg_type & ni_reg_m_series_mask)
2882                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2883                                                       timed);
2884         else
2885                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2886 }
2887
2888 static int ni_ao_insn_read(struct comedi_device *dev,
2889                            struct comedi_subdevice *s, struct comedi_insn *insn,
2890                            unsigned int *data)
2891 {
2892         struct ni_private *devpriv = dev->private;
2893
2894         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2895
2896         return 1;
2897 }
2898
2899 static int ni_ao_insn_write(struct comedi_device *dev,
2900                             struct comedi_subdevice *s,
2901                             struct comedi_insn *insn, unsigned int *data)
2902 {
2903         const struct ni_board_struct *board = comedi_board(dev);
2904         struct ni_private *devpriv = dev->private;
2905         unsigned int chan = CR_CHAN(insn->chanspec);
2906         unsigned int invert;
2907
2908         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2909
2910         devpriv->ao[chan] = data[0];
2911
2912         if (board->reg_type & ni_reg_m_series_mask) {
2913                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2914         } else
2915                 ni_writew(data[0] ^ invert,
2916                           (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
2917
2918         return 1;
2919 }
2920
2921 static int ni_ao_insn_write_671x(struct comedi_device *dev,
2922                                  struct comedi_subdevice *s,
2923                                  struct comedi_insn *insn, unsigned int *data)
2924 {
2925         const struct ni_board_struct *board = comedi_board(dev);
2926         struct ni_private *devpriv = dev->private;
2927         unsigned int chan = CR_CHAN(insn->chanspec);
2928         unsigned int invert;
2929
2930         ao_win_out(1 << chan, AO_Immediate_671x);
2931         invert = 1 << (board->aobits - 1);
2932
2933         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2934
2935         devpriv->ao[chan] = data[0];
2936         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2937
2938         return 1;
2939 }
2940
2941 static int ni_ao_insn_config(struct comedi_device *dev,
2942                              struct comedi_subdevice *s,
2943                              struct comedi_insn *insn, unsigned int *data)
2944 {
2945         const struct ni_board_struct *board = comedi_board(dev);
2946         struct ni_private *devpriv = dev->private;
2947
2948         switch (data[0]) {
2949         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2950                 switch (data[1]) {
2951                 case COMEDI_OUTPUT:
2952                         data[2] = 1 + board->ao_fifo_depth * sizeof(short);
2953                         if (devpriv->mite)
2954                                 data[2] += devpriv->mite->fifo_size;
2955                         break;
2956                 case COMEDI_INPUT:
2957                         data[2] = 0;
2958                         break;
2959                 default:
2960                         return -EINVAL;
2961                         break;
2962                 }
2963                 return 0;
2964         default:
2965                 break;
2966         }
2967
2968         return -EINVAL;
2969 }
2970
2971 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2972                          unsigned int trignum)
2973 {
2974         const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
2975         struct ni_private *devpriv = dev->private;
2976         int ret;
2977         int interrupt_b_bits;
2978         int i;
2979         static const int timeout = 1000;
2980
2981         if (trignum != 0)
2982                 return -EINVAL;
2983
2984         /* Null trig at beginning prevent ao start trigger from executing more than
2985            once per command (and doing things like trying to allocate the ao dma channel
2986            multiple times) */
2987         s->async->inttrig = NULL;
2988
2989         ni_set_bits(dev, Interrupt_B_Enable_Register,
2990                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2991         interrupt_b_bits = AO_Error_Interrupt_Enable;
2992 #ifdef PCIDMA
2993         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2994         if (board->reg_type & ni_reg_6xxx_mask)
2995                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2996         ret = ni_ao_setup_MITE_dma(dev);
2997         if (ret)
2998                 return ret;
2999         ret = ni_ao_wait_for_dma_load(dev);
3000         if (ret < 0)
3001                 return ret;
3002 #else
3003         ret = ni_ao_prep_fifo(dev, s);
3004         if (ret == 0)
3005                 return -EPIPE;
3006
3007         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3008 #endif
3009
3010         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3011                             AO_Mode_3_Register);
3012         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3013         /* wait for DACs to be loaded */
3014         for (i = 0; i < timeout; i++) {
3015                 udelay(1);
3016                 if ((devpriv->stc_readw(dev,
3017                                         Joint_Status_2_Register) &
3018                      AO_TMRDACWRs_In_Progress_St) == 0)
3019                         break;
3020         }
3021         if (i == timeout) {
3022                 comedi_error(dev,
3023                              "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3024                 return -EIO;
3025         }
3026         /*  stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3027         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3028                             Interrupt_B_Ack_Register);
3029
3030         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3031
3032         devpriv->stc_writew(dev,
3033                             devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3034                             | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3035                             AO_Command_1_Register);
3036
3037         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3038                             AO_Command_2_Register);
3039
3040         return 0;
3041 }
3042
3043 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3044 {
3045         const struct ni_board_struct *board = comedi_board(dev);
3046         struct ni_private *devpriv = dev->private;
3047         const struct comedi_cmd *cmd = &s->async->cmd;
3048         int bits;
3049         int i;
3050         unsigned trigvar;
3051
3052         if (dev->irq == 0) {
3053                 comedi_error(dev, "cannot run command without an irq");
3054                 return -EIO;
3055         }
3056
3057         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3058
3059         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3060
3061         if (board->reg_type & ni_reg_6xxx_mask) {
3062                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3063
3064                 bits = 0;
3065                 for (i = 0; i < cmd->chanlist_len; i++) {
3066                         int chan;
3067
3068                         chan = CR_CHAN(cmd->chanlist[i]);
3069                         bits |= 1 << chan;
3070                         ao_win_out(chan, AO_Waveform_Generation_611x);
3071                 }
3072                 ao_win_out(bits, AO_Timed_611x);
3073         }
3074
3075         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3076
3077         if (cmd->stop_src == TRIG_NONE) {
3078                 devpriv->ao_mode1 |= AO_Continuous;
3079                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3080         } else {
3081                 devpriv->ao_mode1 &= ~AO_Continuous;
3082                 devpriv->ao_mode1 |= AO_Trigger_Once;
3083         }
3084         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3085         switch (cmd->start_src) {
3086         case TRIG_INT:
3087         case TRIG_NOW:
3088                 devpriv->ao_trigger_select &=
3089                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3090                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3091                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3092                                     AO_Trigger_Select_Register);
3093                 break;
3094         case TRIG_EXT:
3095                 devpriv->ao_trigger_select =
3096                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3097                 if (cmd->start_arg & CR_INVERT)
3098                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3099                 if (cmd->start_arg & CR_EDGE)
3100                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3101                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3102                                     AO_Trigger_Select_Register);
3103                 break;
3104         default:
3105                 BUG();
3106                 break;
3107         }
3108         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3109         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3110
3111         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3112         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3113         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3114         if (cmd->stop_src == TRIG_NONE)
3115                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3116         else
3117                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3118         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3119         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3120         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3121         switch (cmd->stop_src) {
3122         case TRIG_COUNT:
3123                 if (board->reg_type & ni_reg_m_series_mask) {
3124                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3125                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3126                                             AO_UC_Load_A_Register);
3127                         devpriv->stc_writew(dev, AO_UC_Load,
3128                                             AO_Command_1_Register);
3129                 } else {
3130                         devpriv->stc_writel(dev, cmd->stop_arg,
3131                                             AO_UC_Load_A_Register);
3132                         devpriv->stc_writew(dev, AO_UC_Load,
3133                                             AO_Command_1_Register);
3134                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3135                                             AO_UC_Load_A_Register);
3136                 }
3137                 break;
3138         case TRIG_NONE:
3139                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3140                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3141                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3142                 break;
3143         default:
3144                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3145                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3146                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3147         }
3148
3149         devpriv->ao_mode1 &=
3150             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3151               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3152         switch (cmd->scan_begin_src) {
3153         case TRIG_TIMER:
3154                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3155                 trigvar =
3156                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3157                                    TRIG_ROUND_NEAREST);
3158                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3159                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3160                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3161                 break;
3162         case TRIG_EXT:
3163                 devpriv->ao_mode1 |=
3164                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3165                 if (cmd->scan_begin_arg & CR_INVERT)
3166                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3167                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3168                 break;
3169         default:
3170                 BUG();
3171                 break;
3172         }
3173         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3174         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3175         devpriv->ao_mode2 &=
3176             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3177         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3178
3179         if (cmd->scan_end_arg > 1) {
3180                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3181                 devpriv->stc_writew(dev,
3182                                     AO_Number_Of_Channels(cmd->scan_end_arg -
3183                                                           1) |
3184                                     AO_UPDATE_Output_Select
3185                                     (AO_Update_Output_High_Z),
3186                                     AO_Output_Control_Register);
3187         } else {
3188                 unsigned bits;
3189                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3190                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3191                 if (board->reg_type &
3192                     (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3193                         bits |= AO_Number_Of_Channels(0);
3194                 } else {
3195                         bits |=
3196                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3197                 }
3198                 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3199         }
3200         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3201
3202         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3203                             AO_Command_1_Register);
3204
3205         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3206         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3207
3208         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3209 #ifdef PCIDMA
3210         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3211 #else
3212         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3213 #endif
3214         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3215         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3216
3217         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3218             AO_TMRDACWR_Pulse_Width;
3219         if (board->ao_fifo_depth)
3220                 bits |= AO_FIFO_Enable;
3221         else
3222                 bits |= AO_DMA_PIO_Control;
3223 #if 0
3224         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3225            verified with bus analyzer. */
3226         if (board->reg_type & ni_reg_m_series_mask)
3227                 bits |= AO_Number_Of_DAC_Packages;
3228 #endif
3229         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3230         /*  enable sending of ao dma requests */
3231         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3232
3233         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3234
3235         if (cmd->stop_src == TRIG_COUNT) {
3236                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3237                                     Interrupt_B_Ack_Register);
3238                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3239                             AO_BC_TC_Interrupt_Enable, 1);
3240         }
3241
3242         s->async->inttrig = &ni_ao_inttrig;
3243
3244         return 0;
3245 }
3246
3247 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3248                          struct comedi_cmd *cmd)
3249 {
3250         const struct ni_board_struct *board = comedi_board(dev);
3251         struct ni_private *devpriv = dev->private;
3252         int err = 0;
3253         int tmp;
3254
3255         /* Step 1 : check if triggers are trivially valid */
3256
3257         if ((cmd->flags & CMDF_WRITE) == 0)
3258                 cmd->flags |= CMDF_WRITE;
3259
3260         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3261         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3262                                         TRIG_TIMER | TRIG_EXT);
3263         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3264         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3265         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3266
3267         if (err)
3268                 return 1;
3269
3270         /* Step 2a : make sure trigger sources are unique */
3271
3272         err |= cfc_check_trigger_is_unique(cmd->start_src);
3273         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3274         err |= cfc_check_trigger_is_unique(cmd->stop_src);
3275
3276         /* Step 2b : and mutually compatible */
3277
3278         if (err)
3279                 return 2;
3280
3281         /* Step 3: check if arguments are trivially valid */
3282
3283         if (cmd->start_src == TRIG_EXT) {
3284                 /* external trigger */
3285                 unsigned int tmp = CR_CHAN(cmd->start_arg);
3286
3287                 if (tmp > 18)
3288                         tmp = 18;
3289                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3290                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3291         } else {
3292                 /* true for both TRIG_NOW and TRIG_INT */
3293                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3294         }
3295
3296         if (cmd->scan_begin_src == TRIG_TIMER) {
3297                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3298                                                  board->ao_speed);
3299                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3300                                                  devpriv->clock_ns * 0xffffff);
3301         }
3302
3303         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3304         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3305
3306         if (cmd->stop_src == TRIG_COUNT)
3307                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3308         else    /* TRIG_NONE */
3309                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3310
3311         if (err)
3312                 return 3;
3313
3314         /* step 4: fix up any arguments */
3315         if (cmd->scan_begin_src == TRIG_TIMER) {
3316                 tmp = cmd->scan_begin_arg;
3317                 cmd->scan_begin_arg =
3318                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3319                                                        cmd->scan_begin_arg,
3320                                                        cmd->
3321                                                        flags &
3322                                                        TRIG_ROUND_MASK));
3323                 if (tmp != cmd->scan_begin_arg)
3324                         err++;
3325         }
3326         if (err)
3327                 return 4;
3328
3329         /* step 5: fix up chanlist */
3330
3331         if (err)
3332                 return 5;
3333
3334         return 0;
3335 }
3336
3337 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3338 {
3339         const struct ni_board_struct *board = comedi_board(dev);
3340         struct ni_private *devpriv = dev->private;
3341
3342         /* devpriv->ao0p=0x0000; */
3343         /* ni_writew(devpriv->ao0p,AO_Configuration); */
3344
3345         /* devpriv->ao1p=AO_Channel(1); */
3346         /* ni_writew(devpriv->ao1p,AO_Configuration); */
3347
3348         ni_release_ao_mite_channel(dev);
3349
3350         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3351         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3352         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3353         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3354         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3355         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3356                             AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3357         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3358         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3359         devpriv->ao_cmd1 = 0;
3360         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3361         devpriv->ao_cmd2 = 0;
3362         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3363         devpriv->ao_mode1 = 0;
3364         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3365         devpriv->ao_mode2 = 0;
3366         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3367         if (board->reg_type & ni_reg_m_series_mask)
3368                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3369         else
3370                 devpriv->ao_mode3 = 0;
3371         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3372         devpriv->ao_trigger_select = 0;
3373         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3374                             AO_Trigger_Select_Register);
3375         if (board->reg_type & ni_reg_6xxx_mask) {
3376                 unsigned immediate_bits = 0;
3377                 unsigned i;
3378                 for (i = 0; i < s->n_chan; ++i)
3379                         immediate_bits |= 1 << i;
3380                 ao_win_out(immediate_bits, AO_Immediate_671x);
3381                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3382         }
3383         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3384
3385         return 0;
3386 }
3387
3388 /* digital io */
3389
3390 static int ni_dio_insn_config(struct comedi_device *dev,
3391                               struct comedi_subdevice *s,
3392                               struct comedi_insn *insn,
3393                               unsigned int *data)
3394 {
3395         struct ni_private *devpriv = dev->private;
3396         int ret;
3397
3398         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3399         if (ret)
3400                 return ret;
3401
3402         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3403         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3404         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3405
3406         return insn->n;
3407 }
3408
3409 static int ni_dio_insn_bits(struct comedi_device *dev,
3410                             struct comedi_subdevice *s,
3411                             struct comedi_insn *insn,
3412                             unsigned int *data)
3413 {
3414         struct ni_private *devpriv = dev->private;
3415
3416         /* Make sure we're not using the serial part of the dio */
3417         if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3418                 return -EBUSY;
3419
3420         if (comedi_dio_update_state(s, data)) {
3421                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3422                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3423                 devpriv->stc_writew(dev, devpriv->dio_output,
3424                                     DIO_Output_Register);
3425         }
3426
3427         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3428
3429         return insn->n;
3430 }
3431
3432 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3433                                        struct comedi_subdevice *s,
3434                                        struct comedi_insn *insn,
3435                                        unsigned int *data)
3436 {
3437         struct ni_private *devpriv __maybe_unused = dev->private;
3438         int ret;
3439
3440         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3441         if (ret)
3442                 return ret;
3443
3444         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3445
3446         return insn->n;
3447 }
3448
3449 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3450                                      struct comedi_subdevice *s,
3451                                      struct comedi_insn *insn,
3452                                      unsigned int *data)
3453 {
3454         struct ni_private *devpriv __maybe_unused = dev->private;
3455
3456         if (comedi_dio_update_state(s, data))
3457                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3458
3459         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3460
3461         return insn->n;
3462 }
3463
3464 static int ni_cdio_cmdtest(struct comedi_device *dev,
3465                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3466 {
3467         int err = 0;
3468         int tmp;
3469         unsigned i;
3470
3471         /* Step 1 : check if triggers are trivially valid */
3472
3473         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3474         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3475         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3476         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3477         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3478
3479         if (err)
3480                 return 1;
3481
3482         /* Step 2a : make sure trigger sources are unique */
3483         /* Step 2b : and mutually compatible */
3484
3485         if (err)
3486                 return 2;
3487
3488         /* Step 3: check if arguments are trivially valid */
3489
3490         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3491
3492         tmp = cmd->scan_begin_arg;
3493         tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3494         if (tmp != cmd->scan_begin_arg)
3495                 err |= -EINVAL;
3496
3497         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3498         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3499         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3500
3501         if (err)
3502                 return 3;
3503
3504         /* step 4: fix up any arguments */
3505
3506         if (err)
3507                 return 4;
3508
3509         /* step 5: check chanlist */
3510
3511         for (i = 0; i < cmd->chanlist_len; ++i) {
3512                 if (cmd->chanlist[i] != i)
3513                         err = 1;
3514         }
3515
3516         if (err)
3517                 return 5;
3518
3519         return 0;
3520 }
3521
3522 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3523 {
3524         struct ni_private *devpriv __maybe_unused = dev->private;
3525         const struct comedi_cmd *cmd = &s->async->cmd;
3526         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3527         int retval;
3528
3529         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3530         switch (cmd->scan_begin_src) {
3531         case TRIG_EXT:
3532                 cdo_mode_bits |=
3533                     CR_CHAN(cmd->scan_begin_arg) &
3534                     CDO_Sample_Source_Select_Mask;
3535                 break;
3536         default:
3537                 BUG();
3538                 break;
3539         }
3540         if (cmd->scan_begin_arg & CR_INVERT)
3541                 cdo_mode_bits |= CDO_Polarity_Bit;
3542         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3543         if (s->io_bits) {
3544                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3545                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3546                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3547         } else {
3548                 comedi_error(dev,
3549                              "attempted to run digital output command with no lines configured as outputs");
3550                 return -EIO;
3551         }
3552         retval = ni_request_cdo_mite_channel(dev);
3553         if (retval < 0)
3554                 return retval;
3555         s->async->inttrig = &ni_cdo_inttrig;
3556         return 0;
3557 }
3558
3559 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3560                           unsigned int trignum)
3561 {
3562 #ifdef PCIDMA
3563         struct ni_private *devpriv = dev->private;
3564         unsigned long flags;
3565 #endif
3566         int retval = 0;
3567         unsigned i;
3568         const unsigned timeout = 1000;
3569
3570         s->async->inttrig = NULL;
3571
3572         /* read alloc the entire buffer */
3573         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3574
3575 #ifdef PCIDMA
3576         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3577         if (devpriv->cdo_mite_chan) {
3578                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3579                 mite_dma_arm(devpriv->cdo_mite_chan);
3580         } else {
3581                 comedi_error(dev, "BUG: no cdo mite channel?");
3582                 retval = -EIO;
3583         }
3584         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3585         if (retval < 0)
3586                 return retval;
3587 #endif
3588 /*
3589 * XXX not sure what interrupt C group does
3590 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3591 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3592 */
3593         for (i = 0; i < timeout; ++i) {
3594                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3595                         break;
3596                 udelay(10);
3597         }
3598         if (i == timeout) {
3599                 comedi_error(dev, "dma failed to fill cdo fifo!");
3600                 ni_cdio_cancel(dev, s);
3601                 return -EIO;
3602         }
3603         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3604                   CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3605                   M_Offset_CDIO_Command);
3606         return retval;
3607 }
3608
3609 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3610 {
3611         struct ni_private *devpriv __maybe_unused = dev->private;
3612
3613         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3614                   CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3615                   CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3616                   M_Offset_CDIO_Command);
3617 /*
3618 * XXX not sure what interrupt C group does ni_writeb(0,
3619 * M_Offset_Interrupt_C_Enable);
3620 */
3621         ni_writel(0, M_Offset_CDO_Mask_Enable);
3622         ni_release_cdo_mite_channel(dev);
3623         return 0;
3624 }
3625
3626 static void handle_cdio_interrupt(struct comedi_device *dev)
3627 {
3628         const struct ni_board_struct *board = comedi_board(dev);
3629         struct ni_private *devpriv __maybe_unused = dev->private;
3630         unsigned cdio_status;
3631         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3632 #ifdef PCIDMA
3633         unsigned long flags;
3634 #endif
3635
3636         if ((board->reg_type & ni_reg_m_series_mask) == 0)
3637                 return;
3638 #ifdef PCIDMA
3639         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3640         if (devpriv->cdo_mite_chan) {
3641                 unsigned cdo_mite_status =
3642                     mite_get_status(devpriv->cdo_mite_chan);
3643                 if (cdo_mite_status & CHSR_LINKC) {
3644                         writel(CHOR_CLRLC,
3645                                devpriv->mite->mite_io_addr +
3646                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3647                 }
3648                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3649         }
3650         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3651 #endif
3652
3653         cdio_status = ni_readl(M_Offset_CDIO_Status);
3654         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3655                 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3656                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      /*  XXX just guessing this is needed and does something useful */
3657                 s->async->events |= COMEDI_CB_OVERFLOW;
3658         }
3659         if (cdio_status & CDO_FIFO_Empty_Bit) {
3660                 /* printk("cdio fifo empty\n"); */
3661                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3662                           M_Offset_CDIO_Command);
3663                 /* s->async->events |= COMEDI_CB_EOA; */
3664         }
3665         ni_event(dev, s);
3666 }
3667
3668 static int ni_serial_insn_config(struct comedi_device *dev,
3669                                  struct comedi_subdevice *s,
3670                                  struct comedi_insn *insn, unsigned int *data)
3671 {
3672         struct ni_private *devpriv = dev->private;
3673         int err = insn->n;
3674         unsigned char byte_out, byte_in = 0;
3675
3676         if (insn->n != 2)
3677                 return -EINVAL;
3678
3679         switch (data[0]) {
3680         case INSN_CONFIG_SERIAL_CLOCK:
3681                 devpriv->serial_hw_mode = 1;
3682                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3683
3684                 if (data[1] == SERIAL_DISABLED) {
3685                         devpriv->serial_hw_mode = 0;
3686                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3687                                                   DIO_Software_Serial_Control);
3688                         data[1] = SERIAL_DISABLED;
3689                         devpriv->serial_interval_ns = data[1];
3690                 } else if (data[1] <= SERIAL_600NS) {
3691                         /* Warning: this clock speed is too fast to reliably
3692                            control SCXI. */
3693                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3694                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3695                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3696                         data[1] = SERIAL_600NS;
3697                         devpriv->serial_interval_ns = data[1];
3698                 } else if (data[1] <= SERIAL_1_2US) {
3699                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3700                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3701                             DIO_Serial_Out_Divide_By_2;
3702                         data[1] = SERIAL_1_2US;
3703                         devpriv->serial_interval_ns = data[1];
3704                 } else if (data[1] <= SERIAL_10US) {
3705                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3706                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3707                             DIO_Serial_Out_Divide_By_2;
3708                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3709                            600ns/1.2us. If you turn divide_by_2 off with the
3710                            slow clock, you will still get 10us, except then
3711                            all your delays are wrong. */
3712                         data[1] = SERIAL_10US;
3713                         devpriv->serial_interval_ns = data[1];
3714                 } else {
3715                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3716                                                   DIO_Software_Serial_Control);
3717                         devpriv->serial_hw_mode = 0;
3718                         data[1] = (data[1] / 1000) * 1000;
3719                         devpriv->serial_interval_ns = data[1];
3720                 }
3721
3722                 devpriv->stc_writew(dev, devpriv->dio_control,
3723                                     DIO_Control_Register);
3724                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3725                                     Clock_and_FOUT_Register);
3726                 return 1;
3727
3728                 break;
3729
3730         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3731
3732                 if (devpriv->serial_interval_ns == 0)
3733                         return -EINVAL;
3734
3735                 byte_out = data[1] & 0xFF;
3736
3737                 if (devpriv->serial_hw_mode) {
3738                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3739                                                       &byte_in);
3740                 } else if (devpriv->serial_interval_ns > 0) {
3741                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3742                                                       &byte_in);
3743                 } else {
3744                         printk("ni_serial_insn_config: serial disabled!\n");
3745                         return -EINVAL;
3746                 }
3747                 if (err < 0)
3748                         return err;
3749                 data[1] = byte_in & 0xFF;
3750                 return insn->n;
3751
3752                 break;
3753         default:
3754                 return -EINVAL;
3755         }
3756
3757 }
3758
3759 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3760                                    struct comedi_subdevice *s,
3761                                    unsigned char data_out,
3762                                    unsigned char *data_in)
3763 {
3764         struct ni_private *devpriv = dev->private;
3765         unsigned int status1;
3766         int err = 0, count = 20;
3767
3768         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3769         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3770         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3771
3772         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3773         if (status1 & DIO_Serial_IO_In_Progress_St) {
3774                 err = -EBUSY;
3775                 goto Error;
3776         }
3777
3778         devpriv->dio_control |= DIO_HW_Serial_Start;
3779         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3780         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3781
3782         /* Wait until STC says we're done, but don't loop infinitely. */
3783         while ((status1 =
3784                 devpriv->stc_readw(dev,
3785                                    Joint_Status_1_Register)) &
3786                DIO_Serial_IO_In_Progress_St) {
3787                 /* Delay one bit per loop */
3788                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3789                 if (--count < 0) {
3790                         printk
3791                             ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3792                         err = -ETIME;
3793                         goto Error;
3794                 }
3795         }
3796
3797         /* Delay for last bit. This delay is absolutely necessary, because
3798            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3799         udelay((devpriv->serial_interval_ns + 999) / 1000);
3800
3801         if (data_in != NULL)
3802                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3803
3804 Error:
3805         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3806
3807         return err;
3808 }
3809
3810 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3811                                    struct comedi_subdevice *s,
3812                                    unsigned char data_out,
3813                                    unsigned char *data_in)
3814 {
3815         struct ni_private *devpriv = dev->private;
3816         unsigned char mask, input = 0;
3817
3818         /* Wait for one bit before transfer */
3819         udelay((devpriv->serial_interval_ns + 999) / 1000);
3820
3821         for (mask = 0x80; mask; mask >>= 1) {
3822                 /* Output current bit; note that we cannot touch s->state
3823                    because it is a per-subdevice field, and serial is
3824                    a separate subdevice from DIO. */
3825                 devpriv->dio_output &= ~DIO_SDOUT;
3826                 if (data_out & mask)
3827                         devpriv->dio_output |= DIO_SDOUT;
3828                 devpriv->stc_writew(dev, devpriv->dio_output,
3829                                     DIO_Output_Register);
3830
3831                 /* Assert SDCLK (active low, inverted), wait for half of
3832                    the delay, deassert SDCLK, and wait for the other half. */
3833                 devpriv->dio_control |= DIO_Software_Serial_Control;
3834                 devpriv->stc_writew(dev, devpriv->dio_control,
3835                                     DIO_Control_Register);
3836
3837                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3838
3839                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3840                 devpriv->stc_writew(dev, devpriv->dio_control,
3841                                     DIO_Control_Register);
3842
3843                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3844
3845                 /* Input current bit */
3846                 if (devpriv->stc_readw(dev,
3847                                        DIO_Parallel_Input_Register) & DIO_SDIN) {
3848                         /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3849                         input |= mask;
3850                 }
3851         }
3852
3853         if (data_in)
3854                 *data_in = input;
3855
3856         return 0;
3857 }
3858
3859 static void mio_common_detach(struct comedi_device *dev)
3860 {
3861         struct ni_private *devpriv = dev->private;
3862
3863         if (devpriv) {
3864                 if (devpriv->counter_dev)
3865                         ni_gpct_device_destroy(devpriv->counter_dev);
3866         }
3867 }
3868
3869 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3870 {
3871         int i;
3872
3873         for (i = 0; i < s->n_chan; i++) {
3874                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3875                                AO_Configuration_2_67xx);
3876         }
3877         ao_win_out(0x0, AO_Later_Single_Point_Updates);
3878 }
3879
3880 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3881 {
3882         unsigned stc_register;
3883         switch (reg) {
3884         case NITIO_G0_AUTO_INC:
3885                 stc_register = G_Autoincrement_Register(0);
3886                 break;
3887         case NITIO_G1_AUTO_INC:
3888                 stc_register = G_Autoincrement_Register(1);
3889                 break;
3890         case NITIO_G0_CMD:
3891                 stc_register = G_Command_Register(0);
3892                 break;
3893         case NITIO_G1_CMD:
3894                 stc_register = G_Command_Register(1);
3895                 break;
3896         case NITIO_G0_HW_SAVE:
3897                 stc_register = G_HW_Save_Register(0);
3898                 break;
3899         case NITIO_G1_HW_SAVE:
3900                 stc_register = G_HW_Save_Register(1);
3901                 break;
3902         case NITIO_G0_SW_SAVE:
3903                 stc_register = G_Save_Register(0);
3904                 break;
3905         case NITIO_G1_SW_SAVE:
3906                 stc_register = G_Save_Register(1);
3907                 break;
3908         case NITIO_G0_MODE:
3909                 stc_register = G_Mode_Register(0);
3910                 break;
3911         case NITIO_G1_MODE:
3912                 stc_register = G_Mode_Register(1);
3913                 break;
3914         case NITIO_G0_LOADA:
3915                 stc_register = G_Load_A_Register(0);
3916                 break;
3917         case NITIO_G1_LOADA:
3918                 stc_register = G_Load_A_Register(1);
3919                 break;
3920         case NITIO_G0_LOADB:
3921                 stc_register = G_Load_B_Register(0);
3922                 break;
3923         case NITIO_G1_LOADB:
3924                 stc_register = G_Load_B_Register(1);
3925                 break;
3926         case NITIO_G0_INPUT_SEL:
3927                 stc_register = G_Input_Select_Register(0);
3928                 break;
3929         case NITIO_G1_INPUT_SEL:
3930                 stc_register = G_Input_Select_Register(1);
3931                 break;
3932         case NITIO_G01_STATUS:
3933                 stc_register = G_Status_Register;
3934                 break;
3935         case NITIO_G01_RESET:
3936                 stc_register = Joint_Reset_Register;
3937                 break;
3938         case NITIO_G01_STATUS1:
3939                 stc_register = Joint_Status_1_Register;
3940                 break;
3941         case NITIO_G01_STATUS2:
3942                 stc_register = Joint_Status_2_Register;
3943                 break;
3944         case NITIO_G0_INT_ACK:
3945                 stc_register = Interrupt_A_Ack_Register;
3946                 break;
3947         case NITIO_G1_INT_ACK:
3948                 stc_register = Interrupt_B_Ack_Register;
3949                 break;
3950         case NITIO_G0_STATUS:
3951                 stc_register = AI_Status_1_Register;
3952                 break;
3953         case NITIO_G1_STATUS:
3954                 stc_register = AO_Status_1_Register;
3955                 break;
3956         case NITIO_G0_INT_ENA:
3957                 stc_register = Interrupt_A_Enable_Register;
3958                 break;
3959         case NITIO_G1_INT_ENA:
3960                 stc_register = Interrupt_B_Enable_Register;
3961                 break;
3962         default:
3963                 printk("%s: unhandled register 0x%x in switch.\n",
3964                        __func__, reg);
3965                 BUG();
3966                 return 0;
3967                 break;
3968         }
3969         return stc_register;
3970 }
3971
3972 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3973                                    enum ni_gpct_register reg)
3974 {
3975         struct comedi_device *dev = counter->counter_dev->dev;
3976         struct ni_private *devpriv = dev->private;
3977         unsigned stc_register;
3978         /* bits in the join reset register which are relevant to counters */
3979         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3980         static const unsigned gpct_interrupt_a_enable_mask =
3981             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
3982         static const unsigned gpct_interrupt_b_enable_mask =
3983             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
3984
3985         switch (reg) {
3986                 /* m-series-only registers */
3987         case NITIO_G0_CNT_MODE:
3988                 ni_writew(bits, M_Offset_G0_Counting_Mode);
3989                 break;
3990         case NITIO_G1_CNT_MODE:
3991                 ni_writew(bits, M_Offset_G1_Counting_Mode);
3992                 break;
3993         case NITIO_G0_GATE2:
3994                 ni_writew(bits, M_Offset_G0_Second_Gate);
3995                 break;
3996         case NITIO_G1_GATE2:
3997                 ni_writew(bits, M_Offset_G1_Second_Gate);
3998                 break;
3999         case NITIO_G0_DMA_CFG:
4000                 ni_writew(bits, M_Offset_G0_DMA_Config);
4001                 break;
4002         case NITIO_G1_DMA_CFG:
4003                 ni_writew(bits, M_Offset_G1_DMA_Config);
4004                 break;
4005         case NITIO_G0_ABZ:
4006                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4007                 break;
4008         case NITIO_G1_ABZ:
4009                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4010                 break;
4011
4012                 /* 32 bit registers */
4013         case NITIO_G0_LOADA:
4014         case NITIO_G1_LOADA:
4015         case NITIO_G0_LOADB:
4016         case NITIO_G1_LOADB:
4017                 stc_register = ni_gpct_to_stc_register(reg);
4018                 devpriv->stc_writel(dev, bits, stc_register);
4019                 break;
4020
4021                 /* 16 bit registers */
4022         case NITIO_G0_INT_ENA:
4023                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4024                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4025                                 gpct_interrupt_a_enable_mask, bits);
4026                 break;
4027         case NITIO_G1_INT_ENA:
4028                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4029                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4030                                 gpct_interrupt_b_enable_mask, bits);
4031                 break;
4032         case NITIO_G01_RESET:
4033                 BUG_ON(bits & ~gpct_joint_reset_mask);
4034                 /* fall-through */
4035         default:
4036                 stc_register = ni_gpct_to_stc_register(reg);
4037                 devpriv->stc_writew(dev, bits, stc_register);
4038         }
4039 }
4040
4041 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4042                                       enum ni_gpct_register reg)
4043 {
4044         struct comedi_device *dev = counter->counter_dev->dev;
4045         struct ni_private *devpriv = dev->private;
4046         unsigned stc_register;
4047
4048         switch (reg) {
4049                 /* m-series only registers */
4050         case NITIO_G0_DMA_STATUS:
4051                 return ni_readw(M_Offset_G0_DMA_Status);
4052         case NITIO_G1_DMA_STATUS:
4053                 return ni_readw(M_Offset_G1_DMA_Status);
4054
4055                 /* 32 bit registers */
4056         case NITIO_G0_HW_SAVE:
4057         case NITIO_G1_HW_SAVE:
4058         case NITIO_G0_SW_SAVE:
4059         case NITIO_G1_SW_SAVE:
4060                 stc_register = ni_gpct_to_stc_register(reg);
4061                 return devpriv->stc_readl(dev, stc_register);
4062
4063                 /* 16 bit registers */
4064         default:
4065                 stc_register = ni_gpct_to_stc_register(reg);
4066                 return devpriv->stc_readw(dev, stc_register);
4067                 break;
4068         }
4069         return 0;
4070 }
4071
4072 static int ni_freq_out_insn_read(struct comedi_device *dev,
4073                                  struct comedi_subdevice *s,
4074                                  struct comedi_insn *insn, unsigned int *data)
4075 {
4076         struct ni_private *devpriv = dev->private;
4077
4078         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4079         return 1;
4080 }
4081
4082 static int ni_freq_out_insn_write(struct comedi_device *dev,
4083                                   struct comedi_subdevice *s,
4084                                   struct comedi_insn *insn, unsigned int *data)
4085 {
4086         struct ni_private *devpriv = dev->private;
4087
4088         devpriv->clock_and_fout &= ~FOUT_Enable;
4089         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4090                             Clock_and_FOUT_Register);
4091         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4092         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4093         devpriv->clock_and_fout |= FOUT_Enable;
4094         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4095                             Clock_and_FOUT_Register);
4096         return insn->n;
4097 }
4098
4099 static int ni_set_freq_out_clock(struct comedi_device *dev,
4100                                  unsigned int clock_source)
4101 {
4102         struct ni_private *devpriv = dev->private;
4103
4104         switch (clock_source) {
4105         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4106                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4107                 break;
4108         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4109                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4110                 break;
4111         default:
4112                 return -EINVAL;
4113         }
4114         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4115                             Clock_and_FOUT_Register);
4116         return 3;
4117 }
4118
4119 static void ni_get_freq_out_clock(struct comedi_device *dev,
4120                                   unsigned int *clock_source,
4121                                   unsigned int *clock_period_ns)
4122 {
4123         struct ni_private *devpriv = dev->private;
4124
4125         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4126                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4127                 *clock_period_ns = TIMEBASE_2_NS;
4128         } else {
4129                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4130                 *clock_period_ns = TIMEBASE_1_NS * 2;
4131         }
4132 }
4133
4134 static int ni_freq_out_insn_config(struct comedi_device *dev,
4135                                    struct comedi_subdevice *s,
4136                                    struct comedi_insn *insn, unsigned int *data)
4137 {
4138         switch (data[0]) {
4139         case INSN_CONFIG_SET_CLOCK_SRC:
4140                 return ni_set_freq_out_clock(dev, data[1]);
4141                 break;
4142         case INSN_CONFIG_GET_CLOCK_SRC:
4143                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4144                 return 3;
4145         default:
4146                 break;
4147         }
4148         return -EINVAL;
4149 }
4150
4151 static int ni_alloc_private(struct comedi_device *dev)
4152 {
4153         struct ni_private *devpriv;
4154
4155         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
4156         if (!devpriv)
4157                 return -ENOMEM;
4158
4159         spin_lock_init(&devpriv->window_lock);
4160         spin_lock_init(&devpriv->soft_reg_copy_lock);
4161         spin_lock_init(&devpriv->mite_channel_lock);
4162
4163         return 0;
4164 };
4165
4166 static int ni_E_init(struct comedi_device *dev)
4167 {
4168         const struct ni_board_struct *board = comedi_board(dev);
4169         struct ni_private *devpriv = dev->private;
4170         struct comedi_subdevice *s;
4171         unsigned j;
4172         enum ni_gpct_variant counter_variant;
4173         int ret;
4174
4175         if (board->n_aochan > MAX_N_AO_CHAN) {
4176                 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4177                 return -EINVAL;
4178         }
4179
4180         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4181         if (ret)
4182                 return ret;
4183
4184         /* analog input subdevice */
4185
4186         s = &dev->subdevices[NI_AI_SUBDEV];
4187         dev->read_subdev = s;
4188         if (board->n_adchan) {
4189                 s->type = COMEDI_SUBD_AI;
4190                 s->subdev_flags =
4191                     SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4192                 if (board->reg_type != ni_reg_611x)
4193                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4194                 if (board->adbits > 16)
4195                         s->subdev_flags |= SDF_LSAMPL;
4196                 if (board->reg_type & ni_reg_m_series_mask)
4197                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4198                 s->n_chan = board->n_adchan;
4199                 s->len_chanlist = 512;
4200                 s->maxdata = (1 << board->adbits) - 1;
4201                 s->range_table = ni_range_lkup[board->gainlkup];
4202                 s->insn_read = &ni_ai_insn_read;
4203                 s->insn_config = &ni_ai_insn_config;
4204                 s->do_cmdtest = &ni_ai_cmdtest;
4205                 s->do_cmd = &ni_ai_cmd;
4206                 s->cancel = &ni_ai_reset;
4207                 s->poll = &ni_ai_poll;
4208                 s->munge = &ni_ai_munge;
4209 #ifdef PCIDMA
4210                 s->async_dma_dir = DMA_FROM_DEVICE;
4211 #endif
4212         } else {
4213                 s->type = COMEDI_SUBD_UNUSED;
4214         }
4215
4216         /* analog output subdevice */
4217
4218         s = &dev->subdevices[NI_AO_SUBDEV];
4219         if (board->n_aochan) {
4220                 s->type = COMEDI_SUBD_AO;
4221                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4222                 if (board->reg_type & ni_reg_m_series_mask)
4223                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4224                 s->n_chan = board->n_aochan;
4225                 s->maxdata = (1 << board->aobits) - 1;
4226                 s->range_table = board->ao_range_table;
4227                 s->insn_read = &ni_ao_insn_read;
4228                 if (board->reg_type & ni_reg_6xxx_mask)
4229                         s->insn_write = &ni_ao_insn_write_671x;
4230                 else
4231                         s->insn_write = &ni_ao_insn_write;
4232                 s->insn_config = &ni_ao_insn_config;
4233 #ifdef PCIDMA
4234                 if (board->n_aochan) {
4235                         s->async_dma_dir = DMA_TO_DEVICE;
4236 #else
4237                 if (board->ao_fifo_depth) {
4238 #endif
4239                         dev->write_subdev = s;
4240                         s->subdev_flags |= SDF_CMD_WRITE;
4241                         s->do_cmd = &ni_ao_cmd;
4242                         s->do_cmdtest = &ni_ao_cmdtest;
4243                         s->len_chanlist = board->n_aochan;
4244                         if ((board->reg_type & ni_reg_m_series_mask) == 0)
4245                                 s->munge = ni_ao_munge;
4246                 }
4247                 s->cancel = &ni_ao_reset;
4248         } else {
4249                 s->type = COMEDI_SUBD_UNUSED;
4250         }
4251         if ((board->reg_type & ni_reg_67xx_mask))
4252                 init_ao_67xx(dev, s);
4253
4254         /* digital i/o subdevice */
4255
4256         s = &dev->subdevices[NI_DIO_SUBDEV];
4257         s->type = COMEDI_SUBD_DIO;
4258         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4259         s->maxdata = 1;
4260         s->io_bits = 0;         /* all bits input */
4261         s->range_table = &range_digital;
4262         s->n_chan = board->num_p0_dio_channels;
4263         if (board->reg_type & ni_reg_m_series_mask) {
4264                 s->subdev_flags |=
4265                     SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */;
4266                 s->insn_bits = &ni_m_series_dio_insn_bits;
4267                 s->insn_config = &ni_m_series_dio_insn_config;
4268                 s->do_cmd = &ni_cdio_cmd;
4269                 s->do_cmdtest = &ni_cdio_cmdtest;
4270                 s->cancel = &ni_cdio_cancel;
4271                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4272                 s->len_chanlist = s->n_chan;
4273
4274                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4275                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4276         } else {
4277                 s->insn_bits = &ni_dio_insn_bits;
4278                 s->insn_config = &ni_dio_insn_config;
4279                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4280                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4281         }
4282
4283         /* 8255 device */
4284         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4285         if (board->has_8255)
4286                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4287         else
4288                 s->type = COMEDI_SUBD_UNUSED;
4289
4290         /* formerly general purpose counter/timer device, but no longer used */
4291         s = &dev->subdevices[NI_UNUSED_SUBDEV];
4292         s->type = COMEDI_SUBD_UNUSED;
4293
4294         /* calibration subdevice -- ai and ao */
4295         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4296         s->type = COMEDI_SUBD_CALIB;
4297         if (board->reg_type & ni_reg_m_series_mask) {
4298                 /*  internal PWM analog output used for AI nonlinearity calibration */
4299                 s->subdev_flags = SDF_INTERNAL;
4300                 s->insn_config = &ni_m_series_pwm_config;
4301                 s->n_chan = 1;
4302                 s->maxdata = 0;
4303                 ni_writel(0x0, M_Offset_Cal_PWM);
4304         } else if (board->reg_type == ni_reg_6143) {
4305                 /*  internal PWM analog output used for AI nonlinearity calibration */
4306                 s->subdev_flags = SDF_INTERNAL;
4307                 s->insn_config = &ni_6143_pwm_config;
4308                 s->n_chan = 1;
4309                 s->maxdata = 0;
4310         } else {
4311                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4312                 s->insn_read = &ni_calib_insn_read;
4313                 s->insn_write = &ni_calib_insn_write;
4314                 caldac_setup(dev, s);
4315         }
4316
4317         /* EEPROM */
4318         s = &dev->subdevices[NI_EEPROM_SUBDEV];
4319         s->type = COMEDI_SUBD_MEMORY;
4320         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4321         s->maxdata = 0xff;
4322         if (board->reg_type & ni_reg_m_series_mask) {
4323                 s->n_chan = M_SERIES_EEPROM_SIZE;
4324                 s->insn_read = &ni_m_series_eeprom_insn_read;
4325         } else {
4326                 s->n_chan = 512;
4327                 s->insn_read = &ni_eeprom_insn_read;
4328         }
4329
4330         /* PFI */
4331         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4332         s->type = COMEDI_SUBD_DIO;
4333         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4334         if (board->reg_type & ni_reg_m_series_mask) {
4335                 unsigned i;
4336                 s->n_chan = 16;
4337                 ni_writew(s->state, M_Offset_PFI_DO);
4338                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4339                         ni_writew(devpriv->pfi_output_select_reg[i],
4340                                   M_Offset_PFI_Output_Select(i + 1));
4341                 }
4342         } else {
4343                 s->n_chan = 10;
4344         }
4345         s->maxdata = 1;
4346         if (board->reg_type & ni_reg_m_series_mask)
4347                 s->insn_bits = &ni_pfi_insn_bits;
4348         s->insn_config = &ni_pfi_insn_config;
4349         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4350
4351         /* cs5529 calibration adc */
4352         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4353         if (board->reg_type & ni_reg_67xx_mask) {
4354                 s->type = COMEDI_SUBD_AI;
4355                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4356                 /*  one channel for each analog output channel */
4357                 s->n_chan = board->n_aochan;
4358                 s->maxdata = (1 << 16) - 1;
4359                 s->range_table = &range_unknown;        /* XXX */
4360                 s->insn_read = cs5529_ai_insn_read;
4361                 s->insn_config = NULL;
4362                 init_cs5529(dev);
4363         } else {
4364                 s->type = COMEDI_SUBD_UNUSED;
4365         }
4366
4367         /* Serial */
4368         s = &dev->subdevices[NI_SERIAL_SUBDEV];
4369         s->type = COMEDI_SUBD_SERIAL;
4370         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4371         s->n_chan = 1;
4372         s->maxdata = 0xff;
4373         s->insn_config = ni_serial_insn_config;
4374         devpriv->serial_interval_ns = 0;
4375         devpriv->serial_hw_mode = 0;
4376
4377         /* RTSI */
4378         s = &dev->subdevices[NI_RTSI_SUBDEV];
4379         s->type = COMEDI_SUBD_DIO;
4380         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4381         s->n_chan = 8;
4382         s->maxdata = 1;
4383         s->insn_bits = ni_rtsi_insn_bits;
4384         s->insn_config = ni_rtsi_insn_config;
4385         ni_rtsi_init(dev);
4386
4387         if (board->reg_type & ni_reg_m_series_mask)
4388                 counter_variant = ni_gpct_variant_m_series;
4389         else
4390                 counter_variant = ni_gpct_variant_e_series;
4391         devpriv->counter_dev = ni_gpct_device_construct(dev,
4392                                                         &ni_gpct_write_register,
4393                                                         &ni_gpct_read_register,
4394                                                         counter_variant,
4395                                                         NUM_GPCT);
4396         /* General purpose counters */
4397         for (j = 0; j < NUM_GPCT; ++j) {
4398                 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4399                 s->type = COMEDI_SUBD_COUNTER;
4400                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4401                 s->n_chan = 3;
4402                 if (board->reg_type & ni_reg_m_series_mask)
4403                         s->maxdata = 0xffffffff;
4404                 else
4405                         s->maxdata = 0xffffff;
4406                 s->insn_read = ni_tio_insn_read;
4407                 s->insn_write = ni_tio_insn_read;
4408                 s->insn_config = ni_tio_insn_config;
4409 #ifdef PCIDMA
4410                 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4411                 s->do_cmd = &ni_gpct_cmd;
4412                 s->len_chanlist = 1;
4413                 s->do_cmdtest = ni_tio_cmdtest;
4414                 s->cancel = &ni_gpct_cancel;
4415                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4416 #endif
4417                 s->private = &devpriv->counter_dev->counters[j];
4418
4419                 devpriv->counter_dev->counters[j].chip_index = 0;
4420                 devpriv->counter_dev->counters[j].counter_index = j;
4421                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4422         }
4423
4424         /* Frequency output */
4425         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4426         s->type = COMEDI_SUBD_COUNTER;
4427         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4428         s->n_chan = 1;
4429         s->maxdata = 0xf;
4430         s->insn_read = &ni_freq_out_insn_read;
4431         s->insn_write = &ni_freq_out_insn_write;
4432         s->insn_config = &ni_freq_out_insn_config;
4433
4434         /* ai configuration */
4435         s = &dev->subdevices[NI_AI_SUBDEV];
4436         ni_ai_reset(dev, s);
4437         if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4438                 /*  BEAM is this needed for PCI-6143 ?? */
4439                 devpriv->clock_and_fout =
4440                     Slow_Internal_Time_Divide_By_2 |
4441                     Slow_Internal_Timebase |
4442                     Clock_To_Board_Divide_By_2 |
4443                     Clock_To_Board |
4444                     AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4445         } else {
4446                 devpriv->clock_and_fout =
4447                     Slow_Internal_Time_Divide_By_2 |
4448                     Slow_Internal_Timebase |
4449                     Clock_To_Board_Divide_By_2 | Clock_To_Board;
4450         }
4451         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4452                             Clock_and_FOUT_Register);
4453
4454         /* analog output configuration */
4455         s = &dev->subdevices[NI_AO_SUBDEV];
4456         ni_ao_reset(dev, s);
4457
4458         if (dev->irq) {
4459                 devpriv->stc_writew(dev,
4460                                     (IRQ_POLARITY ? Interrupt_Output_Polarity :
4461                                      0) | (Interrupt_Output_On_3_Pins & 0) |
4462                                     Interrupt_A_Enable | Interrupt_B_Enable |
4463                                     Interrupt_A_Output_Select(interrupt_pin
4464                                                               (dev->irq)) |
4465                                     Interrupt_B_Output_Select(interrupt_pin
4466                                                               (dev->irq)),
4467                                     Interrupt_Control_Register);
4468         }
4469
4470         /* DMA setup */
4471         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4472         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4473
4474         if (board->reg_type & ni_reg_6xxx_mask) {
4475                 ni_writeb(0, Magic_611x);
4476         } else if (board->reg_type & ni_reg_m_series_mask) {
4477                 int channel;
4478                 for (channel = 0; channel < board->n_aochan; ++channel) {
4479                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4480                         ni_writeb(0x0,
4481                                   M_Offset_AO_Reference_Attenuation(channel));
4482                 }
4483                 ni_writeb(0x0, M_Offset_AO_Calibration);
4484         }
4485
4486         printk("\n");
4487         return 0;
4488 }
4489
4490 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4491 {
4492         struct comedi_device *dev = (struct comedi_device *)arg;
4493         struct ni_private *devpriv __maybe_unused = dev->private;
4494
4495         if (dir) {
4496                 ni_writeb(data, Port_A + 2 * port);
4497                 return 0;
4498         } else {
4499                 return ni_readb(Port_A + 2 * port);
4500         }
4501 }
4502
4503 /*
4504         presents the EEPROM as a subdevice
4505 */
4506
4507 static int ni_eeprom_insn_read(struct comedi_device *dev,
4508                                struct comedi_subdevice *s,
4509                                struct comedi_insn *insn, unsigned int *data)
4510 {
4511         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4512
4513         return 1;
4514 }
4515
4516 /*
4517         reads bytes out of eeprom
4518 */
4519
4520 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4521 {
4522         struct ni_private *devpriv __maybe_unused = dev->private;
4523         int bit;
4524         int bitstring;
4525
4526         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4527         ni_writeb(0x04, Serial_Command);
4528         for (bit = 0x8000; bit; bit >>= 1) {
4529                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4530                           Serial_Command);
4531                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4532                           Serial_Command);
4533         }
4534         bitstring = 0;
4535         for (bit = 0x80; bit; bit >>= 1) {
4536                 ni_writeb(0x04, Serial_Command);
4537                 ni_writeb(0x05, Serial_Command);
4538                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4539         }
4540         ni_writeb(0x00, Serial_Command);
4541
4542         return bitstring;
4543 }
4544
4545 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4546                                         struct comedi_subdevice *s,
4547                                         struct comedi_insn *insn,
4548                                         unsigned int *data)
4549 {
4550         struct ni_private *devpriv = dev->private;
4551
4552         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4553
4554         return 1;
4555 }
4556
4557 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4558 {
4559         struct ni_private *devpriv = dev->private;
4560
4561         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4562         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4563         return 3;
4564 }
4565
4566 static int ni_m_series_pwm_config(struct comedi_device *dev,
4567                                   struct comedi_subdevice *s,
4568                                   struct comedi_insn *insn, unsigned int *data)
4569 {
4570         struct ni_private *devpriv = dev->private;
4571         unsigned up_count, down_count;
4572
4573         switch (data[0]) {
4574         case INSN_CONFIG_PWM_OUTPUT:
4575                 switch (data[1]) {
4576                 case TRIG_ROUND_NEAREST:
4577                         up_count =
4578                             (data[2] +
4579                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4580                         break;
4581                 case TRIG_ROUND_DOWN:
4582                         up_count = data[2] / devpriv->clock_ns;
4583                         break;
4584                 case TRIG_ROUND_UP:
4585                         up_count =
4586                             (data[2] + devpriv->clock_ns -
4587                              1) / devpriv->clock_ns;
4588                         break;
4589                 default:
4590                         return -EINVAL;
4591                         break;
4592                 }
4593                 switch (data[3]) {
4594                 case TRIG_ROUND_NEAREST:
4595                         down_count =
4596                             (data[4] +
4597                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4598                         break;
4599                 case TRIG_ROUND_DOWN:
4600                         down_count = data[4] / devpriv->clock_ns;
4601                         break;
4602                 case TRIG_ROUND_UP:
4603                         down_count =
4604                             (data[4] + devpriv->clock_ns -
4605                              1) / devpriv->clock_ns;
4606                         break;
4607                 default:
4608                         return -EINVAL;
4609                         break;
4610                 }
4611                 if (up_count * devpriv->clock_ns != data[2] ||
4612                     down_count * devpriv->clock_ns != data[4]) {
4613                         data[2] = up_count * devpriv->clock_ns;
4614                         data[4] = down_count * devpriv->clock_ns;
4615                         return -EAGAIN;
4616                 }
4617                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4618                           MSeries_Cal_PWM_Low_Time_Bits(down_count),
4619                           M_Offset_Cal_PWM);
4620                 devpriv->pwm_up_count = up_count;
4621                 devpriv->pwm_down_count = down_count;
4622                 return 5;
4623                 break;
4624         case INSN_CONFIG_GET_PWM_OUTPUT:
4625                 return ni_get_pwm_config(dev, data);
4626                 break;
4627         default:
4628                 return -EINVAL;
4629                 break;
4630         }
4631         return 0;
4632 }
4633
4634 static int ni_6143_pwm_config(struct comedi_device *dev,
4635                               struct comedi_subdevice *s,
4636                               struct comedi_insn *insn, unsigned int *data)
4637 {
4638         struct ni_private *devpriv = dev->private;
4639         unsigned up_count, down_count;
4640
4641         switch (data[0]) {
4642         case INSN_CONFIG_PWM_OUTPUT:
4643                 switch (data[1]) {
4644                 case TRIG_ROUND_NEAREST:
4645                         up_count =
4646                             (data[2] +
4647                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4648                         break;
4649                 case TRIG_ROUND_DOWN:
4650                         up_count = data[2] / devpriv->clock_ns;
4651                         break;
4652                 case TRIG_ROUND_UP:
4653                         up_count =
4654                             (data[2] + devpriv->clock_ns -
4655                              1) / devpriv->clock_ns;
4656                         break;
4657                 default:
4658                         return -EINVAL;
4659                         break;
4660                 }
4661                 switch (data[3]) {
4662                 case TRIG_ROUND_NEAREST:
4663                         down_count =
4664                             (data[4] +
4665                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4666                         break;
4667                 case TRIG_ROUND_DOWN:
4668                         down_count = data[4] / devpriv->clock_ns;
4669                         break;
4670                 case TRIG_ROUND_UP:
4671                         down_count =
4672                             (data[4] + devpriv->clock_ns -
4673                              1) / devpriv->clock_ns;
4674                         break;
4675                 default:
4676                         return -EINVAL;
4677                         break;
4678                 }
4679                 if (up_count * devpriv->clock_ns != data[2] ||
4680                     down_count * devpriv->clock_ns != data[4]) {
4681                         data[2] = up_count * devpriv->clock_ns;
4682                         data[4] = down_count * devpriv->clock_ns;
4683                         return -EAGAIN;
4684                 }
4685                 ni_writel(up_count, Calibration_HighTime_6143);
4686                 devpriv->pwm_up_count = up_count;
4687                 ni_writel(down_count, Calibration_LowTime_6143);
4688                 devpriv->pwm_down_count = down_count;
4689                 return 5;
4690                 break;
4691         case INSN_CONFIG_GET_PWM_OUTPUT:
4692                 return ni_get_pwm_config(dev, data);
4693         default:
4694                 return -EINVAL;
4695                 break;
4696         }
4697         return 0;
4698 }
4699
4700 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4701 /*
4702         calibration subdevice
4703 */
4704 static int ni_calib_insn_write(struct comedi_device *dev,
4705                                struct comedi_subdevice *s,
4706                                struct comedi_insn *insn, unsigned int *data)
4707 {
4708         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4709
4710         return 1;
4711 }
4712
4713 static int ni_calib_insn_read(struct comedi_device *dev,
4714                               struct comedi_subdevice *s,
4715                               struct comedi_insn *insn, unsigned int *data)
4716 {
4717         struct ni_private *devpriv = dev->private;
4718
4719         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4720
4721         return 1;
4722 }
4723
4724 static int pack_mb88341(int addr, int val, int *bitstring);
4725 static int pack_dac8800(int addr, int val, int *bitstring);
4726 static int pack_dac8043(int addr, int val, int *bitstring);
4727 static int pack_ad8522(int addr, int val, int *bitstring);
4728 static int pack_ad8804(int addr, int val, int *bitstring);
4729 static int pack_ad8842(int addr, int val, int *bitstring);
4730
4731 struct caldac_struct {
4732         int n_chans;
4733         int n_bits;
4734         int (*packbits)(int, int, int *);
4735 };
4736
4737 static struct caldac_struct caldacs[] = {
4738         [mb88341] = {12, 8, pack_mb88341},
4739         [dac8800] = {8, 8, pack_dac8800},
4740         [dac8043] = {1, 12, pack_dac8043},
4741         [ad8522] = {2, 12, pack_ad8522},
4742         [ad8804] = {12, 8, pack_ad8804},
4743         [ad8842] = {8, 8, pack_ad8842},
4744         [ad8804_debug] = {16, 8, pack_ad8804},
4745 };
4746
4747 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4748 {
4749         const struct ni_board_struct *board = comedi_board(dev);
4750         struct ni_private *devpriv = dev->private;
4751         int i, j;
4752         int n_dacs;
4753         int n_chans = 0;
4754         int n_bits;
4755         int diffbits = 0;
4756         int type;
4757         int chan;
4758
4759         type = board->caldac[0];
4760         if (type == caldac_none)
4761                 return;
4762         n_bits = caldacs[type].n_bits;
4763         for (i = 0; i < 3; i++) {
4764                 type = board->caldac[i];
4765                 if (type == caldac_none)
4766                         break;
4767                 if (caldacs[type].n_bits != n_bits)
4768                         diffbits = 1;
4769                 n_chans += caldacs[type].n_chans;
4770         }
4771         n_dacs = i;
4772         s->n_chan = n_chans;
4773
4774         if (diffbits) {
4775                 unsigned int *maxdata_list;
4776
4777                 if (n_chans > MAX_N_CALDACS)
4778                         printk("BUG! MAX_N_CALDACS too small\n");
4779                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4780                 chan = 0;
4781                 for (i = 0; i < n_dacs; i++) {
4782                         type = board->caldac[i];
4783                         for (j = 0; j < caldacs[type].n_chans; j++) {
4784                                 maxdata_list[chan] =
4785                                     (1 << caldacs[type].n_bits) - 1;
4786                                 chan++;
4787                         }
4788                 }
4789
4790                 for (chan = 0; chan < s->n_chan; chan++)
4791                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4792         } else {
4793                 type = board->caldac[0];
4794                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4795
4796                 for (chan = 0; chan < s->n_chan; chan++)
4797                         ni_write_caldac(dev, i, s->maxdata / 2);
4798         }
4799 }
4800
4801 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4802 {
4803         const struct ni_board_struct *board = comedi_board(dev);
4804         struct ni_private *devpriv = dev->private;
4805         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4806         int i;
4807         int type;
4808
4809         /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4810         if (devpriv->caldacs[addr] == val)
4811                 return;
4812         devpriv->caldacs[addr] = val;
4813
4814         for (i = 0; i < 3; i++) {
4815                 type = board->caldac[i];
4816                 if (type == caldac_none)
4817                         break;
4818                 if (addr < caldacs[type].n_chans) {
4819                         bits = caldacs[type].packbits(addr, val, &bitstring);
4820                         loadbit = SerDacLd(i);
4821                         /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
4822                         break;
4823                 }
4824                 addr -= caldacs[type].n_chans;
4825         }
4826
4827         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4828                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4829                 udelay(1);
4830                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4831                 udelay(1);
4832         }
4833         ni_writeb(loadbit, Serial_Command);
4834         udelay(1);
4835         ni_writeb(0, Serial_Command);
4836 }
4837
4838 static int pack_mb88341(int addr, int val, int *bitstring)
4839 {
4840         /*
4841            Fujitsu MB 88341
4842            Note that address bits are reversed.  Thanks to
4843            Ingo Keen for noticing this.
4844
4845            Note also that the 88341 expects address values from
4846            1-12, whereas we use channel numbers 0-11.  The NI
4847            docs use 1-12, also, so be careful here.
4848          */
4849         addr++;
4850         *bitstring = ((addr & 0x1) << 11) |
4851             ((addr & 0x2) << 9) |
4852             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4853         return 12;
4854 }
4855
4856 static int pack_dac8800(int addr, int val, int *bitstring)
4857 {
4858         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4859         return 11;
4860 }
4861
4862 static int pack_dac8043(int addr, int val, int *bitstring)
4863 {
4864         *bitstring = val & 0xfff;
4865         return 12;
4866 }
4867
4868 static int pack_ad8522(int addr, int val, int *bitstring)
4869 {
4870         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4871         return 16;
4872 }
4873
4874 static int pack_ad8804(int addr, int val, int *bitstring)
4875 {
4876         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4877         return 12;
4878 }
4879
4880 static int pack_ad8842(int addr, int val, int *bitstring)
4881 {
4882         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4883         return 12;
4884 }
4885
4886 #if 0
4887 /*
4888  *      Read the GPCTs current value.
4889  */
4890 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
4891 {
4892         unsigned int hi1, hi2, lo;
4893
4894         devpriv->gpct_command[chan] &= ~G_Save_Trace;
4895         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4896                             G_Command_Register(chan));
4897
4898         devpriv->gpct_command[chan] |= G_Save_Trace;
4899         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4900                             G_Command_Register(chan));
4901
4902         /* This procedure is used because the two registers cannot
4903          * be read atomically. */
4904         do {
4905                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
4906                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
4907                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
4908         } while (hi1 != hi2);
4909
4910         return (hi1 << 16) | lo;
4911 }
4912
4913 static void GPCT_Reset(struct comedi_device *dev, int chan)
4914 {
4915         int temp_ack_reg = 0;
4916
4917         /* printk("GPCT_Reset..."); */
4918         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4919
4920         switch (chan) {
4921         case 0:
4922                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
4923                 ni_set_bits(dev, Interrupt_A_Enable_Register,
4924                             G0_TC_Interrupt_Enable, 0);
4925                 ni_set_bits(dev, Interrupt_A_Enable_Register,
4926                             G0_Gate_Interrupt_Enable, 0);
4927                 temp_ack_reg |= G0_Gate_Error_Confirm;
4928                 temp_ack_reg |= G0_TC_Error_Confirm;
4929                 temp_ack_reg |= G0_TC_Interrupt_Ack;
4930                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
4931                 devpriv->stc_writew(dev, temp_ack_reg,
4932                                     Interrupt_A_Ack_Register);
4933
4934                 /* problem...this interferes with the other ctr... */
4935                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4936                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
4937                                     Analog_Trigger_Etc_Register);
4938                 break;
4939         case 1:
4940                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
4941                 ni_set_bits(dev, Interrupt_B_Enable_Register,
4942                             G1_TC_Interrupt_Enable, 0);
4943                 ni_set_bits(dev, Interrupt_B_Enable_Register,
4944                             G0_Gate_Interrupt_Enable, 0);
4945                 temp_ack_reg |= G1_Gate_Error_Confirm;
4946                 temp_ack_reg |= G1_TC_Error_Confirm;
4947                 temp_ack_reg |= G1_TC_Interrupt_Ack;
4948                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
4949                 devpriv->stc_writew(dev, temp_ack_reg,
4950                                     Interrupt_B_Ack_Register);
4951
4952                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4953                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
4954                                     Analog_Trigger_Etc_Register);
4955                 break;
4956         }
4957
4958         devpriv->gpct_mode[chan] = 0;
4959         devpriv->gpct_input_select[chan] = 0;
4960         devpriv->gpct_command[chan] = 0;
4961
4962         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4963
4964         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
4965                             G_Mode_Register(chan));
4966         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
4967                             G_Input_Select_Register(chan));
4968         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
4969
4970         /* printk("exit GPCT_Reset\n"); */
4971 }
4972
4973 #endif
4974
4975 #ifdef PCIDMA
4976 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4977 {
4978         struct ni_gpct *counter = s->private;
4979         int retval;
4980
4981         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4982                                               COMEDI_INPUT);
4983         if (retval) {
4984                 comedi_error(dev,
4985                              "no dma channel available for use by counter");
4986                 return retval;
4987         }
4988         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
4989         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4990
4991         return ni_tio_cmd(dev, s);
4992 }
4993 #endif
4994
4995 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4996 {
4997 #ifdef PCIDMA
4998         struct ni_gpct *counter = s->private;
4999         int retval;
5000
5001         retval = ni_tio_cancel(counter);
5002         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5003         ni_release_gpct_mite_channel(dev, counter->counter_index);
5004         return retval;
5005 #else
5006         return 0;
5007 #endif
5008 }
5009
5010 /*
5011  *
5012  *  Programmable Function Inputs
5013  *
5014  */
5015
5016 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5017                                        unsigned source)
5018 {
5019         struct ni_private *devpriv = dev->private;
5020         unsigned pfi_reg_index;
5021         unsigned array_offset;
5022
5023         if ((source & 0x1f) != source)
5024                 return -EINVAL;
5025         pfi_reg_index = 1 + chan / 3;
5026         array_offset = pfi_reg_index - 1;
5027         devpriv->pfi_output_select_reg[array_offset] &=
5028             ~MSeries_PFI_Output_Select_Mask(chan);
5029         devpriv->pfi_output_select_reg[array_offset] |=
5030             MSeries_PFI_Output_Select_Bits(chan, source);
5031         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5032                   M_Offset_PFI_Output_Select(pfi_reg_index));
5033         return 2;
5034 }
5035
5036 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5037                                   unsigned source)
5038 {
5039         /*  pre-m-series boards have fixed signals on pfi pins */
5040         if (source != ni_old_get_pfi_routing(dev, chan))
5041                 return -EINVAL;
5042         return 2;
5043 }
5044
5045 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5046                               unsigned source)
5047 {
5048         const struct ni_board_struct *board = comedi_board(dev);
5049
5050         if (board->reg_type & ni_reg_m_series_mask)
5051                 return ni_m_series_set_pfi_routing(dev, chan, source);
5052         else
5053                 return ni_old_set_pfi_routing(dev, chan, source);
5054 }
5055
5056 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5057                                             unsigned chan)
5058 {
5059         struct ni_private *devpriv = dev->private;
5060         const unsigned array_offset = chan / 3;
5061
5062         return MSeries_PFI_Output_Select_Source(chan,
5063                                                 devpriv->
5064                                                 pfi_output_select_reg
5065                                                 [array_offset]);
5066 }
5067
5068 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5069 {
5070         /*  pre-m-series boards have fixed signals on pfi pins */
5071         switch (chan) {
5072         case 0:
5073                 return NI_PFI_OUTPUT_AI_START1;
5074                 break;
5075         case 1:
5076                 return NI_PFI_OUTPUT_AI_START2;
5077                 break;
5078         case 2:
5079                 return NI_PFI_OUTPUT_AI_CONVERT;
5080                 break;
5081         case 3:
5082                 return NI_PFI_OUTPUT_G_SRC1;
5083                 break;
5084         case 4:
5085                 return NI_PFI_OUTPUT_G_GATE1;
5086                 break;
5087         case 5:
5088                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5089                 break;
5090         case 6:
5091                 return NI_PFI_OUTPUT_AO_START1;
5092                 break;
5093         case 7:
5094                 return NI_PFI_OUTPUT_AI_START_PULSE;
5095                 break;
5096         case 8:
5097                 return NI_PFI_OUTPUT_G_SRC0;
5098                 break;
5099         case 9:
5100                 return NI_PFI_OUTPUT_G_GATE0;
5101                 break;
5102         default:
5103                 printk("%s: bug, unhandled case in switch.\n", __func__);
5104                 break;
5105         }
5106         return 0;
5107 }
5108
5109 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5110 {
5111         const struct ni_board_struct *board = comedi_board(dev);
5112
5113         if (board->reg_type & ni_reg_m_series_mask)
5114                 return ni_m_series_get_pfi_routing(dev, chan);
5115         else
5116                 return ni_old_get_pfi_routing(dev, chan);
5117 }
5118
5119 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5120                             enum ni_pfi_filter_select filter)
5121 {
5122         const struct ni_board_struct *board = comedi_board(dev);
5123         struct ni_private *devpriv __maybe_unused = dev->private;
5124         unsigned bits;
5125
5126         if ((board->reg_type & ni_reg_m_series_mask) == 0)
5127                 return -ENOTSUPP;
5128         bits = ni_readl(M_Offset_PFI_Filter);
5129         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5130         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5131         ni_writel(bits, M_Offset_PFI_Filter);
5132         return 0;
5133 }
5134
5135 static int ni_pfi_insn_bits(struct comedi_device *dev,
5136                             struct comedi_subdevice *s,
5137                             struct comedi_insn *insn,
5138                             unsigned int *data)
5139 {
5140         const struct ni_board_struct *board = comedi_board(dev);
5141         struct ni_private *devpriv __maybe_unused = dev->private;
5142
5143         if (!(board->reg_type & ni_reg_m_series_mask))
5144                 return -ENOTSUPP;
5145
5146         if (comedi_dio_update_state(s, data))
5147                 ni_writew(s->state, M_Offset_PFI_DO);
5148
5149         data[1] = ni_readw(M_Offset_PFI_DI);
5150
5151         return insn->n;
5152 }
5153
5154 static int ni_pfi_insn_config(struct comedi_device *dev,
5155                               struct comedi_subdevice *s,
5156                               struct comedi_insn *insn, unsigned int *data)
5157 {
5158         struct ni_private *devpriv = dev->private;
5159         unsigned int chan;
5160
5161         if (insn->n < 1)
5162                 return -EINVAL;
5163
5164         chan = CR_CHAN(insn->chanspec);
5165
5166         switch (data[0]) {
5167         case COMEDI_OUTPUT:
5168                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5169                 break;
5170         case COMEDI_INPUT:
5171                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5172                 break;
5173         case INSN_CONFIG_DIO_QUERY:
5174                 data[1] =
5175                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5176                     COMEDI_OUTPUT : COMEDI_INPUT;
5177                 return 0;
5178                 break;
5179         case INSN_CONFIG_SET_ROUTING:
5180                 return ni_set_pfi_routing(dev, chan, data[1]);
5181                 break;
5182         case INSN_CONFIG_GET_ROUTING:
5183                 data[1] = ni_get_pfi_routing(dev, chan);
5184                 break;
5185         case INSN_CONFIG_FILTER:
5186                 return ni_config_filter(dev, chan, data[1]);
5187                 break;
5188         default:
5189                 return -EINVAL;
5190         }
5191         return 0;
5192 }
5193
5194 /*
5195  *
5196  *  NI RTSI Bus Functions
5197  *
5198  */
5199 static void ni_rtsi_init(struct comedi_device *dev)
5200 {
5201         const struct ni_board_struct *board = comedi_board(dev);
5202         struct ni_private *devpriv = dev->private;
5203
5204         /*  Initialises the RTSI bus signal switch to a default state */
5205
5206         /*  Set clock mode to internal */
5207         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5208         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5209                 printk("ni_set_master_clock failed, bug?");
5210         /*  default internal lines routing to RTSI bus lines */
5211         devpriv->rtsi_trig_a_output_reg =
5212             RTSI_Trig_Output_Bits(0,
5213                                   NI_RTSI_OUTPUT_ADR_START1) |
5214             RTSI_Trig_Output_Bits(1,
5215                                   NI_RTSI_OUTPUT_ADR_START2) |
5216             RTSI_Trig_Output_Bits(2,
5217                                   NI_RTSI_OUTPUT_SCLKG) |
5218             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5219         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5220                             RTSI_Trig_A_Output_Register);
5221         devpriv->rtsi_trig_b_output_reg =
5222             RTSI_Trig_Output_Bits(4,
5223                                   NI_RTSI_OUTPUT_DA_START1) |
5224             RTSI_Trig_Output_Bits(5,
5225                                   NI_RTSI_OUTPUT_G_SRC0) |
5226             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5227         if (board->reg_type & ni_reg_m_series_mask)
5228                 devpriv->rtsi_trig_b_output_reg |=
5229                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5230         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5231                             RTSI_Trig_B_Output_Register);
5232
5233 /*
5234 * Sets the source and direction of the 4 on board lines
5235 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5236 */
5237 }
5238
5239 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5240                              struct comedi_subdevice *s,
5241                              struct comedi_insn *insn, unsigned int *data)
5242 {
5243         data[1] = 0;
5244
5245         return insn->n;
5246 }
5247
5248 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5249  * given an arbitrary frequency input clock */
5250 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5251                                          unsigned *freq_divider,
5252                                          unsigned *freq_multiplier,
5253                                          unsigned *actual_period_ns)
5254 {
5255         unsigned div;
5256         unsigned best_div = 1;
5257         static const unsigned max_div = 0x10;
5258         unsigned mult;
5259         unsigned best_mult = 1;
5260         static const unsigned max_mult = 0x100;
5261         static const unsigned pico_per_nano = 1000;
5262
5263         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5264         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5265          * 20 MHz for most timing clocks */
5266         static const unsigned target_picosec = 12500;
5267         static const unsigned fudge_factor_80_to_20Mhz = 4;
5268         int best_period_picosec = 0;
5269         for (div = 1; div <= max_div; ++div) {
5270                 for (mult = 1; mult <= max_mult; ++mult) {
5271                         unsigned new_period_ps =
5272                             (reference_picosec * div) / mult;
5273                         if (abs(new_period_ps - target_picosec) <
5274                             abs(best_period_picosec - target_picosec)) {
5275                                 best_period_picosec = new_period_ps;
5276                                 best_div = div;
5277                                 best_mult = mult;
5278                         }
5279                 }
5280         }
5281         if (best_period_picosec == 0) {
5282                 printk("%s: bug, failed to find pll parameters\n", __func__);
5283                 return -EIO;
5284         }
5285         *freq_divider = best_div;
5286         *freq_multiplier = best_mult;
5287         *actual_period_ns =
5288             (best_period_picosec * fudge_factor_80_to_20Mhz +
5289              (pico_per_nano / 2)) / pico_per_nano;
5290         return 0;
5291 }
5292
5293 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5294 {
5295         const struct ni_board_struct *board = comedi_board(dev);
5296
5297         if (board->reg_type & ni_reg_m_series_mask)
5298                 return 8;
5299         else
5300                 return 7;
5301 }
5302
5303 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5304                                            unsigned source, unsigned period_ns)
5305 {
5306         struct ni_private *devpriv = dev->private;
5307         static const unsigned min_period_ns = 50;
5308         static const unsigned max_period_ns = 1000;
5309         static const unsigned timeout = 1000;
5310         unsigned pll_control_bits;
5311         unsigned freq_divider;
5312         unsigned freq_multiplier;
5313         unsigned i;
5314         int retval;
5315
5316         if (source == NI_MIO_PLL_PXI10_CLOCK)
5317                 period_ns = 100;
5318         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5319         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5320                 printk
5321                     ("%s: you must specify an input clock frequency between %i and %i nanosec "
5322                      "for the phased-lock loop.\n", __func__,
5323                      min_period_ns, max_period_ns);
5324                 return -EINVAL;
5325         }
5326         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5327         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5328                             RTSI_Trig_Direction_Register);
5329         pll_control_bits =
5330             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5331         devpriv->clock_and_fout2 |=
5332             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5333         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5334         switch (source) {
5335         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5336                 devpriv->clock_and_fout2 |=
5337                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5338                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5339                                                        &freq_multiplier,
5340                                                        &devpriv->clock_ns);
5341                 if (retval < 0)
5342                         return retval;
5343                 break;
5344         case NI_MIO_PLL_PXI10_CLOCK:
5345                 /* pxi clock is 10MHz */
5346                 devpriv->clock_and_fout2 |=
5347                     MSeries_PLL_In_Source_Select_PXI_Clock10;
5348                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5349                                                        &freq_multiplier,
5350                                                        &devpriv->clock_ns);
5351                 if (retval < 0)
5352                         return retval;
5353                 break;
5354         default:
5355                 {
5356                         unsigned rtsi_channel;
5357                         static const unsigned max_rtsi_channel = 7;
5358                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5359                              ++rtsi_channel) {
5360                                 if (source ==
5361                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5362                                         devpriv->clock_and_fout2 |=
5363                                             MSeries_PLL_In_Source_Select_RTSI_Bits
5364                                             (rtsi_channel);
5365                                         break;
5366                                 }
5367                         }
5368                         if (rtsi_channel > max_rtsi_channel)
5369                                 return -EINVAL;
5370                         retval = ni_mseries_get_pll_parameters(period_ns,
5371                                                                &freq_divider,
5372                                                                &freq_multiplier,
5373                                                                &devpriv->
5374                                                                clock_ns);
5375                         if (retval < 0)
5376                                 return retval;
5377                 }
5378                 break;
5379         }
5380         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5381         pll_control_bits |=
5382             MSeries_PLL_Divisor_Bits(freq_divider) |
5383             MSeries_PLL_Multiplier_Bits(freq_multiplier);
5384
5385         /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5386          * freq_divider, freq_multiplier, pll_control_bits); */
5387         /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5388         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5389         devpriv->clock_source = source;
5390         /* it seems to typically take a few hundred microseconds for PLL to lock */
5391         for (i = 0; i < timeout; ++i) {
5392                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
5393                         break;
5394                 udelay(1);
5395         }
5396         if (i == timeout) {
5397                 printk
5398                     ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5399                      __func__, source, period_ns);
5400                 return -ETIMEDOUT;
5401         }
5402         return 3;
5403 }
5404
5405 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5406                                unsigned period_ns)
5407 {
5408         const struct ni_board_struct *board = comedi_board(dev);
5409         struct ni_private *devpriv = dev->private;
5410
5411         if (source == NI_MIO_INTERNAL_CLOCK) {
5412                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5413                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5414                                     RTSI_Trig_Direction_Register);
5415                 devpriv->clock_ns = TIMEBASE_1_NS;
5416                 if (board->reg_type & ni_reg_m_series_mask) {
5417                         devpriv->clock_and_fout2 &=
5418                             ~(MSeries_Timebase1_Select_Bit |
5419                               MSeries_Timebase3_Select_Bit);
5420                         ni_writew(devpriv->clock_and_fout2,
5421                                   M_Offset_Clock_and_Fout2);
5422                         ni_writew(0, M_Offset_PLL_Control);
5423                 }
5424                 devpriv->clock_source = source;
5425         } else {
5426                 if (board->reg_type & ni_reg_m_series_mask) {
5427                         return ni_mseries_set_pll_master_clock(dev, source,
5428                                                                period_ns);
5429                 } else {
5430                         if (source == NI_MIO_RTSI_CLOCK) {
5431                                 devpriv->rtsi_trig_direction_reg |=
5432                                     Use_RTSI_Clock_Bit;
5433                                 devpriv->stc_writew(dev,
5434                                                     devpriv->
5435                                                     rtsi_trig_direction_reg,
5436                                                     RTSI_Trig_Direction_Register);
5437                                 if (period_ns == 0) {
5438                                         printk
5439                                             ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5440                                              __func__);
5441                                         return -EINVAL;
5442                                 } else {
5443                                         devpriv->clock_ns = period_ns;
5444                                 }
5445                                 devpriv->clock_source = source;
5446                         } else
5447                                 return -EINVAL;
5448                 }
5449         }
5450         return 3;
5451 }
5452
5453 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5454                                        unsigned source)
5455 {
5456         const struct ni_board_struct *board = comedi_board(dev);
5457
5458         if (chan >= num_configurable_rtsi_channels(dev)) {
5459                 if (chan == old_RTSI_clock_channel) {
5460                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5461                                 return 1;
5462                         else {
5463                                 printk
5464                                     ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5465                                      __func__, chan, old_RTSI_clock_channel);
5466                                 return 0;
5467                         }
5468                 }
5469                 return 0;
5470         }
5471         switch (source) {
5472         case NI_RTSI_OUTPUT_ADR_START1:
5473         case NI_RTSI_OUTPUT_ADR_START2:
5474         case NI_RTSI_OUTPUT_SCLKG:
5475         case NI_RTSI_OUTPUT_DACUPDN:
5476         case NI_RTSI_OUTPUT_DA_START1:
5477         case NI_RTSI_OUTPUT_G_SRC0:
5478         case NI_RTSI_OUTPUT_G_GATE0:
5479         case NI_RTSI_OUTPUT_RGOUT0:
5480         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5481                 return 1;
5482                 break;
5483         case NI_RTSI_OUTPUT_RTSI_OSC:
5484                 if (board->reg_type & ni_reg_m_series_mask)
5485                         return 1;
5486                 else
5487                         return 0;
5488                 break;
5489         default:
5490                 return 0;
5491                 break;
5492         }
5493 }
5494
5495 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5496                                unsigned source)
5497 {
5498         struct ni_private *devpriv = dev->private;
5499
5500         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5501                 return -EINVAL;
5502         if (chan < 4) {
5503                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5504                 devpriv->rtsi_trig_a_output_reg |=
5505                     RTSI_Trig_Output_Bits(chan, source);
5506                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5507                                     RTSI_Trig_A_Output_Register);
5508         } else if (chan < 8) {
5509                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5510                 devpriv->rtsi_trig_b_output_reg |=
5511                     RTSI_Trig_Output_Bits(chan, source);
5512                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5513                                     RTSI_Trig_B_Output_Register);
5514         }
5515         return 2;
5516 }
5517
5518 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5519 {
5520         struct ni_private *devpriv = dev->private;
5521
5522         if (chan < 4) {
5523                 return RTSI_Trig_Output_Source(chan,
5524                                                devpriv->rtsi_trig_a_output_reg);
5525         } else if (chan < num_configurable_rtsi_channels(dev)) {
5526                 return RTSI_Trig_Output_Source(chan,
5527                                                devpriv->rtsi_trig_b_output_reg);
5528         } else {
5529                 if (chan == old_RTSI_clock_channel)
5530                         return NI_RTSI_OUTPUT_RTSI_OSC;
5531                 printk("%s: bug! should never get here?\n", __func__);
5532                 return 0;
5533         }
5534 }
5535
5536 static int ni_rtsi_insn_config(struct comedi_device *dev,
5537                                struct comedi_subdevice *s,
5538                                struct comedi_insn *insn, unsigned int *data)
5539 {
5540         const struct ni_board_struct *board = comedi_board(dev);
5541         struct ni_private *devpriv = dev->private;
5542         unsigned int chan = CR_CHAN(insn->chanspec);
5543
5544         switch (data[0]) {
5545         case INSN_CONFIG_DIO_OUTPUT:
5546                 if (chan < num_configurable_rtsi_channels(dev)) {
5547                         devpriv->rtsi_trig_direction_reg |=
5548                             RTSI_Output_Bit(chan,
5549                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5550                 } else if (chan == old_RTSI_clock_channel) {
5551                         devpriv->rtsi_trig_direction_reg |=
5552                             Drive_RTSI_Clock_Bit;
5553                 }
5554                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5555                                     RTSI_Trig_Direction_Register);
5556                 break;
5557         case INSN_CONFIG_DIO_INPUT:
5558                 if (chan < num_configurable_rtsi_channels(dev)) {
5559                         devpriv->rtsi_trig_direction_reg &=
5560                             ~RTSI_Output_Bit(chan,
5561                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5562                 } else if (chan == old_RTSI_clock_channel) {
5563                         devpriv->rtsi_trig_direction_reg &=
5564                             ~Drive_RTSI_Clock_Bit;
5565                 }
5566                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5567                                     RTSI_Trig_Direction_Register);
5568                 break;
5569         case INSN_CONFIG_DIO_QUERY:
5570                 if (chan < num_configurable_rtsi_channels(dev)) {
5571                         data[1] =
5572                             (devpriv->rtsi_trig_direction_reg &
5573                              RTSI_Output_Bit(chan,
5574                                 (board->reg_type & ni_reg_m_series_mask) != 0))
5575                                 ? INSN_CONFIG_DIO_OUTPUT
5576                                 : INSN_CONFIG_DIO_INPUT;
5577                 } else if (chan == old_RTSI_clock_channel) {
5578                         data[1] =
5579                             (devpriv->rtsi_trig_direction_reg &
5580                              Drive_RTSI_Clock_Bit)
5581                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5582                 }
5583                 return 2;
5584                 break;
5585         case INSN_CONFIG_SET_CLOCK_SRC:
5586                 return ni_set_master_clock(dev, data[1], data[2]);
5587                 break;
5588         case INSN_CONFIG_GET_CLOCK_SRC:
5589                 data[1] = devpriv->clock_source;
5590                 data[2] = devpriv->clock_ns;
5591                 return 3;
5592                 break;
5593         case INSN_CONFIG_SET_ROUTING:
5594                 return ni_set_rtsi_routing(dev, chan, data[1]);
5595                 break;
5596         case INSN_CONFIG_GET_ROUTING:
5597                 data[1] = ni_get_rtsi_routing(dev, chan);
5598                 return 2;
5599                 break;
5600         default:
5601                 return -EINVAL;
5602                 break;
5603         }
5604         return 1;
5605 }
5606
5607 static int cs5529_wait_for_idle(struct comedi_device *dev)
5608 {
5609         unsigned short status;
5610         const int timeout = HZ;
5611         int i;
5612
5613         for (i = 0; i < timeout; i++) {
5614                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5615                 if ((status & CSS_ADC_BUSY) == 0)
5616                         break;
5617                 set_current_state(TASK_INTERRUPTIBLE);
5618                 if (schedule_timeout(1))
5619                         return -EIO;
5620         }
5621 /* printk("looped %i times waiting for idle\n", i); */
5622         if (i == timeout) {
5623                 printk("%s: %s: timeout\n", __FILE__, __func__);
5624                 return -ETIME;
5625         }
5626         return 0;
5627 }
5628
5629 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5630 {
5631         static const int timeout = 100;
5632         int i;
5633
5634         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5635         /* give time for command to start being serially clocked into cs5529.
5636          * this insures that the CSS_ADC_BUSY bit will get properly
5637          * set before we exit this function.
5638          */
5639         for (i = 0; i < timeout; i++) {
5640                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5641                         break;
5642                 udelay(1);
5643         }
5644 /* printk("looped %i times writing command to cs5529\n", i); */
5645         if (i == timeout)
5646                 comedi_error(dev, "possible problem - never saw adc go busy?");
5647 }
5648
5649 /* write to cs5529 register */
5650 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5651                                 unsigned int reg_select_bits)
5652 {
5653         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5654                        CAL_ADC_Config_Data_High_Word_67xx);
5655         ni_ao_win_outw(dev, (value & 0xffff),
5656                        CAL_ADC_Config_Data_Low_Word_67xx);
5657         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5658         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5659         if (cs5529_wait_for_idle(dev))
5660                 comedi_error(dev, "time or signal in cs5529_config_write()");
5661 }
5662
5663 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5664 {
5665         int retval;
5666         unsigned short status;
5667
5668         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5669         retval = cs5529_wait_for_idle(dev);
5670         if (retval) {
5671                 comedi_error(dev,
5672                              "timeout or signal in cs5529_do_conversion()");
5673                 return -ETIME;
5674         }
5675         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5676         if (status & CSS_OSC_DETECT) {
5677                 printk
5678                     ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5679                 return -EIO;
5680         }
5681         if (status & CSS_OVERRANGE) {
5682                 printk
5683                     ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5684         }
5685         if (data) {
5686                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5687                 /* cs5529 returns 16 bit signed data in bipolar mode */
5688                 *data ^= (1 << 15);
5689         }
5690         return 0;
5691 }
5692
5693 static int cs5529_ai_insn_read(struct comedi_device *dev,
5694                                struct comedi_subdevice *s,
5695                                struct comedi_insn *insn, unsigned int *data)
5696 {
5697         int n, retval;
5698         unsigned short sample;
5699         unsigned int channel_select;
5700         const unsigned int INTERNAL_REF = 0x1000;
5701
5702         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5703          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5704          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5705         if (insn->chanspec & CR_ALT_SOURCE)
5706                 channel_select = INTERNAL_REF;
5707         else
5708                 channel_select = CR_CHAN(insn->chanspec);
5709         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5710
5711         for (n = 0; n < insn->n; n++) {
5712                 retval = cs5529_do_conversion(dev, &sample);
5713                 if (retval < 0)
5714                         return retval;
5715                 data[n] = sample;
5716         }
5717         return insn->n;
5718 }
5719
5720 static int init_cs5529(struct comedi_device *dev)
5721 {
5722         unsigned int config_bits =
5723             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5724
5725 #if 1
5726         /* do self-calibration */
5727         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5728                             CSCMD_CONFIG_REGISTER);
5729         /* need to force a conversion for calibration to run */
5730         cs5529_do_conversion(dev, NULL);
5731 #else
5732         /* force gain calibration to 1 */
5733         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5734         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5735                             CSCMD_CONFIG_REGISTER);
5736         if (cs5529_wait_for_idle(dev))
5737                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5738 #endif
5739         return 0;
5740 }