drivers/staging/rdma/hfi1/verbs.c

   1 /*
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2015 Intel Corporation.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * BSD LICENSE
  20  *
  21  * Copyright(c) 2015 Intel Corporation.
  22  *
  23  * Redistribution and use in source and binary forms, with or without
  24  * modification, are permitted provided that the following conditions
  25  * are met:
  26  *
  27  *  - Redistributions of source code must retain the above copyright
  28  *    notice, this list of conditions and the following disclaimer.
  29  *  - Redistributions in binary form must reproduce the above copyright
  30  *    notice, this list of conditions and the following disclaimer in
  31  *    the documentation and/or other materials provided with the
  32  *    distribution.
  33  *  - Neither the name of Intel Corporation nor the names of its
  34  *    contributors may be used to endorse or promote products derived
  35  *    from this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  */
  50
  51 #include <rdma/ib_mad.h>
  52 #include <rdma/ib_user_verbs.h>
  53 #include <linux/io.h>
  54 #include <linux/module.h>
  55 #include <linux/utsname.h>
  56 #include <linux/rculist.h>
  57 #include <linux/mm.h>
  58 #include <linux/random.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "hfi.h"
  62 #include "common.h"
  63 #include "device.h"
  64 #include "trace.h"
  65 #include "qp.h"
  66 #include "sdma.h"
  67
  68 unsigned int hfi1_lkey_table_size = 16;
  69 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
  70                    S_IRUGO);
  71 MODULE_PARM_DESC(lkey_table_size,
  72                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  73
  74 static unsigned int hfi1_max_pds = 0xFFFF;
  75 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
  76 MODULE_PARM_DESC(max_pds,
  77                  "Maximum number of protection domains to support");
  78
  79 static unsigned int hfi1_max_ahs = 0xFFFF;
  80 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
  81 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  82
  83 unsigned int hfi1_max_cqes = 0x2FFFF;
  84 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
  85 MODULE_PARM_DESC(max_cqes,
  86                  "Maximum number of completion queue entries to support");
  87
  88 unsigned int hfi1_max_cqs = 0x1FFFF;
  89 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
  90 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  91
  92 unsigned int hfi1_max_qp_wrs = 0x3FFF;
  93 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
  94 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  95
  96 unsigned int hfi1_max_qps = 16384;
  97 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
  98 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  99
 100 unsigned int hfi1_max_sges = 0x60;
 101 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
 102 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
 103
 104 unsigned int hfi1_max_mcast_grps = 16384;
 105 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
 106 MODULE_PARM_DESC(max_mcast_grps,
 107                  "Maximum number of multicast groups to support");
 108
 109 unsigned int hfi1_max_mcast_qp_attached = 16;
 110 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
 111                    uint, S_IRUGO);
 112 MODULE_PARM_DESC(max_mcast_qp_attached,
 113                  "Maximum number of attached QPs to support");
 114
 115 unsigned int hfi1_max_srqs = 1024;
 116 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
 117 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 118
 119 unsigned int hfi1_max_srq_sges = 128;
 120 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
 121 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 122
 123 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
 124 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
 125 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 126
 127 static void verbs_sdma_complete(
 128         struct sdma_txreq *cookie,
 129         int status,
 130         int drained);
 131
 132 /* Length of buffer to create verbs txreq cache name */
 133 #define TXREQ_NAME_LEN 24
 134
 135 /*
 136  * Note that it is OK to post send work requests in the SQE and ERR
 137  * states; hfi1_do_send() will process them and generate error
 138  * completions as per IB 1.2 C10-96.
 139  */
 140 const int ib_hfi1_state_ops[IB_QPS_ERR + 1] = {
 141         [IB_QPS_RESET] = 0,
 142         [IB_QPS_INIT] = HFI1_POST_RECV_OK,
 143         [IB_QPS_RTR] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK,
 144         [IB_QPS_RTS] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 145             HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK |
 146             HFI1_PROCESS_NEXT_SEND_OK,
 147         [IB_QPS_SQD] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 148             HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK,
 149         [IB_QPS_SQE] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 150             HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
 151         [IB_QPS_ERR] = HFI1_POST_RECV_OK | HFI1_FLUSH_RECV |
 152             HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
 153 };
 154
 155 struct hfi1_ucontext {
 156         struct ib_ucontext ibucontext;
 157 };
 158
 159 static inline struct hfi1_ucontext *to_iucontext(struct ib_ucontext
 160                                                   *ibucontext)
 161 {
 162         return container_of(ibucontext, struct hfi1_ucontext, ibucontext);
 163 }
 164
 165 /*
 166  * Translate ib_wr_opcode into ib_wc_opcode.
 167  */
 168 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
 169         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 170         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 171         [IB_WR_SEND] = IB_WC_SEND,
 172         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 173         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 174         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 175         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
 176 };
 177
 178 /*
 179  * Length of header by opcode, 0 --> not supported
 180  */
 181 const u8 hdr_len_by_opcode[256] = {
 182         /* RC */
 183         [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
 184         [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
 185         [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
 186         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 187         [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
 188         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 189         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 190         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 191         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
 192         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 193         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 194         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 195         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
 196         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
 197         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
 198         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
 199         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
 200         [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
 201         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4,
 202         [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
 203         [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
 204         /* UC */
 205         [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
 206         [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
 207         [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
 208         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 209         [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
 210         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 211         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 212         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 213         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
 214         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 215         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 216         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 217         /* UD */
 218         [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
 219         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
 220 };
 221
 222 static const opcode_handler opcode_handler_tbl[256] = {
 223         /* RC */
 224         [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
 225         [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
 226         [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
 227         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 228         [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
 229         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 230         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
 231         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
 232         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
 233         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 234         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
 235         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 236         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
 237         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
 238         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
 239         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
 240         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
 241         [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
 242         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
 243         [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
 244         [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
 245         /* UC */
 246         [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
 247         [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
 248         [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
 249         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 250         [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
 251         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 252         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
 253         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
 254         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
 255         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 256         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
 257         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 258         /* UD */
 259         [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
 260         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
 261         /* CNP */
 262         [IB_OPCODE_CNP]                               = &hfi1_cnp_rcv
 263 };
 264
 265 /*
 266  * System image GUID.
 267  */
 268 __be64 ib_hfi1_sys_image_guid;
 269
 270 /**
 271  * hfi1_copy_sge - copy data to SGE memory
 272  * @ss: the SGE state
 273  * @data: the data to copy
 274  * @length: the length of the data
 275  */
 276 void hfi1_copy_sge(
 277         struct hfi1_sge_state *ss,
 278         void *data, u32 length,
 279         int release)
 280 {
 281         struct hfi1_sge *sge = &ss->sge;
 282
 283         while (length) {
 284                 u32 len = sge->length;
 285
 286                 if (len > length)
 287                         len = length;
 288                 if (len > sge->sge_length)
 289                         len = sge->sge_length;
 290                 WARN_ON_ONCE(len == 0);
 291                 memcpy(sge->vaddr, data, len);
 292                 sge->vaddr += len;
 293                 sge->length -= len;
 294                 sge->sge_length -= len;
 295                 if (sge->sge_length == 0) {
 296                         if (release)
 297                                 hfi1_put_mr(sge->mr);
 298                         if (--ss->num_sge)
 299                                 *sge = *ss->sg_list++;
 300                 } else if (sge->length == 0 && sge->mr->lkey) {
 301                         if (++sge->n >= HFI1_SEGSZ) {
 302                                 if (++sge->m >= sge->mr->mapsz)
 303                                         break;
 304                                 sge->n = 0;
 305                         }
 306                         sge->vaddr =
 307                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 308                         sge->length =
 309                                 sge->mr->map[sge->m]->segs[sge->n].length;
 310                 }
 311                 data += len;
 312                 length -= len;
 313         }
 314 }
 315
 316 /**
 317  * hfi1_skip_sge - skip over SGE memory
 318  * @ss: the SGE state
 319  * @length: the number of bytes to skip
 320  */
 321 void hfi1_skip_sge(struct hfi1_sge_state *ss, u32 length, int release)
 322 {
 323         struct hfi1_sge *sge = &ss->sge;
 324
 325         while (length) {
 326                 u32 len = sge->length;
 327
 328                 if (len > length)
 329                         len = length;
 330                 if (len > sge->sge_length)
 331                         len = sge->sge_length;
 332                 WARN_ON_ONCE(len == 0);
 333                 sge->vaddr += len;
 334                 sge->length -= len;
 335                 sge->sge_length -= len;
 336                 if (sge->sge_length == 0) {
 337                         if (release)
 338                                 hfi1_put_mr(sge->mr);
 339                         if (--ss->num_sge)
 340                                 *sge = *ss->sg_list++;
 341                 } else if (sge->length == 0 && sge->mr->lkey) {
 342                         if (++sge->n >= HFI1_SEGSZ) {
 343                                 if (++sge->m >= sge->mr->mapsz)
 344                                         break;
 345                                 sge->n = 0;
 346                         }
 347                         sge->vaddr =
 348                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 349                         sge->length =
 350                                 sge->mr->map[sge->m]->segs[sge->n].length;
 351                 }
 352                 length -= len;
 353         }
 354 }
 355
 356 /**
 357  * post_one_send - post one RC, UC, or UD send work request
 358  * @qp: the QP to post on
 359  * @wr: the work request to send
 360  */
 361 static int post_one_send(struct hfi1_qp *qp, struct ib_send_wr *wr)
 362 {
 363         struct hfi1_swqe *wqe;
 364         u32 next;
 365         int i;
 366         int j;
 367         int acc;
 368         struct hfi1_lkey_table *rkt;
 369         struct hfi1_pd *pd;
 370         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
 371         struct hfi1_pportdata *ppd;
 372         struct hfi1_ibport *ibp;
 373
 374         /* IB spec says that num_sge == 0 is OK. */
 375         if (unlikely(wr->num_sge > qp->s_max_sge))
 376                 return -EINVAL;
 377
 378         ppd = &dd->pport[qp->port_num - 1];
 379         ibp = &ppd->ibport_data;
 380
 381         /*
 382          * Don't allow RDMA reads or atomic operations on UC or
 383          * undefined operations.
 384          * Make sure buffer is large enough to hold the result for atomics.
 385          */
 386         if (qp->ibqp.qp_type == IB_QPT_UC) {
 387                 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
 388                         return -EINVAL;
 389         } else if (qp->ibqp.qp_type != IB_QPT_RC) {
 390                 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
 391                 if (wr->opcode != IB_WR_SEND &&
 392                     wr->opcode != IB_WR_SEND_WITH_IMM)
 393                         return -EINVAL;
 394                 /* Check UD destination address PD */
 395                 if (qp->ibqp.pd != ud_wr(wr)->ah->pd)
 396                         return -EINVAL;
 397         } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
 398                 return -EINVAL;
 399         else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
 400                    (wr->num_sge == 0 ||
 401                     wr->sg_list[0].length < sizeof(u64) ||
 402                     wr->sg_list[0].addr & (sizeof(u64) - 1)))
 403                 return -EINVAL;
 404         else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
 405                 return -EINVAL;
 406
 407         next = qp->s_head + 1;
 408         if (next >= qp->s_size)
 409                 next = 0;
 410         if (next == qp->s_last)
 411                 return -ENOMEM;
 412
 413         rkt = &to_idev(qp->ibqp.device)->lk_table;
 414         pd = to_ipd(qp->ibqp.pd);
 415         wqe = get_swqe_ptr(qp, qp->s_head);
 416
 417
 418         if (qp->ibqp.qp_type != IB_QPT_UC &&
 419             qp->ibqp.qp_type != IB_QPT_RC)
 420                 memcpy(&wqe->ud_wr, ud_wr(wr), sizeof(wqe->ud_wr));
 421         else if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM ||
 422                  wr->opcode == IB_WR_RDMA_WRITE ||
 423                  wr->opcode == IB_WR_RDMA_READ)
 424                 memcpy(&wqe->rdma_wr, rdma_wr(wr), sizeof(wqe->rdma_wr));
 425         else if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
 426                  wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
 427                 memcpy(&wqe->atomic_wr, atomic_wr(wr), sizeof(wqe->atomic_wr));
 428         else
 429                 memcpy(&wqe->wr, wr, sizeof(wqe->wr));
 430
 431         wqe->length = 0;
 432         j = 0;
 433         if (wr->num_sge) {
 434                 acc = wr->opcode >= IB_WR_RDMA_READ ?
 435                         IB_ACCESS_LOCAL_WRITE : 0;
 436                 for (i = 0; i < wr->num_sge; i++) {
 437                         u32 length = wr->sg_list[i].length;
 438                         int ok;
 439
 440                         if (length == 0)
 441                                 continue;
 442                         ok = hfi1_lkey_ok(rkt, pd, &wqe->sg_list[j],
 443                                           &wr->sg_list[i], acc);
 444                         if (!ok)
 445                                 goto bail_inval_free;
 446                         wqe->length += length;
 447                         j++;
 448                 }
 449                 wqe->wr.num_sge = j;
 450         }
 451         if (qp->ibqp.qp_type == IB_QPT_UC ||
 452             qp->ibqp.qp_type == IB_QPT_RC) {
 453                 if (wqe->length > 0x80000000U)
 454                         goto bail_inval_free;
 455         } else {
 456                 struct hfi1_ah *ah = to_iah(ud_wr(wr)->ah);
 457
 458                 atomic_inc(&ah->refcount);
 459         }
 460         wqe->ssn = qp->s_ssn++;
 461         qp->s_head = next;
 462
 463         return 0;
 464
 465 bail_inval_free:
 466         /* release mr holds */
 467         while (j) {
 468                 struct hfi1_sge *sge = &wqe->sg_list[--j];
 469
 470                 hfi1_put_mr(sge->mr);
 471         }
 472         return -EINVAL;
 473 }
 474
 475 /**
 476  * post_send - post a send on a QP
 477  * @ibqp: the QP to post the send on
 478  * @wr: the list of work requests to post
 479  * @bad_wr: the first bad WR is put here
 480  *
 481  * This may be called from interrupt context.
 482  */
 483 static int post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 484                      struct ib_send_wr **bad_wr)
 485 {
 486         struct hfi1_qp *qp = to_iqp(ibqp);
 487         int err = 0;
 488         int call_send;
 489         unsigned long flags;
 490         unsigned nreq = 0;
 491
 492         spin_lock_irqsave(&qp->s_lock, flags);
 493
 494         /* Check that state is OK to post send. */
 495         if (unlikely(!(ib_hfi1_state_ops[qp->state] & HFI1_POST_SEND_OK))) {
 496                 spin_unlock_irqrestore(&qp->s_lock, flags);
 497                 return -EINVAL;
 498         }
 499
 500         /* sq empty and not list -> call send */
 501         call_send = qp->s_head == qp->s_last && !wr->next;
 502
 503         for (; wr; wr = wr->next) {
 504                 err = post_one_send(qp, wr);
 505                 if (unlikely(err)) {
 506                         *bad_wr = wr;
 507                         goto bail;
 508                 }
 509                 nreq++;
 510         }
 511 bail:
 512         if (nreq && !call_send)
 513                 hfi1_schedule_send(qp);
 514         spin_unlock_irqrestore(&qp->s_lock, flags);
 515         if (nreq && call_send)
 516                 hfi1_do_send(&qp->s_iowait.iowork);
 517         return err;
 518 }
 519
 520 /**
 521  * post_receive - post a receive on a QP
 522  * @ibqp: the QP to post the receive on
 523  * @wr: the WR to post
 524  * @bad_wr: the first bad WR is put here
 525  *
 526  * This may be called from interrupt context.
 527  */
 528 static int post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 529                         struct ib_recv_wr **bad_wr)
 530 {
 531         struct hfi1_qp *qp = to_iqp(ibqp);
 532         struct hfi1_rwq *wq = qp->r_rq.wq;
 533         unsigned long flags;
 534         int ret;
 535
 536         /* Check that state is OK to post receive. */
 537         if (!(ib_hfi1_state_ops[qp->state] & HFI1_POST_RECV_OK) || !wq) {
 538                 *bad_wr = wr;
 539                 ret = -EINVAL;
 540                 goto bail;
 541         }
 542
 543         for (; wr; wr = wr->next) {
 544                 struct hfi1_rwqe *wqe;
 545                 u32 next;
 546                 int i;
 547
 548                 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
 549                         *bad_wr = wr;
 550                         ret = -EINVAL;
 551                         goto bail;
 552                 }
 553
 554                 spin_lock_irqsave(&qp->r_rq.lock, flags);
 555                 next = wq->head + 1;
 556                 if (next >= qp->r_rq.size)
 557                         next = 0;
 558                 if (next == wq->tail) {
 559                         spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 560                         *bad_wr = wr;
 561                         ret = -ENOMEM;
 562                         goto bail;
 563                 }
 564
 565                 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
 566                 wqe->wr_id = wr->wr_id;
 567                 wqe->num_sge = wr->num_sge;
 568                 for (i = 0; i < wr->num_sge; i++)
 569                         wqe->sg_list[i] = wr->sg_list[i];
 570                 /* Make sure queue entry is written before the head index. */
 571                 smp_wmb();
 572                 wq->head = next;
 573                 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 574         }
 575         ret = 0;
 576
 577 bail:
 578         return ret;
 579 }
 580
 581 /*
 582  * Make sure the QP is ready and able to accept the given opcode.
 583  */
 584 static inline int qp_ok(int opcode, struct hfi1_packet *packet)
 585 {
 586         struct hfi1_ibport *ibp;
 587
 588         if (!(ib_hfi1_state_ops[packet->qp->state] & HFI1_PROCESS_RECV_OK))
 589                 goto dropit;
 590         if (((opcode & OPCODE_QP_MASK) == packet->qp->allowed_ops) ||
 591             (opcode == IB_OPCODE_CNP))
 592                 return 1;
 593 dropit:
 594         ibp = &packet->rcd->ppd->ibport_data;
 595         ibp->n_pkt_drops++;
 596         return 0;
 597 }
 598
 599
 600 /**
 601  * hfi1_ib_rcv - process an incoming packet
 602  * @packet: data packet information
 603  *
 604  * This is called to process an incoming packet at interrupt level.
 605  *
 606  * Tlen is the length of the header + data + CRC in bytes.
 607  */
 608 void hfi1_ib_rcv(struct hfi1_packet *packet)
 609 {
 610         struct hfi1_ctxtdata *rcd = packet->rcd;
 611         struct hfi1_ib_header *hdr = packet->hdr;
 612         u32 tlen = packet->tlen;
 613         struct hfi1_pportdata *ppd = rcd->ppd;
 614         struct hfi1_ibport *ibp = &ppd->ibport_data;
 615         unsigned long flags;
 616         u32 qp_num;
 617         int lnh;
 618         u8 opcode;
 619         u16 lid;
 620
 621         /* Check for GRH */
 622         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
 623         if (lnh == HFI1_LRH_BTH)
 624                 packet->ohdr = &hdr->u.oth;
 625         else if (lnh == HFI1_LRH_GRH) {
 626                 u32 vtf;
 627
 628                 packet->ohdr = &hdr->u.l.oth;
 629                 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
 630                         goto drop;
 631                 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
 632                 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
 633                         goto drop;
 634                 packet->rcv_flags |= HFI1_HAS_GRH;
 635         } else
 636                 goto drop;
 637
 638         trace_input_ibhdr(rcd->dd, hdr);
 639
 640         opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
 641         inc_opstats(tlen, &rcd->opstats->stats[opcode]);
 642
 643         /* Get the destination QP number. */
 644         qp_num = be32_to_cpu(packet->ohdr->bth[1]) & HFI1_QPN_MASK;
 645         lid = be16_to_cpu(hdr->lrh[1]);
 646         if (unlikely((lid >= HFI1_MULTICAST_LID_BASE) &&
 647             (lid != HFI1_PERMISSIVE_LID))) {
 648                 struct hfi1_mcast *mcast;
 649                 struct hfi1_mcast_qp *p;
 650
 651                 if (lnh != HFI1_LRH_GRH)
 652                         goto drop;
 653                 mcast = hfi1_mcast_find(ibp, &hdr->u.l.grh.dgid);
 654                 if (mcast == NULL)
 655                         goto drop;
 656                 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 657                         packet->qp = p->qp;
 658                         spin_lock_irqsave(&packet->qp->r_lock, flags);
 659                         if (likely((qp_ok(opcode, packet))))
 660                                 opcode_handler_tbl[opcode](packet);
 661                         spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 662                 }
 663                 /*
 664                  * Notify hfi1_multicast_detach() if it is waiting for us
 665                  * to finish.
 666                  */
 667                 if (atomic_dec_return(&mcast->refcount) <= 1)
 668                         wake_up(&mcast->wait);
 669         } else {
 670                 rcu_read_lock();
 671                 packet->qp = hfi1_lookup_qpn(ibp, qp_num);
 672                 if (!packet->qp) {
 673                         rcu_read_unlock();
 674                         goto drop;
 675                 }
 676                 spin_lock_irqsave(&packet->qp->r_lock, flags);
 677                 if (likely((qp_ok(opcode, packet))))
 678                         opcode_handler_tbl[opcode](packet);
 679                 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 680                 rcu_read_unlock();
 681         }
 682         return;
 683
 684 drop:
 685         ibp->n_pkt_drops++;
 686 }
 687
 688 /*
 689  * This is called from a timer to check for QPs
 690  * which need kernel memory in order to send a packet.
 691  */
 692 static void mem_timer(unsigned long data)
 693 {
 694         struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
 695         struct list_head *list = &dev->memwait;
 696         struct hfi1_qp *qp = NULL;
 697         struct iowait *wait;
 698         unsigned long flags;
 699
 700         write_seqlock_irqsave(&dev->iowait_lock, flags);
 701         if (!list_empty(list)) {
 702                 wait = list_first_entry(list, struct iowait, list);
 703                 qp = container_of(wait, struct hfi1_qp, s_iowait);
 704                 list_del_init(&qp->s_iowait.list);
 705                 /* refcount held until actual wake up */
 706                 if (!list_empty(list))
 707                         mod_timer(&dev->mem_timer, jiffies + 1);
 708         }
 709         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 710
 711         if (qp)
 712                 hfi1_qp_wakeup(qp, HFI1_S_WAIT_KMEM);
 713 }
 714
 715 void update_sge(struct hfi1_sge_state *ss, u32 length)
 716 {
 717         struct hfi1_sge *sge = &ss->sge;
 718
 719         sge->vaddr += length;
 720         sge->length -= length;
 721         sge->sge_length -= length;
 722         if (sge->sge_length == 0) {
 723                 if (--ss->num_sge)
 724                         *sge = *ss->sg_list++;
 725         } else if (sge->length == 0 && sge->mr->lkey) {
 726                 if (++sge->n >= HFI1_SEGSZ) {
 727                         if (++sge->m >= sge->mr->mapsz)
 728                                 return;
 729                         sge->n = 0;
 730                 }
 731                 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
 732                 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
 733         }
 734 }
 735
 736 static noinline struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev,
 737                                                 struct hfi1_qp *qp)
 738 {
 739         struct verbs_txreq *tx;
 740         unsigned long flags;
 741
 742         tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
 743         if (!tx) {
 744                 spin_lock_irqsave(&qp->s_lock, flags);
 745                 write_seqlock(&dev->iowait_lock);
 746                 if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK &&
 747                     list_empty(&qp->s_iowait.list)) {
 748                         dev->n_txwait++;
 749                         qp->s_flags |= HFI1_S_WAIT_TX;
 750                         list_add_tail(&qp->s_iowait.list, &dev->txwait);
 751                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_TX);
 752                         atomic_inc(&qp->refcount);
 753                 }
 754                 qp->s_flags &= ~HFI1_S_BUSY;
 755                 write_sequnlock(&dev->iowait_lock);
 756                 spin_unlock_irqrestore(&qp->s_lock, flags);
 757                 tx = ERR_PTR(-EBUSY);
 758         }
 759         return tx;
 760 }
 761
 762 static inline struct verbs_txreq *get_txreq(struct hfi1_ibdev *dev,
 763                                             struct hfi1_qp *qp)
 764 {
 765         struct verbs_txreq *tx;
 766
 767         tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
 768         if (!tx) {
 769                 /* call slow path to get the lock */
 770                 tx =  __get_txreq(dev, qp);
 771                 if (IS_ERR(tx))
 772                         return tx;
 773         }
 774         tx->qp = qp;
 775         return tx;
 776 }
 777
 778 void hfi1_put_txreq(struct verbs_txreq *tx)
 779 {
 780         struct hfi1_ibdev *dev;
 781         struct hfi1_qp *qp;
 782         unsigned long flags;
 783         unsigned int seq;
 784
 785         qp = tx->qp;
 786         dev = to_idev(qp->ibqp.device);
 787
 788         if (tx->mr) {
 789                 hfi1_put_mr(tx->mr);
 790                 tx->mr = NULL;
 791         }
 792         sdma_txclean(dd_from_dev(dev), &tx->txreq);
 793
 794         /* Free verbs_txreq and return to slab cache */
 795         kmem_cache_free(dev->verbs_txreq_cache, tx);
 796
 797         do {
 798                 seq = read_seqbegin(&dev->iowait_lock);
 799                 if (!list_empty(&dev->txwait)) {
 800                         struct iowait *wait;
 801
 802                         write_seqlock_irqsave(&dev->iowait_lock, flags);
 803                         /* Wake up first QP wanting a free struct */
 804                         wait = list_first_entry(&dev->txwait, struct iowait,
 805                                                 list);
 806                         qp = container_of(wait, struct hfi1_qp, s_iowait);
 807                         list_del_init(&qp->s_iowait.list);
 808                         /* refcount held until actual wake up */
 809                         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 810                         hfi1_qp_wakeup(qp, HFI1_S_WAIT_TX);
 811                         break;
 812                 }
 813         } while (read_seqretry(&dev->iowait_lock, seq));
 814 }
 815
 816 /*
 817  * This is called with progress side lock held.
 818  */
 819 /* New API */
 820 static void verbs_sdma_complete(
 821         struct sdma_txreq *cookie,
 822         int status,
 823         int drained)
 824 {
 825         struct verbs_txreq *tx =
 826                 container_of(cookie, struct verbs_txreq, txreq);
 827         struct hfi1_qp *qp = tx->qp;
 828
 829         spin_lock(&qp->s_lock);
 830         if (tx->wqe)
 831                 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 832         else if (qp->ibqp.qp_type == IB_QPT_RC) {
 833                 struct hfi1_ib_header *hdr;
 834
 835                 hdr = &tx->phdr.hdr;
 836                 hfi1_rc_send_complete(qp, hdr);
 837         }
 838         if (drained) {
 839                 /*
 840                  * This happens when the send engine notes
 841                  * a QP in the error state and cannot
 842                  * do the flush work until that QP's
 843                  * sdma work has finished.
 844                  */
 845                 if (qp->s_flags & HFI1_S_WAIT_DMA) {
 846                         qp->s_flags &= ~HFI1_S_WAIT_DMA;
 847                         hfi1_schedule_send(qp);
 848                 }
 849         }
 850         spin_unlock(&qp->s_lock);
 851
 852         hfi1_put_txreq(tx);
 853 }
 854
 855 static int wait_kmem(struct hfi1_ibdev *dev, struct hfi1_qp *qp)
 856 {
 857         unsigned long flags;
 858         int ret = 0;
 859
 860         spin_lock_irqsave(&qp->s_lock, flags);
 861         if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
 862                 write_seqlock(&dev->iowait_lock);
 863                 if (list_empty(&qp->s_iowait.list)) {
 864                         if (list_empty(&dev->memwait))
 865                                 mod_timer(&dev->mem_timer, jiffies + 1);
 866                         qp->s_flags |= HFI1_S_WAIT_KMEM;
 867                         list_add_tail(&qp->s_iowait.list, &dev->memwait);
 868                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_KMEM);
 869                         atomic_inc(&qp->refcount);
 870                 }
 871                 write_sequnlock(&dev->iowait_lock);
 872                 qp->s_flags &= ~HFI1_S_BUSY;
 873                 ret = -EBUSY;
 874         }
 875         spin_unlock_irqrestore(&qp->s_lock, flags);
 876
 877         return ret;
 878 }
 879
 880 /*
 881  * This routine calls txadds for each sg entry.
 882  *
 883  * Add failures will revert the sge cursor
 884  */
 885 static int build_verbs_ulp_payload(
 886         struct sdma_engine *sde,
 887         struct hfi1_sge_state *ss,
 888         u32 length,
 889         struct verbs_txreq *tx)
 890 {
 891         struct hfi1_sge *sg_list = ss->sg_list;
 892         struct hfi1_sge sge = ss->sge;
 893         u8 num_sge = ss->num_sge;
 894         u32 len;
 895         int ret = 0;
 896
 897         while (length) {
 898                 len = ss->sge.length;
 899                 if (len > length)
 900                         len = length;
 901                 if (len > ss->sge.sge_length)
 902                         len = ss->sge.sge_length;
 903                 WARN_ON_ONCE(len == 0);
 904                 ret = sdma_txadd_kvaddr(
 905                         sde->dd,
 906                         &tx->txreq,
 907                         ss->sge.vaddr,
 908                         len);
 909                 if (ret)
 910                         goto bail_txadd;
 911                 update_sge(ss, len);
 912                 length -= len;
 913         }
 914         return ret;
 915 bail_txadd:
 916         /* unwind cursor */
 917         ss->sge = sge;
 918         ss->num_sge = num_sge;
 919         ss->sg_list = sg_list;
 920         return ret;
 921 }
 922
 923 /*
 924  * Build the number of DMA descriptors needed to send length bytes of data.
 925  *
 926  * NOTE: DMA mapping is held in the tx until completed in the ring or
 927  *       the tx desc is freed without having been submitted to the ring
 928  *
 929  * This routine insures the following all the helper routine
 930  * calls succeed.
 931  */
 932 /* New API */
 933 static int build_verbs_tx_desc(
 934         struct sdma_engine *sde,
 935         struct hfi1_sge_state *ss,
 936         u32 length,
 937         struct verbs_txreq *tx,
 938         struct ahg_ib_header *ahdr,
 939         u64 pbc)
 940 {
 941         int ret = 0;
 942         struct hfi1_pio_header *phdr;
 943         u16 hdrbytes = tx->hdr_dwords << 2;
 944
 945         phdr = &tx->phdr;
 946         if (!ahdr->ahgcount) {
 947                 ret = sdma_txinit_ahg(
 948                         &tx->txreq,
 949                         ahdr->tx_flags,
 950                         hdrbytes + length,
 951                         ahdr->ahgidx,
 952                         0,
 953                         NULL,
 954                         0,
 955                         verbs_sdma_complete);
 956                 if (ret)
 957                         goto bail_txadd;
 958                 phdr->pbc = cpu_to_le64(pbc);
 959                 memcpy(&phdr->hdr, &ahdr->ibh, hdrbytes - sizeof(phdr->pbc));
 960                 /* add the header */
 961                 ret = sdma_txadd_kvaddr(
 962                         sde->dd,
 963                         &tx->txreq,
 964                         &tx->phdr,
 965                         tx->hdr_dwords << 2);
 966                 if (ret)
 967                         goto bail_txadd;
 968         } else {
 969                 struct hfi1_other_headers *sohdr = &ahdr->ibh.u.oth;
 970                 struct hfi1_other_headers *dohdr = &phdr->hdr.u.oth;
 971
 972                 /* needed in rc_send_complete() */
 973                 phdr->hdr.lrh[0] = ahdr->ibh.lrh[0];
 974                 if ((be16_to_cpu(phdr->hdr.lrh[0]) & 3) == HFI1_LRH_GRH) {
 975                         sohdr = &ahdr->ibh.u.l.oth;
 976                         dohdr = &phdr->hdr.u.l.oth;
 977                 }
 978                 /* opcode */
 979                 dohdr->bth[0] = sohdr->bth[0];
 980                 /* PSN/ACK  */
 981                 dohdr->bth[2] = sohdr->bth[2];
 982                 ret = sdma_txinit_ahg(
 983                         &tx->txreq,
 984                         ahdr->tx_flags,
 985                         length,
 986                         ahdr->ahgidx,
 987                         ahdr->ahgcount,
 988                         ahdr->ahgdesc,
 989                         hdrbytes,
 990                         verbs_sdma_complete);
 991                 if (ret)
 992                         goto bail_txadd;
 993         }
 994
 995         /* add the ulp payload - if any.  ss can be NULL for acks */
 996         if (ss)
 997                 ret = build_verbs_ulp_payload(sde, ss, length, tx);
 998 bail_txadd:
 999         return ret;
1000 }
1001
1002 int hfi1_verbs_send_dma(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
1003                         u32 hdrwords, struct hfi1_sge_state *ss, u32 len,
1004                         u32 plen, u32 dwords, u64 pbc)
1005 {
1006         struct hfi1_ibdev *dev = to_idev(qp->ibqp.device);
1007         struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1008         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1009         struct verbs_txreq *tx;
1010         struct sdma_txreq *stx;
1011         u64 pbc_flags = 0;
1012         struct sdma_engine *sde;
1013         u8 sc5 = qp->s_sc;
1014         int ret;
1015
1016         if (!list_empty(&qp->s_iowait.tx_head)) {
1017                 stx = list_first_entry(
1018                         &qp->s_iowait.tx_head,
1019                         struct sdma_txreq,
1020                         list);
1021                 list_del_init(&stx->list);
1022                 tx = container_of(stx, struct verbs_txreq, txreq);
1023                 ret = sdma_send_txreq(tx->sde, &qp->s_iowait, stx);
1024                 if (unlikely(ret == -ECOMM))
1025                         goto bail_ecomm;
1026                 return ret;
1027         }
1028
1029         tx = get_txreq(dev, qp);
1030         if (IS_ERR(tx))
1031                 goto bail_tx;
1032
1033         if (!qp->s_hdr->sde) {
1034                 tx->sde = sde = qp_to_sdma_engine(qp, sc5);
1035                 if (!sde)
1036                         goto bail_no_sde;
1037         } else
1038                 tx->sde = sde = qp->s_hdr->sde;
1039
1040         if (likely(pbc == 0)) {
1041                 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1042                 /* No vl15 here */
1043                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1044                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1045
1046                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1047         }
1048         tx->wqe = qp->s_wqe;
1049         tx->mr = qp->s_rdma_mr;
1050         if (qp->s_rdma_mr)
1051                 qp->s_rdma_mr = NULL;
1052         tx->hdr_dwords = hdrwords + 2;
1053         ret = build_verbs_tx_desc(sde, ss, len, tx, ahdr, pbc);
1054         if (unlikely(ret))
1055                 goto bail_build;
1056         trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1057         ret =  sdma_send_txreq(sde, &qp->s_iowait, &tx->txreq);
1058         if (unlikely(ret == -ECOMM))
1059                 goto bail_ecomm;
1060         return ret;
1061
1062 bail_no_sde:
1063         hfi1_put_txreq(tx);
1064 bail_ecomm:
1065         /* The current one got "sent" */
1066         return 0;
1067 bail_build:
1068         /* kmalloc or mapping fail */
1069         hfi1_put_txreq(tx);
1070         return wait_kmem(dev, qp);
1071 bail_tx:
1072         return PTR_ERR(tx);
1073 }
1074
1075 /*
1076  * If we are now in the error state, return zero to flush the
1077  * send work request.
1078  */
1079 static int no_bufs_available(struct hfi1_qp *qp, struct send_context *sc)
1080 {
1081         struct hfi1_devdata *dd = sc->dd;
1082         struct hfi1_ibdev *dev = &dd->verbs_dev;
1083         unsigned long flags;
1084         int ret = 0;
1085
1086         /*
1087          * Note that as soon as want_buffer() is called and
1088          * possibly before it returns, sc_piobufavail()
1089          * could be called. Therefore, put QP on the I/O wait list before
1090          * enabling the PIO avail interrupt.
1091          */
1092         spin_lock_irqsave(&qp->s_lock, flags);
1093         if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
1094                 write_seqlock(&dev->iowait_lock);
1095                 if (list_empty(&qp->s_iowait.list)) {
1096                         struct hfi1_ibdev *dev = &dd->verbs_dev;
1097                         int was_empty;
1098
1099                         dev->n_piowait++;
1100                         qp->s_flags |= HFI1_S_WAIT_PIO;
1101                         was_empty = list_empty(&sc->piowait);
1102                         list_add_tail(&qp->s_iowait.list, &sc->piowait);
1103                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_PIO);
1104                         atomic_inc(&qp->refcount);
1105                         /* counting: only call wantpiobuf_intr if first user */
1106                         if (was_empty)
1107                                 hfi1_sc_wantpiobuf_intr(sc, 1);
1108                 }
1109                 write_sequnlock(&dev->iowait_lock);
1110                 qp->s_flags &= ~HFI1_S_BUSY;
1111                 ret = -EBUSY;
1112         }
1113         spin_unlock_irqrestore(&qp->s_lock, flags);
1114         return ret;
1115 }
1116
1117 struct send_context *qp_to_send_context(struct hfi1_qp *qp, u8 sc5)
1118 {
1119         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1120         struct hfi1_pportdata *ppd = dd->pport + (qp->port_num - 1);
1121         u8 vl;
1122
1123         vl = sc_to_vlt(dd, sc5);
1124         if (vl >= ppd->vls_supported && vl != 15)
1125                 return NULL;
1126         return dd->vld[vl].sc;
1127 }
1128
1129 int hfi1_verbs_send_pio(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
1130                         u32 hdrwords, struct hfi1_sge_state *ss, u32 len,
1131                         u32 plen, u32 dwords, u64 pbc)
1132 {
1133         struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1134         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1135         u32 *hdr = (u32 *)&ahdr->ibh;
1136         u64 pbc_flags = 0;
1137         u32 sc5;
1138         unsigned long flags = 0;
1139         struct send_context *sc;
1140         struct pio_buf *pbuf;
1141         int wc_status = IB_WC_SUCCESS;
1142
1143         /* vl15 special case taken care of in ud.c */
1144         sc5 = qp->s_sc;
1145         sc = qp_to_send_context(qp, sc5);
1146
1147         if (!sc)
1148                 return -EINVAL;
1149         if (likely(pbc == 0)) {
1150                 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1151                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1152                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1153                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1154         }
1155         pbuf = sc_buffer_alloc(sc, plen, NULL, NULL);
1156         if (unlikely(pbuf == NULL)) {
1157                 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1158                         /*
1159                          * If we have filled the PIO buffers to capacity and are
1160                          * not in an active state this request is not going to
1161                          * go out to so just complete it with an error or else a
1162                          * ULP or the core may be stuck waiting.
1163                          */
1164                         hfi1_cdbg(
1165                                 PIO,
1166                                 "alloc failed. state not active, completing");
1167                         wc_status = IB_WC_GENERAL_ERR;
1168                         goto pio_bail;
1169                 } else {
1170                         /*
1171                          * This is a normal occurrence. The PIO buffs are full
1172                          * up but we are still happily sending, well we could be
1173                          * so lets continue to queue the request.
1174                          */
1175                         hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1176                         return no_bufs_available(qp, sc);
1177                 }
1178         }
1179
1180         if (len == 0) {
1181                 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1182         } else {
1183                 if (ss) {
1184                         seg_pio_copy_start(pbuf, pbc, hdr, hdrwords*4);
1185                         while (len) {
1186                                 void *addr = ss->sge.vaddr;
1187                                 u32 slen = ss->sge.length;
1188
1189                                 if (slen > len)
1190                                         slen = len;
1191                                 update_sge(ss, slen);
1192                                 seg_pio_copy_mid(pbuf, addr, slen);
1193                                 len -= slen;
1194                         }
1195                         seg_pio_copy_end(pbuf);
1196                 }
1197         }
1198
1199         trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1200
1201         if (qp->s_rdma_mr) {
1202                 hfi1_put_mr(qp->s_rdma_mr);
1203                 qp->s_rdma_mr = NULL;
1204         }
1205
1206 pio_bail:
1207         if (qp->s_wqe) {
1208                 spin_lock_irqsave(&qp->s_lock, flags);
1209                 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1210                 spin_unlock_irqrestore(&qp->s_lock, flags);
1211         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1212                 spin_lock_irqsave(&qp->s_lock, flags);
1213                 hfi1_rc_send_complete(qp, &ahdr->ibh);
1214                 spin_unlock_irqrestore(&qp->s_lock, flags);
1215         }
1216         return 0;
1217 }
1218
1219 /*
1220  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1221  * being an entry from the ingress partition key table), return 0
1222  * otherwise. Use the matching criteria for egress partition keys
1223  * specified in the OPAv1 spec., section 9.1l.7.
1224  */
1225 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1226 {
1227         u16 mkey = pkey & PKEY_LOW_15_MASK;
1228         u16 ment = ent & PKEY_LOW_15_MASK;
1229
1230         if (mkey == ment) {
1231                 /*
1232                  * If pkey[15] is set (full partition member),
1233                  * is bit 15 in the corresponding table element
1234                  * clear (limited member)?
1235                  */
1236                 if (pkey & PKEY_MEMBER_MASK)
1237                         return !!(ent & PKEY_MEMBER_MASK);
1238                 return 1;
1239         }
1240         return 0;
1241 }
1242
1243 /*
1244  * egress_pkey_check - return 0 if hdr's pkey matches according to the
1245  * criteria in the OPAv1 spec., section 9.11.7.
1246  */
1247 static inline int egress_pkey_check(struct hfi1_pportdata *ppd,
1248                                     struct hfi1_ib_header *hdr,
1249                                     struct hfi1_qp *qp)
1250 {
1251         struct hfi1_other_headers *ohdr;
1252         struct hfi1_devdata *dd;
1253         int i = 0;
1254         u16 pkey;
1255         u8 lnh, sc5 = qp->s_sc;
1256
1257         if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1258                 return 0;
1259
1260         /* locate the pkey within the headers */
1261         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
1262         if (lnh == HFI1_LRH_GRH)
1263                 ohdr = &hdr->u.l.oth;
1264         else
1265                 ohdr = &hdr->u.oth;
1266
1267         pkey = (u16)be32_to_cpu(ohdr->bth[0]);
1268
1269         /* If SC15, pkey[0:14] must be 0x7fff */
1270         if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1271                 goto bad;
1272
1273
1274         /* Is the pkey = 0x0, or 0x8000? */
1275         if ((pkey & PKEY_LOW_15_MASK) == 0)
1276                 goto bad;
1277
1278         /* The most likely matching pkey has index qp->s_pkey_index */
1279         if (unlikely(!egress_pkey_matches_entry(pkey,
1280                                         ppd->pkeys[qp->s_pkey_index]))) {
1281                 /* no match - try the entire table */
1282                 for (; i < MAX_PKEY_VALUES; i++) {
1283                         if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1284                                 break;
1285                 }
1286         }
1287
1288         if (i < MAX_PKEY_VALUES)
1289                 return 0;
1290 bad:
1291         incr_cntr64(&ppd->port_xmit_constraint_errors);
1292         dd = ppd->dd;
1293         if (!(dd->err_info_xmit_constraint.status & OPA_EI_STATUS_SMASK)) {
1294                 u16 slid = be16_to_cpu(hdr->lrh[3]);
1295
1296                 dd->err_info_xmit_constraint.status |= OPA_EI_STATUS_SMASK;
1297                 dd->err_info_xmit_constraint.slid = slid;
1298                 dd->err_info_xmit_constraint.pkey = pkey;
1299         }
1300         return 1;
1301 }
1302
1303 /**
1304  * hfi1_verbs_send - send a packet
1305  * @qp: the QP to send on
1306  * @ahdr: the packet header
1307  * @hdrwords: the number of 32-bit words in the header
1308  * @ss: the SGE to send
1309  * @len: the length of the packet in bytes
1310  *
1311  * Return zero if packet is sent or queued OK.
1312  * Return non-zero and clear qp->s_flags HFI1_S_BUSY otherwise.
1313  */
1314 int hfi1_verbs_send(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
1315                     u32 hdrwords, struct hfi1_sge_state *ss, u32 len)
1316 {
1317         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1318         u32 plen;
1319         int ret;
1320         int pio = 0;
1321         unsigned long flags = 0;
1322         u32 dwords = (len + 3) >> 2;
1323
1324         /*
1325          * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1326          * can defer SDMA restart until link goes ACTIVE without
1327          * worrying about just how we got there.
1328          */
1329         if ((qp->ibqp.qp_type == IB_QPT_SMI) ||
1330             !(dd->flags & HFI1_HAS_SEND_DMA))
1331                 pio = 1;
1332
1333         ret = egress_pkey_check(dd->pport, &ahdr->ibh, qp);
1334         if (unlikely(ret)) {
1335                 /*
1336                  * The value we are returning here does not get propagated to
1337                  * the verbs caller. Thus we need to complete the request with
1338                  * error otherwise the caller could be sitting waiting on the
1339                  * completion event. Only do this for PIO. SDMA has its own
1340                  * mechanism for handling the errors. So for SDMA we can just
1341                  * return.
1342                  */
1343                 if (pio) {
1344                         hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1345                                   __func__);
1346                         spin_lock_irqsave(&qp->s_lock, flags);
1347                         hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1348                         spin_unlock_irqrestore(&qp->s_lock, flags);
1349                 }
1350                 return -EINVAL;
1351         }
1352
1353         /*
1354          * Calculate the send buffer trigger address.
1355          * The +2 counts for the pbc control qword
1356          */
1357         plen = hdrwords + dwords + 2;
1358
1359         if (pio) {
1360                 ret = dd->process_pio_send(
1361                         qp, ahdr, hdrwords, ss, len, plen, dwords, 0);
1362         } else {
1363 #ifdef CONFIG_SDMA_VERBOSITY
1364                 dd_dev_err(dd, "CONFIG SDMA %s:%d %s()\n",
1365                            slashstrip(__FILE__), __LINE__, __func__);
1366                 dd_dev_err(dd, "SDMA hdrwords = %u, len = %u\n", hdrwords, len);
1367 #endif
1368                 ret = dd->process_dma_send(
1369                         qp, ahdr, hdrwords, ss, len, plen, dwords, 0);
1370         }
1371
1372         return ret;
1373 }
1374
1375 static int query_device(struct ib_device *ibdev,
1376                         struct ib_device_attr *props,
1377                         struct ib_udata *uhw)
1378 {
1379         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1380         struct hfi1_ibdev *dev = to_idev(ibdev);
1381
1382         if (uhw->inlen || uhw->outlen)
1383                 return -EINVAL;
1384         memset(props, 0, sizeof(*props));
1385
1386         props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1387                 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1388                 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1389                 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1390
1391         props->page_size_cap = PAGE_SIZE;
1392         props->vendor_id =
1393                 dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1394         props->vendor_part_id = dd->pcidev->device;
1395         props->hw_ver = dd->minrev;
1396         props->sys_image_guid = ib_hfi1_sys_image_guid;
1397         props->max_mr_size = ~0ULL;
1398         props->max_qp = hfi1_max_qps;
1399         props->max_qp_wr = hfi1_max_qp_wrs;
1400         props->max_sge = hfi1_max_sges;
1401         props->max_sge_rd = hfi1_max_sges;
1402         props->max_cq = hfi1_max_cqs;
1403         props->max_ah = hfi1_max_ahs;
1404         props->max_cqe = hfi1_max_cqes;
1405         props->max_mr = dev->lk_table.max;
1406         props->max_fmr = dev->lk_table.max;
1407         props->max_map_per_fmr = 32767;
1408         props->max_pd = hfi1_max_pds;
1409         props->max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1410         props->max_qp_init_rd_atom = 255;
1411         /* props->max_res_rd_atom */
1412         props->max_srq = hfi1_max_srqs;
1413         props->max_srq_wr = hfi1_max_srq_wrs;
1414         props->max_srq_sge = hfi1_max_srq_sges;
1415         /* props->local_ca_ack_delay */
1416         props->atomic_cap = IB_ATOMIC_GLOB;
1417         props->max_pkeys = hfi1_get_npkeys(dd);
1418         props->max_mcast_grp = hfi1_max_mcast_grps;
1419         props->max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1420         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1421                 props->max_mcast_grp;
1422
1423         return 0;
1424 }
1425
1426 static inline u16 opa_speed_to_ib(u16 in)
1427 {
1428         u16 out = 0;
1429
1430         if (in & OPA_LINK_SPEED_25G)
1431                 out |= IB_SPEED_EDR;
1432         if (in & OPA_LINK_SPEED_12_5G)
1433                 out |= IB_SPEED_FDR;
1434
1435         return out;
1436 }
1437
1438 /*
1439  * Convert a single OPA link width (no multiple flags) to an IB value.
1440  * A zero OPA link width means link down, which means the IB width value
1441  * is a don't care.
1442  */
1443 static inline u16 opa_width_to_ib(u16 in)
1444 {
1445         switch (in) {
1446         case OPA_LINK_WIDTH_1X:
1447         /* map 2x and 3x to 1x as they don't exist in IB */
1448         case OPA_LINK_WIDTH_2X:
1449         case OPA_LINK_WIDTH_3X:
1450                 return IB_WIDTH_1X;
1451         default: /* link down or unknown, return our largest width */
1452         case OPA_LINK_WIDTH_4X:
1453                 return IB_WIDTH_4X;
1454         }
1455 }
1456
1457 static int query_port(struct ib_device *ibdev, u8 port,
1458                       struct ib_port_attr *props)
1459 {
1460         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1461         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1462         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1463         u16 lid = ppd->lid;
1464
1465         memset(props, 0, sizeof(*props));
1466         props->lid = lid ? lid : 0;
1467         props->lmc = ppd->lmc;
1468         props->sm_lid = ibp->sm_lid;
1469         props->sm_sl = ibp->sm_sl;
1470         /* OPA logical states match IB logical states */
1471         props->state = driver_lstate(ppd);
1472         props->phys_state = hfi1_ibphys_portstate(ppd);
1473         props->port_cap_flags = ibp->port_cap_flags;
1474         props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1475         props->max_msg_sz = 0x80000000;
1476         props->pkey_tbl_len = hfi1_get_npkeys(dd);
1477         props->bad_pkey_cntr = ibp->pkey_violations;
1478         props->qkey_viol_cntr = ibp->qkey_violations;
1479         props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1480         /* see rate_show() in ib core/sysfs.c */
1481         props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1482         props->max_vl_num = ppd->vls_supported;
1483         props->init_type_reply = 0;
1484
1485         /* Once we are a "first class" citizen and have added the OPA MTUs to
1486          * the core we can advertise the larger MTU enum to the ULPs, for now
1487          * advertise only 4K.
1488          *
1489          * Those applications which are either OPA aware or pass the MTU enum
1490          * from the Path Records to us will get the new 8k MTU.  Those that
1491          * attempt to process the MTU enum may fail in various ways.
1492          */
1493         props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1494                                       4096 : hfi1_max_mtu), IB_MTU_4096);
1495         props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1496                 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1497         props->subnet_timeout = ibp->subnet_timeout;
1498
1499         return 0;
1500 }
1501
1502 static int port_immutable(struct ib_device *ibdev, u8 port_num,
1503                           struct ib_port_immutable *immutable)
1504 {
1505         struct ib_port_attr attr;
1506         int err;
1507
1508         err = query_port(ibdev, port_num, &attr);
1509         if (err)
1510                 return err;
1511
1512         memset(immutable, 0, sizeof(*immutable));
1513
1514         immutable->pkey_tbl_len = attr.pkey_tbl_len;
1515         immutable->gid_tbl_len = attr.gid_tbl_len;
1516         immutable->core_cap_flags = RDMA_CORE_PORT_INTEL_OPA;
1517         immutable->max_mad_size = OPA_MGMT_MAD_SIZE;
1518
1519         return 0;
1520 }
1521
1522 static int modify_device(struct ib_device *device,
1523                          int device_modify_mask,
1524                          struct ib_device_modify *device_modify)
1525 {
1526         struct hfi1_devdata *dd = dd_from_ibdev(device);
1527         unsigned i;
1528         int ret;
1529
1530         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1531                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1532                 ret = -EOPNOTSUPP;
1533                 goto bail;
1534         }
1535
1536         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1537                 memcpy(device->node_desc, device_modify->node_desc, 64);
1538                 for (i = 0; i < dd->num_pports; i++) {
1539                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1540
1541                         hfi1_node_desc_chg(ibp);
1542                 }
1543         }
1544
1545         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1546                 ib_hfi1_sys_image_guid =
1547                         cpu_to_be64(device_modify->sys_image_guid);
1548                 for (i = 0; i < dd->num_pports; i++) {
1549                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1550
1551                         hfi1_sys_guid_chg(ibp);
1552                 }
1553         }
1554
1555         ret = 0;
1556
1557 bail:
1558         return ret;
1559 }
1560
1561 static int modify_port(struct ib_device *ibdev, u8 port,
1562                        int port_modify_mask, struct ib_port_modify *props)
1563 {
1564         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1565         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1566         int ret = 0;
1567
1568         ibp->port_cap_flags |= props->set_port_cap_mask;
1569         ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1570         if (props->set_port_cap_mask || props->clr_port_cap_mask)
1571                 hfi1_cap_mask_chg(ibp);
1572         if (port_modify_mask & IB_PORT_SHUTDOWN) {
1573                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1574                   OPA_LINKDOWN_REASON_UNKNOWN);
1575                 ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1576         }
1577         if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1578                 ibp->qkey_violations = 0;
1579         return ret;
1580 }
1581
1582 static int query_gid(struct ib_device *ibdev, u8 port,
1583                      int index, union ib_gid *gid)
1584 {
1585         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1586         int ret = 0;
1587
1588         if (!port || port > dd->num_pports)
1589                 ret = -EINVAL;
1590         else {
1591                 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1592                 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1593
1594                 gid->global.subnet_prefix = ibp->gid_prefix;
1595                 if (index == 0)
1596                         gid->global.interface_id = cpu_to_be64(ppd->guid);
1597                 else if (index < HFI1_GUIDS_PER_PORT)
1598                         gid->global.interface_id = ibp->guids[index - 1];
1599                 else
1600                         ret = -EINVAL;
1601         }
1602
1603         return ret;
1604 }
1605
1606 static struct ib_pd *alloc_pd(struct ib_device *ibdev,
1607                               struct ib_ucontext *context,
1608                               struct ib_udata *udata)
1609 {
1610         struct hfi1_ibdev *dev = to_idev(ibdev);
1611         struct hfi1_pd *pd;
1612         struct ib_pd *ret;
1613
1614         /*
1615          * This is actually totally arbitrary.  Some correctness tests
1616          * assume there's a maximum number of PDs that can be allocated.
1617          * We don't actually have this limit, but we fail the test if
1618          * we allow allocations of more than we report for this value.
1619          */
1620
1621         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1622         if (!pd) {
1623                 ret = ERR_PTR(-ENOMEM);
1624                 goto bail;
1625         }
1626
1627         spin_lock(&dev->n_pds_lock);
1628         if (dev->n_pds_allocated == hfi1_max_pds) {
1629                 spin_unlock(&dev->n_pds_lock);
1630                 kfree(pd);
1631                 ret = ERR_PTR(-ENOMEM);
1632                 goto bail;
1633         }
1634
1635         dev->n_pds_allocated++;
1636         spin_unlock(&dev->n_pds_lock);
1637
1638         /* ib_alloc_pd() will initialize pd->ibpd. */
1639         pd->user = udata != NULL;
1640
1641         ret = &pd->ibpd;
1642
1643 bail:
1644         return ret;
1645 }
1646
1647 static int dealloc_pd(struct ib_pd *ibpd)
1648 {
1649         struct hfi1_pd *pd = to_ipd(ibpd);
1650         struct hfi1_ibdev *dev = to_idev(ibpd->device);
1651
1652         spin_lock(&dev->n_pds_lock);
1653         dev->n_pds_allocated--;
1654         spin_unlock(&dev->n_pds_lock);
1655
1656         kfree(pd);
1657
1658         return 0;
1659 }
1660
1661 /*
1662  * convert ah port,sl to sc
1663  */
1664 u8 ah_to_sc(struct ib_device *ibdev, struct ib_ah_attr *ah)
1665 {
1666         struct hfi1_ibport *ibp = to_iport(ibdev, ah->port_num);
1667
1668         return ibp->sl_to_sc[ah->sl];
1669 }
1670
1671 int hfi1_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1672 {
1673         struct hfi1_ibport *ibp;
1674         struct hfi1_pportdata *ppd;
1675         struct hfi1_devdata *dd;
1676         u8 sc5;
1677
1678         /* A multicast address requires a GRH (see ch. 8.4.1). */
1679         if (ah_attr->dlid >= HFI1_MULTICAST_LID_BASE &&
1680             ah_attr->dlid != HFI1_PERMISSIVE_LID &&
1681             !(ah_attr->ah_flags & IB_AH_GRH))
1682                 goto bail;
1683         if ((ah_attr->ah_flags & IB_AH_GRH) &&
1684             ah_attr->grh.sgid_index >= HFI1_GUIDS_PER_PORT)
1685                 goto bail;
1686         if (ah_attr->dlid == 0)
1687                 goto bail;
1688         if (ah_attr->port_num < 1 ||
1689             ah_attr->port_num > ibdev->phys_port_cnt)
1690                 goto bail;
1691         if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1692             ib_rate_to_mbps(ah_attr->static_rate) < 0)
1693                 goto bail;
1694         if (ah_attr->sl >= OPA_MAX_SLS)
1695                 goto bail;
1696         /* test the mapping for validity */
1697         ibp = to_iport(ibdev, ah_attr->port_num);
1698         ppd = ppd_from_ibp(ibp);
1699         sc5 = ibp->sl_to_sc[ah_attr->sl];
1700         dd = dd_from_ppd(ppd);
1701         if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1702                 goto bail;
1703         return 0;
1704 bail:
1705         return -EINVAL;
1706 }
1707
1708 /**
1709  * create_ah - create an address handle
1710  * @pd: the protection domain
1711  * @ah_attr: the attributes of the AH
1712  *
1713  * This may be called from interrupt context.
1714  */
1715 static struct ib_ah *create_ah(struct ib_pd *pd,
1716                                struct ib_ah_attr *ah_attr)
1717 {
1718         struct hfi1_ah *ah;
1719         struct ib_ah *ret;
1720         struct hfi1_ibdev *dev = to_idev(pd->device);
1721         unsigned long flags;
1722
1723         if (hfi1_check_ah(pd->device, ah_attr)) {
1724                 ret = ERR_PTR(-EINVAL);
1725                 goto bail;
1726         }
1727
1728         ah = kmalloc(sizeof(*ah), GFP_ATOMIC);
1729         if (!ah) {
1730                 ret = ERR_PTR(-ENOMEM);
1731                 goto bail;
1732         }
1733
1734         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1735         if (dev->n_ahs_allocated == hfi1_max_ahs) {
1736                 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1737                 kfree(ah);
1738                 ret = ERR_PTR(-ENOMEM);
1739                 goto bail;
1740         }
1741
1742         dev->n_ahs_allocated++;
1743         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1744
1745         /* ib_create_ah() will initialize ah->ibah. */
1746         ah->attr = *ah_attr;
1747         atomic_set(&ah->refcount, 0);
1748
1749         ret = &ah->ibah;
1750
1751 bail:
1752         return ret;
1753 }
1754
1755 struct ib_ah *hfi1_create_qp0_ah(struct hfi1_ibport *ibp, u16 dlid)
1756 {
1757         struct ib_ah_attr attr;
1758         struct ib_ah *ah = ERR_PTR(-EINVAL);
1759         struct hfi1_qp *qp0;
1760
1761         memset(&attr, 0, sizeof(attr));
1762         attr.dlid = dlid;
1763         attr.port_num = ppd_from_ibp(ibp)->port;
1764         rcu_read_lock();
1765         qp0 = rcu_dereference(ibp->qp[0]);
1766         if (qp0)
1767                 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1768         rcu_read_unlock();
1769         return ah;
1770 }
1771
1772 /**
1773  * destroy_ah - destroy an address handle
1774  * @ibah: the AH to destroy
1775  *
1776  * This may be called from interrupt context.
1777  */
1778 static int destroy_ah(struct ib_ah *ibah)
1779 {
1780         struct hfi1_ibdev *dev = to_idev(ibah->device);
1781         struct hfi1_ah *ah = to_iah(ibah);
1782         unsigned long flags;
1783
1784         if (atomic_read(&ah->refcount) != 0)
1785                 return -EBUSY;
1786
1787         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1788         dev->n_ahs_allocated--;
1789         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1790
1791         kfree(ah);
1792
1793         return 0;
1794 }
1795
1796 static int modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1797 {
1798         struct hfi1_ah *ah = to_iah(ibah);
1799
1800         if (hfi1_check_ah(ibah->device, ah_attr))
1801                 return -EINVAL;
1802
1803         ah->attr = *ah_attr;
1804
1805         return 0;
1806 }
1807
1808 static int query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1809 {
1810         struct hfi1_ah *ah = to_iah(ibah);
1811
1812         *ah_attr = ah->attr;
1813
1814         return 0;
1815 }
1816
1817 /**
1818  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1819  * @dd: the hfi1_ib device
1820  */
1821 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1822 {
1823         return ARRAY_SIZE(dd->pport[0].pkeys);
1824 }
1825
1826 static int query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1827                       u16 *pkey)
1828 {
1829         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1830         int ret;
1831
1832         if (index >= hfi1_get_npkeys(dd)) {
1833                 ret = -EINVAL;
1834                 goto bail;
1835         }
1836
1837         *pkey = hfi1_get_pkey(to_iport(ibdev, port), index);
1838         ret = 0;
1839
1840 bail:
1841         return ret;
1842 }
1843
1844 /**
1845  * alloc_ucontext - allocate a ucontest
1846  * @ibdev: the infiniband device
1847  * @udata: not used by the driver
1848  */
1849
1850 static struct ib_ucontext *alloc_ucontext(struct ib_device *ibdev,
1851                                           struct ib_udata *udata)
1852 {
1853         struct hfi1_ucontext *context;
1854         struct ib_ucontext *ret;
1855
1856         context = kmalloc(sizeof(*context), GFP_KERNEL);
1857         if (!context) {
1858                 ret = ERR_PTR(-ENOMEM);
1859                 goto bail;
1860         }
1861
1862         ret = &context->ibucontext;
1863
1864 bail:
1865         return ret;
1866 }
1867
1868 static int dealloc_ucontext(struct ib_ucontext *context)
1869 {
1870         kfree(to_iucontext(context));
1871         return 0;
1872 }
1873
1874 static void init_ibport(struct hfi1_pportdata *ppd)
1875 {
1876         struct hfi1_ibport *ibp = &ppd->ibport_data;
1877         size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1878         int i;
1879
1880         for (i = 0; i < sz; i++) {
1881                 ibp->sl_to_sc[i] = i;
1882                 ibp->sc_to_sl[i] = i;
1883         }
1884
1885         spin_lock_init(&ibp->lock);
1886         /* Set the prefix to the default value (see ch. 4.1.1) */
1887         ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
1888         ibp->sm_lid = 0;
1889         /* Below should only set bits defined in OPA PortInfo.CapabilityMask */
1890         ibp->port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1891                 IB_PORT_CAP_MASK_NOTICE_SUP;
1892         ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1893         ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1894         ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1895         ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1896         ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1897
1898         RCU_INIT_POINTER(ibp->qp[0], NULL);
1899         RCU_INIT_POINTER(ibp->qp[1], NULL);
1900 }
1901
1902 static void verbs_txreq_kmem_cache_ctor(void *obj)
1903 {
1904         struct verbs_txreq *tx = obj;
1905
1906         memset(tx, 0, sizeof(*tx));
1907 }
1908
1909 /**
1910  * hfi1_register_ib_device - register our device with the infiniband core
1911  * @dd: the device data structure
1912  * Return 0 if successful, errno if unsuccessful.
1913  */
1914 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1915 {
1916         struct hfi1_ibdev *dev = &dd->verbs_dev;
1917         struct ib_device *ibdev = &dev->ibdev;
1918         struct hfi1_pportdata *ppd = dd->pport;
1919         unsigned i, lk_tab_size;
1920         int ret;
1921         size_t lcpysz = IB_DEVICE_NAME_MAX;
1922         u16 descq_cnt;
1923         char buf[TXREQ_NAME_LEN];
1924
1925         ret = hfi1_qp_init(dev);
1926         if (ret)
1927                 goto err_qp_init;
1928
1929
1930         for (i = 0; i < dd->num_pports; i++)
1931                 init_ibport(ppd + i);
1932
1933         /* Only need to initialize non-zero fields. */
1934         spin_lock_init(&dev->n_pds_lock);
1935         spin_lock_init(&dev->n_ahs_lock);
1936         spin_lock_init(&dev->n_cqs_lock);
1937         spin_lock_init(&dev->n_qps_lock);
1938         spin_lock_init(&dev->n_srqs_lock);
1939         spin_lock_init(&dev->n_mcast_grps_lock);
1940         init_timer(&dev->mem_timer);
1941         dev->mem_timer.function = mem_timer;
1942         dev->mem_timer.data = (unsigned long) dev;
1943
1944         /*
1945          * The top hfi1_lkey_table_size bits are used to index the
1946          * table.  The lower 8 bits can be owned by the user (copied from
1947          * the LKEY).  The remaining bits act as a generation number or tag.
1948          */
1949         spin_lock_init(&dev->lk_table.lock);
1950         dev->lk_table.max = 1 << hfi1_lkey_table_size;
1951         /* ensure generation is at least 4 bits (keys.c) */
1952         if (hfi1_lkey_table_size > MAX_LKEY_TABLE_BITS) {
1953                 dd_dev_warn(dd, "lkey bits %u too large, reduced to %u\n",
1954                               hfi1_lkey_table_size, MAX_LKEY_TABLE_BITS);
1955                 hfi1_lkey_table_size = MAX_LKEY_TABLE_BITS;
1956         }
1957         lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
1958         dev->lk_table.table = (struct hfi1_mregion __rcu **)
1959                 vmalloc(lk_tab_size);
1960         if (dev->lk_table.table == NULL) {
1961                 ret = -ENOMEM;
1962                 goto err_lk;
1963         }
1964         RCU_INIT_POINTER(dev->dma_mr, NULL);
1965         for (i = 0; i < dev->lk_table.max; i++)
1966                 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
1967         INIT_LIST_HEAD(&dev->pending_mmaps);
1968         spin_lock_init(&dev->pending_lock);
1969         seqlock_init(&dev->iowait_lock);
1970         dev->mmap_offset = PAGE_SIZE;
1971         spin_lock_init(&dev->mmap_offset_lock);
1972         INIT_LIST_HEAD(&dev->txwait);
1973         INIT_LIST_HEAD(&dev->memwait);
1974
1975         descq_cnt = sdma_get_descq_cnt();
1976
1977         snprintf(buf, sizeof(buf), "hfi1_%u_vtxreq_cache", dd->unit);
1978         /* SLAB_HWCACHE_ALIGN for AHG */
1979         dev->verbs_txreq_cache = kmem_cache_create(buf,
1980                                                    sizeof(struct verbs_txreq),
1981                                                    0, SLAB_HWCACHE_ALIGN,
1982                                                    verbs_txreq_kmem_cache_ctor);
1983         if (!dev->verbs_txreq_cache) {
1984                 ret = -ENOMEM;
1985                 goto err_verbs_txreq;
1986         }
1987
1988         /*
1989          * The system image GUID is supposed to be the same for all
1990          * HFIs in a single system but since there can be other
1991          * device types in the system, we can't be sure this is unique.
1992          */
1993         if (!ib_hfi1_sys_image_guid)
1994                 ib_hfi1_sys_image_guid = cpu_to_be64(ppd->guid);
1995         lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1996         strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1997         ibdev->owner = THIS_MODULE;
1998         ibdev->node_guid = cpu_to_be64(ppd->guid);
1999         ibdev->uverbs_abi_ver = HFI1_UVERBS_ABI_VERSION;
2000         ibdev->uverbs_cmd_mask =
2001                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2002                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2003                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2004                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2005                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2006                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
2007                 (1ull << IB_USER_VERBS_CMD_MODIFY_AH)           |
2008                 (1ull << IB_USER_VERBS_CMD_QUERY_AH)            |
2009                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
2010                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2011                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2012                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2013                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2014                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2015                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2016                 (1ull << IB_USER_VERBS_CMD_POLL_CQ)             |
2017                 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ)       |
2018                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2019                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2020                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2021                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2022                 (1ull << IB_USER_VERBS_CMD_POST_SEND)           |
2023                 (1ull << IB_USER_VERBS_CMD_POST_RECV)           |
2024                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2025                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2026                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2027                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2028                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2029                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2030                 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2031         ibdev->node_type = RDMA_NODE_IB_CA;
2032         ibdev->phys_port_cnt = dd->num_pports;
2033         ibdev->num_comp_vectors = 1;
2034         ibdev->dma_device = &dd->pcidev->dev;
2035         ibdev->query_device = query_device;
2036         ibdev->modify_device = modify_device;
2037         ibdev->query_port = query_port;
2038         ibdev->modify_port = modify_port;
2039         ibdev->query_pkey = query_pkey;
2040         ibdev->query_gid = query_gid;
2041         ibdev->alloc_ucontext = alloc_ucontext;
2042         ibdev->dealloc_ucontext = dealloc_ucontext;
2043         ibdev->alloc_pd = alloc_pd;
2044         ibdev->dealloc_pd = dealloc_pd;
2045         ibdev->create_ah = create_ah;
2046         ibdev->destroy_ah = destroy_ah;
2047         ibdev->modify_ah = modify_ah;
2048         ibdev->query_ah = query_ah;
2049         ibdev->create_srq = hfi1_create_srq;
2050         ibdev->modify_srq = hfi1_modify_srq;
2051         ibdev->query_srq = hfi1_query_srq;
2052         ibdev->destroy_srq = hfi1_destroy_srq;
2053         ibdev->create_qp = hfi1_create_qp;
2054         ibdev->modify_qp = hfi1_modify_qp;
2055         ibdev->query_qp = hfi1_query_qp;
2056         ibdev->destroy_qp = hfi1_destroy_qp;
2057         ibdev->post_send = post_send;
2058         ibdev->post_recv = post_receive;
2059         ibdev->post_srq_recv = hfi1_post_srq_receive;
2060         ibdev->create_cq = hfi1_create_cq;
2061         ibdev->destroy_cq = hfi1_destroy_cq;
2062         ibdev->resize_cq = hfi1_resize_cq;
2063         ibdev->poll_cq = hfi1_poll_cq;
2064         ibdev->req_notify_cq = hfi1_req_notify_cq;
2065         ibdev->get_dma_mr = hfi1_get_dma_mr;
2066         ibdev->reg_phys_mr = hfi1_reg_phys_mr;
2067         ibdev->reg_user_mr = hfi1_reg_user_mr;
2068         ibdev->dereg_mr = hfi1_dereg_mr;
2069         ibdev->alloc_mr = hfi1_alloc_mr;
2070         ibdev->alloc_fmr = hfi1_alloc_fmr;
2071         ibdev->map_phys_fmr = hfi1_map_phys_fmr;
2072         ibdev->unmap_fmr = hfi1_unmap_fmr;
2073         ibdev->dealloc_fmr = hfi1_dealloc_fmr;
2074         ibdev->attach_mcast = hfi1_multicast_attach;
2075         ibdev->detach_mcast = hfi1_multicast_detach;
2076         ibdev->process_mad = hfi1_process_mad;
2077         ibdev->mmap = hfi1_mmap;
2078         ibdev->dma_ops = &hfi1_dma_mapping_ops;
2079         ibdev->get_port_immutable = port_immutable;
2080
2081         strncpy(ibdev->node_desc, init_utsname()->nodename,
2082                 sizeof(ibdev->node_desc));
2083
2084         ret = ib_register_device(ibdev, hfi1_create_port_files);
2085         if (ret)
2086                 goto err_reg;
2087
2088         ret = hfi1_create_agents(dev);
2089         if (ret)
2090                 goto err_agents;
2091
2092         ret = hfi1_verbs_register_sysfs(dd);
2093         if (ret)
2094                 goto err_class;
2095
2096         goto bail;
2097
2098 err_class:
2099         hfi1_free_agents(dev);
2100 err_agents:
2101         ib_unregister_device(ibdev);
2102 err_reg:
2103 err_verbs_txreq:
2104         kmem_cache_destroy(dev->verbs_txreq_cache);
2105         vfree(dev->lk_table.table);
2106 err_lk:
2107         hfi1_qp_exit(dev);
2108 err_qp_init:
2109         dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2110 bail:
2111         return ret;
2112 }
2113
2114 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
2115 {
2116         struct hfi1_ibdev *dev = &dd->verbs_dev;
2117         struct ib_device *ibdev = &dev->ibdev;
2118
2119         hfi1_verbs_unregister_sysfs(dd);
2120
2121         hfi1_free_agents(dev);
2122
2123         ib_unregister_device(ibdev);
2124
2125         if (!list_empty(&dev->txwait))
2126                 dd_dev_err(dd, "txwait list not empty!\n");
2127         if (!list_empty(&dev->memwait))
2128                 dd_dev_err(dd, "memwait list not empty!\n");
2129         if (dev->dma_mr)
2130                 dd_dev_err(dd, "DMA MR not NULL!\n");
2131
2132         hfi1_qp_exit(dev);
2133         del_timer_sync(&dev->mem_timer);
2134         kmem_cache_destroy(dev->verbs_txreq_cache);
2135         vfree(dev->lk_table.table);
2136 }
2137
2138 /*
2139  * This must be called with s_lock held.
2140  */
2141 void hfi1_schedule_send(struct hfi1_qp *qp)
2142 {
2143         if (hfi1_send_ok(qp)) {
2144                 struct hfi1_ibport *ibp =
2145                         to_iport(qp->ibqp.device, qp->port_num);
2146                 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2147
2148                 iowait_schedule(&qp->s_iowait, ppd->hfi1_wq);
2149         }
2150 }
2151
2152 void hfi1_cnp_rcv(struct hfi1_packet *packet)
2153 {
2154         struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2155
2156         if (packet->qp->ibqp.qp_type == IB_QPT_UC)
2157                 hfi1_uc_rcv(packet);
2158         else if (packet->qp->ibqp.qp_type == IB_QPT_UD)
2159                 hfi1_ud_rcv(packet);
2160         else
2161                 ibp->n_pkt_drops++;
2162 }