drivers/tty/serial/8250/8250_ingenic.c

   1 /*
   2  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
   3  * Copyright (C) 2015 Imagination Technologies
   4  *
   5  * Ingenic SoC UART support
   6  *
   7  * This program is free software; you can redistribute   it and/or modify it
   8  * under  the terms of   the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the   License, or (at your
  10  * option) any later version.
  11  *
  12  * You should have received a copy of the  GNU General Public License along
  13  * with this program; if not, write  to the Free Software Foundation, Inc.,
  14  * 675 Mass Ave, Cambridge, MA 02139, USA.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/console.h>
  19 #include <linux/io.h>
  20 #include <linux/libfdt.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_fdt.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/serial_8250.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/serial_reg.h>
  28
  29 struct ingenic_uart_data {
  30         struct clk      *clk_module;
  31         struct clk      *clk_baud;
  32         int             line;
  33 };
  34
  35 #define UART_FCR_UME    BIT(4)
  36
  37 static struct earlycon_device *early_device;
  38
  39 static uint8_t __init early_in(struct uart_port *port, int offset)
  40 {
  41         return readl(port->membase + (offset << 2));
  42 }
  43
  44 static void __init early_out(struct uart_port *port, int offset, uint8_t value)
  45 {
  46         writel(value, port->membase + (offset << 2));
  47 }
  48
  49 static void __init ingenic_early_console_putc(struct uart_port *port, int c)
  50 {
  51         uint8_t lsr;
  52
  53         do {
  54                 lsr = early_in(port, UART_LSR);
  55         } while ((lsr & UART_LSR_TEMT) == 0);
  56
  57         early_out(port, UART_TX, c);
  58 }
  59
  60 static void __init ingenic_early_console_write(struct console *console,
  61                                               const char *s, unsigned int count)
  62 {
  63         uart_console_write(&early_device->port, s, count,
  64                            ingenic_early_console_putc);
  65 }
  66
  67 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
  68 {
  69         void *fdt = initial_boot_params;
  70         const __be32 *prop;
  71         int offset;
  72
  73         offset = fdt_path_offset(fdt, "/ext");
  74         if (offset < 0)
  75                 return;
  76
  77         prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
  78         if (!prop)
  79                 return;
  80
  81         dev->port.uartclk = be32_to_cpup(prop);
  82 }
  83
  84 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
  85                                               const char *opt)
  86 {
  87         struct uart_port *port = &dev->port;
  88         unsigned int baud, divisor;
  89
  90         if (!dev->port.membase)
  91                 return -ENODEV;
  92
  93         ingenic_early_console_setup_clock(dev);
  94
  95         baud = dev->baud ?: 115200;
  96         divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
  97
  98         early_out(port, UART_IER, 0);
  99         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 100         early_out(port, UART_DLL, 0);
 101         early_out(port, UART_DLM, 0);
 102         early_out(port, UART_LCR, UART_LCR_WLEN8);
 103         early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
 104                         UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
 105         early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
 106
 107         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 108         early_out(port, UART_DLL, divisor & 0xff);
 109         early_out(port, UART_DLM, (divisor >> 8) & 0xff);
 110         early_out(port, UART_LCR, UART_LCR_WLEN8);
 111
 112         early_device = dev;
 113         dev->con->write = ingenic_early_console_write;
 114
 115         return 0;
 116 }
 117
 118 EARLYCON_DECLARE(jz4740_uart, ingenic_early_console_setup);
 119 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
 120                     ingenic_early_console_setup);
 121
 122 EARLYCON_DECLARE(jz4775_uart, ingenic_early_console_setup);
 123 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
 124                     ingenic_early_console_setup);
 125
 126 EARLYCON_DECLARE(jz4780_uart, ingenic_early_console_setup);
 127 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
 128                     ingenic_early_console_setup);
 129
 130 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
 131 {
 132         switch (offset) {
 133         case UART_FCR:
 134                 /* UART module enable */
 135                 value |= UART_FCR_UME;
 136                 break;
 137
 138         case UART_IER:
 139                 value |= (value & 0x4) << 2;
 140                 break;
 141
 142         default:
 143                 break;
 144         }
 145
 146         writeb(value, p->membase + (offset << p->regshift));
 147 }
 148
 149 static int ingenic_uart_probe(struct platform_device *pdev)
 150 {
 151         struct uart_8250_port uart = {};
 152         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 153         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 154         struct ingenic_uart_data *data;
 155         int err, line;
 156
 157         if (!regs || !irq) {
 158                 dev_err(&pdev->dev, "no registers/irq defined\n");
 159                 return -EINVAL;
 160         }
 161
 162         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 163         if (!data)
 164                 return -ENOMEM;
 165
 166         spin_lock_init(&uart.port.lock);
 167         uart.port.type = PORT_16550;
 168         uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
 169         uart.port.iotype = UPIO_MEM;
 170         uart.port.mapbase = regs->start;
 171         uart.port.regshift = 2;
 172         uart.port.serial_out = ingenic_uart_serial_out;
 173         uart.port.irq = irq->start;
 174         uart.port.dev = &pdev->dev;
 175
 176         /* Check for a fixed line number */
 177         line = of_alias_get_id(pdev->dev.of_node, "serial");
 178         if (line >= 0)
 179                 uart.port.line = line;
 180
 181         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 182                                          resource_size(regs));
 183         if (!uart.port.membase)
 184                 return -ENOMEM;
 185
 186         data->clk_module = devm_clk_get(&pdev->dev, "module");
 187         if (IS_ERR(data->clk_module)) {
 188                 err = PTR_ERR(data->clk_module);
 189                 if (err != -EPROBE_DEFER)
 190                         dev_err(&pdev->dev,
 191                                 "unable to get module clock: %d\n", err);
 192                 return err;
 193         }
 194
 195         data->clk_baud = devm_clk_get(&pdev->dev, "baud");
 196         if (IS_ERR(data->clk_baud)) {
 197                 err = PTR_ERR(data->clk_baud);
 198                 if (err != -EPROBE_DEFER)
 199                         dev_err(&pdev->dev,
 200                                 "unable to get baud clock: %d\n", err);
 201                 return err;
 202         }
 203
 204         err = clk_prepare_enable(data->clk_module);
 205         if (err) {
 206                 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
 207                 goto out;
 208         }
 209
 210         err = clk_prepare_enable(data->clk_baud);
 211         if (err) {
 212                 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
 213                 goto out_disable_moduleclk;
 214         }
 215         uart.port.uartclk = clk_get_rate(data->clk_baud);
 216
 217         data->line = serial8250_register_8250_port(&uart);
 218         if (data->line < 0) {
 219                 err = data->line;
 220                 goto out_disable_baudclk;
 221         }
 222
 223         platform_set_drvdata(pdev, data);
 224         return 0;
 225
 226 out_disable_baudclk:
 227         clk_disable_unprepare(data->clk_baud);
 228 out_disable_moduleclk:
 229         clk_disable_unprepare(data->clk_module);
 230 out:
 231         return err;
 232 }
 233
 234 static int ingenic_uart_remove(struct platform_device *pdev)
 235 {
 236         struct ingenic_uart_data *data = platform_get_drvdata(pdev);
 237
 238         serial8250_unregister_port(data->line);
 239         clk_disable_unprepare(data->clk_module);
 240         clk_disable_unprepare(data->clk_baud);
 241         return 0;
 242 }
 243
 244 static const struct of_device_id of_match[] = {
 245         { .compatible = "ingenic,jz4740-uart" },
 246         { .compatible = "ingenic,jz4775-uart" },
 247         { .compatible = "ingenic,jz4780-uart" },
 248         { /* sentinel */ }
 249 };
 250 MODULE_DEVICE_TABLE(of, of_match);
 251
 252 static struct platform_driver ingenic_uart_platform_driver = {
 253         .driver = {
 254                 .name           = "ingenic-uart",
 255                 .of_match_table = of_match,
 256         },
 257         .probe                  = ingenic_uart_probe,
 258         .remove                 = ingenic_uart_remove,
 259 };
 260
 261 module_platform_driver(ingenic_uart_platform_driver);
 262
 263 MODULE_AUTHOR("Paul Burton");
 264 MODULE_LICENSE("GPL");
 265 MODULE_DESCRIPTION("Ingenic SoC UART driver");