2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 #include <linux/rational.h>
26 #include <asm/byteorder.h>
29 #include <linux/dmaengine.h>
30 #include <linux/platform_data/dma-dw.h>
35 * init function returns:
36 * > 0 - number of ports
37 * = 0 - use board->num_ports
40 struct pci_serial_quirk {
45 int (*probe)(struct pci_dev *dev);
46 int (*init)(struct pci_dev *dev);
47 int (*setup)(struct serial_private *,
48 const struct pciserial_board *,
49 struct uart_8250_port *, int);
50 void (*exit)(struct pci_dev *dev);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private {
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
63 static int pci_default_setup(struct serial_private*,
64 const struct pciserial_board*, struct uart_8250_port *, int);
66 static void moan_device(const char *str, struct pci_dev *dev)
70 "Please send the output of lspci -vv, this\n"
71 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
72 "manufacturer and name of serial board or\n"
73 "modem board to <linux-serial@vger.kernel.org>.\n",
74 pci_name(dev), str, dev->vendor, dev->device,
75 dev->subsystem_vendor, dev->subsystem_device);
79 setup_port(struct serial_private *priv, struct uart_8250_port *port,
80 int bar, int offset, int regshift)
82 struct pci_dev *dev = priv->dev;
84 if (bar >= PCI_NUM_BAR_RESOURCES)
87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
90 if (!priv->remapped_bar[bar])
93 port->port.iotype = UPIO_MEM;
94 port->port.iobase = 0;
95 port->port.mapbase = pci_resource_start(dev, bar) + offset;
96 port->port.membase = priv->remapped_bar[bar] + offset;
97 port->port.regshift = regshift;
99 port->port.iotype = UPIO_PORT;
100 port->port.iobase = pci_resource_start(dev, bar) + offset;
101 port->port.mapbase = 0;
102 port->port.membase = NULL;
103 port->port.regshift = 0;
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_8250_port *port, int idx)
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
128 offset += ((idx - 6) * board->uart_offset);
131 return setup_port(priv, port, bar, offset, board->reg_shift);
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_8250_port *port, int idx)
142 unsigned int bar, offset = board->first_offset;
144 bar = FL_GET_BASE(board->flags);
149 offset += (idx - 4) * board->uart_offset;
152 return setup_port(priv, port, bar, offset, board->reg_shift);
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
162 static int pci_hp_diva_init(struct pci_dev *dev)
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
193 pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_8250_port *port, int idx)
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
215 offset += idx * board->uart_offset;
217 return setup_port(priv, port, bar, offset, board->reg_shift);
221 * Added for EKF Intel i960 serial boards
223 static int pci_inteli960ni_init(struct pci_dev *dev)
227 if (!(dev->subsystem_device & 0x1000))
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, &oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
245 static int pci_plx9050_init(struct pci_dev *dev)
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
272 * enable/disable interrupts
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277 writel(irq_config, p + 0x4c);
280 * Read the register back to ensure that it took effect.
288 static void pci_plx9050_exit(struct pci_dev *dev)
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
303 * Read the register back to ensure that it took effect.
310 #define NI8420_INT_ENABLE_REG 0x38
311 #define NI8420_INT_ENABLE_BIT 0x2000
313 static void pci_ni8420_exit(struct pci_dev *dev)
316 unsigned int bar = 0;
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
323 p = pci_ioremap_bar(dev, bar);
327 /* Disable the CPU Interrupt */
328 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
329 p + NI8420_INT_ENABLE_REG);
335 #define MITE_IOWBSR1 0xc4
336 #define MITE_IOWCR1 0xf4
337 #define MITE_LCIMR1 0x08
338 #define MITE_LCIMR2 0x10
340 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342 static void pci_ni8430_exit(struct pci_dev *dev)
345 unsigned int bar = 0;
347 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
348 moan_device("no memory in bar", dev);
352 p = pci_ioremap_bar(dev, bar);
356 /* Disable the CPU Interrupt */
357 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
361 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
364 struct uart_8250_port *port, int idx)
366 unsigned int bar, offset = board->first_offset;
371 /* first four channels map to 0, 0x100, 0x200, 0x300 */
372 offset += idx * board->uart_offset;
373 } else if (idx < 8) {
374 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
375 offset += idx * board->uart_offset + 0xC00;
376 } else /* we have only 8 ports on PMC-OCTALPRO */
379 return setup_port(priv, port, bar, offset, board->reg_shift);
383 * This does initialization for PMC OCTALPRO cards:
384 * maps the device memory, resets the UARTs (needed, bc
385 * if the module is removed and inserted again, the card
386 * is in the sleep mode) and enables global interrupt.
389 /* global control register offset for SBS PMC-OctalPro */
390 #define OCT_REG_CR_OFF 0x500
392 static int sbs_init(struct pci_dev *dev)
396 p = pci_ioremap_bar(dev, 0);
400 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
401 writeb(0x10, p + OCT_REG_CR_OFF);
403 writeb(0x0, p + OCT_REG_CR_OFF);
405 /* Set bit-2 (INTENABLE) of Control Register */
406 writeb(0x4, p + OCT_REG_CR_OFF);
413 * Disables the global interrupt of PMC-OctalPro
416 static void sbs_exit(struct pci_dev *dev)
420 p = pci_ioremap_bar(dev, 0);
421 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 writeb(0, p + OCT_REG_CR_OFF);
428 * SIIG serial cards have an PCI interface chip which also controls
429 * the UART clocking frequency. Each UART can be clocked independently
430 * (except cards equipped with 4 UARTs) and initial clocking settings
431 * are stored in the EEPROM chip. It can cause problems because this
432 * version of serial driver doesn't support differently clocked UART's
433 * on single PCI card. To prevent this, initialization functions set
434 * high frequency clocking for all UART's on given card. It is safe (I
435 * hope) because it doesn't touch EEPROM settings to prevent conflicts
436 * with other OSes (like M$ DOS).
438 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
440 * There is two family of SIIG serial cards with different PCI
441 * interface chip and different configuration methods:
442 * - 10x cards have control registers in IO and/or memory space;
443 * - 20x cards have control registers in standard PCI configuration space.
445 * Note: all 10x cards have PCI device ids 0x10..
446 * all 20x cards have PCI device ids 0x20..
448 * There are also Quartet Serial cards which use Oxford Semiconductor
449 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 * Note: some SIIG cards are probed by the parport_serial object.
454 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
455 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457 static int pci_siig10x_init(struct pci_dev *dev)
462 switch (dev->device & 0xfff8) {
463 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
466 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
469 default: /* 1S1P, 4S */
474 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
478 writew(readw(p + 0x28) & data, p + 0x28);
484 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
485 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487 static int pci_siig20x_init(struct pci_dev *dev)
491 /* Change clock frequency for the first UART. */
492 pci_read_config_byte(dev, 0x6f, &data);
493 pci_write_config_byte(dev, 0x6f, data & 0xef);
495 /* If this card has 2 UART, we have to do the same with second UART. */
496 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
497 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
498 pci_read_config_byte(dev, 0x73, &data);
499 pci_write_config_byte(dev, 0x73, data & 0xef);
504 static int pci_siig_init(struct pci_dev *dev)
506 unsigned int type = dev->device & 0xff00;
509 return pci_siig10x_init(dev);
510 else if (type == 0x2000)
511 return pci_siig20x_init(dev);
513 moan_device("Unknown SIIG card", dev);
517 static int pci_siig_setup(struct serial_private *priv,
518 const struct pciserial_board *board,
519 struct uart_8250_port *port, int idx)
521 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
525 offset = (idx - 4) * 8;
528 return setup_port(priv, port, bar, offset, 0);
532 * Timedia has an explosion of boards, and to avoid the PCI table from
533 * growing *huge*, we use this function to collapse some 70 entries
534 * in the PCI table into one, for sanity's and compactness's sake.
536 static const unsigned short timedia_single_port[] = {
537 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
540 static const unsigned short timedia_dual_port[] = {
541 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
542 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
543 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
544 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
548 static const unsigned short timedia_quad_port[] = {
549 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
550 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
551 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
555 static const unsigned short timedia_eight_port[] = {
556 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
557 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
560 static const struct timedia_struct {
562 const unsigned short *ids;
564 { 1, timedia_single_port },
565 { 2, timedia_dual_port },
566 { 4, timedia_quad_port },
567 { 8, timedia_eight_port }
571 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
572 * listing them individually, this driver merely grabs them all with
573 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
574 * and should be left free to be claimed by parport_serial instead.
576 static int pci_timedia_probe(struct pci_dev *dev)
579 * Check the third digit of the subdevice ID
580 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 "ignoring Timedia subdevice %04x for parport_serial\n",
585 dev->subsystem_device);
592 static int pci_timedia_init(struct pci_dev *dev)
594 const unsigned short *ids;
597 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
598 ids = timedia_data[i].ids;
599 for (j = 0; ids[j]; j++)
600 if (dev->subsystem_device == ids[j])
601 return timedia_data[i].num;
607 * Timedia/SUNIX uses a mixture of BARs and offsets
608 * Ugh, this is ugly as all hell --- TYT
611 pci_timedia_setup(struct serial_private *priv,
612 const struct pciserial_board *board,
613 struct uart_8250_port *port, int idx)
615 unsigned int bar = 0, offset = board->first_offset;
622 offset = board->uart_offset;
629 offset = board->uart_offset;
638 return setup_port(priv, port, bar, offset, board->reg_shift);
642 * Some Titan cards are also a little weird
645 titan_400l_800l_setup(struct serial_private *priv,
646 const struct pciserial_board *board,
647 struct uart_8250_port *port, int idx)
649 unsigned int bar, offset = board->first_offset;
660 offset = (idx - 2) * board->uart_offset;
663 return setup_port(priv, port, bar, offset, board->reg_shift);
666 static int pci_xircom_init(struct pci_dev *dev)
672 static int pci_ni8420_init(struct pci_dev *dev)
675 unsigned int bar = 0;
677 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
678 moan_device("no memory in bar", dev);
682 p = pci_ioremap_bar(dev, bar);
686 /* Enable CPU Interrupt */
687 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
688 p + NI8420_INT_ENABLE_REG);
694 #define MITE_IOWBSR1_WSIZE 0xa
695 #define MITE_IOWBSR1_WIN_OFFSET 0x800
696 #define MITE_IOWBSR1_WENAB (1 << 7)
697 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
698 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
699 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701 static int pci_ni8430_init(struct pci_dev *dev)
704 struct pci_bus_region region;
706 unsigned int bar = 0;
708 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
709 moan_device("no memory in bar", dev);
713 p = pci_ioremap_bar(dev, bar);
718 * Set device window address and size in BAR0, while acknowledging that
719 * the resource structure may contain a translated address that differs
720 * from the address the device responds to.
722 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
723 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
724 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
725 writel(device_window, p + MITE_IOWBSR1);
727 /* Set window access to go to RAMSEL IO address space */
728 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
731 /* Enable IO Bus Interrupt 0 */
732 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734 /* Enable CPU Interrupt */
735 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
741 /* UART Port Control Register */
742 #define NI8430_PORTCON 0x0f
743 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
746 pci_ni8430_setup(struct serial_private *priv,
747 const struct pciserial_board *board,
748 struct uart_8250_port *port, int idx)
750 struct pci_dev *dev = priv->dev;
752 unsigned int bar, offset = board->first_offset;
754 if (idx >= board->num_ports)
757 bar = FL_GET_BASE(board->flags);
758 offset += idx * board->uart_offset;
760 p = pci_ioremap_bar(dev, bar);
764 /* enable the transceiver */
765 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
766 p + offset + NI8430_PORTCON);
770 return setup_port(priv, port, bar, offset, board->reg_shift);
773 static int pci_netmos_9900_setup(struct serial_private *priv,
774 const struct pciserial_board *board,
775 struct uart_8250_port *port, int idx)
779 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
780 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
781 /* netmos apparently orders BARs by datasheet layout, so serial
782 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
786 return setup_port(priv, port, bar, 0, board->reg_shift);
788 return pci_default_setup(priv, board, port, idx);
792 /* the 99xx series comes with a range of device IDs and a variety
795 * 9900 has varying capabilities and can cascade to sub-controllers
796 * (cascading should be purely internal)
797 * 9904 is hardwired with 4 serial ports
798 * 9912 and 9922 are hardwired with 2 serial ports
800 static int pci_netmos_9900_numports(struct pci_dev *dev)
802 unsigned int c = dev->class;
804 unsigned short sub_serports;
810 } else if ((pi == 0) &&
811 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
812 /* two possibilities: 0x30ps encodes number of parallel and
813 * serial ports, or 0x1000 indicates *something*. This is not
814 * immediately obvious, since the 2s1p+4s configuration seems
815 * to offer all functionality on functions 0..2, while still
816 * advertising the same function 3 as the 4s+2s1p config.
818 sub_serports = dev->subsystem_device & 0xf;
819 if (sub_serports > 0) {
822 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
827 moan_device("unknown NetMos/Mostech program interface", dev);
831 static int pci_netmos_init(struct pci_dev *dev)
833 /* subdevice 0x00PS means <P> parallel, <S> serial */
834 unsigned int num_serial = dev->subsystem_device & 0xf;
836 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
837 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
840 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
841 dev->subsystem_device == 0x0299)
844 switch (dev->device) { /* FALLTHROUGH on all */
845 case PCI_DEVICE_ID_NETMOS_9904:
846 case PCI_DEVICE_ID_NETMOS_9912:
847 case PCI_DEVICE_ID_NETMOS_9922:
848 case PCI_DEVICE_ID_NETMOS_9900:
849 num_serial = pci_netmos_9900_numports(dev);
853 if (num_serial == 0 ) {
854 moan_device("unknown NetMos/Mostech device", dev);
865 * These chips are available with optionally one parallel port and up to
866 * two serial ports. Unfortunately they all have the same product id.
868 * Basic configuration is done over a region of 32 I/O ports. The base
869 * ioport is called INTA or INTC, depending on docs/other drivers.
871 * The region of the 32 I/O ports is configured in POSIO0R...
875 #define ITE_887x_MISCR 0x9c
876 #define ITE_887x_INTCBAR 0x78
877 #define ITE_887x_UARTBAR 0x7c
878 #define ITE_887x_PS0BAR 0x10
879 #define ITE_887x_POSIO0 0x60
882 #define ITE_887x_IOSIZE 32
883 /* I/O space size (bits 26-24; 8 bytes = 011b) */
884 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
885 /* I/O space size (bits 26-24; 32 bytes = 101b) */
886 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
887 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
888 #define ITE_887x_POSIO_SPEED (3 << 29)
889 /* enable IO_Space bit */
890 #define ITE_887x_POSIO_ENABLE (1 << 31)
892 static int pci_ite887x_init(struct pci_dev *dev)
894 /* inta_addr are the configuration addresses of the ITE */
895 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
898 struct resource *iobase = NULL;
899 u32 miscr, uartbar, ioport;
901 /* search for the base-ioport */
903 while (inta_addr[i] && iobase == NULL) {
904 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 if (iobase != NULL) {
907 /* write POSIO0R - speed | size | ioport */
908 pci_write_config_dword(dev, ITE_887x_POSIO0,
909 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
910 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
911 /* write INTCBAR - ioport */
912 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 ret = inb(inta_addr[i]);
916 /* ioport connected */
919 release_region(iobase->start, ITE_887x_IOSIZE);
926 dev_err(&dev->dev, "ite887x: could not find iobase\n");
930 /* start of undocumented type checking (see parport_pc.c) */
931 type = inb(iobase->start + 0x18) & 0x0f;
934 case 0x2: /* ITE8871 (1P) */
935 case 0xa: /* ITE8875 (1P) */
938 case 0xe: /* ITE8872 (2S1P) */
941 case 0x6: /* ITE8873 (1S) */
944 case 0x8: /* ITE8874 (2S) */
948 moan_device("Unknown ITE887x", dev);
952 /* configure all serial ports */
953 for (i = 0; i < ret; i++) {
954 /* read the I/O port from the device */
955 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 ioport &= 0x0000FF00; /* the actual base address */
958 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
959 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
960 ITE_887x_POSIO_IOSIZE_8 | ioport);
962 /* write the ioport to the UARTBAR */
963 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
964 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
965 uartbar |= (ioport << (16 * i)); /* set the ioport */
966 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968 /* get current config */
969 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
970 /* disable interrupts (UARTx_Routing[3:0]) */
971 miscr &= ~(0xf << (12 - 4 * i));
972 /* activate the UART (UARTx_En) */
973 miscr |= 1 << (23 - i);
974 /* write new config with activated UART */
975 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
979 /* the device has no UARTs if we get here */
980 release_region(iobase->start, ITE_887x_IOSIZE);
986 static void pci_ite887x_exit(struct pci_dev *dev)
989 /* the ioport is bit 0-15 in POSIO0R */
990 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 release_region(ioport, ITE_887x_IOSIZE);
996 * EndRun Technologies.
997 * Determine the number of ports available on the device.
999 #define PCI_VENDOR_ID_ENDRUN 0x7401
1000 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002 static int pci_endrun_init(struct pci_dev *dev)
1005 unsigned long deviceID;
1006 unsigned int number_uarts = 0;
1008 /* EndRun device is all 0xexxx */
1009 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1010 (dev->device & 0xf000) != 0xe000)
1013 p = pci_iomap(dev, 0, 5);
1017 deviceID = ioread32(p);
1019 if (deviceID == 0x07000200) {
1020 number_uarts = ioread8(p + 4);
1022 "%d ports detected on EndRun PCI Express device\n",
1025 pci_iounmap(dev, p);
1026 return number_uarts;
1030 * Oxford Semiconductor Inc.
1031 * Check that device is part of the Tornado range of devices, then determine
1032 * the number of ports available on the device.
1034 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1037 unsigned long deviceID;
1038 unsigned int number_uarts = 0;
1040 /* OxSemi Tornado devices are all 0xCxxx */
1041 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1042 (dev->device & 0xF000) != 0xC000)
1045 p = pci_iomap(dev, 0, 5);
1049 deviceID = ioread32(p);
1050 /* Tornado device */
1051 if (deviceID == 0x07000200) {
1052 number_uarts = ioread8(p + 4);
1054 "%d ports detected on Oxford PCI Express device\n",
1057 pci_iounmap(dev, p);
1058 return number_uarts;
1061 static int pci_asix_setup(struct serial_private *priv,
1062 const struct pciserial_board *board,
1063 struct uart_8250_port *port, int idx)
1065 port->bugs |= UART_BUG_PARITY;
1066 return pci_default_setup(priv, board, port, idx);
1069 /* Quatech devices have their own extra interface features */
1071 struct quatech_feature {
1076 #define QPCR_TEST_FOR1 0x3F
1077 #define QPCR_TEST_GET1 0x00
1078 #define QPCR_TEST_FOR2 0x40
1079 #define QPCR_TEST_GET2 0x40
1080 #define QPCR_TEST_FOR3 0x80
1081 #define QPCR_TEST_GET3 0x40
1082 #define QPCR_TEST_FOR4 0xC0
1083 #define QPCR_TEST_GET4 0x80
1085 #define QOPR_CLOCK_X1 0x0000
1086 #define QOPR_CLOCK_X2 0x0001
1087 #define QOPR_CLOCK_X4 0x0002
1088 #define QOPR_CLOCK_X8 0x0003
1089 #define QOPR_CLOCK_RATE_MASK 0x0003
1092 static struct quatech_feature quatech_cards[] = {
1093 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1096 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1098 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1100 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1109 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1115 static int pci_quatech_amcc(u16 devid)
1117 struct quatech_feature *qf = &quatech_cards[0];
1119 if (qf->devid == devid)
1123 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1127 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 unsigned long base = port->port.iobase;
1132 LCR = inb(base + UART_LCR);
1133 outb(0xBF, base + UART_LCR);
1134 val = inb(base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1139 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 unsigned long base = port->port.iobase;
1144 LCR = inb(base + UART_LCR);
1145 outb(0xBF, base + UART_LCR);
1146 val = inb(base + UART_SCR);
1147 outb(qopr, base + UART_SCR);
1148 outb(LCR, base + UART_LCR);
1151 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 unsigned long base = port->port.iobase;
1156 LCR = inb(base + UART_LCR);
1157 outb(0xBF, base + UART_LCR);
1158 val = inb(base + UART_SCR);
1159 outb(val | 0x10, base + UART_SCR);
1160 qmcr = inb(base + UART_MCR);
1161 outb(val, base + UART_SCR);
1162 outb(LCR, base + UART_LCR);
1167 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 unsigned long base = port->port.iobase;
1172 LCR = inb(base + UART_LCR);
1173 outb(0xBF, base + UART_LCR);
1174 val = inb(base + UART_SCR);
1175 outb(val | 0x10, base + UART_SCR);
1176 outb(qmcr, base + UART_MCR);
1177 outb(val, base + UART_SCR);
1178 outb(LCR, base + UART_LCR);
1181 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 unsigned long base = port->port.iobase;
1186 LCR = inb(base + UART_LCR);
1187 outb(0xBF, base + UART_LCR);
1188 val = inb(base + UART_SCR);
1190 outb(0x80, UART_LCR);
1191 if (!(inb(UART_SCR) & 0x20)) {
1192 outb(LCR, base + UART_LCR);
1199 static int pci_quatech_test(struct uart_8250_port *port)
1202 u8 qopr = pci_quatech_rqopr(port);
1203 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET1)
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET2)
1211 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1212 reg = pci_quatech_rqopr(port) & 0xC0;
1213 if (reg != QPCR_TEST_GET3)
1215 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1216 reg = pci_quatech_rqopr(port) & 0xC0;
1217 if (reg != QPCR_TEST_GET4)
1220 pci_quatech_wqopr(port, qopr);
1224 static int pci_quatech_clock(struct uart_8250_port *port)
1227 unsigned long clock;
1229 if (pci_quatech_test(port) < 0)
1232 qopr = pci_quatech_rqopr(port);
1234 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1235 reg = pci_quatech_rqopr(port);
1236 if (reg & QOPR_CLOCK_X8) {
1240 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1241 reg = pci_quatech_rqopr(port);
1242 if (!(reg & QOPR_CLOCK_X8)) {
1246 reg &= QOPR_CLOCK_X8;
1247 if (reg == QOPR_CLOCK_X2) {
1249 set = QOPR_CLOCK_X2;
1250 } else if (reg == QOPR_CLOCK_X4) {
1252 set = QOPR_CLOCK_X4;
1253 } else if (reg == QOPR_CLOCK_X8) {
1255 set = QOPR_CLOCK_X8;
1258 set = QOPR_CLOCK_X1;
1260 qopr &= ~QOPR_CLOCK_RATE_MASK;
1264 pci_quatech_wqopr(port, qopr);
1268 static int pci_quatech_rs422(struct uart_8250_port *port)
1273 if (!pci_quatech_has_qmcr(port))
1275 qmcr = pci_quatech_rqmcr(port);
1276 pci_quatech_wqmcr(port, 0xFF);
1277 if (pci_quatech_rqmcr(port))
1279 pci_quatech_wqmcr(port, qmcr);
1283 static int pci_quatech_init(struct pci_dev *dev)
1285 if (pci_quatech_amcc(dev->device)) {
1286 unsigned long base = pci_resource_start(dev, 0);
1289 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1290 tmp = inl(base + 0x3c);
1291 outl(tmp | 0x01000000, base + 0x3c);
1292 outl(tmp &= ~0x01000000, base + 0x3c);
1298 static int pci_quatech_setup(struct serial_private *priv,
1299 const struct pciserial_board *board,
1300 struct uart_8250_port *port, int idx)
1302 /* Needed by pci_quatech calls below */
1303 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1304 /* Set up the clocking */
1305 port->port.uartclk = pci_quatech_clock(port);
1306 /* For now just warn about RS422 */
1307 if (pci_quatech_rs422(port))
1308 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1309 return pci_default_setup(priv, board, port, idx);
1312 static void pci_quatech_exit(struct pci_dev *dev)
1316 static int pci_default_setup(struct serial_private *priv,
1317 const struct pciserial_board *board,
1318 struct uart_8250_port *port, int idx)
1320 unsigned int bar, offset = board->first_offset, maxnr;
1322 bar = FL_GET_BASE(board->flags);
1323 if (board->flags & FL_BASE_BARS)
1326 offset += idx * board->uart_offset;
1328 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1329 (board->reg_shift + 3);
1331 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1334 return setup_port(priv, port, bar, offset, board->reg_shift);
1337 static int pci_pericom_setup(struct serial_private *priv,
1338 const struct pciserial_board *board,
1339 struct uart_8250_port *port, int idx)
1341 unsigned int bar, offset = board->first_offset, maxnr;
1343 bar = FL_GET_BASE(board->flags);
1344 if (board->flags & FL_BASE_BARS)
1347 offset += idx * board->uart_offset;
1349 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1350 (board->reg_shift + 3);
1352 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1355 port->port.uartclk = 14745600;
1357 return setup_port(priv, port, bar, offset, board->reg_shift);
1361 ce4100_serial_setup(struct serial_private *priv,
1362 const struct pciserial_board *board,
1363 struct uart_8250_port *port, int idx)
1367 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1368 port->port.iotype = UPIO_MEM32;
1369 port->port.type = PORT_XSCALE;
1370 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1371 port->port.regshift = 2;
1376 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1379 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1382 #define BYT_PRV_CLK 0x800
1383 #define BYT_PRV_CLK_EN (1 << 0)
1384 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1385 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1386 #define BYT_PRV_CLK_UPDATE (1 << 31)
1388 #define BYT_TX_OVF_INT 0x820
1389 #define BYT_TX_OVF_INT_MASK (1 << 1)
1392 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1393 struct ktermios *old)
1395 unsigned int baud = tty_termios_baud_rate(termios);
1396 unsigned long fref = 100000000, fuart = baud * 16;
1397 unsigned long w = BIT(15) - 1;
1401 /* Get Fuart closer to Fref */
1402 fuart *= rounddown_pow_of_two(fref / fuart);
1405 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1406 * dividers must be adjusted.
1408 * uartclk = (m / n) * 100 MHz, where m <= n
1410 rational_best_approximation(fuart, fref, w, w, &m, &n);
1413 /* Reset the clock */
1414 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1415 writel(reg, p->membase + BYT_PRV_CLK);
1416 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1417 writel(reg, p->membase + BYT_PRV_CLK);
1419 p->status &= ~UPSTAT_AUTOCTS;
1420 if (termios->c_cflag & CRTSCTS)
1421 p->status |= UPSTAT_AUTOCTS;
1423 serial8250_do_set_termios(p, termios, old);
1426 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1428 struct dw_dma_slave *dws = param;
1430 if (dws->dma_dev != chan->device->dev)
1433 chan->private = dws;
1438 byt_serial_setup(struct serial_private *priv,
1439 const struct pciserial_board *board,
1440 struct uart_8250_port *port, int idx)
1442 struct pci_dev *pdev = priv->dev;
1443 struct device *dev = port->port.dev;
1444 struct uart_8250_dma *dma;
1445 struct dw_dma_slave *tx_param, *rx_param;
1446 struct pci_dev *dma_dev;
1449 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1453 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1457 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1461 switch (pdev->device) {
1462 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1463 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1464 rx_param->src_id = 3;
1465 tx_param->dst_id = 2;
1467 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1468 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1469 rx_param->src_id = 5;
1470 tx_param->dst_id = 4;
1476 rx_param->src_master = 1;
1477 rx_param->dst_master = 0;
1479 dma->rxconf.src_maxburst = 16;
1481 tx_param->src_master = 1;
1482 tx_param->dst_master = 0;
1484 dma->txconf.dst_maxburst = 16;
1486 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1487 rx_param->dma_dev = &dma_dev->dev;
1488 tx_param->dma_dev = &dma_dev->dev;
1490 dma->fn = byt_dma_filter;
1491 dma->rx_param = rx_param;
1492 dma->tx_param = tx_param;
1494 ret = pci_default_setup(priv, board, port, idx);
1495 port->port.iotype = UPIO_MEM;
1496 port->port.type = PORT_16550A;
1497 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1498 port->port.set_termios = byt_set_termios;
1499 port->port.fifosize = 64;
1500 port->tx_loadsz = 64;
1502 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1504 /* Disable Tx counter interrupts */
1505 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1511 pci_omegapci_setup(struct serial_private *priv,
1512 const struct pciserial_board *board,
1513 struct uart_8250_port *port, int idx)
1515 return setup_port(priv, port, 2, idx * 8, 0);
1519 pci_brcm_trumanage_setup(struct serial_private *priv,
1520 const struct pciserial_board *board,
1521 struct uart_8250_port *port, int idx)
1523 int ret = pci_default_setup(priv, board, port, idx);
1525 port->port.type = PORT_BRCM_TRUMANAGE;
1526 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1530 /* RTS will control by MCR if this bit is 0 */
1531 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1532 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1533 #define FINTEK_RTS_INVERT BIT(5)
1535 /* We should do proper H/W transceiver setting before change to RS485 mode */
1536 static int pci_fintek_rs485_config(struct uart_port *port,
1537 struct serial_rs485 *rs485)
1540 u8 *index = (u8 *) port->private_data;
1541 struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1544 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1547 rs485 = &port->rs485;
1548 else if (rs485->flags & SER_RS485_ENABLED)
1549 memset(rs485->padding, 0, sizeof(rs485->padding));
1551 memset(rs485, 0, sizeof(*rs485));
1553 /* F81504/508/512 not support RTS delay before or after send */
1554 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1556 if (rs485->flags & SER_RS485_ENABLED) {
1557 /* Enable RTS H/W control mode */
1558 setting |= FINTEK_RTS_CONTROL_BY_HW;
1560 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1561 /* RTS driving high on TX */
1562 setting &= ~FINTEK_RTS_INVERT;
1564 /* RTS driving low on TX */
1565 setting |= FINTEK_RTS_INVERT;
1568 rs485->delay_rts_after_send = 0;
1569 rs485->delay_rts_before_send = 0;
1571 /* Disable RTS H/W control mode */
1572 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1575 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1577 if (rs485 != &port->rs485)
1578 port->rs485 = *rs485;
1583 static int pci_fintek_setup(struct serial_private *priv,
1584 const struct pciserial_board *board,
1585 struct uart_8250_port *port, int idx)
1587 struct pci_dev *pdev = priv->dev;
1592 config_base = 0x40 + 0x08 * idx;
1594 /* Get the io address from configuration space */
1595 pci_read_config_word(pdev, config_base + 4, &iobase);
1597 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1599 port->port.iotype = UPIO_PORT;
1600 port->port.iobase = iobase;
1601 port->port.rs485_config = pci_fintek_rs485_config;
1603 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1607 /* preserve index in PCI configuration space */
1609 port->port.private_data = data;
1614 static int pci_fintek_init(struct pci_dev *dev)
1616 unsigned long iobase;
1620 struct serial_private *priv = pci_get_drvdata(dev);
1621 struct uart_8250_port *port;
1623 switch (dev->device) {
1624 case 0x1104: /* 4 ports */
1625 case 0x1108: /* 8 ports */
1626 max_port = dev->device & 0xff;
1628 case 0x1112: /* 12 ports */
1635 /* Get the io address dispatch from the BIOS */
1636 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1637 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1638 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1640 for (i = 0; i < max_port; ++i) {
1641 /* UART0 configuration offset start from 0x40 */
1642 config_base = 0x40 + 0x08 * i;
1644 /* Calculate Real IO Port */
1645 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1647 /* Enable UART I/O port */
1648 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1650 /* Select 128-byte FIFO and 8x FIFO threshold */
1651 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1654 pci_write_config_byte(dev, config_base + 0x04,
1655 (u8)(iobase & 0xff));
1658 pci_write_config_byte(dev, config_base + 0x05,
1659 (u8)((iobase & 0xff00) >> 8));
1661 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1664 /* re-apply RS232/485 mode when
1665 * pciserial_resume_ports()
1667 port = serial8250_get_port(priv->line[i]);
1668 pci_fintek_rs485_config(&port->port, NULL);
1670 /* First init without port data
1671 * force init to RS232 Mode
1673 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1680 static int skip_tx_en_setup(struct serial_private *priv,
1681 const struct pciserial_board *board,
1682 struct uart_8250_port *port, int idx)
1684 port->port.flags |= UPF_NO_TXEN_TEST;
1685 dev_dbg(&priv->dev->dev,
1686 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1687 priv->dev->vendor, priv->dev->device,
1688 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1690 return pci_default_setup(priv, board, port, idx);
1693 static void kt_handle_break(struct uart_port *p)
1695 struct uart_8250_port *up = up_to_u8250p(p);
1697 * On receipt of a BI, serial device in Intel ME (Intel
1698 * management engine) needs to have its fifos cleared for sane
1699 * SOL (Serial Over Lan) output.
1701 serial8250_clear_and_reinit_fifos(up);
1704 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1706 struct uart_8250_port *up = up_to_u8250p(p);
1710 * When the Intel ME (management engine) gets reset its serial
1711 * port registers could return 0 momentarily. Functions like
1712 * serial8250_console_write, read and save the IER, perform
1713 * some operation and then restore it. In order to avoid
1714 * setting IER register inadvertently to 0, if the value read
1715 * is 0, double check with ier value in uart_8250_port and use
1716 * that instead. up->ier should be the same value as what is
1717 * currently configured.
1719 val = inb(p->iobase + offset);
1720 if (offset == UART_IER) {
1727 static int kt_serial_setup(struct serial_private *priv,
1728 const struct pciserial_board *board,
1729 struct uart_8250_port *port, int idx)
1731 port->port.flags |= UPF_BUG_THRE;
1732 port->port.serial_in = kt_serial_in;
1733 port->port.handle_break = kt_handle_break;
1734 return skip_tx_en_setup(priv, board, port, idx);
1737 static int pci_eg20t_init(struct pci_dev *dev)
1739 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1746 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1747 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1750 pci_xr17c154_setup(struct serial_private *priv,
1751 const struct pciserial_board *board,
1752 struct uart_8250_port *port, int idx)
1754 port->port.flags |= UPF_EXAR_EFR;
1755 return pci_default_setup(priv, board, port, idx);
1759 xr17v35x_has_slave(struct serial_private *priv)
1761 const int dev_id = priv->dev->device;
1763 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1764 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1768 pci_xr17v35x_setup(struct serial_private *priv,
1769 const struct pciserial_board *board,
1770 struct uart_8250_port *port, int idx)
1774 p = pci_ioremap_bar(priv->dev, 0);
1778 port->port.flags |= UPF_EXAR_EFR;
1781 * Setup the uart clock for the devices on expansion slot to
1782 * half the clock speed of the main chip (which is 125MHz)
1784 if (xr17v35x_has_slave(priv) && idx >= 8)
1785 port->port.uartclk = (7812500 * 16 / 2);
1788 * Setup Multipurpose Input/Output pins.
1791 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1792 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1793 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1794 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1795 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1796 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1797 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1798 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1799 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1800 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1801 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1802 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1804 writeb(0x00, p + UART_EXAR_8XMODE);
1805 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1806 writeb(128, p + UART_EXAR_TXTRG);
1807 writeb(128, p + UART_EXAR_RXTRG);
1810 return pci_default_setup(priv, board, port, idx);
1813 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1814 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1815 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1816 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1819 pci_fastcom335_setup(struct serial_private *priv,
1820 const struct pciserial_board *board,
1821 struct uart_8250_port *port, int idx)
1825 p = pci_ioremap_bar(priv->dev, 0);
1829 port->port.flags |= UPF_EXAR_EFR;
1832 * Setup Multipurpose Input/Output pins.
1835 switch (priv->dev->device) {
1836 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1837 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1838 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1839 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1840 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1842 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1843 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1844 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1845 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1846 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1849 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1850 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1851 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1853 writeb(0x00, p + UART_EXAR_8XMODE);
1854 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1855 writeb(32, p + UART_EXAR_TXTRG);
1856 writeb(32, p + UART_EXAR_RXTRG);
1859 return pci_default_setup(priv, board, port, idx);
1863 pci_wch_ch353_setup(struct serial_private *priv,
1864 const struct pciserial_board *board,
1865 struct uart_8250_port *port, int idx)
1867 port->port.flags |= UPF_FIXED_TYPE;
1868 port->port.type = PORT_16550A;
1869 return pci_default_setup(priv, board, port, idx);
1873 pci_wch_ch38x_setup(struct serial_private *priv,
1874 const struct pciserial_board *board,
1875 struct uart_8250_port *port, int idx)
1877 port->port.flags |= UPF_FIXED_TYPE;
1878 port->port.type = PORT_16850;
1879 return pci_default_setup(priv, board, port, idx);
1882 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1883 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1884 #define PCI_DEVICE_ID_OCTPRO 0x0001
1885 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1886 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1887 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1888 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1889 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1890 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1891 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1892 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1893 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1894 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1895 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1896 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1897 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1898 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1899 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1900 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1901 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1902 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1903 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1904 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1905 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1906 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1907 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1908 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1909 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1910 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1911 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1912 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1913 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1914 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1915 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1916 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1917 #define PCI_VENDOR_ID_WCH 0x4348
1918 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1919 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1920 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1921 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1922 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1923 #define PCI_VENDOR_ID_AGESTAR 0x5372
1924 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1925 #define PCI_VENDOR_ID_ASIX 0x9710
1926 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1927 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1928 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1929 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1930 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1931 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1933 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1934 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1936 #define PCIE_VENDOR_ID_WCH 0x1c00
1937 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1938 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1940 #define PCI_VENDOR_ID_PERICOM 0x12D8
1941 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1942 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1943 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1944 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1946 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1947 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1948 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1951 * Master list of serial port init/setup/exit quirks.
1952 * This does not describe the general nature of the port.
1953 * (ie, baud base, number and location of ports, etc)
1955 * This list is ordered alphabetically by vendor then device.
1956 * Specific entries must come before more generic entries.
1958 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1960 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1963 .vendor = PCI_VENDOR_ID_AMCC,
1964 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1965 .subvendor = PCI_ANY_ID,
1966 .subdevice = PCI_ANY_ID,
1967 .setup = addidata_apci7800_setup,
1970 * AFAVLAB cards - these may be called via parport_serial
1971 * It is not clear whether this applies to all products.
1974 .vendor = PCI_VENDOR_ID_AFAVLAB,
1975 .device = PCI_ANY_ID,
1976 .subvendor = PCI_ANY_ID,
1977 .subdevice = PCI_ANY_ID,
1978 .setup = afavlab_setup,
1984 .vendor = PCI_VENDOR_ID_HP,
1985 .device = PCI_DEVICE_ID_HP_DIVA,
1986 .subvendor = PCI_ANY_ID,
1987 .subdevice = PCI_ANY_ID,
1988 .init = pci_hp_diva_init,
1989 .setup = pci_hp_diva_setup,
1995 .vendor = PCI_VENDOR_ID_INTEL,
1996 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1997 .subvendor = 0xe4bf,
1998 .subdevice = PCI_ANY_ID,
1999 .init = pci_inteli960ni_init,
2000 .setup = pci_default_setup,
2003 .vendor = PCI_VENDOR_ID_INTEL,
2004 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2005 .subvendor = PCI_ANY_ID,
2006 .subdevice = PCI_ANY_ID,
2007 .setup = skip_tx_en_setup,
2010 .vendor = PCI_VENDOR_ID_INTEL,
2011 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .setup = skip_tx_en_setup,
2017 .vendor = PCI_VENDOR_ID_INTEL,
2018 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2019 .subvendor = PCI_ANY_ID,
2020 .subdevice = PCI_ANY_ID,
2021 .setup = skip_tx_en_setup,
2024 .vendor = PCI_VENDOR_ID_INTEL,
2025 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2026 .subvendor = PCI_ANY_ID,
2027 .subdevice = PCI_ANY_ID,
2028 .setup = ce4100_serial_setup,
2031 .vendor = PCI_VENDOR_ID_INTEL,
2032 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2033 .subvendor = PCI_ANY_ID,
2034 .subdevice = PCI_ANY_ID,
2035 .setup = kt_serial_setup,
2038 .vendor = PCI_VENDOR_ID_INTEL,
2039 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2040 .subvendor = PCI_ANY_ID,
2041 .subdevice = PCI_ANY_ID,
2042 .setup = byt_serial_setup,
2045 .vendor = PCI_VENDOR_ID_INTEL,
2046 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2047 .subvendor = PCI_ANY_ID,
2048 .subdevice = PCI_ANY_ID,
2049 .setup = byt_serial_setup,
2052 .vendor = PCI_VENDOR_ID_INTEL,
2053 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2054 .subvendor = PCI_ANY_ID,
2055 .subdevice = PCI_ANY_ID,
2056 .setup = byt_serial_setup,
2059 .vendor = PCI_VENDOR_ID_INTEL,
2060 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2061 .subvendor = PCI_ANY_ID,
2062 .subdevice = PCI_ANY_ID,
2063 .setup = byt_serial_setup,
2069 .vendor = PCI_VENDOR_ID_ITE,
2070 .device = PCI_DEVICE_ID_ITE_8872,
2071 .subvendor = PCI_ANY_ID,
2072 .subdevice = PCI_ANY_ID,
2073 .init = pci_ite887x_init,
2074 .setup = pci_default_setup,
2075 .exit = pci_ite887x_exit,
2078 * National Instruments
2081 .vendor = PCI_VENDOR_ID_NI,
2082 .device = PCI_DEVICE_ID_NI_PCI23216,
2083 .subvendor = PCI_ANY_ID,
2084 .subdevice = PCI_ANY_ID,
2085 .init = pci_ni8420_init,
2086 .setup = pci_default_setup,
2087 .exit = pci_ni8420_exit,
2090 .vendor = PCI_VENDOR_ID_NI,
2091 .device = PCI_DEVICE_ID_NI_PCI2328,
2092 .subvendor = PCI_ANY_ID,
2093 .subdevice = PCI_ANY_ID,
2094 .init = pci_ni8420_init,
2095 .setup = pci_default_setup,
2096 .exit = pci_ni8420_exit,
2099 .vendor = PCI_VENDOR_ID_NI,
2100 .device = PCI_DEVICE_ID_NI_PCI2324,
2101 .subvendor = PCI_ANY_ID,
2102 .subdevice = PCI_ANY_ID,
2103 .init = pci_ni8420_init,
2104 .setup = pci_default_setup,
2105 .exit = pci_ni8420_exit,
2108 .vendor = PCI_VENDOR_ID_NI,
2109 .device = PCI_DEVICE_ID_NI_PCI2322,
2110 .subvendor = PCI_ANY_ID,
2111 .subdevice = PCI_ANY_ID,
2112 .init = pci_ni8420_init,
2113 .setup = pci_default_setup,
2114 .exit = pci_ni8420_exit,
2117 .vendor = PCI_VENDOR_ID_NI,
2118 .device = PCI_DEVICE_ID_NI_PCI2324I,
2119 .subvendor = PCI_ANY_ID,
2120 .subdevice = PCI_ANY_ID,
2121 .init = pci_ni8420_init,
2122 .setup = pci_default_setup,
2123 .exit = pci_ni8420_exit,
2126 .vendor = PCI_VENDOR_ID_NI,
2127 .device = PCI_DEVICE_ID_NI_PCI2322I,
2128 .subvendor = PCI_ANY_ID,
2129 .subdevice = PCI_ANY_ID,
2130 .init = pci_ni8420_init,
2131 .setup = pci_default_setup,
2132 .exit = pci_ni8420_exit,
2135 .vendor = PCI_VENDOR_ID_NI,
2136 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2137 .subvendor = PCI_ANY_ID,
2138 .subdevice = PCI_ANY_ID,
2139 .init = pci_ni8420_init,
2140 .setup = pci_default_setup,
2141 .exit = pci_ni8420_exit,
2144 .vendor = PCI_VENDOR_ID_NI,
2145 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2146 .subvendor = PCI_ANY_ID,
2147 .subdevice = PCI_ANY_ID,
2148 .init = pci_ni8420_init,
2149 .setup = pci_default_setup,
2150 .exit = pci_ni8420_exit,
2153 .vendor = PCI_VENDOR_ID_NI,
2154 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2155 .subvendor = PCI_ANY_ID,
2156 .subdevice = PCI_ANY_ID,
2157 .init = pci_ni8420_init,
2158 .setup = pci_default_setup,
2159 .exit = pci_ni8420_exit,
2162 .vendor = PCI_VENDOR_ID_NI,
2163 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2164 .subvendor = PCI_ANY_ID,
2165 .subdevice = PCI_ANY_ID,
2166 .init = pci_ni8420_init,
2167 .setup = pci_default_setup,
2168 .exit = pci_ni8420_exit,
2171 .vendor = PCI_VENDOR_ID_NI,
2172 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2173 .subvendor = PCI_ANY_ID,
2174 .subdevice = PCI_ANY_ID,
2175 .init = pci_ni8420_init,
2176 .setup = pci_default_setup,
2177 .exit = pci_ni8420_exit,
2180 .vendor = PCI_VENDOR_ID_NI,
2181 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2182 .subvendor = PCI_ANY_ID,
2183 .subdevice = PCI_ANY_ID,
2184 .init = pci_ni8420_init,
2185 .setup = pci_default_setup,
2186 .exit = pci_ni8420_exit,
2189 .vendor = PCI_VENDOR_ID_NI,
2190 .device = PCI_ANY_ID,
2191 .subvendor = PCI_ANY_ID,
2192 .subdevice = PCI_ANY_ID,
2193 .init = pci_ni8430_init,
2194 .setup = pci_ni8430_setup,
2195 .exit = pci_ni8430_exit,
2199 .vendor = PCI_VENDOR_ID_QUATECH,
2200 .device = PCI_ANY_ID,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .init = pci_quatech_init,
2204 .setup = pci_quatech_setup,
2205 .exit = pci_quatech_exit,
2211 .vendor = PCI_VENDOR_ID_PANACOM,
2212 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2213 .subvendor = PCI_ANY_ID,
2214 .subdevice = PCI_ANY_ID,
2215 .init = pci_plx9050_init,
2216 .setup = pci_default_setup,
2217 .exit = pci_plx9050_exit,
2220 .vendor = PCI_VENDOR_ID_PANACOM,
2221 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .init = pci_plx9050_init,
2225 .setup = pci_default_setup,
2226 .exit = pci_plx9050_exit,
2232 .vendor = PCI_VENDOR_ID_PERICOM,
2233 .device = PCI_ANY_ID,
2234 .subvendor = PCI_ANY_ID,
2235 .subdevice = PCI_ANY_ID,
2236 .setup = pci_pericom_setup,
2242 .vendor = PCI_VENDOR_ID_PLX,
2243 .device = PCI_DEVICE_ID_PLX_9050,
2244 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2245 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2246 .init = pci_plx9050_init,
2247 .setup = pci_default_setup,
2248 .exit = pci_plx9050_exit,
2251 .vendor = PCI_VENDOR_ID_PLX,
2252 .device = PCI_DEVICE_ID_PLX_9050,
2253 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2254 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2255 .init = pci_plx9050_init,
2256 .setup = pci_default_setup,
2257 .exit = pci_plx9050_exit,
2260 .vendor = PCI_VENDOR_ID_PLX,
2261 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2262 .subvendor = PCI_VENDOR_ID_PLX,
2263 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2264 .init = pci_plx9050_init,
2265 .setup = pci_default_setup,
2266 .exit = pci_plx9050_exit,
2269 * SBS Technologies, Inc., PMC-OCTALPRO 232
2272 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2273 .device = PCI_DEVICE_ID_OCTPRO,
2274 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2275 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2281 * SBS Technologies, Inc., PMC-OCTALPRO 422
2284 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2285 .device = PCI_DEVICE_ID_OCTPRO,
2286 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2287 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2293 * SBS Technologies, Inc., P-Octal 232
2296 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2297 .device = PCI_DEVICE_ID_OCTPRO,
2298 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2299 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2305 * SBS Technologies, Inc., P-Octal 422
2308 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2309 .device = PCI_DEVICE_ID_OCTPRO,
2310 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2311 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2317 * SIIG cards - these may be called via parport_serial
2320 .vendor = PCI_VENDOR_ID_SIIG,
2321 .device = PCI_ANY_ID,
2322 .subvendor = PCI_ANY_ID,
2323 .subdevice = PCI_ANY_ID,
2324 .init = pci_siig_init,
2325 .setup = pci_siig_setup,
2331 .vendor = PCI_VENDOR_ID_TITAN,
2332 .device = PCI_DEVICE_ID_TITAN_400L,
2333 .subvendor = PCI_ANY_ID,
2334 .subdevice = PCI_ANY_ID,
2335 .setup = titan_400l_800l_setup,
2338 .vendor = PCI_VENDOR_ID_TITAN,
2339 .device = PCI_DEVICE_ID_TITAN_800L,
2340 .subvendor = PCI_ANY_ID,
2341 .subdevice = PCI_ANY_ID,
2342 .setup = titan_400l_800l_setup,
2348 .vendor = PCI_VENDOR_ID_TIMEDIA,
2349 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2350 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2351 .subdevice = PCI_ANY_ID,
2352 .probe = pci_timedia_probe,
2353 .init = pci_timedia_init,
2354 .setup = pci_timedia_setup,
2357 .vendor = PCI_VENDOR_ID_TIMEDIA,
2358 .device = PCI_ANY_ID,
2359 .subvendor = PCI_ANY_ID,
2360 .subdevice = PCI_ANY_ID,
2361 .setup = pci_timedia_setup,
2364 * SUNIX (Timedia) cards
2365 * Do not "probe" for these cards as there is at least one combination
2366 * card that should be handled by parport_pc that doesn't match the
2367 * rule in pci_timedia_probe.
2368 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2369 * There are some boards with part number SER5037AL that report
2370 * subdevice ID 0x0002.
2373 .vendor = PCI_VENDOR_ID_SUNIX,
2374 .device = PCI_DEVICE_ID_SUNIX_1999,
2375 .subvendor = PCI_VENDOR_ID_SUNIX,
2376 .subdevice = PCI_ANY_ID,
2377 .init = pci_timedia_init,
2378 .setup = pci_timedia_setup,
2384 .vendor = PCI_VENDOR_ID_EXAR,
2385 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2386 .subvendor = PCI_ANY_ID,
2387 .subdevice = PCI_ANY_ID,
2388 .setup = pci_xr17c154_setup,
2391 .vendor = PCI_VENDOR_ID_EXAR,
2392 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2393 .subvendor = PCI_ANY_ID,
2394 .subdevice = PCI_ANY_ID,
2395 .setup = pci_xr17c154_setup,
2398 .vendor = PCI_VENDOR_ID_EXAR,
2399 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2400 .subvendor = PCI_ANY_ID,
2401 .subdevice = PCI_ANY_ID,
2402 .setup = pci_xr17c154_setup,
2405 .vendor = PCI_VENDOR_ID_EXAR,
2406 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .setup = pci_xr17v35x_setup,
2412 .vendor = PCI_VENDOR_ID_EXAR,
2413 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2414 .subvendor = PCI_ANY_ID,
2415 .subdevice = PCI_ANY_ID,
2416 .setup = pci_xr17v35x_setup,
2419 .vendor = PCI_VENDOR_ID_EXAR,
2420 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2421 .subvendor = PCI_ANY_ID,
2422 .subdevice = PCI_ANY_ID,
2423 .setup = pci_xr17v35x_setup,
2426 .vendor = PCI_VENDOR_ID_EXAR,
2427 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
2430 .setup = pci_xr17v35x_setup,
2433 .vendor = PCI_VENDOR_ID_EXAR,
2434 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2435 .subvendor = PCI_ANY_ID,
2436 .subdevice = PCI_ANY_ID,
2437 .setup = pci_xr17v35x_setup,
2443 .vendor = PCI_VENDOR_ID_XIRCOM,
2444 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2445 .subvendor = PCI_ANY_ID,
2446 .subdevice = PCI_ANY_ID,
2447 .init = pci_xircom_init,
2448 .setup = pci_default_setup,
2451 * Netmos cards - these may be called via parport_serial
2454 .vendor = PCI_VENDOR_ID_NETMOS,
2455 .device = PCI_ANY_ID,
2456 .subvendor = PCI_ANY_ID,
2457 .subdevice = PCI_ANY_ID,
2458 .init = pci_netmos_init,
2459 .setup = pci_netmos_9900_setup,
2462 * EndRun Technologies
2465 .vendor = PCI_VENDOR_ID_ENDRUN,
2466 .device = PCI_ANY_ID,
2467 .subvendor = PCI_ANY_ID,
2468 .subdevice = PCI_ANY_ID,
2469 .init = pci_endrun_init,
2470 .setup = pci_default_setup,
2473 * For Oxford Semiconductor Tornado based devices
2476 .vendor = PCI_VENDOR_ID_OXSEMI,
2477 .device = PCI_ANY_ID,
2478 .subvendor = PCI_ANY_ID,
2479 .subdevice = PCI_ANY_ID,
2480 .init = pci_oxsemi_tornado_init,
2481 .setup = pci_default_setup,
2484 .vendor = PCI_VENDOR_ID_MAINPINE,
2485 .device = PCI_ANY_ID,
2486 .subvendor = PCI_ANY_ID,
2487 .subdevice = PCI_ANY_ID,
2488 .init = pci_oxsemi_tornado_init,
2489 .setup = pci_default_setup,
2492 .vendor = PCI_VENDOR_ID_DIGI,
2493 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2494 .subvendor = PCI_SUBVENDOR_ID_IBM,
2495 .subdevice = PCI_ANY_ID,
2496 .init = pci_oxsemi_tornado_init,
2497 .setup = pci_default_setup,
2500 .vendor = PCI_VENDOR_ID_INTEL,
2502 .subvendor = PCI_ANY_ID,
2503 .subdevice = PCI_ANY_ID,
2504 .init = pci_eg20t_init,
2505 .setup = pci_default_setup,
2508 .vendor = PCI_VENDOR_ID_INTEL,
2510 .subvendor = PCI_ANY_ID,
2511 .subdevice = PCI_ANY_ID,
2512 .init = pci_eg20t_init,
2513 .setup = pci_default_setup,
2516 .vendor = PCI_VENDOR_ID_INTEL,
2518 .subvendor = PCI_ANY_ID,
2519 .subdevice = PCI_ANY_ID,
2520 .init = pci_eg20t_init,
2521 .setup = pci_default_setup,
2524 .vendor = PCI_VENDOR_ID_INTEL,
2526 .subvendor = PCI_ANY_ID,
2527 .subdevice = PCI_ANY_ID,
2528 .init = pci_eg20t_init,
2529 .setup = pci_default_setup,
2534 .subvendor = PCI_ANY_ID,
2535 .subdevice = PCI_ANY_ID,
2536 .init = pci_eg20t_init,
2537 .setup = pci_default_setup,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .init = pci_eg20t_init,
2545 .setup = pci_default_setup,
2550 .subvendor = PCI_ANY_ID,
2551 .subdevice = PCI_ANY_ID,
2552 .init = pci_eg20t_init,
2553 .setup = pci_default_setup,
2558 .subvendor = PCI_ANY_ID,
2559 .subdevice = PCI_ANY_ID,
2560 .init = pci_eg20t_init,
2561 .setup = pci_default_setup,
2566 .subvendor = PCI_ANY_ID,
2567 .subdevice = PCI_ANY_ID,
2568 .init = pci_eg20t_init,
2569 .setup = pci_default_setup,
2572 * Cronyx Omega PCI (PLX-chip based)
2575 .vendor = PCI_VENDOR_ID_PLX,
2576 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2577 .subvendor = PCI_ANY_ID,
2578 .subdevice = PCI_ANY_ID,
2579 .setup = pci_omegapci_setup,
2581 /* WCH CH353 1S1P card (16550 clone) */
2583 .vendor = PCI_VENDOR_ID_WCH,
2584 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2585 .subvendor = PCI_ANY_ID,
2586 .subdevice = PCI_ANY_ID,
2587 .setup = pci_wch_ch353_setup,
2589 /* WCH CH353 2S1P card (16550 clone) */
2591 .vendor = PCI_VENDOR_ID_WCH,
2592 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2593 .subvendor = PCI_ANY_ID,
2594 .subdevice = PCI_ANY_ID,
2595 .setup = pci_wch_ch353_setup,
2597 /* WCH CH353 4S card (16550 clone) */
2599 .vendor = PCI_VENDOR_ID_WCH,
2600 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2601 .subvendor = PCI_ANY_ID,
2602 .subdevice = PCI_ANY_ID,
2603 .setup = pci_wch_ch353_setup,
2605 /* WCH CH353 2S1PF card (16550 clone) */
2607 .vendor = PCI_VENDOR_ID_WCH,
2608 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2609 .subvendor = PCI_ANY_ID,
2610 .subdevice = PCI_ANY_ID,
2611 .setup = pci_wch_ch353_setup,
2613 /* WCH CH352 2S card (16550 clone) */
2615 .vendor = PCI_VENDOR_ID_WCH,
2616 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2617 .subvendor = PCI_ANY_ID,
2618 .subdevice = PCI_ANY_ID,
2619 .setup = pci_wch_ch353_setup,
2621 /* WCH CH382 2S1P card (16850 clone) */
2623 .vendor = PCIE_VENDOR_ID_WCH,
2624 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2625 .subvendor = PCI_ANY_ID,
2626 .subdevice = PCI_ANY_ID,
2627 .setup = pci_wch_ch38x_setup,
2629 /* WCH CH384 4S card (16850 clone) */
2631 .vendor = PCIE_VENDOR_ID_WCH,
2632 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2633 .subvendor = PCI_ANY_ID,
2634 .subdevice = PCI_ANY_ID,
2635 .setup = pci_wch_ch38x_setup,
2638 * ASIX devices with FIFO bug
2641 .vendor = PCI_VENDOR_ID_ASIX,
2642 .device = PCI_ANY_ID,
2643 .subvendor = PCI_ANY_ID,
2644 .subdevice = PCI_ANY_ID,
2645 .setup = pci_asix_setup,
2648 * Commtech, Inc. Fastcom adapters
2652 .vendor = PCI_VENDOR_ID_COMMTECH,
2653 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2654 .subvendor = PCI_ANY_ID,
2655 .subdevice = PCI_ANY_ID,
2656 .setup = pci_fastcom335_setup,
2659 .vendor = PCI_VENDOR_ID_COMMTECH,
2660 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2661 .subvendor = PCI_ANY_ID,
2662 .subdevice = PCI_ANY_ID,
2663 .setup = pci_fastcom335_setup,
2666 .vendor = PCI_VENDOR_ID_COMMTECH,
2667 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2668 .subvendor = PCI_ANY_ID,
2669 .subdevice = PCI_ANY_ID,
2670 .setup = pci_fastcom335_setup,
2673 .vendor = PCI_VENDOR_ID_COMMTECH,
2674 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2675 .subvendor = PCI_ANY_ID,
2676 .subdevice = PCI_ANY_ID,
2677 .setup = pci_fastcom335_setup,
2680 .vendor = PCI_VENDOR_ID_COMMTECH,
2681 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2682 .subvendor = PCI_ANY_ID,
2683 .subdevice = PCI_ANY_ID,
2684 .setup = pci_xr17v35x_setup,
2687 .vendor = PCI_VENDOR_ID_COMMTECH,
2688 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2689 .subvendor = PCI_ANY_ID,
2690 .subdevice = PCI_ANY_ID,
2691 .setup = pci_xr17v35x_setup,
2694 .vendor = PCI_VENDOR_ID_COMMTECH,
2695 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2696 .subvendor = PCI_ANY_ID,
2697 .subdevice = PCI_ANY_ID,
2698 .setup = pci_xr17v35x_setup,
2701 * Broadcom TruManage (NetXtreme)
2704 .vendor = PCI_VENDOR_ID_BROADCOM,
2705 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2706 .subvendor = PCI_ANY_ID,
2707 .subdevice = PCI_ANY_ID,
2708 .setup = pci_brcm_trumanage_setup,
2713 .subvendor = PCI_ANY_ID,
2714 .subdevice = PCI_ANY_ID,
2715 .setup = pci_fintek_setup,
2716 .init = pci_fintek_init,
2721 .subvendor = PCI_ANY_ID,
2722 .subdevice = PCI_ANY_ID,
2723 .setup = pci_fintek_setup,
2724 .init = pci_fintek_init,
2729 .subvendor = PCI_ANY_ID,
2730 .subdevice = PCI_ANY_ID,
2731 .setup = pci_fintek_setup,
2732 .init = pci_fintek_init,
2736 * Default "match everything" terminator entry
2739 .vendor = PCI_ANY_ID,
2740 .device = PCI_ANY_ID,
2741 .subvendor = PCI_ANY_ID,
2742 .subdevice = PCI_ANY_ID,
2743 .setup = pci_default_setup,
2747 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2749 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2752 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2754 struct pci_serial_quirk *quirk;
2756 for (quirk = pci_serial_quirks; ; quirk++)
2757 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2758 quirk_id_matches(quirk->device, dev->device) &&
2759 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2760 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2765 static inline int get_pci_irq(struct pci_dev *dev,
2766 const struct pciserial_board *board)
2768 if (board->flags & FL_NOIRQ)
2775 * This is the configuration table for all of the PCI serial boards
2776 * which we support. It is directly indexed by the pci_board_num_t enum
2777 * value, which is encoded in the pci_device_id PCI probe table's
2778 * driver_data member.
2780 * The makeup of these names are:
2781 * pbn_bn{_bt}_n_baud{_offsetinhex}
2783 * bn = PCI BAR number
2784 * bt = Index using PCI BARs
2785 * n = number of serial ports
2787 * offsetinhex = offset for each sequential port (in hex)
2789 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2791 * Please note: in theory if n = 1, _bt infix should make no difference.
2792 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2794 enum pci_board_num_t {
2811 pbn_b0_2_1152000_200,
2812 pbn_b0_4_1152000_200,
2813 pbn_b0_8_1152000_200,
2818 pbn_b0_2_1843200_200,
2819 pbn_b0_4_1843200_200,
2820 pbn_b0_8_1843200_200,
2894 * Board-specific versions.
2900 pbn_endrun_2_4000000,
2902 pbn_oxsemi_1_4000000,
2903 pbn_oxsemi_2_4000000,
2904 pbn_oxsemi_4_4000000,
2905 pbn_oxsemi_8_4000000,
2920 pbn_exar_ibm_saturn,
2926 pbn_ADDIDATA_PCIe_1_3906250,
2927 pbn_ADDIDATA_PCIe_2_3906250,
2928 pbn_ADDIDATA_PCIe_4_3906250,
2929 pbn_ADDIDATA_PCIe_8_3906250,
2930 pbn_ce4100_1_115200,
2934 pbn_NETMOS9900_2s_115200,
2940 pbn_pericom_PI7C9X7951,
2941 pbn_pericom_PI7C9X7952,
2942 pbn_pericom_PI7C9X7954,
2943 pbn_pericom_PI7C9X7958,
2947 * uart_offset - the space between channels
2948 * reg_shift - describes how the UART registers are mapped
2949 * to PCI memory by the card.
2950 * For example IER register on SBS, Inc. PMC-OctPro is located at
2951 * offset 0x10 from the UART base, while UART_IER is defined as 1
2952 * in include/linux/serial_reg.h,
2953 * see first lines of serial_in() and serial_out() in 8250.c
2956 static struct pciserial_board pci_boards[] = {
2960 .base_baud = 115200,
2963 [pbn_b0_1_115200] = {
2966 .base_baud = 115200,
2969 [pbn_b0_2_115200] = {
2972 .base_baud = 115200,
2975 [pbn_b0_4_115200] = {
2978 .base_baud = 115200,
2981 [pbn_b0_5_115200] = {
2984 .base_baud = 115200,
2987 [pbn_b0_8_115200] = {
2990 .base_baud = 115200,
2993 [pbn_b0_1_921600] = {
2996 .base_baud = 921600,
2999 [pbn_b0_2_921600] = {
3002 .base_baud = 921600,
3005 [pbn_b0_4_921600] = {
3008 .base_baud = 921600,
3012 [pbn_b0_2_1130000] = {
3015 .base_baud = 1130000,
3019 [pbn_b0_4_1152000] = {
3022 .base_baud = 1152000,
3026 [pbn_b0_2_1152000_200] = {
3029 .base_baud = 1152000,
3030 .uart_offset = 0x200,
3033 [pbn_b0_4_1152000_200] = {
3036 .base_baud = 1152000,
3037 .uart_offset = 0x200,
3040 [pbn_b0_8_1152000_200] = {
3043 .base_baud = 1152000,
3044 .uart_offset = 0x200,
3047 [pbn_b0_2_1843200] = {
3050 .base_baud = 1843200,
3053 [pbn_b0_4_1843200] = {
3056 .base_baud = 1843200,
3060 [pbn_b0_2_1843200_200] = {
3063 .base_baud = 1843200,
3064 .uart_offset = 0x200,
3066 [pbn_b0_4_1843200_200] = {
3069 .base_baud = 1843200,
3070 .uart_offset = 0x200,
3072 [pbn_b0_8_1843200_200] = {
3075 .base_baud = 1843200,
3076 .uart_offset = 0x200,
3078 [pbn_b0_1_4000000] = {
3081 .base_baud = 4000000,
3085 [pbn_b0_bt_1_115200] = {
3086 .flags = FL_BASE0|FL_BASE_BARS,
3088 .base_baud = 115200,
3091 [pbn_b0_bt_2_115200] = {
3092 .flags = FL_BASE0|FL_BASE_BARS,
3094 .base_baud = 115200,
3097 [pbn_b0_bt_4_115200] = {
3098 .flags = FL_BASE0|FL_BASE_BARS,
3100 .base_baud = 115200,
3103 [pbn_b0_bt_8_115200] = {
3104 .flags = FL_BASE0|FL_BASE_BARS,
3106 .base_baud = 115200,
3110 [pbn_b0_bt_1_460800] = {
3111 .flags = FL_BASE0|FL_BASE_BARS,
3113 .base_baud = 460800,
3116 [pbn_b0_bt_2_460800] = {
3117 .flags = FL_BASE0|FL_BASE_BARS,
3119 .base_baud = 460800,
3122 [pbn_b0_bt_4_460800] = {
3123 .flags = FL_BASE0|FL_BASE_BARS,
3125 .base_baud = 460800,
3129 [pbn_b0_bt_1_921600] = {
3130 .flags = FL_BASE0|FL_BASE_BARS,
3132 .base_baud = 921600,
3135 [pbn_b0_bt_2_921600] = {
3136 .flags = FL_BASE0|FL_BASE_BARS,
3138 .base_baud = 921600,
3141 [pbn_b0_bt_4_921600] = {
3142 .flags = FL_BASE0|FL_BASE_BARS,
3144 .base_baud = 921600,
3147 [pbn_b0_bt_8_921600] = {
3148 .flags = FL_BASE0|FL_BASE_BARS,
3150 .base_baud = 921600,
3154 [pbn_b1_1_115200] = {
3157 .base_baud = 115200,
3160 [pbn_b1_2_115200] = {
3163 .base_baud = 115200,
3166 [pbn_b1_4_115200] = {
3169 .base_baud = 115200,
3172 [pbn_b1_8_115200] = {
3175 .base_baud = 115200,
3178 [pbn_b1_16_115200] = {
3181 .base_baud = 115200,
3185 [pbn_b1_1_921600] = {
3188 .base_baud = 921600,
3191 [pbn_b1_2_921600] = {
3194 .base_baud = 921600,
3197 [pbn_b1_4_921600] = {
3200 .base_baud = 921600,
3203 [pbn_b1_8_921600] = {
3206 .base_baud = 921600,
3209 [pbn_b1_2_1250000] = {
3212 .base_baud = 1250000,
3216 [pbn_b1_bt_1_115200] = {
3217 .flags = FL_BASE1|FL_BASE_BARS,
3219 .base_baud = 115200,
3222 [pbn_b1_bt_2_115200] = {
3223 .flags = FL_BASE1|FL_BASE_BARS,
3225 .base_baud = 115200,
3228 [pbn_b1_bt_4_115200] = {
3229 .flags = FL_BASE1|FL_BASE_BARS,
3231 .base_baud = 115200,
3235 [pbn_b1_bt_2_921600] = {
3236 .flags = FL_BASE1|FL_BASE_BARS,
3238 .base_baud = 921600,
3242 [pbn_b1_1_1382400] = {
3245 .base_baud = 1382400,
3248 [pbn_b1_2_1382400] = {
3251 .base_baud = 1382400,
3254 [pbn_b1_4_1382400] = {
3257 .base_baud = 1382400,
3260 [pbn_b1_8_1382400] = {
3263 .base_baud = 1382400,
3267 [pbn_b2_1_115200] = {
3270 .base_baud = 115200,
3273 [pbn_b2_2_115200] = {
3276 .base_baud = 115200,
3279 [pbn_b2_4_115200] = {
3282 .base_baud = 115200,
3285 [pbn_b2_8_115200] = {
3288 .base_baud = 115200,
3292 [pbn_b2_1_460800] = {
3295 .base_baud = 460800,
3298 [pbn_b2_4_460800] = {
3301 .base_baud = 460800,
3304 [pbn_b2_8_460800] = {
3307 .base_baud = 460800,
3310 [pbn_b2_16_460800] = {
3313 .base_baud = 460800,
3317 [pbn_b2_1_921600] = {
3320 .base_baud = 921600,
3323 [pbn_b2_4_921600] = {
3326 .base_baud = 921600,
3329 [pbn_b2_8_921600] = {
3332 .base_baud = 921600,
3336 [pbn_b2_8_1152000] = {
3339 .base_baud = 1152000,
3343 [pbn_b2_bt_1_115200] = {
3344 .flags = FL_BASE2|FL_BASE_BARS,
3346 .base_baud = 115200,
3349 [pbn_b2_bt_2_115200] = {
3350 .flags = FL_BASE2|FL_BASE_BARS,
3352 .base_baud = 115200,
3355 [pbn_b2_bt_4_115200] = {
3356 .flags = FL_BASE2|FL_BASE_BARS,
3358 .base_baud = 115200,
3362 [pbn_b2_bt_2_921600] = {
3363 .flags = FL_BASE2|FL_BASE_BARS,
3365 .base_baud = 921600,
3368 [pbn_b2_bt_4_921600] = {
3369 .flags = FL_BASE2|FL_BASE_BARS,
3371 .base_baud = 921600,
3375 [pbn_b3_2_115200] = {
3378 .base_baud = 115200,
3381 [pbn_b3_4_115200] = {
3384 .base_baud = 115200,
3387 [pbn_b3_8_115200] = {
3390 .base_baud = 115200,
3394 [pbn_b4_bt_2_921600] = {
3397 .base_baud = 921600,
3400 [pbn_b4_bt_4_921600] = {
3403 .base_baud = 921600,
3406 [pbn_b4_bt_8_921600] = {
3409 .base_baud = 921600,
3414 * Entries following this are board-specific.
3423 .base_baud = 921600,
3424 .uart_offset = 0x400,
3428 .flags = FL_BASE2|FL_BASE_BARS,
3430 .base_baud = 921600,
3431 .uart_offset = 0x400,
3435 .flags = FL_BASE2|FL_BASE_BARS,
3437 .base_baud = 921600,
3438 .uart_offset = 0x400,
3442 /* I think this entry is broken - the first_offset looks wrong --rmk */
3443 [pbn_plx_romulus] = {
3446 .base_baud = 921600,
3447 .uart_offset = 8 << 2,
3449 .first_offset = 0x03,
3453 * EndRun Technologies
3454 * Uses the size of PCI Base region 0 to
3455 * signal now many ports are available
3456 * 2 port 952 Uart support
3458 [pbn_endrun_2_4000000] = {
3461 .base_baud = 4000000,
3462 .uart_offset = 0x200,
3463 .first_offset = 0x1000,
3467 * This board uses the size of PCI Base region 0 to
3468 * signal now many ports are available
3471 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3473 .base_baud = 115200,
3476 [pbn_oxsemi_1_4000000] = {
3479 .base_baud = 4000000,
3480 .uart_offset = 0x200,
3481 .first_offset = 0x1000,
3483 [pbn_oxsemi_2_4000000] = {
3486 .base_baud = 4000000,
3487 .uart_offset = 0x200,
3488 .first_offset = 0x1000,
3490 [pbn_oxsemi_4_4000000] = {
3493 .base_baud = 4000000,
3494 .uart_offset = 0x200,
3495 .first_offset = 0x1000,
3497 [pbn_oxsemi_8_4000000] = {
3500 .base_baud = 4000000,
3501 .uart_offset = 0x200,
3502 .first_offset = 0x1000,
3507 * EKF addition for i960 Boards form EKF with serial port.
3510 [pbn_intel_i960] = {
3513 .base_baud = 921600,
3514 .uart_offset = 8 << 2,
3516 .first_offset = 0x10000,
3519 .flags = FL_BASE0|FL_NOIRQ,
3521 .base_baud = 458333,
3524 .first_offset = 0x20178,
3528 * Computone - uses IOMEM.
3530 [pbn_computone_4] = {
3533 .base_baud = 921600,
3534 .uart_offset = 0x40,
3536 .first_offset = 0x200,
3538 [pbn_computone_6] = {
3541 .base_baud = 921600,
3542 .uart_offset = 0x40,
3544 .first_offset = 0x200,
3546 [pbn_computone_8] = {
3549 .base_baud = 921600,
3550 .uart_offset = 0x40,
3552 .first_offset = 0x200,
3557 .base_baud = 460800,
3562 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3563 * Only basic 16550A support.
3564 * XR17C15[24] are not tested, but they should work.
3566 [pbn_exar_XR17C152] = {
3569 .base_baud = 921600,
3570 .uart_offset = 0x200,
3572 [pbn_exar_XR17C154] = {
3575 .base_baud = 921600,
3576 .uart_offset = 0x200,
3578 [pbn_exar_XR17C158] = {
3581 .base_baud = 921600,
3582 .uart_offset = 0x200,
3584 [pbn_exar_XR17V352] = {
3587 .base_baud = 7812500,
3588 .uart_offset = 0x400,
3592 [pbn_exar_XR17V354] = {
3595 .base_baud = 7812500,
3596 .uart_offset = 0x400,
3600 [pbn_exar_XR17V358] = {
3603 .base_baud = 7812500,
3604 .uart_offset = 0x400,
3608 [pbn_exar_XR17V4358] = {
3611 .base_baud = 7812500,
3612 .uart_offset = 0x400,
3616 [pbn_exar_XR17V8358] = {
3619 .base_baud = 7812500,
3620 .uart_offset = 0x400,
3624 [pbn_exar_ibm_saturn] = {
3627 .base_baud = 921600,
3628 .uart_offset = 0x200,
3632 * PA Semi PWRficient PA6T-1682M on-chip UART
3634 [pbn_pasemi_1682M] = {
3637 .base_baud = 8333333,
3640 * National Instruments 843x
3645 .base_baud = 3686400,
3646 .uart_offset = 0x10,
3647 .first_offset = 0x800,
3652 .base_baud = 3686400,
3653 .uart_offset = 0x10,
3654 .first_offset = 0x800,
3659 .base_baud = 3686400,
3660 .uart_offset = 0x10,
3661 .first_offset = 0x800,
3666 .base_baud = 3686400,
3667 .uart_offset = 0x10,
3668 .first_offset = 0x800,
3671 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3673 [pbn_ADDIDATA_PCIe_1_3906250] = {
3676 .base_baud = 3906250,
3677 .uart_offset = 0x200,
3678 .first_offset = 0x1000,
3680 [pbn_ADDIDATA_PCIe_2_3906250] = {
3683 .base_baud = 3906250,
3684 .uart_offset = 0x200,
3685 .first_offset = 0x1000,
3687 [pbn_ADDIDATA_PCIe_4_3906250] = {
3690 .base_baud = 3906250,
3691 .uart_offset = 0x200,
3692 .first_offset = 0x1000,
3694 [pbn_ADDIDATA_PCIe_8_3906250] = {
3697 .base_baud = 3906250,
3698 .uart_offset = 0x200,
3699 .first_offset = 0x1000,
3701 [pbn_ce4100_1_115200] = {
3702 .flags = FL_BASE_BARS,
3704 .base_baud = 921600,
3708 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3709 * but is overridden by byt_set_termios.
3714 .base_baud = 2764800,
3715 .uart_offset = 0x80,
3721 .base_baud = 2764800,
3727 .base_baud = 115200,
3728 .uart_offset = 0x200,
3730 [pbn_NETMOS9900_2s_115200] = {
3733 .base_baud = 115200,
3735 [pbn_brcm_trumanage] = {
3739 .base_baud = 115200,
3744 .base_baud = 115200,
3745 .first_offset = 0x40,
3750 .base_baud = 115200,
3751 .first_offset = 0x40,
3756 .base_baud = 115200,
3757 .first_offset = 0x40,
3762 .base_baud = 115200,
3764 .first_offset = 0xC0,
3767 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3769 [pbn_pericom_PI7C9X7951] = {
3772 .base_baud = 921600,
3775 [pbn_pericom_PI7C9X7952] = {
3778 .base_baud = 921600,
3781 [pbn_pericom_PI7C9X7954] = {
3784 .base_baud = 921600,
3787 [pbn_pericom_PI7C9X7958] = {
3790 .base_baud = 921600,
3795 static const struct pci_device_id blacklist[] = {
3797 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3798 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3799 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3801 /* multi-io cards handled by parport_serial */
3802 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3803 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3804 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3805 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3807 /* Intel platforms with MID UART */
3808 { PCI_VDEVICE(INTEL, 0x081b), },
3809 { PCI_VDEVICE(INTEL, 0x081c), },
3810 { PCI_VDEVICE(INTEL, 0x081d), },
3811 { PCI_VDEVICE(INTEL, 0x1191), },
3812 { PCI_VDEVICE(INTEL, 0x19d8), },
3816 * Given a complete unknown PCI device, try to use some heuristics to
3817 * guess what the configuration might be, based on the pitiful PCI
3818 * serial specs. Returns 0 on success, 1 on failure.
3821 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3823 const struct pci_device_id *bldev;
3824 int num_iomem, num_port, first_port = -1, i;
3827 * If it is not a communications device or the programming
3828 * interface is greater than 6, give up.
3830 * (Should we try to make guesses for multiport serial devices
3833 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3834 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3835 (dev->class & 0xff) > 6)
3839 * Do not access blacklisted devices that are known not to
3840 * feature serial ports or are handled by other modules.
3842 for (bldev = blacklist;
3843 bldev < blacklist + ARRAY_SIZE(blacklist);
3845 if (dev->vendor == bldev->vendor &&
3846 dev->device == bldev->device)
3850 num_iomem = num_port = 0;
3851 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3852 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3854 if (first_port == -1)
3857 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3862 * If there is 1 or 0 iomem regions, and exactly one port,
3863 * use it. We guess the number of ports based on the IO
3866 if (num_iomem <= 1 && num_port == 1) {
3867 board->flags = first_port;
3868 board->num_ports = pci_resource_len(dev, first_port) / 8;
3873 * Now guess if we've got a board which indexes by BARs.
3874 * Each IO BAR should be 8 bytes, and they should follow
3879 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3880 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3881 pci_resource_len(dev, i) == 8 &&
3882 (first_port == -1 || (first_port + num_port) == i)) {
3884 if (first_port == -1)
3890 board->flags = first_port | FL_BASE_BARS;
3891 board->num_ports = num_port;
3899 serial_pci_matches(const struct pciserial_board *board,
3900 const struct pciserial_board *guessed)
3903 board->num_ports == guessed->num_ports &&
3904 board->base_baud == guessed->base_baud &&
3905 board->uart_offset == guessed->uart_offset &&
3906 board->reg_shift == guessed->reg_shift &&
3907 board->first_offset == guessed->first_offset;
3910 struct serial_private *
3911 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3913 struct uart_8250_port uart;
3914 struct serial_private *priv;
3915 struct pci_serial_quirk *quirk;
3916 int rc, nr_ports, i;
3918 nr_ports = board->num_ports;
3921 * Find an init and setup quirks.
3923 quirk = find_quirk(dev);
3926 * Run the new-style initialization function.
3927 * The initialization function returns:
3929 * 0 - use board->num_ports
3930 * >0 - number of ports
3933 rc = quirk->init(dev);
3942 priv = kzalloc(sizeof(struct serial_private) +
3943 sizeof(unsigned int) * nr_ports,
3946 priv = ERR_PTR(-ENOMEM);
3951 priv->quirk = quirk;
3953 memset(&uart, 0, sizeof(uart));
3954 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3955 uart.port.uartclk = board->base_baud * 16;
3956 uart.port.irq = get_pci_irq(dev, board);
3957 uart.port.dev = &dev->dev;
3959 for (i = 0; i < nr_ports; i++) {
3960 if (quirk->setup(priv, board, &uart, i))
3963 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3964 uart.port.iobase, uart.port.irq, uart.port.iotype);
3966 priv->line[i] = serial8250_register_8250_port(&uart);
3967 if (priv->line[i] < 0) {
3969 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3970 uart.port.iobase, uart.port.irq,
3971 uart.port.iotype, priv->line[i]);
3984 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3986 void pciserial_remove_ports(struct serial_private *priv)
3988 struct pci_serial_quirk *quirk;
3991 for (i = 0; i < priv->nr; i++)
3992 serial8250_unregister_port(priv->line[i]);
3994 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3995 if (priv->remapped_bar[i])
3996 iounmap(priv->remapped_bar[i]);
3997 priv->remapped_bar[i] = NULL;
4001 * Find the exit quirks.
4003 quirk = find_quirk(priv->dev);
4005 quirk->exit(priv->dev);
4009 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4011 void pciserial_suspend_ports(struct serial_private *priv)
4015 for (i = 0; i < priv->nr; i++)
4016 if (priv->line[i] >= 0)
4017 serial8250_suspend_port(priv->line[i]);
4020 * Ensure that every init quirk is properly torn down
4022 if (priv->quirk->exit)
4023 priv->quirk->exit(priv->dev);
4025 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4027 void pciserial_resume_ports(struct serial_private *priv)
4032 * Ensure that the board is correctly configured.
4034 if (priv->quirk->init)
4035 priv->quirk->init(priv->dev);
4037 for (i = 0; i < priv->nr; i++)
4038 if (priv->line[i] >= 0)
4039 serial8250_resume_port(priv->line[i]);
4041 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4044 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4045 * to the arrangement of serial ports on a PCI card.
4048 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4050 struct pci_serial_quirk *quirk;
4051 struct serial_private *priv;
4052 const struct pciserial_board *board;
4053 struct pciserial_board tmp;
4056 quirk = find_quirk(dev);
4058 rc = quirk->probe(dev);
4063 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4064 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4069 board = &pci_boards[ent->driver_data];
4071 rc = pci_enable_device(dev);
4072 pci_save_state(dev);
4076 if (ent->driver_data == pbn_default) {
4078 * Use a copy of the pci_board entry for this;
4079 * avoid changing entries in the table.
4081 memcpy(&tmp, board, sizeof(struct pciserial_board));
4085 * We matched one of our class entries. Try to
4086 * determine the parameters of this board.
4088 rc = serial_pci_guess_board(dev, &tmp);
4093 * We matched an explicit entry. If we are able to
4094 * detect this boards settings with our heuristic,
4095 * then we no longer need this entry.
4097 memcpy(&tmp, &pci_boards[pbn_default],
4098 sizeof(struct pciserial_board));
4099 rc = serial_pci_guess_board(dev, &tmp);
4100 if (rc == 0 && serial_pci_matches(board, &tmp))
4101 moan_device("Redundant entry in serial pci_table.",
4105 priv = pciserial_init_ports(dev, board);
4106 if (!IS_ERR(priv)) {
4107 pci_set_drvdata(dev, priv);
4114 pci_disable_device(dev);
4118 static void pciserial_remove_one(struct pci_dev *dev)
4120 struct serial_private *priv = pci_get_drvdata(dev);
4122 pciserial_remove_ports(priv);
4124 pci_disable_device(dev);
4127 #ifdef CONFIG_PM_SLEEP
4128 static int pciserial_suspend_one(struct device *dev)
4130 struct pci_dev *pdev = to_pci_dev(dev);
4131 struct serial_private *priv = pci_get_drvdata(pdev);
4134 pciserial_suspend_ports(priv);
4139 static int pciserial_resume_one(struct device *dev)
4141 struct pci_dev *pdev = to_pci_dev(dev);
4142 struct serial_private *priv = pci_get_drvdata(pdev);
4147 * The device may have been disabled. Re-enable it.
4149 err = pci_enable_device(pdev);
4150 /* FIXME: We cannot simply error out here */
4152 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4153 pciserial_resume_ports(priv);
4159 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4160 pciserial_resume_one);
4162 static struct pci_device_id serial_pci_tbl[] = {
4163 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4164 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4165 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4167 /* Advantech also use 0x3618 and 0xf618 */
4168 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4169 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4171 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4172 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4174 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4175 PCI_SUBVENDOR_ID_CONNECT_TECH,
4176 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4178 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4179 PCI_SUBVENDOR_ID_CONNECT_TECH,
4180 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4182 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4183 PCI_SUBVENDOR_ID_CONNECT_TECH,
4184 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4186 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4187 PCI_SUBVENDOR_ID_CONNECT_TECH,
4188 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4190 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4191 PCI_SUBVENDOR_ID_CONNECT_TECH,
4192 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4194 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4195 PCI_SUBVENDOR_ID_CONNECT_TECH,
4196 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4198 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4199 PCI_SUBVENDOR_ID_CONNECT_TECH,
4200 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4202 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4203 PCI_SUBVENDOR_ID_CONNECT_TECH,
4204 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4206 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4207 PCI_SUBVENDOR_ID_CONNECT_TECH,
4208 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4210 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4211 PCI_SUBVENDOR_ID_CONNECT_TECH,
4212 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4214 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4215 PCI_SUBVENDOR_ID_CONNECT_TECH,
4216 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4218 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4219 PCI_SUBVENDOR_ID_CONNECT_TECH,
4220 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4222 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4223 PCI_SUBVENDOR_ID_CONNECT_TECH,
4224 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4226 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4227 PCI_SUBVENDOR_ID_CONNECT_TECH,
4228 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4230 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4231 PCI_SUBVENDOR_ID_CONNECT_TECH,
4232 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4234 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4235 PCI_SUBVENDOR_ID_CONNECT_TECH,
4236 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4238 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4239 PCI_SUBVENDOR_ID_CONNECT_TECH,
4240 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4242 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4243 PCI_VENDOR_ID_AFAVLAB,
4244 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4246 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4247 PCI_SUBVENDOR_ID_CONNECT_TECH,
4248 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4249 pbn_b0_2_1843200_200 },
4250 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4251 PCI_SUBVENDOR_ID_CONNECT_TECH,
4252 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4253 pbn_b0_4_1843200_200 },
4254 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4255 PCI_SUBVENDOR_ID_CONNECT_TECH,
4256 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4257 pbn_b0_8_1843200_200 },
4258 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4259 PCI_SUBVENDOR_ID_CONNECT_TECH,
4260 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4261 pbn_b0_2_1843200_200 },
4262 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4263 PCI_SUBVENDOR_ID_CONNECT_TECH,
4264 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4265 pbn_b0_4_1843200_200 },
4266 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4267 PCI_SUBVENDOR_ID_CONNECT_TECH,
4268 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4269 pbn_b0_8_1843200_200 },
4270 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4271 PCI_SUBVENDOR_ID_CONNECT_TECH,
4272 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4273 pbn_b0_2_1843200_200 },
4274 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4275 PCI_SUBVENDOR_ID_CONNECT_TECH,
4276 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4277 pbn_b0_4_1843200_200 },
4278 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4279 PCI_SUBVENDOR_ID_CONNECT_TECH,
4280 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4281 pbn_b0_8_1843200_200 },
4282 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4283 PCI_SUBVENDOR_ID_CONNECT_TECH,
4284 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4285 pbn_b0_2_1843200_200 },
4286 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4287 PCI_SUBVENDOR_ID_CONNECT_TECH,
4288 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4289 pbn_b0_4_1843200_200 },
4290 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4291 PCI_SUBVENDOR_ID_CONNECT_TECH,
4292 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4293 pbn_b0_8_1843200_200 },
4294 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4295 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4296 0, 0, pbn_exar_ibm_saturn },
4298 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300 pbn_b2_bt_1_115200 },
4301 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_b2_bt_2_115200 },
4304 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_b2_bt_4_115200 },
4307 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_b2_bt_2_115200 },
4310 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_b2_bt_4_115200 },
4313 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4323 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325 pbn_b2_bt_2_115200 },
4326 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 pbn_b2_bt_2_921600 },
4330 * VScom SPCOM800, from sl@s.pl
4332 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338 /* Unknown card - subdevice 0x1584 */
4339 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4341 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4343 /* Unknown card - subdevice 0x1588 */
4344 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4346 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4348 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4349 PCI_SUBVENDOR_ID_KEYSPAN,
4350 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4352 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4358 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4359 PCI_VENDOR_ID_ESDGMBH,
4360 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4362 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4363 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4364 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4366 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4367 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4368 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4370 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4371 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4372 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4374 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4375 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4376 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4378 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4379 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4380 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4382 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4383 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4384 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4386 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4387 PCI_SUBVENDOR_ID_EXSYS,
4388 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4391 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4394 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4395 0x10b5, 0x106a, 0, 0,
4398 * EndRun Technologies. PCI express device range.
4399 * EndRun PTP/1588 has 2 Native UARTs.
4401 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_endrun_2_4000000 },
4405 * Quatech cards. These actually have configurable clocks but for
4406 * now we just use the default.
4408 * 100 series are RS232, 200 series RS422,
4410 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4469 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4472 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4473 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4476 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_b0_bt_2_921600 },
4481 * The below card is a little controversial since it is the
4482 * subject of a PCI vendor/device ID clash. (See
4483 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4484 * For now just used the hex ID 0x950a.
4486 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4487 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4488 0, 0, pbn_b0_2_115200 },
4489 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4490 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4491 0, 0, pbn_b0_2_115200 },
4492 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4496 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4498 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b0_bt_2_921600 },
4504 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4505 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4509 * Oxford Semiconductor Inc. Tornado PCI express device range.
4511 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 pbn_oxsemi_1_4000000 },
4520 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 pbn_oxsemi_1_4000000 },
4523 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 pbn_oxsemi_1_4000000 },
4532 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 pbn_oxsemi_1_4000000 },
4535 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 pbn_oxsemi_2_4000000 },
4550 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552 pbn_oxsemi_2_4000000 },
4553 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555 pbn_oxsemi_4_4000000 },
4556 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558 pbn_oxsemi_4_4000000 },
4559 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4561 pbn_oxsemi_8_4000000 },
4562 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564 pbn_oxsemi_8_4000000 },
4565 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567 pbn_oxsemi_1_4000000 },
4568 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570 pbn_oxsemi_1_4000000 },
4571 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573 pbn_oxsemi_1_4000000 },
4574 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576 pbn_oxsemi_1_4000000 },
4577 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579 pbn_oxsemi_1_4000000 },
4580 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582 pbn_oxsemi_1_4000000 },
4583 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585 pbn_oxsemi_1_4000000 },
4586 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588 pbn_oxsemi_1_4000000 },
4589 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591 pbn_oxsemi_1_4000000 },
4592 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594 pbn_oxsemi_1_4000000 },
4595 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597 pbn_oxsemi_1_4000000 },
4598 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_oxsemi_1_4000000 },
4601 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_oxsemi_1_4000000 },
4604 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606 pbn_oxsemi_1_4000000 },
4607 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 pbn_oxsemi_1_4000000 },
4610 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_oxsemi_1_4000000 },
4613 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_oxsemi_1_4000000 },
4616 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_oxsemi_1_4000000 },
4619 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_oxsemi_1_4000000 },
4622 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_oxsemi_1_4000000 },
4625 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_oxsemi_1_4000000 },
4628 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_oxsemi_1_4000000 },
4631 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_oxsemi_1_4000000 },
4634 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_oxsemi_1_4000000 },
4637 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_oxsemi_1_4000000 },
4640 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_oxsemi_1_4000000 },
4644 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4646 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4647 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4648 pbn_oxsemi_1_4000000 },
4649 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4650 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4651 pbn_oxsemi_2_4000000 },
4652 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4653 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4654 pbn_oxsemi_4_4000000 },
4655 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4656 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4657 pbn_oxsemi_8_4000000 },
4660 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4662 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4663 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4664 pbn_oxsemi_2_4000000 },
4667 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4668 * from skokodyn@yahoo.com
4670 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4671 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4673 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4674 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4676 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4677 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4679 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4680 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4684 * Digitan DS560-558, from jimd@esoft.com
4686 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 * Titan Electronic cards
4692 * The 400L and 800L have a custom setup quirk.
4694 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_b1_bt_2_921600 },
4712 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_b0_bt_4_921600 },
4715 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_b0_bt_8_921600 },
4718 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_b4_bt_2_921600 },
4721 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_b4_bt_4_921600 },
4724 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_b4_bt_8_921600 },
4727 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_oxsemi_1_4000000 },
4739 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_oxsemi_2_4000000 },
4742 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 pbn_oxsemi_4_4000000 },
4745 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 pbn_oxsemi_8_4000000 },
4748 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_oxsemi_2_4000000 },
4751 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 pbn_oxsemi_2_4000000 },
4754 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_b0_bt_2_921600 },
4757 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_b2_bt_2_921600 },
4782 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_b2_bt_2_921600 },
4785 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_b2_bt_2_921600 },
4788 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_b2_bt_4_921600 },
4791 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_b2_bt_4_921600 },
4794 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_b2_bt_4_921600 },
4797 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_b0_bt_2_921600 },
4809 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_b0_bt_2_921600 },
4812 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_b0_bt_2_921600 },
4815 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_b0_bt_4_921600 },
4818 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_b0_bt_4_921600 },
4821 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 pbn_b0_bt_4_921600 },
4824 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 pbn_b0_bt_8_921600 },
4827 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829 pbn_b0_bt_8_921600 },
4830 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 pbn_b0_bt_8_921600 },
4835 * Computone devices submitted by Doug McNash dmcnash@computone.com
4837 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4838 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4839 0, 0, pbn_computone_4 },
4840 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4841 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4842 0, 0, pbn_computone_8 },
4843 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4844 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4845 0, 0, pbn_computone_6 },
4847 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4850 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4851 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4852 pbn_b0_bt_1_921600 },
4857 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4858 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4859 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4860 pbn_b0_bt_1_921600 },
4862 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4863 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4864 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4865 pbn_b0_bt_1_921600 },
4868 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4870 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_b0_bt_8_115200 },
4873 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 pbn_b0_bt_8_115200 },
4877 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_b0_bt_2_115200 },
4880 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 pbn_b0_bt_2_115200 },
4883 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 pbn_b0_bt_2_115200 },
4886 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 pbn_b0_bt_2_115200 },
4889 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b0_bt_2_115200 },
4892 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_b0_bt_4_460800 },
4895 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 pbn_b0_bt_4_460800 },
4898 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 pbn_b0_bt_2_460800 },
4901 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 pbn_b0_bt_2_460800 },
4904 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 pbn_b0_bt_2_460800 },
4907 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 pbn_b0_bt_1_115200 },
4910 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 pbn_b0_bt_1_460800 },
4915 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4916 * Cards are identified by their subsystem vendor IDs, which
4917 * (in hex) match the model number.
4919 * Note that JC140x are RS422/485 cards which require ox950
4920 * ACR = 0x10, and as such are not currently fully supported.
4922 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4923 0x1204, 0x0004, 0, 0,
4925 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4926 0x1208, 0x0004, 0, 0,
4928 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4929 0x1402, 0x0002, 0, 0,
4930 pbn_b0_2_921600 }, */
4931 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4932 0x1404, 0x0004, 0, 0,
4933 pbn_b0_4_921600 }, */
4934 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4935 0x1208, 0x0004, 0, 0,
4938 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4939 0x1204, 0x0004, 0, 0,
4941 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4942 0x1208, 0x0004, 0, 0,
4944 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4945 0x1208, 0x0004, 0, 0,
4948 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4950 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4955 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4957 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 * RAStel 2 port modem, gerg@moreton.com.au
4964 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 pbn_b2_bt_2_115200 },
4969 * EKF addition for i960 Boards form EKF with serial port
4971 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4972 0xE4BF, PCI_ANY_ID, 0, 0,
4976 * Xircom Cardbus/Ethernet combos
4978 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4982 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4984 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 * Untested PCI modems, sent in from various folks...
4993 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4995 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4996 0x1048, 0x1500, 0, 0,
4999 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5006 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5007 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5009 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5019 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5022 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5029 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5030 PCI_ANY_ID, PCI_ANY_ID,
5032 0, pbn_exar_XR17C152 },
5033 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5034 PCI_ANY_ID, PCI_ANY_ID,
5036 0, pbn_exar_XR17C154 },
5037 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5038 PCI_ANY_ID, PCI_ANY_ID,
5040 0, pbn_exar_XR17C158 },
5042 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5044 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5045 PCI_ANY_ID, PCI_ANY_ID,
5047 0, pbn_exar_XR17V352 },
5048 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5049 PCI_ANY_ID, PCI_ANY_ID,
5051 0, pbn_exar_XR17V354 },
5052 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5053 PCI_ANY_ID, PCI_ANY_ID,
5055 0, pbn_exar_XR17V358 },
5056 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5057 PCI_ANY_ID, PCI_ANY_ID,
5059 0, pbn_exar_XR17V4358 },
5060 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5061 PCI_ANY_ID, PCI_ANY_ID,
5063 0, pbn_exar_XR17V8358 },
5065 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5067 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5068 PCI_ANY_ID, PCI_ANY_ID,
5070 0, pbn_pericom_PI7C9X7951 },
5071 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5072 PCI_ANY_ID, PCI_ANY_ID,
5074 0, pbn_pericom_PI7C9X7952 },
5075 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5076 PCI_ANY_ID, PCI_ANY_ID,
5078 0, pbn_pericom_PI7C9X7954 },
5079 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5080 PCI_ANY_ID, PCI_ANY_ID,
5082 0, pbn_pericom_PI7C9X7958 },
5084 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5086 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5093 PCI_ANY_ID, PCI_ANY_ID,
5095 pbn_b1_bt_1_115200 },
5100 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5106 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5110 * Perle PCI-RAS cards
5112 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5113 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5114 0, 0, pbn_b2_4_921600 },
5115 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5116 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5117 0, 0, pbn_b2_8_921600 },
5120 * Mainpine series cards: Fairly standard layout but fools
5121 * parts of the autodetect in some cases and uses otherwise
5122 * unmatched communications subclasses in the PCI Express case
5125 { /* RockForceDUO */
5126 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5127 PCI_VENDOR_ID_MAINPINE, 0x0200,
5128 0, 0, pbn_b0_2_115200 },
5129 { /* RockForceQUATRO */
5130 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5131 PCI_VENDOR_ID_MAINPINE, 0x0300,
5132 0, 0, pbn_b0_4_115200 },
5133 { /* RockForceDUO+ */
5134 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5135 PCI_VENDOR_ID_MAINPINE, 0x0400,
5136 0, 0, pbn_b0_2_115200 },
5137 { /* RockForceQUATRO+ */
5138 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5139 PCI_VENDOR_ID_MAINPINE, 0x0500,
5140 0, 0, pbn_b0_4_115200 },
5142 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5143 PCI_VENDOR_ID_MAINPINE, 0x0600,
5144 0, 0, pbn_b0_2_115200 },
5146 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5147 PCI_VENDOR_ID_MAINPINE, 0x0700,
5148 0, 0, pbn_b0_4_115200 },
5149 { /* RockForceOCTO+ */
5150 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5151 PCI_VENDOR_ID_MAINPINE, 0x0800,
5152 0, 0, pbn_b0_8_115200 },
5153 { /* RockForceDUO+ */
5154 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5155 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5156 0, 0, pbn_b0_2_115200 },
5157 { /* RockForceQUARTRO+ */
5158 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5159 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5160 0, 0, pbn_b0_4_115200 },
5161 { /* RockForceOCTO+ */
5162 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5163 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5164 0, 0, pbn_b0_8_115200 },
5166 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5167 PCI_VENDOR_ID_MAINPINE, 0x2000,
5168 0, 0, pbn_b0_1_115200 },
5170 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5171 PCI_VENDOR_ID_MAINPINE, 0x2100,
5172 0, 0, pbn_b0_1_115200 },
5174 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5175 PCI_VENDOR_ID_MAINPINE, 0x2200,
5176 0, 0, pbn_b0_2_115200 },
5178 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5179 PCI_VENDOR_ID_MAINPINE, 0x2300,
5180 0, 0, pbn_b0_2_115200 },
5182 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5183 PCI_VENDOR_ID_MAINPINE, 0x2400,
5184 0, 0, pbn_b0_4_115200 },
5186 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5187 PCI_VENDOR_ID_MAINPINE, 0x2500,
5188 0, 0, pbn_b0_4_115200 },
5190 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5191 PCI_VENDOR_ID_MAINPINE, 0x2600,
5192 0, 0, pbn_b0_8_115200 },
5194 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5195 PCI_VENDOR_ID_MAINPINE, 0x2700,
5196 0, 0, pbn_b0_8_115200 },
5197 { /* IQ Express D1 */
5198 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5199 PCI_VENDOR_ID_MAINPINE, 0x3000,
5200 0, 0, pbn_b0_1_115200 },
5201 { /* IQ Express F1 */
5202 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5203 PCI_VENDOR_ID_MAINPINE, 0x3100,
5204 0, 0, pbn_b0_1_115200 },
5205 { /* IQ Express D2 */
5206 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5207 PCI_VENDOR_ID_MAINPINE, 0x3200,
5208 0, 0, pbn_b0_2_115200 },
5209 { /* IQ Express F2 */
5210 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5211 PCI_VENDOR_ID_MAINPINE, 0x3300,
5212 0, 0, pbn_b0_2_115200 },
5213 { /* IQ Express D4 */
5214 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5215 PCI_VENDOR_ID_MAINPINE, 0x3400,
5216 0, 0, pbn_b0_4_115200 },
5217 { /* IQ Express F4 */
5218 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5219 PCI_VENDOR_ID_MAINPINE, 0x3500,
5220 0, 0, pbn_b0_4_115200 },
5221 { /* IQ Express D8 */
5222 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5223 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5224 0, 0, pbn_b0_8_115200 },
5225 { /* IQ Express F8 */
5226 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5227 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5228 0, 0, pbn_b0_8_115200 },
5232 * PA Semi PA6T-1682M on-chip UART
5234 { PCI_VENDOR_ID_PASEMI, 0xa004,
5235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5239 * National Instruments
5241 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5244 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5247 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5249 pbn_b1_bt_4_115200 },
5250 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5252 pbn_b1_bt_2_115200 },
5253 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5255 pbn_b1_bt_4_115200 },
5256 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5258 pbn_b1_bt_2_115200 },
5259 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5262 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5265 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267 pbn_b1_bt_4_115200 },
5268 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270 pbn_b1_bt_2_115200 },
5271 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5273 pbn_b1_bt_4_115200 },
5274 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5276 pbn_b1_bt_2_115200 },
5277 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5280 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5283 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5286 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5289 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5292 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5295 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5298 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5301 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5304 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5307 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5310 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5315 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5317 { PCI_VENDOR_ID_ADDIDATA,
5318 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5325 { PCI_VENDOR_ID_ADDIDATA,
5326 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5333 { PCI_VENDOR_ID_ADDIDATA,
5334 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5341 { PCI_VENDOR_ID_AMCC,
5342 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5349 { PCI_VENDOR_ID_ADDIDATA,
5350 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5357 { PCI_VENDOR_ID_ADDIDATA,
5358 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5365 { PCI_VENDOR_ID_ADDIDATA,
5366 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5373 { PCI_VENDOR_ID_ADDIDATA,
5374 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5381 { PCI_VENDOR_ID_ADDIDATA,
5382 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5389 { PCI_VENDOR_ID_ADDIDATA,
5390 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5397 { PCI_VENDOR_ID_ADDIDATA,
5398 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5405 { PCI_VENDOR_ID_ADDIDATA,
5406 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5411 pbn_ADDIDATA_PCIe_4_3906250 },
5413 { PCI_VENDOR_ID_ADDIDATA,
5414 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5419 pbn_ADDIDATA_PCIe_2_3906250 },
5421 { PCI_VENDOR_ID_ADDIDATA,
5422 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5427 pbn_ADDIDATA_PCIe_1_3906250 },
5429 { PCI_VENDOR_ID_ADDIDATA,
5430 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5435 pbn_ADDIDATA_PCIe_8_3906250 },
5437 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5438 PCI_VENDOR_ID_IBM, 0x0299,
5439 0, 0, pbn_b0_bt_2_115200 },
5442 * other NetMos 9835 devices are most likely handled by the
5443 * parport_serial driver, check drivers/parport/parport_serial.c
5444 * before adding them here.
5447 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5449 0, 0, pbn_b0_1_115200 },
5451 /* the 9901 is a rebranded 9912 */
5452 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5454 0, 0, pbn_b0_1_115200 },
5456 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5458 0, 0, pbn_b0_1_115200 },
5460 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5462 0, 0, pbn_b0_1_115200 },
5464 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5466 0, 0, pbn_b0_1_115200 },
5468 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5470 0, 0, pbn_NETMOS9900_2s_115200 },
5473 * Best Connectivity and Rosewill PCI Multi I/O cards
5476 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5478 0, 0, pbn_b0_1_115200 },
5480 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5482 0, 0, pbn_b0_bt_2_115200 },
5484 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5486 0, 0, pbn_b0_bt_4_115200 },
5488 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5490 pbn_ce4100_1_115200 },
5491 /* Intel BayTrail */
5492 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5493 PCI_ANY_ID, PCI_ANY_ID,
5494 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5496 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5497 PCI_ANY_ID, PCI_ANY_ID,
5498 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5500 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5501 PCI_ANY_ID, PCI_ANY_ID,
5502 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5504 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5505 PCI_ANY_ID, PCI_ANY_ID,
5506 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5512 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5518 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5523 * Broadcom TruManage
5525 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5527 pbn_brcm_trumanage },
5530 * AgeStar as-prs2-009
5532 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5533 PCI_ANY_ID, PCI_ANY_ID,
5534 0, 0, pbn_b0_bt_2_115200 },
5537 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5538 * so not listed here.
5540 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5541 PCI_ANY_ID, PCI_ANY_ID,
5542 0, 0, pbn_b0_bt_4_115200 },
5544 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5545 PCI_ANY_ID, PCI_ANY_ID,
5546 0, 0, pbn_b0_bt_2_115200 },
5548 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5549 PCI_ANY_ID, PCI_ANY_ID,
5550 0, 0, pbn_wch384_4 },
5553 * Commtech, Inc. Fastcom adapters
5555 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5556 PCI_ANY_ID, PCI_ANY_ID,
5558 0, pbn_b0_2_1152000_200 },
5559 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5560 PCI_ANY_ID, PCI_ANY_ID,
5562 0, pbn_b0_4_1152000_200 },
5563 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5564 PCI_ANY_ID, PCI_ANY_ID,
5566 0, pbn_b0_4_1152000_200 },
5567 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5568 PCI_ANY_ID, PCI_ANY_ID,
5570 0, pbn_b0_8_1152000_200 },
5571 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5572 PCI_ANY_ID, PCI_ANY_ID,
5574 0, pbn_exar_XR17V352 },
5575 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5576 PCI_ANY_ID, PCI_ANY_ID,
5578 0, pbn_exar_XR17V354 },
5579 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5580 PCI_ANY_ID, PCI_ANY_ID,
5582 0, pbn_exar_XR17V358 },
5584 /* Fintek PCI serial cards */
5585 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5586 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5587 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5590 * These entries match devices with class COMMUNICATION_SERIAL,
5591 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5593 { PCI_ANY_ID, PCI_ANY_ID,
5594 PCI_ANY_ID, PCI_ANY_ID,
5595 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5596 0xffff00, pbn_default },
5597 { PCI_ANY_ID, PCI_ANY_ID,
5598 PCI_ANY_ID, PCI_ANY_ID,
5599 PCI_CLASS_COMMUNICATION_MODEM << 8,
5600 0xffff00, pbn_default },
5601 { PCI_ANY_ID, PCI_ANY_ID,
5602 PCI_ANY_ID, PCI_ANY_ID,
5603 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5604 0xffff00, pbn_default },
5608 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5609 pci_channel_state_t state)
5611 struct serial_private *priv = pci_get_drvdata(dev);
5613 if (state == pci_channel_io_perm_failure)
5614 return PCI_ERS_RESULT_DISCONNECT;
5617 pciserial_suspend_ports(priv);
5619 pci_disable_device(dev);
5621 return PCI_ERS_RESULT_NEED_RESET;
5624 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5628 rc = pci_enable_device(dev);
5631 return PCI_ERS_RESULT_DISCONNECT;
5633 pci_restore_state(dev);
5634 pci_save_state(dev);
5636 return PCI_ERS_RESULT_RECOVERED;
5639 static void serial8250_io_resume(struct pci_dev *dev)
5641 struct serial_private *priv = pci_get_drvdata(dev);
5644 pciserial_resume_ports(priv);
5647 static const struct pci_error_handlers serial8250_err_handler = {
5648 .error_detected = serial8250_io_error_detected,
5649 .slot_reset = serial8250_io_slot_reset,
5650 .resume = serial8250_io_resume,
5653 static struct pci_driver serial_pci_driver = {
5655 .probe = pciserial_init_one,
5656 .remove = pciserial_remove_one,
5658 .pm = &pciserial_pm_ops,
5660 .id_table = serial_pci_tbl,
5661 .err_handler = &serial8250_err_handler,
5664 module_pci_driver(serial_pci_driver);
5666 MODULE_LICENSE("GPL");
5667 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5668 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);