drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24
  25 #include <asm/byteorder.h>
  26 #include <asm/io.h>
  27
  28 #include <linux/dmaengine.h>
  29 #include <linux/platform_data/dma-dw.h>
  30
  31 #include "8250.h"
  32
  33 /*
  34  * init function returns:
  35  *  > 0 - number of ports
  36  *  = 0 - use board->num_ports
  37  *  < 0 - error
  38  */
  39 struct pci_serial_quirk {
  40         u32     vendor;
  41         u32     device;
  42         u32     subvendor;
  43         u32     subdevice;
  44         int     (*probe)(struct pci_dev *dev);
  45         int     (*init)(struct pci_dev *dev);
  46         int     (*setup)(struct serial_private *,
  47                          const struct pciserial_board *,
  48                          struct uart_8250_port *, int);
  49         void    (*exit)(struct pci_dev *dev);
  50 };
  51
  52 #define PCI_NUM_BAR_RESOURCES   6
  53
  54 struct serial_private {
  55         struct pci_dev          *dev;
  56         unsigned int            nr;
  57         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  58         struct pci_serial_quirk *quirk;
  59         int                     line[0];
  60 };
  61
  62 static int pci_default_setup(struct serial_private*,
  63           const struct pciserial_board*, struct uart_8250_port *, int);
  64
  65 static void moan_device(const char *str, struct pci_dev *dev)
  66 {
  67         dev_err(&dev->dev,
  68                "%s: %s\n"
  69                "Please send the output of lspci -vv, this\n"
  70                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  71                "manufacturer and name of serial board or\n"
  72                "modem board to rmk+serial@arm.linux.org.uk.\n",
  73                pci_name(dev), str, dev->vendor, dev->device,
  74                dev->subsystem_vendor, dev->subsystem_device);
  75 }
  76
  77 static int
  78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  79            int bar, int offset, int regshift)
  80 {
  81         struct pci_dev *dev = priv->dev;
  82         unsigned long base, len;
  83
  84         if (bar >= PCI_NUM_BAR_RESOURCES)
  85                 return -EINVAL;
  86
  87         base = pci_resource_start(dev, bar);
  88
  89         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  90                 len =  pci_resource_len(dev, bar);
  91
  92                 if (!priv->remapped_bar[bar])
  93                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  94                 if (!priv->remapped_bar[bar])
  95                         return -ENOMEM;
  96
  97                 port->port.iotype = UPIO_MEM;
  98                 port->port.iobase = 0;
  99                 port->port.mapbase = base + offset;
 100                 port->port.membase = priv->remapped_bar[bar] + offset;
 101                 port->port.regshift = regshift;
 102         } else {
 103                 port->port.iotype = UPIO_PORT;
 104                 port->port.iobase = base + offset;
 105                 port->port.mapbase = 0;
 106                 port->port.membase = NULL;
 107                 port->port.regshift = 0;
 108         }
 109         return 0;
 110 }
 111
 112 /*
 113  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 114  */
 115 static int addidata_apci7800_setup(struct serial_private *priv,
 116                                 const struct pciserial_board *board,
 117                                 struct uart_8250_port *port, int idx)
 118 {
 119         unsigned int bar = 0, offset = board->first_offset;
 120         bar = FL_GET_BASE(board->flags);
 121
 122         if (idx < 2) {
 123                 offset += idx * board->uart_offset;
 124         } else if ((idx >= 2) && (idx < 4)) {
 125                 bar += 1;
 126                 offset += ((idx - 2) * board->uart_offset);
 127         } else if ((idx >= 4) && (idx < 6)) {
 128                 bar += 2;
 129                 offset += ((idx - 4) * board->uart_offset);
 130         } else if (idx >= 6) {
 131                 bar += 3;
 132                 offset += ((idx - 6) * board->uart_offset);
 133         }
 134
 135         return setup_port(priv, port, bar, offset, board->reg_shift);
 136 }
 137
 138 /*
 139  * AFAVLAB uses a different mixture of BARs and offsets
 140  * Not that ugly ;) -- HW
 141  */
 142 static int
 143 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 144               struct uart_8250_port *port, int idx)
 145 {
 146         unsigned int bar, offset = board->first_offset;
 147
 148         bar = FL_GET_BASE(board->flags);
 149         if (idx < 4)
 150                 bar += idx;
 151         else {
 152                 bar = 4;
 153                 offset += (idx - 4) * board->uart_offset;
 154         }
 155
 156         return setup_port(priv, port, bar, offset, board->reg_shift);
 157 }
 158
 159 /*
 160  * HP's Remote Management Console.  The Diva chip came in several
 161  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 162  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 163  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 164  * one Diva chip, but it has been expanded to 5 UARTs.
 165  */
 166 static int pci_hp_diva_init(struct pci_dev *dev)
 167 {
 168         int rc = 0;
 169
 170         switch (dev->subsystem_device) {
 171         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 172         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 173         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 174         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 175                 rc = 3;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 178                 rc = 2;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 181                 rc = 4;
 182                 break;
 183         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 184         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 185                 rc = 1;
 186                 break;
 187         }
 188
 189         return rc;
 190 }
 191
 192 /*
 193  * HP's Diva chip puts the 4th/5th serial port further out, and
 194  * some serial ports are supposed to be hidden on certain models.
 195  */
 196 static int
 197 pci_hp_diva_setup(struct serial_private *priv,
 198                 const struct pciserial_board *board,
 199                 struct uart_8250_port *port, int idx)
 200 {
 201         unsigned int offset = board->first_offset;
 202         unsigned int bar = FL_GET_BASE(board->flags);
 203
 204         switch (priv->dev->subsystem_device) {
 205         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 206                 if (idx == 3)
 207                         idx++;
 208                 break;
 209         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 210                 if (idx > 0)
 211                         idx++;
 212                 if (idx > 2)
 213                         idx++;
 214                 break;
 215         }
 216         if (idx > 2)
 217                 offset = 0x18;
 218
 219         offset += idx * board->uart_offset;
 220
 221         return setup_port(priv, port, bar, offset, board->reg_shift);
 222 }
 223
 224 /*
 225  * Added for EKF Intel i960 serial boards
 226  */
 227 static int pci_inteli960ni_init(struct pci_dev *dev)
 228 {
 229         unsigned long oldval;
 230
 231         if (!(dev->subsystem_device & 0x1000))
 232                 return -ENODEV;
 233
 234         /* is firmware started? */
 235         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 236         if (oldval == 0x00001000L) { /* RESET value */
 237                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 238                 return -ENODEV;
 239         }
 240         return 0;
 241 }
 242
 243 /*
 244  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 245  * that the card interrupt be explicitly enabled or disabled.  This
 246  * seems to be mainly needed on card using the PLX which also use I/O
 247  * mapped memory.
 248  */
 249 static int pci_plx9050_init(struct pci_dev *dev)
 250 {
 251         u8 irq_config;
 252         void __iomem *p;
 253
 254         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 255                 moan_device("no memory in bar 0", dev);
 256                 return 0;
 257         }
 258
 259         irq_config = 0x41;
 260         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 261             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 262                 irq_config = 0x43;
 263
 264         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 265             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 266                 /*
 267                  * As the megawolf cards have the int pins active
 268                  * high, and have 2 UART chips, both ints must be
 269                  * enabled on the 9050. Also, the UARTS are set in
 270                  * 16450 mode by default, so we have to enable the
 271                  * 16C950 'enhanced' mode so that we can use the
 272                  * deep FIFOs
 273                  */
 274                 irq_config = 0x5b;
 275         /*
 276          * enable/disable interrupts
 277          */
 278         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 279         if (p == NULL)
 280                 return -ENOMEM;
 281         writel(irq_config, p + 0x4c);
 282
 283         /*
 284          * Read the register back to ensure that it took effect.
 285          */
 286         readl(p + 0x4c);
 287         iounmap(p);
 288
 289         return 0;
 290 }
 291
 292 static void pci_plx9050_exit(struct pci_dev *dev)
 293 {
 294         u8 __iomem *p;
 295
 296         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 297                 return;
 298
 299         /*
 300          * disable interrupts
 301          */
 302         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 303         if (p != NULL) {
 304                 writel(0, p + 0x4c);
 305
 306                 /*
 307                  * Read the register back to ensure that it took effect.
 308                  */
 309                 readl(p + 0x4c);
 310                 iounmap(p);
 311         }
 312 }
 313
 314 #define NI8420_INT_ENABLE_REG   0x38
 315 #define NI8420_INT_ENABLE_BIT   0x2000
 316
 317 static void pci_ni8420_exit(struct pci_dev *dev)
 318 {
 319         void __iomem *p;
 320         unsigned long base, len;
 321         unsigned int bar = 0;
 322
 323         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 324                 moan_device("no memory in bar", dev);
 325                 return;
 326         }
 327
 328         base = pci_resource_start(dev, bar);
 329         len =  pci_resource_len(dev, bar);
 330         p = ioremap_nocache(base, len);
 331         if (p == NULL)
 332                 return;
 333
 334         /* Disable the CPU Interrupt */
 335         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 336                p + NI8420_INT_ENABLE_REG);
 337         iounmap(p);
 338 }
 339
 340
 341 /* MITE registers */
 342 #define MITE_IOWBSR1    0xc4
 343 #define MITE_IOWCR1     0xf4
 344 #define MITE_LCIMR1     0x08
 345 #define MITE_LCIMR2     0x10
 346
 347 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 348
 349 static void pci_ni8430_exit(struct pci_dev *dev)
 350 {
 351         void __iomem *p;
 352         unsigned long base, len;
 353         unsigned int bar = 0;
 354
 355         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 356                 moan_device("no memory in bar", dev);
 357                 return;
 358         }
 359
 360         base = pci_resource_start(dev, bar);
 361         len =  pci_resource_len(dev, bar);
 362         p = ioremap_nocache(base, len);
 363         if (p == NULL)
 364                 return;
 365
 366         /* Disable the CPU Interrupt */
 367         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 368         iounmap(p);
 369 }
 370
 371 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 372 static int
 373 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 374                 struct uart_8250_port *port, int idx)
 375 {
 376         unsigned int bar, offset = board->first_offset;
 377
 378         bar = 0;
 379
 380         if (idx < 4) {
 381                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 382                 offset += idx * board->uart_offset;
 383         } else if (idx < 8) {
 384                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 385                 offset += idx * board->uart_offset + 0xC00;
 386         } else /* we have only 8 ports on PMC-OCTALPRO */
 387                 return 1;
 388
 389         return setup_port(priv, port, bar, offset, board->reg_shift);
 390 }
 391
 392 /*
 393 * This does initialization for PMC OCTALPRO cards:
 394 * maps the device memory, resets the UARTs (needed, bc
 395 * if the module is removed and inserted again, the card
 396 * is in the sleep mode) and enables global interrupt.
 397 */
 398
 399 /* global control register offset for SBS PMC-OctalPro */
 400 #define OCT_REG_CR_OFF          0x500
 401
 402 static int sbs_init(struct pci_dev *dev)
 403 {
 404         u8 __iomem *p;
 405
 406         p = pci_ioremap_bar(dev, 0);
 407
 408         if (p == NULL)
 409                 return -ENOMEM;
 410         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 411         writeb(0x10, p + OCT_REG_CR_OFF);
 412         udelay(50);
 413         writeb(0x0, p + OCT_REG_CR_OFF);
 414
 415         /* Set bit-2 (INTENABLE) of Control Register */
 416         writeb(0x4, p + OCT_REG_CR_OFF);
 417         iounmap(p);
 418
 419         return 0;
 420 }
 421
 422 /*
 423  * Disables the global interrupt of PMC-OctalPro
 424  */
 425
 426 static void sbs_exit(struct pci_dev *dev)
 427 {
 428         u8 __iomem *p;
 429
 430         p = pci_ioremap_bar(dev, 0);
 431         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 432         if (p != NULL)
 433                 writeb(0, p + OCT_REG_CR_OFF);
 434         iounmap(p);
 435 }
 436
 437 /*
 438  * SIIG serial cards have an PCI interface chip which also controls
 439  * the UART clocking frequency. Each UART can be clocked independently
 440  * (except cards equipped with 4 UARTs) and initial clocking settings
 441  * are stored in the EEPROM chip. It can cause problems because this
 442  * version of serial driver doesn't support differently clocked UART's
 443  * on single PCI card. To prevent this, initialization functions set
 444  * high frequency clocking for all UART's on given card. It is safe (I
 445  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 446  * with other OSes (like M$ DOS).
 447  *
 448  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 449  *
 450  * There is two family of SIIG serial cards with different PCI
 451  * interface chip and different configuration methods:
 452  *     - 10x cards have control registers in IO and/or memory space;
 453  *     - 20x cards have control registers in standard PCI configuration space.
 454  *
 455  * Note: all 10x cards have PCI device ids 0x10..
 456  *       all 20x cards have PCI device ids 0x20..
 457  *
 458  * There are also Quartet Serial cards which use Oxford Semiconductor
 459  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 460  *
 461  * Note: some SIIG cards are probed by the parport_serial object.
 462  */
 463
 464 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 465 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 466
 467 static int pci_siig10x_init(struct pci_dev *dev)
 468 {
 469         u16 data;
 470         void __iomem *p;
 471
 472         switch (dev->device & 0xfff8) {
 473         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 474                 data = 0xffdf;
 475                 break;
 476         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 477                 data = 0xf7ff;
 478                 break;
 479         default:                        /* 1S1P, 4S */
 480                 data = 0xfffb;
 481                 break;
 482         }
 483
 484         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 485         if (p == NULL)
 486                 return -ENOMEM;
 487
 488         writew(readw(p + 0x28) & data, p + 0x28);
 489         readw(p + 0x28);
 490         iounmap(p);
 491         return 0;
 492 }
 493
 494 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 495 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 496
 497 static int pci_siig20x_init(struct pci_dev *dev)
 498 {
 499         u8 data;
 500
 501         /* Change clock frequency for the first UART. */
 502         pci_read_config_byte(dev, 0x6f, &data);
 503         pci_write_config_byte(dev, 0x6f, data & 0xef);
 504
 505         /* If this card has 2 UART, we have to do the same with second UART. */
 506         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 507             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 508                 pci_read_config_byte(dev, 0x73, &data);
 509                 pci_write_config_byte(dev, 0x73, data & 0xef);
 510         }
 511         return 0;
 512 }
 513
 514 static int pci_siig_init(struct pci_dev *dev)
 515 {
 516         unsigned int type = dev->device & 0xff00;
 517
 518         if (type == 0x1000)
 519                 return pci_siig10x_init(dev);
 520         else if (type == 0x2000)
 521                 return pci_siig20x_init(dev);
 522
 523         moan_device("Unknown SIIG card", dev);
 524         return -ENODEV;
 525 }
 526
 527 static int pci_siig_setup(struct serial_private *priv,
 528                           const struct pciserial_board *board,
 529                           struct uart_8250_port *port, int idx)
 530 {
 531         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 532
 533         if (idx > 3) {
 534                 bar = 4;
 535                 offset = (idx - 4) * 8;
 536         }
 537
 538         return setup_port(priv, port, bar, offset, 0);
 539 }
 540
 541 /*
 542  * Timedia has an explosion of boards, and to avoid the PCI table from
 543  * growing *huge*, we use this function to collapse some 70 entries
 544  * in the PCI table into one, for sanity's and compactness's sake.
 545  */
 546 static const unsigned short timedia_single_port[] = {
 547         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 548 };
 549
 550 static const unsigned short timedia_dual_port[] = {
 551         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 552         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 553         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 554         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 555         0xD079, 0
 556 };
 557
 558 static const unsigned short timedia_quad_port[] = {
 559         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 560         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 561         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 562         0xB157, 0
 563 };
 564
 565 static const unsigned short timedia_eight_port[] = {
 566         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 567         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 568 };
 569
 570 static const struct timedia_struct {
 571         int num;
 572         const unsigned short *ids;
 573 } timedia_data[] = {
 574         { 1, timedia_single_port },
 575         { 2, timedia_dual_port },
 576         { 4, timedia_quad_port },
 577         { 8, timedia_eight_port }
 578 };
 579
 580 /*
 581  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 582  * listing them individually, this driver merely grabs them all with
 583  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 584  * and should be left free to be claimed by parport_serial instead.
 585  */
 586 static int pci_timedia_probe(struct pci_dev *dev)
 587 {
 588         /*
 589          * Check the third digit of the subdevice ID
 590          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 591          */
 592         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 593                 dev_info(&dev->dev,
 594                         "ignoring Timedia subdevice %04x for parport_serial\n",
 595                         dev->subsystem_device);
 596                 return -ENODEV;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static int pci_timedia_init(struct pci_dev *dev)
 603 {
 604         const unsigned short *ids;
 605         int i, j;
 606
 607         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 608                 ids = timedia_data[i].ids;
 609                 for (j = 0; ids[j]; j++)
 610                         if (dev->subsystem_device == ids[j])
 611                                 return timedia_data[i].num;
 612         }
 613         return 0;
 614 }
 615
 616 /*
 617  * Timedia/SUNIX uses a mixture of BARs and offsets
 618  * Ugh, this is ugly as all hell --- TYT
 619  */
 620 static int
 621 pci_timedia_setup(struct serial_private *priv,
 622                   const struct pciserial_board *board,
 623                   struct uart_8250_port *port, int idx)
 624 {
 625         unsigned int bar = 0, offset = board->first_offset;
 626
 627         switch (idx) {
 628         case 0:
 629                 bar = 0;
 630                 break;
 631         case 1:
 632                 offset = board->uart_offset;
 633                 bar = 0;
 634                 break;
 635         case 2:
 636                 bar = 1;
 637                 break;
 638         case 3:
 639                 offset = board->uart_offset;
 640                 /* FALLTHROUGH */
 641         case 4: /* BAR 2 */
 642         case 5: /* BAR 3 */
 643         case 6: /* BAR 4 */
 644         case 7: /* BAR 5 */
 645                 bar = idx - 2;
 646         }
 647
 648         return setup_port(priv, port, bar, offset, board->reg_shift);
 649 }
 650
 651 /*
 652  * Some Titan cards are also a little weird
 653  */
 654 static int
 655 titan_400l_800l_setup(struct serial_private *priv,
 656                       const struct pciserial_board *board,
 657                       struct uart_8250_port *port, int idx)
 658 {
 659         unsigned int bar, offset = board->first_offset;
 660
 661         switch (idx) {
 662         case 0:
 663                 bar = 1;
 664                 break;
 665         case 1:
 666                 bar = 2;
 667                 break;
 668         default:
 669                 bar = 4;
 670                 offset = (idx - 2) * board->uart_offset;
 671         }
 672
 673         return setup_port(priv, port, bar, offset, board->reg_shift);
 674 }
 675
 676 static int pci_xircom_init(struct pci_dev *dev)
 677 {
 678         msleep(100);
 679         return 0;
 680 }
 681
 682 static int pci_ni8420_init(struct pci_dev *dev)
 683 {
 684         void __iomem *p;
 685         unsigned long base, len;
 686         unsigned int bar = 0;
 687
 688         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 689                 moan_device("no memory in bar", dev);
 690                 return 0;
 691         }
 692
 693         base = pci_resource_start(dev, bar);
 694         len =  pci_resource_len(dev, bar);
 695         p = ioremap_nocache(base, len);
 696         if (p == NULL)
 697                 return -ENOMEM;
 698
 699         /* Enable CPU Interrupt */
 700         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 701                p + NI8420_INT_ENABLE_REG);
 702
 703         iounmap(p);
 704         return 0;
 705 }
 706
 707 #define MITE_IOWBSR1_WSIZE      0xa
 708 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 709 #define MITE_IOWBSR1_WENAB      (1 << 7)
 710 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 711 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 712 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 713
 714 static int pci_ni8430_init(struct pci_dev *dev)
 715 {
 716         void __iomem *p;
 717         unsigned long base, len;
 718         u32 device_window;
 719         unsigned int bar = 0;
 720
 721         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 722                 moan_device("no memory in bar", dev);
 723                 return 0;
 724         }
 725
 726         base = pci_resource_start(dev, bar);
 727         len =  pci_resource_len(dev, bar);
 728         p = ioremap_nocache(base, len);
 729         if (p == NULL)
 730                 return -ENOMEM;
 731
 732         /* Set device window address and size in BAR0 */
 733         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 734                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 735         writel(device_window, p + MITE_IOWBSR1);
 736
 737         /* Set window access to go to RAMSEL IO address space */
 738         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 739                p + MITE_IOWCR1);
 740
 741         /* Enable IO Bus Interrupt 0 */
 742         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 743
 744         /* Enable CPU Interrupt */
 745         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 746
 747         iounmap(p);
 748         return 0;
 749 }
 750
 751 /* UART Port Control Register */
 752 #define NI8430_PORTCON  0x0f
 753 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 754
 755 static int
 756 pci_ni8430_setup(struct serial_private *priv,
 757                  const struct pciserial_board *board,
 758                  struct uart_8250_port *port, int idx)
 759 {
 760         void __iomem *p;
 761         unsigned long base, len;
 762         unsigned int bar, offset = board->first_offset;
 763
 764         if (idx >= board->num_ports)
 765                 return 1;
 766
 767         bar = FL_GET_BASE(board->flags);
 768         offset += idx * board->uart_offset;
 769
 770         base = pci_resource_start(priv->dev, bar);
 771         len =  pci_resource_len(priv->dev, bar);
 772         p = ioremap_nocache(base, len);
 773
 774         /* enable the transceiver */
 775         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 776                p + offset + NI8430_PORTCON);
 777
 778         iounmap(p);
 779
 780         return setup_port(priv, port, bar, offset, board->reg_shift);
 781 }
 782
 783 static int pci_netmos_9900_setup(struct serial_private *priv,
 784                                 const struct pciserial_board *board,
 785                                 struct uart_8250_port *port, int idx)
 786 {
 787         unsigned int bar;
 788
 789         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 790             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 791                 /* netmos apparently orders BARs by datasheet layout, so serial
 792                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 793                  */
 794                 bar = 3 * idx;
 795
 796                 return setup_port(priv, port, bar, 0, board->reg_shift);
 797         } else {
 798                 return pci_default_setup(priv, board, port, idx);
 799         }
 800 }
 801
 802 /* the 99xx series comes with a range of device IDs and a variety
 803  * of capabilities:
 804  *
 805  * 9900 has varying capabilities and can cascade to sub-controllers
 806  *   (cascading should be purely internal)
 807  * 9904 is hardwired with 4 serial ports
 808  * 9912 and 9922 are hardwired with 2 serial ports
 809  */
 810 static int pci_netmos_9900_numports(struct pci_dev *dev)
 811 {
 812         unsigned int c = dev->class;
 813         unsigned int pi;
 814         unsigned short sub_serports;
 815
 816         pi = (c & 0xff);
 817
 818         if (pi == 2) {
 819                 return 1;
 820         } else if ((pi == 0) &&
 821                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 822                 /* two possibilities: 0x30ps encodes number of parallel and
 823                  * serial ports, or 0x1000 indicates *something*. This is not
 824                  * immediately obvious, since the 2s1p+4s configuration seems
 825                  * to offer all functionality on functions 0..2, while still
 826                  * advertising the same function 3 as the 4s+2s1p config.
 827                  */
 828                 sub_serports = dev->subsystem_device & 0xf;
 829                 if (sub_serports > 0) {
 830                         return sub_serports;
 831                 } else {
 832                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 833                         return 0;
 834                 }
 835         }
 836
 837         moan_device("unknown NetMos/Mostech program interface", dev);
 838         return 0;
 839 }
 840
 841 static int pci_netmos_init(struct pci_dev *dev)
 842 {
 843         /* subdevice 0x00PS means <P> parallel, <S> serial */
 844         unsigned int num_serial = dev->subsystem_device & 0xf;
 845
 846         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 847                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 848                 return 0;
 849
 850         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 851                         dev->subsystem_device == 0x0299)
 852                 return 0;
 853
 854         switch (dev->device) { /* FALLTHROUGH on all */
 855                 case PCI_DEVICE_ID_NETMOS_9904:
 856                 case PCI_DEVICE_ID_NETMOS_9912:
 857                 case PCI_DEVICE_ID_NETMOS_9922:
 858                 case PCI_DEVICE_ID_NETMOS_9900:
 859                         num_serial = pci_netmos_9900_numports(dev);
 860                         break;
 861
 862                 default:
 863                         if (num_serial == 0 ) {
 864                                 moan_device("unknown NetMos/Mostech device", dev);
 865                         }
 866         }
 867
 868         if (num_serial == 0)
 869                 return -ENODEV;
 870
 871         return num_serial;
 872 }
 873
 874 /*
 875  * These chips are available with optionally one parallel port and up to
 876  * two serial ports. Unfortunately they all have the same product id.
 877  *
 878  * Basic configuration is done over a region of 32 I/O ports. The base
 879  * ioport is called INTA or INTC, depending on docs/other drivers.
 880  *
 881  * The region of the 32 I/O ports is configured in POSIO0R...
 882  */
 883
 884 /* registers */
 885 #define ITE_887x_MISCR          0x9c
 886 #define ITE_887x_INTCBAR        0x78
 887 #define ITE_887x_UARTBAR        0x7c
 888 #define ITE_887x_PS0BAR         0x10
 889 #define ITE_887x_POSIO0         0x60
 890
 891 /* I/O space size */
 892 #define ITE_887x_IOSIZE         32
 893 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 894 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 895 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 896 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 897 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 898 #define ITE_887x_POSIO_SPEED            (3 << 29)
 899 /* enable IO_Space bit */
 900 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 901
 902 static int pci_ite887x_init(struct pci_dev *dev)
 903 {
 904         /* inta_addr are the configuration addresses of the ITE */
 905         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 906                                                         0x200, 0x280, 0 };
 907         int ret, i, type;
 908         struct resource *iobase = NULL;
 909         u32 miscr, uartbar, ioport;
 910
 911         /* search for the base-ioport */
 912         i = 0;
 913         while (inta_addr[i] && iobase == NULL) {
 914                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 915                                                                 "ite887x");
 916                 if (iobase != NULL) {
 917                         /* write POSIO0R - speed | size | ioport */
 918                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 919                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 920                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 921                         /* write INTCBAR - ioport */
 922                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 923                                                                 inta_addr[i]);
 924                         ret = inb(inta_addr[i]);
 925                         if (ret != 0xff) {
 926                                 /* ioport connected */
 927                                 break;
 928                         }
 929                         release_region(iobase->start, ITE_887x_IOSIZE);
 930                         iobase = NULL;
 931                 }
 932                 i++;
 933         }
 934
 935         if (!inta_addr[i]) {
 936                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 937                 return -ENODEV;
 938         }
 939
 940         /* start of undocumented type checking (see parport_pc.c) */
 941         type = inb(iobase->start + 0x18) & 0x0f;
 942
 943         switch (type) {
 944         case 0x2:       /* ITE8871 (1P) */
 945         case 0xa:       /* ITE8875 (1P) */
 946                 ret = 0;
 947                 break;
 948         case 0xe:       /* ITE8872 (2S1P) */
 949                 ret = 2;
 950                 break;
 951         case 0x6:       /* ITE8873 (1S) */
 952                 ret = 1;
 953                 break;
 954         case 0x8:       /* ITE8874 (2S) */
 955                 ret = 2;
 956                 break;
 957         default:
 958                 moan_device("Unknown ITE887x", dev);
 959                 ret = -ENODEV;
 960         }
 961
 962         /* configure all serial ports */
 963         for (i = 0; i < ret; i++) {
 964                 /* read the I/O port from the device */
 965                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 966                                                                 &ioport);
 967                 ioport &= 0x0000FF00;   /* the actual base address */
 968                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 969                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 970                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 971
 972                 /* write the ioport to the UARTBAR */
 973                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 974                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 975                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 976                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 977
 978                 /* get current config */
 979                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 980                 /* disable interrupts (UARTx_Routing[3:0]) */
 981                 miscr &= ~(0xf << (12 - 4 * i));
 982                 /* activate the UART (UARTx_En) */
 983                 miscr |= 1 << (23 - i);
 984                 /* write new config with activated UART */
 985                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 986         }
 987
 988         if (ret <= 0) {
 989                 /* the device has no UARTs if we get here */
 990                 release_region(iobase->start, ITE_887x_IOSIZE);
 991         }
 992
 993         return ret;
 994 }
 995
 996 static void pci_ite887x_exit(struct pci_dev *dev)
 997 {
 998         u32 ioport;
 999         /* the ioport is bit 0-15 in POSIO0R */
1000         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1001         ioport &= 0xffff;
1002         release_region(ioport, ITE_887x_IOSIZE);
1003 }
1004
1005 /*
1006  * Oxford Semiconductor Inc.
1007  * Check that device is part of the Tornado range of devices, then determine
1008  * the number of ports available on the device.
1009  */
1010 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1011 {
1012         u8 __iomem *p;
1013         unsigned long deviceID;
1014         unsigned int  number_uarts = 0;
1015
1016         /* OxSemi Tornado devices are all 0xCxxx */
1017         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1018             (dev->device & 0xF000) != 0xC000)
1019                 return 0;
1020
1021         p = pci_iomap(dev, 0, 5);
1022         if (p == NULL)
1023                 return -ENOMEM;
1024
1025         deviceID = ioread32(p);
1026         /* Tornado device */
1027         if (deviceID == 0x07000200) {
1028                 number_uarts = ioread8(p + 4);
1029                 dev_dbg(&dev->dev,
1030                         "%d ports detected on Oxford PCI Express device\n",
1031                         number_uarts);
1032         }
1033         pci_iounmap(dev, p);
1034         return number_uarts;
1035 }
1036
1037 static int pci_asix_setup(struct serial_private *priv,
1038                   const struct pciserial_board *board,
1039                   struct uart_8250_port *port, int idx)
1040 {
1041         port->bugs |= UART_BUG_PARITY;
1042         return pci_default_setup(priv, board, port, idx);
1043 }
1044
1045 /* Quatech devices have their own extra interface features */
1046
1047 struct quatech_feature {
1048         u16 devid;
1049         bool amcc;
1050 };
1051
1052 #define QPCR_TEST_FOR1          0x3F
1053 #define QPCR_TEST_GET1          0x00
1054 #define QPCR_TEST_FOR2          0x40
1055 #define QPCR_TEST_GET2          0x40
1056 #define QPCR_TEST_FOR3          0x80
1057 #define QPCR_TEST_GET3          0x40
1058 #define QPCR_TEST_FOR4          0xC0
1059 #define QPCR_TEST_GET4          0x80
1060
1061 #define QOPR_CLOCK_X1           0x0000
1062 #define QOPR_CLOCK_X2           0x0001
1063 #define QOPR_CLOCK_X4           0x0002
1064 #define QOPR_CLOCK_X8           0x0003
1065 #define QOPR_CLOCK_RATE_MASK    0x0003
1066
1067
1068 static struct quatech_feature quatech_cards[] = {
1069         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1070         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1071         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1072         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1073         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1074         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1075         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1076         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1077         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1078         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1079         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1080         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1081         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1082         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1083         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1084         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1085         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1086         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1087         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1088         { 0, }
1089 };
1090
1091 static int pci_quatech_amcc(u16 devid)
1092 {
1093         struct quatech_feature *qf = &quatech_cards[0];
1094         while (qf->devid) {
1095                 if (qf->devid == devid)
1096                         return qf->amcc;
1097                 qf++;
1098         }
1099         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1100         return 0;
1101 };
1102
1103 static int pci_quatech_rqopr(struct uart_8250_port *port)
1104 {
1105         unsigned long base = port->port.iobase;
1106         u8 LCR, val;
1107
1108         LCR = inb(base + UART_LCR);
1109         outb(0xBF, base + UART_LCR);
1110         val = inb(base + UART_SCR);
1111         outb(LCR, base + UART_LCR);
1112         return val;
1113 }
1114
1115 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1116 {
1117         unsigned long base = port->port.iobase;
1118         u8 LCR, val;
1119
1120         LCR = inb(base + UART_LCR);
1121         outb(0xBF, base + UART_LCR);
1122         val = inb(base + UART_SCR);
1123         outb(qopr, base + UART_SCR);
1124         outb(LCR, base + UART_LCR);
1125 }
1126
1127 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1128 {
1129         unsigned long base = port->port.iobase;
1130         u8 LCR, val, qmcr;
1131
1132         LCR = inb(base + UART_LCR);
1133         outb(0xBF, base + UART_LCR);
1134         val = inb(base + UART_SCR);
1135         outb(val | 0x10, base + UART_SCR);
1136         qmcr = inb(base + UART_MCR);
1137         outb(val, base + UART_SCR);
1138         outb(LCR, base + UART_LCR);
1139
1140         return qmcr;
1141 }
1142
1143 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1144 {
1145         unsigned long base = port->port.iobase;
1146         u8 LCR, val;
1147
1148         LCR = inb(base + UART_LCR);
1149         outb(0xBF, base + UART_LCR);
1150         val = inb(base + UART_SCR);
1151         outb(val | 0x10, base + UART_SCR);
1152         outb(qmcr, base + UART_MCR);
1153         outb(val, base + UART_SCR);
1154         outb(LCR, base + UART_LCR);
1155 }
1156
1157 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1158 {
1159         unsigned long base = port->port.iobase;
1160         u8 LCR, val;
1161
1162         LCR = inb(base + UART_LCR);
1163         outb(0xBF, base + UART_LCR);
1164         val = inb(base + UART_SCR);
1165         if (val & 0x20) {
1166                 outb(0x80, UART_LCR);
1167                 if (!(inb(UART_SCR) & 0x20)) {
1168                         outb(LCR, base + UART_LCR);
1169                         return 1;
1170                 }
1171         }
1172         return 0;
1173 }
1174
1175 static int pci_quatech_test(struct uart_8250_port *port)
1176 {
1177         u8 reg;
1178         u8 qopr = pci_quatech_rqopr(port);
1179         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1180         reg = pci_quatech_rqopr(port) & 0xC0;
1181         if (reg != QPCR_TEST_GET1)
1182                 return -EINVAL;
1183         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1184         reg = pci_quatech_rqopr(port) & 0xC0;
1185         if (reg != QPCR_TEST_GET2)
1186                 return -EINVAL;
1187         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1188         reg = pci_quatech_rqopr(port) & 0xC0;
1189         if (reg != QPCR_TEST_GET3)
1190                 return -EINVAL;
1191         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1192         reg = pci_quatech_rqopr(port) & 0xC0;
1193         if (reg != QPCR_TEST_GET4)
1194                 return -EINVAL;
1195
1196         pci_quatech_wqopr(port, qopr);
1197         return 0;
1198 }
1199
1200 static int pci_quatech_clock(struct uart_8250_port *port)
1201 {
1202         u8 qopr, reg, set;
1203         unsigned long clock;
1204
1205         if (pci_quatech_test(port) < 0)
1206                 return 1843200;
1207
1208         qopr = pci_quatech_rqopr(port);
1209
1210         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1211         reg = pci_quatech_rqopr(port);
1212         if (reg & QOPR_CLOCK_X8) {
1213                 clock = 1843200;
1214                 goto out;
1215         }
1216         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1217         reg = pci_quatech_rqopr(port);
1218         if (!(reg & QOPR_CLOCK_X8)) {
1219                 clock = 1843200;
1220                 goto out;
1221         }
1222         reg &= QOPR_CLOCK_X8;
1223         if (reg == QOPR_CLOCK_X2) {
1224                 clock =  3685400;
1225                 set = QOPR_CLOCK_X2;
1226         } else if (reg == QOPR_CLOCK_X4) {
1227                 clock = 7372800;
1228                 set = QOPR_CLOCK_X4;
1229         } else if (reg == QOPR_CLOCK_X8) {
1230                 clock = 14745600;
1231                 set = QOPR_CLOCK_X8;
1232         } else {
1233                 clock = 1843200;
1234                 set = QOPR_CLOCK_X1;
1235         }
1236         qopr &= ~QOPR_CLOCK_RATE_MASK;
1237         qopr |= set;
1238
1239 out:
1240         pci_quatech_wqopr(port, qopr);
1241         return clock;
1242 }
1243
1244 static int pci_quatech_rs422(struct uart_8250_port *port)
1245 {
1246         u8 qmcr;
1247         int rs422 = 0;
1248
1249         if (!pci_quatech_has_qmcr(port))
1250                 return 0;
1251         qmcr = pci_quatech_rqmcr(port);
1252         pci_quatech_wqmcr(port, 0xFF);
1253         if (pci_quatech_rqmcr(port))
1254                 rs422 = 1;
1255         pci_quatech_wqmcr(port, qmcr);
1256         return rs422;
1257 }
1258
1259 static int pci_quatech_init(struct pci_dev *dev)
1260 {
1261         if (pci_quatech_amcc(dev->device)) {
1262                 unsigned long base = pci_resource_start(dev, 0);
1263                 if (base) {
1264                         u32 tmp;
1265                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1266                         tmp = inl(base + 0x3c);
1267                         outl(tmp | 0x01000000, base + 0x3c);
1268                         outl(tmp &= ~0x01000000, base + 0x3c);
1269                 }
1270         }
1271         return 0;
1272 }
1273
1274 static int pci_quatech_setup(struct serial_private *priv,
1275                   const struct pciserial_board *board,
1276                   struct uart_8250_port *port, int idx)
1277 {
1278         /* Needed by pci_quatech calls below */
1279         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1280         /* Set up the clocking */
1281         port->port.uartclk = pci_quatech_clock(port);
1282         /* For now just warn about RS422 */
1283         if (pci_quatech_rs422(port))
1284                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1285         return pci_default_setup(priv, board, port, idx);
1286 }
1287
1288 static void pci_quatech_exit(struct pci_dev *dev)
1289 {
1290 }
1291
1292 static int pci_default_setup(struct serial_private *priv,
1293                   const struct pciserial_board *board,
1294                   struct uart_8250_port *port, int idx)
1295 {
1296         unsigned int bar, offset = board->first_offset, maxnr;
1297
1298         bar = FL_GET_BASE(board->flags);
1299         if (board->flags & FL_BASE_BARS)
1300                 bar += idx;
1301         else
1302                 offset += idx * board->uart_offset;
1303
1304         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1305                 (board->reg_shift + 3);
1306
1307         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1308                 return 1;
1309
1310         return setup_port(priv, port, bar, offset, board->reg_shift);
1311 }
1312
1313 static int pci_pericom_setup(struct serial_private *priv,
1314                   const struct pciserial_board *board,
1315                   struct uart_8250_port *port, int idx)
1316 {
1317         unsigned int bar, offset = board->first_offset, maxnr;
1318
1319         bar = FL_GET_BASE(board->flags);
1320         if (board->flags & FL_BASE_BARS)
1321                 bar += idx;
1322         else
1323                 offset += idx * board->uart_offset;
1324
1325         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1326                 (board->reg_shift + 3);
1327
1328         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1329                 return 1;
1330
1331         port->port.uartclk = 14745600;
1332
1333         return setup_port(priv, port, bar, offset, board->reg_shift);
1334 }
1335
1336 static int
1337 ce4100_serial_setup(struct serial_private *priv,
1338                   const struct pciserial_board *board,
1339                   struct uart_8250_port *port, int idx)
1340 {
1341         int ret;
1342
1343         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1344         port->port.iotype = UPIO_MEM32;
1345         port->port.type = PORT_XSCALE;
1346         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1347         port->port.regshift = 2;
1348
1349         return ret;
1350 }
1351
1352 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1354
1355 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1357
1358 #define BYT_PRV_CLK                     0x800
1359 #define BYT_PRV_CLK_EN                  (1 << 0)
1360 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1361 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1362 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1363
1364 #define BYT_TX_OVF_INT                  0x820
1365 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1366
1367 static void
1368 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1369                 struct ktermios *old)
1370 {
1371         unsigned int baud = tty_termios_baud_rate(termios);
1372         unsigned int m, n;
1373         u32 reg;
1374
1375         /*
1376          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1377          * dividers must be adjusted.
1378          *
1379          * uartclk = (m / n) * 100 MHz, where m <= n
1380          */
1381         switch (baud) {
1382         case 500000:
1383         case 1000000:
1384         case 2000000:
1385         case 4000000:
1386                 m = 64;
1387                 n = 100;
1388                 p->uartclk = 64000000;
1389                 break;
1390         case 3500000:
1391                 m = 56;
1392                 n = 100;
1393                 p->uartclk = 56000000;
1394                 break;
1395         case 1500000:
1396         case 3000000:
1397                 m = 48;
1398                 n = 100;
1399                 p->uartclk = 48000000;
1400                 break;
1401         case 2500000:
1402                 m = 40;
1403                 n = 100;
1404                 p->uartclk = 40000000;
1405                 break;
1406         default:
1407                 m = 2304;
1408                 n = 3125;
1409                 p->uartclk = 73728000;
1410         }
1411
1412         /* Reset the clock */
1413         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1414         writel(reg, p->membase + BYT_PRV_CLK);
1415         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1416         writel(reg, p->membase + BYT_PRV_CLK);
1417
1418         serial8250_do_set_termios(p, termios, old);
1419 }
1420
1421 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1422 {
1423         struct dw_dma_slave *dws = param;
1424
1425         if (dws->dma_dev != chan->device->dev)
1426                 return false;
1427
1428         chan->private = dws;
1429         return true;
1430 }
1431
1432 static int
1433 byt_serial_setup(struct serial_private *priv,
1434                  const struct pciserial_board *board,
1435                  struct uart_8250_port *port, int idx)
1436 {
1437         struct pci_dev *pdev = priv->dev;
1438         struct device *dev = port->port.dev;
1439         struct uart_8250_dma *dma;
1440         struct dw_dma_slave *tx_param, *rx_param;
1441         struct pci_dev *dma_dev;
1442         int ret;
1443
1444         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1445         if (!dma)
1446                 return -ENOMEM;
1447
1448         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1449         if (!tx_param)
1450                 return -ENOMEM;
1451
1452         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1453         if (!rx_param)
1454                 return -ENOMEM;
1455
1456         switch (pdev->device) {
1457         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1458         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1459                 rx_param->src_id = 3;
1460                 tx_param->dst_id = 2;
1461                 break;
1462         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1463         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1464                 rx_param->src_id = 5;
1465                 tx_param->dst_id = 4;
1466                 break;
1467         default:
1468                 return -EINVAL;
1469         }
1470
1471         rx_param->src_master = 1;
1472         rx_param->dst_master = 0;
1473
1474         dma->rxconf.src_maxburst = 16;
1475
1476         tx_param->src_master = 1;
1477         tx_param->dst_master = 0;
1478
1479         dma->txconf.dst_maxburst = 16;
1480
1481         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1482         rx_param->dma_dev = &dma_dev->dev;
1483         tx_param->dma_dev = &dma_dev->dev;
1484
1485         dma->fn = byt_dma_filter;
1486         dma->rx_param = rx_param;
1487         dma->tx_param = tx_param;
1488
1489         ret = pci_default_setup(priv, board, port, idx);
1490         port->port.iotype = UPIO_MEM;
1491         port->port.type = PORT_16550A;
1492         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1493         port->port.set_termios = byt_set_termios;
1494         port->port.fifosize = 64;
1495         port->tx_loadsz = 64;
1496         port->dma = dma;
1497         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1498
1499         /* Disable Tx counter interrupts */
1500         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1501
1502         return ret;
1503 }
1504
1505 static int
1506 pci_omegapci_setup(struct serial_private *priv,
1507                       const struct pciserial_board *board,
1508                       struct uart_8250_port *port, int idx)
1509 {
1510         return setup_port(priv, port, 2, idx * 8, 0);
1511 }
1512
1513 static int
1514 pci_brcm_trumanage_setup(struct serial_private *priv,
1515                          const struct pciserial_board *board,
1516                          struct uart_8250_port *port, int idx)
1517 {
1518         int ret = pci_default_setup(priv, board, port, idx);
1519
1520         port->port.type = PORT_BRCM_TRUMANAGE;
1521         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1522         return ret;
1523 }
1524
1525 static int pci_fintek_setup(struct serial_private *priv,
1526                             const struct pciserial_board *board,
1527                             struct uart_8250_port *port, int idx)
1528 {
1529         struct pci_dev *pdev = priv->dev;
1530         unsigned long base;
1531         unsigned long iobase;
1532         unsigned long ciobase = 0;
1533         u8 config_base;
1534
1535         /*
1536          * We are supposed to be able to read these from the PCI config space,
1537          * but the values there don't seem to match what we need to use, so
1538          * just use these hard-coded values for now, as they are correct.
1539          */
1540         switch (idx) {
1541         case 0: iobase = 0xe000; config_base = 0x40; break;
1542         case 1: iobase = 0xe008; config_base = 0x48; break;
1543         case 2: iobase = 0xe010; config_base = 0x50; break;
1544         case 3: iobase = 0xe018; config_base = 0x58; break;
1545         case 4: iobase = 0xe020; config_base = 0x60; break;
1546         case 5: iobase = 0xe028; config_base = 0x68; break;
1547         case 6: iobase = 0xe030; config_base = 0x70; break;
1548         case 7: iobase = 0xe038; config_base = 0x78; break;
1549         case 8: iobase = 0xe040; config_base = 0x80; break;
1550         case 9: iobase = 0xe048; config_base = 0x88; break;
1551         case 10: iobase = 0xe050; config_base = 0x90; break;
1552         case 11: iobase = 0xe058; config_base = 0x98; break;
1553         default:
1554                 /* Unknown number of ports, get out of here */
1555                 return -EINVAL;
1556         }
1557
1558         if (idx < 4) {
1559                 base = pci_resource_start(priv->dev, 3);
1560                 ciobase = (int)(base + (0x8 * idx));
1561         }
1562
1563         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1564                 __func__, idx, iobase, ciobase, config_base);
1565
1566         /* Enable UART I/O port */
1567         pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1568
1569         /* Select 128-byte FIFO and 8x FIFO threshold */
1570         pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1571
1572         /* LSB UART */
1573         pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1574
1575         /* MSB UART */
1576         pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1577
1578         /* irq number, this usually fails, but the spec says to do it anyway. */
1579         pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1580
1581         port->port.iotype = UPIO_PORT;
1582         port->port.iobase = iobase;
1583         port->port.mapbase = 0;
1584         port->port.membase = NULL;
1585         port->port.regshift = 0;
1586
1587         return 0;
1588 }
1589
1590 static int skip_tx_en_setup(struct serial_private *priv,
1591                         const struct pciserial_board *board,
1592                         struct uart_8250_port *port, int idx)
1593 {
1594         port->port.flags |= UPF_NO_TXEN_TEST;
1595         dev_dbg(&priv->dev->dev,
1596                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1597                 priv->dev->vendor, priv->dev->device,
1598                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1599
1600         return pci_default_setup(priv, board, port, idx);
1601 }
1602
1603 static void kt_handle_break(struct uart_port *p)
1604 {
1605         struct uart_8250_port *up = up_to_u8250p(p);
1606         /*
1607          * On receipt of a BI, serial device in Intel ME (Intel
1608          * management engine) needs to have its fifos cleared for sane
1609          * SOL (Serial Over Lan) output.
1610          */
1611         serial8250_clear_and_reinit_fifos(up);
1612 }
1613
1614 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1615 {
1616         struct uart_8250_port *up = up_to_u8250p(p);
1617         unsigned int val;
1618
1619         /*
1620          * When the Intel ME (management engine) gets reset its serial
1621          * port registers could return 0 momentarily.  Functions like
1622          * serial8250_console_write, read and save the IER, perform
1623          * some operation and then restore it.  In order to avoid
1624          * setting IER register inadvertently to 0, if the value read
1625          * is 0, double check with ier value in uart_8250_port and use
1626          * that instead.  up->ier should be the same value as what is
1627          * currently configured.
1628          */
1629         val = inb(p->iobase + offset);
1630         if (offset == UART_IER) {
1631                 if (val == 0)
1632                         val = up->ier;
1633         }
1634         return val;
1635 }
1636
1637 static int kt_serial_setup(struct serial_private *priv,
1638                            const struct pciserial_board *board,
1639                            struct uart_8250_port *port, int idx)
1640 {
1641         port->port.flags |= UPF_BUG_THRE;
1642         port->port.serial_in = kt_serial_in;
1643         port->port.handle_break = kt_handle_break;
1644         return skip_tx_en_setup(priv, board, port, idx);
1645 }
1646
1647 static int pci_eg20t_init(struct pci_dev *dev)
1648 {
1649 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1650         return -ENODEV;
1651 #else
1652         return 0;
1653 #endif
1654 }
1655
1656 static int
1657 pci_xr17c154_setup(struct serial_private *priv,
1658                   const struct pciserial_board *board,
1659                   struct uart_8250_port *port, int idx)
1660 {
1661         port->port.flags |= UPF_EXAR_EFR;
1662         return pci_default_setup(priv, board, port, idx);
1663 }
1664
1665 static int
1666 pci_xr17v35x_setup(struct serial_private *priv,
1667                   const struct pciserial_board *board,
1668                   struct uart_8250_port *port, int idx)
1669 {
1670         u8 __iomem *p;
1671
1672         p = pci_ioremap_bar(priv->dev, 0);
1673         if (p == NULL)
1674                 return -ENOMEM;
1675
1676         port->port.flags |= UPF_EXAR_EFR;
1677
1678         /*
1679          * Setup Multipurpose Input/Output pins.
1680          */
1681         if (idx == 0) {
1682                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1683                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1684                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1685                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1686                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1687                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1688                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1689                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1690                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1691                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1692                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1693                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1694         }
1695         writeb(0x00, p + UART_EXAR_8XMODE);
1696         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1697         writeb(128, p + UART_EXAR_TXTRG);
1698         writeb(128, p + UART_EXAR_RXTRG);
1699         iounmap(p);
1700
1701         return pci_default_setup(priv, board, port, idx);
1702 }
1703
1704 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1705 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1706 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1707 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1708
1709 static int
1710 pci_fastcom335_setup(struct serial_private *priv,
1711                   const struct pciserial_board *board,
1712                   struct uart_8250_port *port, int idx)
1713 {
1714         u8 __iomem *p;
1715
1716         p = pci_ioremap_bar(priv->dev, 0);
1717         if (p == NULL)
1718                 return -ENOMEM;
1719
1720         port->port.flags |= UPF_EXAR_EFR;
1721
1722         /*
1723          * Setup Multipurpose Input/Output pins.
1724          */
1725         if (idx == 0) {
1726                 switch (priv->dev->device) {
1727                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1728                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1729                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1730                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1731                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1732                         break;
1733                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1734                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1735                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1736                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1737                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1738                         break;
1739                 }
1740                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1741                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1742                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1743         }
1744         writeb(0x00, p + UART_EXAR_8XMODE);
1745         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1746         writeb(32, p + UART_EXAR_TXTRG);
1747         writeb(32, p + UART_EXAR_RXTRG);
1748         iounmap(p);
1749
1750         return pci_default_setup(priv, board, port, idx);
1751 }
1752
1753 static int
1754 pci_wch_ch353_setup(struct serial_private *priv,
1755                     const struct pciserial_board *board,
1756                     struct uart_8250_port *port, int idx)
1757 {
1758         port->port.flags |= UPF_FIXED_TYPE;
1759         port->port.type = PORT_16550A;
1760         return pci_default_setup(priv, board, port, idx);
1761 }
1762
1763 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1764 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1765 #define PCI_DEVICE_ID_OCTPRO            0x0001
1766 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1767 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1768 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1769 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1770 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1771 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1772 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1773 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1774 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1775 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1776 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1777 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1778 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1779 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1780 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1781 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1782 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1783 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1784 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1785 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1786 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1787 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1788 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1789 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1790 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1791 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1792 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1793 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1794 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1795 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1796 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1797 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1798 #define PCI_VENDOR_ID_WCH               0x4348
1799 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1800 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1801 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1802 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1803 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1804 #define PCI_VENDOR_ID_AGESTAR           0x5372
1805 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1806 #define PCI_VENDOR_ID_ASIX              0x9710
1807 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1808 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1809 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1810 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1811 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1812 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1813
1814 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1815 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1816
1817
1818 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1819 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1820 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1821
1822 /*
1823  * Master list of serial port init/setup/exit quirks.
1824  * This does not describe the general nature of the port.
1825  * (ie, baud base, number and location of ports, etc)
1826  *
1827  * This list is ordered alphabetically by vendor then device.
1828  * Specific entries must come before more generic entries.
1829  */
1830 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1831         /*
1832         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1833         */
1834         {
1835                 .vendor         = PCI_VENDOR_ID_AMCC,
1836                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1837                 .subvendor      = PCI_ANY_ID,
1838                 .subdevice      = PCI_ANY_ID,
1839                 .setup          = addidata_apci7800_setup,
1840         },
1841         /*
1842          * AFAVLAB cards - these may be called via parport_serial
1843          *  It is not clear whether this applies to all products.
1844          */
1845         {
1846                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1847                 .device         = PCI_ANY_ID,
1848                 .subvendor      = PCI_ANY_ID,
1849                 .subdevice      = PCI_ANY_ID,
1850                 .setup          = afavlab_setup,
1851         },
1852         /*
1853          * HP Diva
1854          */
1855         {
1856                 .vendor         = PCI_VENDOR_ID_HP,
1857                 .device         = PCI_DEVICE_ID_HP_DIVA,
1858                 .subvendor      = PCI_ANY_ID,
1859                 .subdevice      = PCI_ANY_ID,
1860                 .init           = pci_hp_diva_init,
1861                 .setup          = pci_hp_diva_setup,
1862         },
1863         /*
1864          * Intel
1865          */
1866         {
1867                 .vendor         = PCI_VENDOR_ID_INTEL,
1868                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1869                 .subvendor      = 0xe4bf,
1870                 .subdevice      = PCI_ANY_ID,
1871                 .init           = pci_inteli960ni_init,
1872                 .setup          = pci_default_setup,
1873         },
1874         {
1875                 .vendor         = PCI_VENDOR_ID_INTEL,
1876                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1877                 .subvendor      = PCI_ANY_ID,
1878                 .subdevice      = PCI_ANY_ID,
1879                 .setup          = skip_tx_en_setup,
1880         },
1881         {
1882                 .vendor         = PCI_VENDOR_ID_INTEL,
1883                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1884                 .subvendor      = PCI_ANY_ID,
1885                 .subdevice      = PCI_ANY_ID,
1886                 .setup          = skip_tx_en_setup,
1887         },
1888         {
1889                 .vendor         = PCI_VENDOR_ID_INTEL,
1890                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1891                 .subvendor      = PCI_ANY_ID,
1892                 .subdevice      = PCI_ANY_ID,
1893                 .setup          = skip_tx_en_setup,
1894         },
1895         {
1896                 .vendor         = PCI_VENDOR_ID_INTEL,
1897                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1898                 .subvendor      = PCI_ANY_ID,
1899                 .subdevice      = PCI_ANY_ID,
1900                 .setup          = ce4100_serial_setup,
1901         },
1902         {
1903                 .vendor         = PCI_VENDOR_ID_INTEL,
1904                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1905                 .subvendor      = PCI_ANY_ID,
1906                 .subdevice      = PCI_ANY_ID,
1907                 .setup          = kt_serial_setup,
1908         },
1909         {
1910                 .vendor         = PCI_VENDOR_ID_INTEL,
1911                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
1912                 .subvendor      = PCI_ANY_ID,
1913                 .subdevice      = PCI_ANY_ID,
1914                 .setup          = byt_serial_setup,
1915         },
1916         {
1917                 .vendor         = PCI_VENDOR_ID_INTEL,
1918                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
1919                 .subvendor      = PCI_ANY_ID,
1920                 .subdevice      = PCI_ANY_ID,
1921                 .setup          = byt_serial_setup,
1922         },
1923         {
1924                 .vendor         = PCI_VENDOR_ID_INTEL,
1925                 .device         = PCI_DEVICE_ID_INTEL_QRK_UART,
1926                 .subvendor      = PCI_ANY_ID,
1927                 .subdevice      = PCI_ANY_ID,
1928                 .setup          = pci_default_setup,
1929         },
1930         {
1931                 .vendor         = PCI_VENDOR_ID_INTEL,
1932                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
1933                 .subvendor      = PCI_ANY_ID,
1934                 .subdevice      = PCI_ANY_ID,
1935                 .setup          = byt_serial_setup,
1936         },
1937         {
1938                 .vendor         = PCI_VENDOR_ID_INTEL,
1939                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
1940                 .subvendor      = PCI_ANY_ID,
1941                 .subdevice      = PCI_ANY_ID,
1942                 .setup          = byt_serial_setup,
1943         },
1944         /*
1945          * ITE
1946          */
1947         {
1948                 .vendor         = PCI_VENDOR_ID_ITE,
1949                 .device         = PCI_DEVICE_ID_ITE_8872,
1950                 .subvendor      = PCI_ANY_ID,
1951                 .subdevice      = PCI_ANY_ID,
1952                 .init           = pci_ite887x_init,
1953                 .setup          = pci_default_setup,
1954                 .exit           = pci_ite887x_exit,
1955         },
1956         /*
1957          * National Instruments
1958          */
1959         {
1960                 .vendor         = PCI_VENDOR_ID_NI,
1961                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1962                 .subvendor      = PCI_ANY_ID,
1963                 .subdevice      = PCI_ANY_ID,
1964                 .init           = pci_ni8420_init,
1965                 .setup          = pci_default_setup,
1966                 .exit           = pci_ni8420_exit,
1967         },
1968         {
1969                 .vendor         = PCI_VENDOR_ID_NI,
1970                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1971                 .subvendor      = PCI_ANY_ID,
1972                 .subdevice      = PCI_ANY_ID,
1973                 .init           = pci_ni8420_init,
1974                 .setup          = pci_default_setup,
1975                 .exit           = pci_ni8420_exit,
1976         },
1977         {
1978                 .vendor         = PCI_VENDOR_ID_NI,
1979                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1980                 .subvendor      = PCI_ANY_ID,
1981                 .subdevice      = PCI_ANY_ID,
1982                 .init           = pci_ni8420_init,
1983                 .setup          = pci_default_setup,
1984                 .exit           = pci_ni8420_exit,
1985         },
1986         {
1987                 .vendor         = PCI_VENDOR_ID_NI,
1988                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1989                 .subvendor      = PCI_ANY_ID,
1990                 .subdevice      = PCI_ANY_ID,
1991                 .init           = pci_ni8420_init,
1992                 .setup          = pci_default_setup,
1993                 .exit           = pci_ni8420_exit,
1994         },
1995         {
1996                 .vendor         = PCI_VENDOR_ID_NI,
1997                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1998                 .subvendor      = PCI_ANY_ID,
1999                 .subdevice      = PCI_ANY_ID,
2000                 .init           = pci_ni8420_init,
2001                 .setup          = pci_default_setup,
2002                 .exit           = pci_ni8420_exit,
2003         },
2004         {
2005                 .vendor         = PCI_VENDOR_ID_NI,
2006                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2007                 .subvendor      = PCI_ANY_ID,
2008                 .subdevice      = PCI_ANY_ID,
2009                 .init           = pci_ni8420_init,
2010                 .setup          = pci_default_setup,
2011                 .exit           = pci_ni8420_exit,
2012         },
2013         {
2014                 .vendor         = PCI_VENDOR_ID_NI,
2015                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2016                 .subvendor      = PCI_ANY_ID,
2017                 .subdevice      = PCI_ANY_ID,
2018                 .init           = pci_ni8420_init,
2019                 .setup          = pci_default_setup,
2020                 .exit           = pci_ni8420_exit,
2021         },
2022         {
2023                 .vendor         = PCI_VENDOR_ID_NI,
2024                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2025                 .subvendor      = PCI_ANY_ID,
2026                 .subdevice      = PCI_ANY_ID,
2027                 .init           = pci_ni8420_init,
2028                 .setup          = pci_default_setup,
2029                 .exit           = pci_ni8420_exit,
2030         },
2031         {
2032                 .vendor         = PCI_VENDOR_ID_NI,
2033                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2034                 .subvendor      = PCI_ANY_ID,
2035                 .subdevice      = PCI_ANY_ID,
2036                 .init           = pci_ni8420_init,
2037                 .setup          = pci_default_setup,
2038                 .exit           = pci_ni8420_exit,
2039         },
2040         {
2041                 .vendor         = PCI_VENDOR_ID_NI,
2042                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2043                 .subvendor      = PCI_ANY_ID,
2044                 .subdevice      = PCI_ANY_ID,
2045                 .init           = pci_ni8420_init,
2046                 .setup          = pci_default_setup,
2047                 .exit           = pci_ni8420_exit,
2048         },
2049         {
2050                 .vendor         = PCI_VENDOR_ID_NI,
2051                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2052                 .subvendor      = PCI_ANY_ID,
2053                 .subdevice      = PCI_ANY_ID,
2054                 .init           = pci_ni8420_init,
2055                 .setup          = pci_default_setup,
2056                 .exit           = pci_ni8420_exit,
2057         },
2058         {
2059                 .vendor         = PCI_VENDOR_ID_NI,
2060                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2061                 .subvendor      = PCI_ANY_ID,
2062                 .subdevice      = PCI_ANY_ID,
2063                 .init           = pci_ni8420_init,
2064                 .setup          = pci_default_setup,
2065                 .exit           = pci_ni8420_exit,
2066         },
2067         {
2068                 .vendor         = PCI_VENDOR_ID_NI,
2069                 .device         = PCI_ANY_ID,
2070                 .subvendor      = PCI_ANY_ID,
2071                 .subdevice      = PCI_ANY_ID,
2072                 .init           = pci_ni8430_init,
2073                 .setup          = pci_ni8430_setup,
2074                 .exit           = pci_ni8430_exit,
2075         },
2076         /* Quatech */
2077         {
2078                 .vendor         = PCI_VENDOR_ID_QUATECH,
2079                 .device         = PCI_ANY_ID,
2080                 .subvendor      = PCI_ANY_ID,
2081                 .subdevice      = PCI_ANY_ID,
2082                 .init           = pci_quatech_init,
2083                 .setup          = pci_quatech_setup,
2084                 .exit           = pci_quatech_exit,
2085         },
2086         /*
2087          * Panacom
2088          */
2089         {
2090                 .vendor         = PCI_VENDOR_ID_PANACOM,
2091                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2092                 .subvendor      = PCI_ANY_ID,
2093                 .subdevice      = PCI_ANY_ID,
2094                 .init           = pci_plx9050_init,
2095                 .setup          = pci_default_setup,
2096                 .exit           = pci_plx9050_exit,
2097         },
2098         {
2099                 .vendor         = PCI_VENDOR_ID_PANACOM,
2100                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2101                 .subvendor      = PCI_ANY_ID,
2102                 .subdevice      = PCI_ANY_ID,
2103                 .init           = pci_plx9050_init,
2104                 .setup          = pci_default_setup,
2105                 .exit           = pci_plx9050_exit,
2106         },
2107         /*
2108          * Pericom
2109          */
2110         {
2111                 .vendor         = 0x12d8,
2112                 .device         = 0x7952,
2113                 .subvendor      = PCI_ANY_ID,
2114                 .subdevice      = PCI_ANY_ID,
2115                 .setup          = pci_pericom_setup,
2116         },
2117         {
2118                 .vendor         = 0x12d8,
2119                 .device         = 0x7954,
2120                 .subvendor      = PCI_ANY_ID,
2121                 .subdevice      = PCI_ANY_ID,
2122                 .setup          = pci_pericom_setup,
2123         },
2124         {
2125                 .vendor         = 0x12d8,
2126                 .device         = 0x7958,
2127                 .subvendor      = PCI_ANY_ID,
2128                 .subdevice      = PCI_ANY_ID,
2129                 .setup          = pci_pericom_setup,
2130         },
2131
2132         /*
2133          * PLX
2134          */
2135         {
2136                 .vendor         = PCI_VENDOR_ID_PLX,
2137                 .device         = PCI_DEVICE_ID_PLX_9030,
2138                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
2139                 .subdevice      = PCI_ANY_ID,
2140                 .setup          = pci_default_setup,
2141         },
2142         {
2143                 .vendor         = PCI_VENDOR_ID_PLX,
2144                 .device         = PCI_DEVICE_ID_PLX_9050,
2145                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2146                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2147                 .init           = pci_plx9050_init,
2148                 .setup          = pci_default_setup,
2149                 .exit           = pci_plx9050_exit,
2150         },
2151         {
2152                 .vendor         = PCI_VENDOR_ID_PLX,
2153                 .device         = PCI_DEVICE_ID_PLX_9050,
2154                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2155                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2156                 .init           = pci_plx9050_init,
2157                 .setup          = pci_default_setup,
2158                 .exit           = pci_plx9050_exit,
2159         },
2160         {
2161                 .vendor         = PCI_VENDOR_ID_PLX,
2162                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2163                 .subvendor      = PCI_VENDOR_ID_PLX,
2164                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2165                 .init           = pci_plx9050_init,
2166                 .setup          = pci_default_setup,
2167                 .exit           = pci_plx9050_exit,
2168         },
2169         /*
2170          * SBS Technologies, Inc., PMC-OCTALPRO 232
2171          */
2172         {
2173                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2174                 .device         = PCI_DEVICE_ID_OCTPRO,
2175                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2176                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2177                 .init           = sbs_init,
2178                 .setup          = sbs_setup,
2179                 .exit           = sbs_exit,
2180         },
2181         /*
2182          * SBS Technologies, Inc., PMC-OCTALPRO 422
2183          */
2184         {
2185                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2186                 .device         = PCI_DEVICE_ID_OCTPRO,
2187                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2188                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2189                 .init           = sbs_init,
2190                 .setup          = sbs_setup,
2191                 .exit           = sbs_exit,
2192         },
2193         /*
2194          * SBS Technologies, Inc., P-Octal 232
2195          */
2196         {
2197                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2198                 .device         = PCI_DEVICE_ID_OCTPRO,
2199                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2200                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2201                 .init           = sbs_init,
2202                 .setup          = sbs_setup,
2203                 .exit           = sbs_exit,
2204         },
2205         /*
2206          * SBS Technologies, Inc., P-Octal 422
2207          */
2208         {
2209                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2210                 .device         = PCI_DEVICE_ID_OCTPRO,
2211                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2212                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2213                 .init           = sbs_init,
2214                 .setup          = sbs_setup,
2215                 .exit           = sbs_exit,
2216         },
2217         /*
2218          * SIIG cards - these may be called via parport_serial
2219          */
2220         {
2221                 .vendor         = PCI_VENDOR_ID_SIIG,
2222                 .device         = PCI_ANY_ID,
2223                 .subvendor      = PCI_ANY_ID,
2224                 .subdevice      = PCI_ANY_ID,
2225                 .init           = pci_siig_init,
2226                 .setup          = pci_siig_setup,
2227         },
2228         /*
2229          * Titan cards
2230          */
2231         {
2232                 .vendor         = PCI_VENDOR_ID_TITAN,
2233                 .device         = PCI_DEVICE_ID_TITAN_400L,
2234                 .subvendor      = PCI_ANY_ID,
2235                 .subdevice      = PCI_ANY_ID,
2236                 .setup          = titan_400l_800l_setup,
2237         },
2238         {
2239                 .vendor         = PCI_VENDOR_ID_TITAN,
2240                 .device         = PCI_DEVICE_ID_TITAN_800L,
2241                 .subvendor      = PCI_ANY_ID,
2242                 .subdevice      = PCI_ANY_ID,
2243                 .setup          = titan_400l_800l_setup,
2244         },
2245         /*
2246          * Timedia cards
2247          */
2248         {
2249                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2250                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2251                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2252                 .subdevice      = PCI_ANY_ID,
2253                 .probe          = pci_timedia_probe,
2254                 .init           = pci_timedia_init,
2255                 .setup          = pci_timedia_setup,
2256         },
2257         {
2258                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2259                 .device         = PCI_ANY_ID,
2260                 .subvendor      = PCI_ANY_ID,
2261                 .subdevice      = PCI_ANY_ID,
2262                 .setup          = pci_timedia_setup,
2263         },
2264         /*
2265          * SUNIX (Timedia) cards
2266          * Do not "probe" for these cards as there is at least one combination
2267          * card that should be handled by parport_pc that doesn't match the
2268          * rule in pci_timedia_probe.
2269          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2270          * There are some boards with part number SER5037AL that report
2271          * subdevice ID 0x0002.
2272          */
2273         {
2274                 .vendor         = PCI_VENDOR_ID_SUNIX,
2275                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2276                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2277                 .subdevice      = PCI_ANY_ID,
2278                 .init           = pci_timedia_init,
2279                 .setup          = pci_timedia_setup,
2280         },
2281         /*
2282          * Exar cards
2283          */
2284         {
2285                 .vendor = PCI_VENDOR_ID_EXAR,
2286                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2287                 .subvendor      = PCI_ANY_ID,
2288                 .subdevice      = PCI_ANY_ID,
2289                 .setup          = pci_xr17c154_setup,
2290         },
2291         {
2292                 .vendor = PCI_VENDOR_ID_EXAR,
2293                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2294                 .subvendor      = PCI_ANY_ID,
2295                 .subdevice      = PCI_ANY_ID,
2296                 .setup          = pci_xr17c154_setup,
2297         },
2298         {
2299                 .vendor = PCI_VENDOR_ID_EXAR,
2300                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2301                 .subvendor      = PCI_ANY_ID,
2302                 .subdevice      = PCI_ANY_ID,
2303                 .setup          = pci_xr17c154_setup,
2304         },
2305         {
2306                 .vendor = PCI_VENDOR_ID_EXAR,
2307                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2308                 .subvendor      = PCI_ANY_ID,
2309                 .subdevice      = PCI_ANY_ID,
2310                 .setup          = pci_xr17v35x_setup,
2311         },
2312         {
2313                 .vendor = PCI_VENDOR_ID_EXAR,
2314                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2315                 .subvendor      = PCI_ANY_ID,
2316                 .subdevice      = PCI_ANY_ID,
2317                 .setup          = pci_xr17v35x_setup,
2318         },
2319         {
2320                 .vendor = PCI_VENDOR_ID_EXAR,
2321                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2322                 .subvendor      = PCI_ANY_ID,
2323                 .subdevice      = PCI_ANY_ID,
2324                 .setup          = pci_xr17v35x_setup,
2325         },
2326         /*
2327          * Xircom cards
2328          */
2329         {
2330                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2331                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2332                 .subvendor      = PCI_ANY_ID,
2333                 .subdevice      = PCI_ANY_ID,
2334                 .init           = pci_xircom_init,
2335                 .setup          = pci_default_setup,
2336         },
2337         /*
2338          * Netmos cards - these may be called via parport_serial
2339          */
2340         {
2341                 .vendor         = PCI_VENDOR_ID_NETMOS,
2342                 .device         = PCI_ANY_ID,
2343                 .subvendor      = PCI_ANY_ID,
2344                 .subdevice      = PCI_ANY_ID,
2345                 .init           = pci_netmos_init,
2346                 .setup          = pci_netmos_9900_setup,
2347         },
2348         /*
2349          * For Oxford Semiconductor Tornado based devices
2350          */
2351         {
2352                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2353                 .device         = PCI_ANY_ID,
2354                 .subvendor      = PCI_ANY_ID,
2355                 .subdevice      = PCI_ANY_ID,
2356                 .init           = pci_oxsemi_tornado_init,
2357                 .setup          = pci_default_setup,
2358         },
2359         {
2360                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2361                 .device         = PCI_ANY_ID,
2362                 .subvendor      = PCI_ANY_ID,
2363                 .subdevice      = PCI_ANY_ID,
2364                 .init           = pci_oxsemi_tornado_init,
2365                 .setup          = pci_default_setup,
2366         },
2367         {
2368                 .vendor         = PCI_VENDOR_ID_DIGI,
2369                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2370                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2371                 .subdevice              = PCI_ANY_ID,
2372                 .init                   = pci_oxsemi_tornado_init,
2373                 .setup          = pci_default_setup,
2374         },
2375         {
2376                 .vendor         = PCI_VENDOR_ID_INTEL,
2377                 .device         = 0x8811,
2378                 .subvendor      = PCI_ANY_ID,
2379                 .subdevice      = PCI_ANY_ID,
2380                 .init           = pci_eg20t_init,
2381                 .setup          = pci_default_setup,
2382         },
2383         {
2384                 .vendor         = PCI_VENDOR_ID_INTEL,
2385                 .device         = 0x8812,
2386                 .subvendor      = PCI_ANY_ID,
2387                 .subdevice      = PCI_ANY_ID,
2388                 .init           = pci_eg20t_init,
2389                 .setup          = pci_default_setup,
2390         },
2391         {
2392                 .vendor         = PCI_VENDOR_ID_INTEL,
2393                 .device         = 0x8813,
2394                 .subvendor      = PCI_ANY_ID,
2395                 .subdevice      = PCI_ANY_ID,
2396                 .init           = pci_eg20t_init,
2397                 .setup          = pci_default_setup,
2398         },
2399         {
2400                 .vendor         = PCI_VENDOR_ID_INTEL,
2401                 .device         = 0x8814,
2402                 .subvendor      = PCI_ANY_ID,
2403                 .subdevice      = PCI_ANY_ID,
2404                 .init           = pci_eg20t_init,
2405                 .setup          = pci_default_setup,
2406         },
2407         {
2408                 .vendor         = 0x10DB,
2409                 .device         = 0x8027,
2410                 .subvendor      = PCI_ANY_ID,
2411                 .subdevice      = PCI_ANY_ID,
2412                 .init           = pci_eg20t_init,
2413                 .setup          = pci_default_setup,
2414         },
2415         {
2416                 .vendor         = 0x10DB,
2417                 .device         = 0x8028,
2418                 .subvendor      = PCI_ANY_ID,
2419                 .subdevice      = PCI_ANY_ID,
2420                 .init           = pci_eg20t_init,
2421                 .setup          = pci_default_setup,
2422         },
2423         {
2424                 .vendor         = 0x10DB,
2425                 .device         = 0x8029,
2426                 .subvendor      = PCI_ANY_ID,
2427                 .subdevice      = PCI_ANY_ID,
2428                 .init           = pci_eg20t_init,
2429                 .setup          = pci_default_setup,
2430         },
2431         {
2432                 .vendor         = 0x10DB,
2433                 .device         = 0x800C,
2434                 .subvendor      = PCI_ANY_ID,
2435                 .subdevice      = PCI_ANY_ID,
2436                 .init           = pci_eg20t_init,
2437                 .setup          = pci_default_setup,
2438         },
2439         {
2440                 .vendor         = 0x10DB,
2441                 .device         = 0x800D,
2442                 .subvendor      = PCI_ANY_ID,
2443                 .subdevice      = PCI_ANY_ID,
2444                 .init           = pci_eg20t_init,
2445                 .setup          = pci_default_setup,
2446         },
2447         /*
2448          * Cronyx Omega PCI (PLX-chip based)
2449          */
2450         {
2451                 .vendor         = PCI_VENDOR_ID_PLX,
2452                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2453                 .subvendor      = PCI_ANY_ID,
2454                 .subdevice      = PCI_ANY_ID,
2455                 .setup          = pci_omegapci_setup,
2456         },
2457         /* WCH CH353 1S1P card (16550 clone) */
2458         {
2459                 .vendor         = PCI_VENDOR_ID_WCH,
2460                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2461                 .subvendor      = PCI_ANY_ID,
2462                 .subdevice      = PCI_ANY_ID,
2463                 .setup          = pci_wch_ch353_setup,
2464         },
2465         /* WCH CH353 2S1P card (16550 clone) */
2466         {
2467                 .vendor         = PCI_VENDOR_ID_WCH,
2468                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2469                 .subvendor      = PCI_ANY_ID,
2470                 .subdevice      = PCI_ANY_ID,
2471                 .setup          = pci_wch_ch353_setup,
2472         },
2473         /* WCH CH353 4S card (16550 clone) */
2474         {
2475                 .vendor         = PCI_VENDOR_ID_WCH,
2476                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2477                 .subvendor      = PCI_ANY_ID,
2478                 .subdevice      = PCI_ANY_ID,
2479                 .setup          = pci_wch_ch353_setup,
2480         },
2481         /* WCH CH353 2S1PF card (16550 clone) */
2482         {
2483                 .vendor         = PCI_VENDOR_ID_WCH,
2484                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2485                 .subvendor      = PCI_ANY_ID,
2486                 .subdevice      = PCI_ANY_ID,
2487                 .setup          = pci_wch_ch353_setup,
2488         },
2489         /* WCH CH352 2S card (16550 clone) */
2490         {
2491                 .vendor         = PCI_VENDOR_ID_WCH,
2492                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2493                 .subvendor      = PCI_ANY_ID,
2494                 .subdevice      = PCI_ANY_ID,
2495                 .setup          = pci_wch_ch353_setup,
2496         },
2497         /*
2498          * ASIX devices with FIFO bug
2499          */
2500         {
2501                 .vendor         = PCI_VENDOR_ID_ASIX,
2502                 .device         = PCI_ANY_ID,
2503                 .subvendor      = PCI_ANY_ID,
2504                 .subdevice      = PCI_ANY_ID,
2505                 .setup          = pci_asix_setup,
2506         },
2507         /*
2508          * Commtech, Inc. Fastcom adapters
2509          *
2510          */
2511         {
2512                 .vendor = PCI_VENDOR_ID_COMMTECH,
2513                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2514                 .subvendor      = PCI_ANY_ID,
2515                 .subdevice      = PCI_ANY_ID,
2516                 .setup          = pci_fastcom335_setup,
2517         },
2518         {
2519                 .vendor = PCI_VENDOR_ID_COMMTECH,
2520                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2521                 .subvendor      = PCI_ANY_ID,
2522                 .subdevice      = PCI_ANY_ID,
2523                 .setup          = pci_fastcom335_setup,
2524         },
2525         {
2526                 .vendor = PCI_VENDOR_ID_COMMTECH,
2527                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2528                 .subvendor      = PCI_ANY_ID,
2529                 .subdevice      = PCI_ANY_ID,
2530                 .setup          = pci_fastcom335_setup,
2531         },
2532         {
2533                 .vendor = PCI_VENDOR_ID_COMMTECH,
2534                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2535                 .subvendor      = PCI_ANY_ID,
2536                 .subdevice      = PCI_ANY_ID,
2537                 .setup          = pci_fastcom335_setup,
2538         },
2539         {
2540                 .vendor = PCI_VENDOR_ID_COMMTECH,
2541                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2542                 .subvendor      = PCI_ANY_ID,
2543                 .subdevice      = PCI_ANY_ID,
2544                 .setup          = pci_xr17v35x_setup,
2545         },
2546         {
2547                 .vendor = PCI_VENDOR_ID_COMMTECH,
2548                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2549                 .subvendor      = PCI_ANY_ID,
2550                 .subdevice      = PCI_ANY_ID,
2551                 .setup          = pci_xr17v35x_setup,
2552         },
2553         {
2554                 .vendor = PCI_VENDOR_ID_COMMTECH,
2555                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2556                 .subvendor      = PCI_ANY_ID,
2557                 .subdevice      = PCI_ANY_ID,
2558                 .setup          = pci_xr17v35x_setup,
2559         },
2560         /*
2561          * Broadcom TruManage (NetXtreme)
2562          */
2563         {
2564                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2565                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2566                 .subvendor      = PCI_ANY_ID,
2567                 .subdevice      = PCI_ANY_ID,
2568                 .setup          = pci_brcm_trumanage_setup,
2569         },
2570         {
2571                 .vendor         = 0x1c29,
2572                 .device         = 0x1104,
2573                 .subvendor      = PCI_ANY_ID,
2574                 .subdevice      = PCI_ANY_ID,
2575                 .setup          = pci_fintek_setup,
2576         },
2577         {
2578                 .vendor         = 0x1c29,
2579                 .device         = 0x1108,
2580                 .subvendor      = PCI_ANY_ID,
2581                 .subdevice      = PCI_ANY_ID,
2582                 .setup          = pci_fintek_setup,
2583         },
2584         {
2585                 .vendor         = 0x1c29,
2586                 .device         = 0x1112,
2587                 .subvendor      = PCI_ANY_ID,
2588                 .subdevice      = PCI_ANY_ID,
2589                 .setup          = pci_fintek_setup,
2590         },
2591
2592         /*
2593          * Default "match everything" terminator entry
2594          */
2595         {
2596                 .vendor         = PCI_ANY_ID,
2597                 .device         = PCI_ANY_ID,
2598                 .subvendor      = PCI_ANY_ID,
2599                 .subdevice      = PCI_ANY_ID,
2600                 .setup          = pci_default_setup,
2601         }
2602 };
2603
2604 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2605 {
2606         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2607 }
2608
2609 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2610 {
2611         struct pci_serial_quirk *quirk;
2612
2613         for (quirk = pci_serial_quirks; ; quirk++)
2614                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2615                     quirk_id_matches(quirk->device, dev->device) &&
2616                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2617                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2618                         break;
2619         return quirk;
2620 }
2621
2622 static inline int get_pci_irq(struct pci_dev *dev,
2623                                 const struct pciserial_board *board)
2624 {
2625         if (board->flags & FL_NOIRQ)
2626                 return 0;
2627         else
2628                 return dev->irq;
2629 }
2630
2631 /*
2632  * This is the configuration table for all of the PCI serial boards
2633  * which we support.  It is directly indexed by the pci_board_num_t enum
2634  * value, which is encoded in the pci_device_id PCI probe table's
2635  * driver_data member.
2636  *
2637  * The makeup of these names are:
2638  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2639  *
2640  *  bn          = PCI BAR number
2641  *  bt          = Index using PCI BARs
2642  *  n           = number of serial ports
2643  *  baud        = baud rate
2644  *  offsetinhex = offset for each sequential port (in hex)
2645  *
2646  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2647  *
2648  * Please note: in theory if n = 1, _bt infix should make no difference.
2649  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2650  */
2651 enum pci_board_num_t {
2652         pbn_default = 0,
2653
2654         pbn_b0_1_115200,
2655         pbn_b0_2_115200,
2656         pbn_b0_4_115200,
2657         pbn_b0_5_115200,
2658         pbn_b0_8_115200,
2659
2660         pbn_b0_1_921600,
2661         pbn_b0_2_921600,
2662         pbn_b0_4_921600,
2663
2664         pbn_b0_2_1130000,
2665
2666         pbn_b0_4_1152000,
2667
2668         pbn_b0_2_1152000_200,
2669         pbn_b0_4_1152000_200,
2670         pbn_b0_8_1152000_200,
2671
2672         pbn_b0_2_1843200,
2673         pbn_b0_4_1843200,
2674
2675         pbn_b0_2_1843200_200,
2676         pbn_b0_4_1843200_200,
2677         pbn_b0_8_1843200_200,
2678
2679         pbn_b0_1_4000000,
2680
2681         pbn_b0_bt_1_115200,
2682         pbn_b0_bt_2_115200,
2683         pbn_b0_bt_4_115200,
2684         pbn_b0_bt_8_115200,
2685
2686         pbn_b0_bt_1_460800,
2687         pbn_b0_bt_2_460800,
2688         pbn_b0_bt_4_460800,
2689
2690         pbn_b0_bt_1_921600,
2691         pbn_b0_bt_2_921600,
2692         pbn_b0_bt_4_921600,
2693         pbn_b0_bt_8_921600,
2694
2695         pbn_b1_1_115200,
2696         pbn_b1_2_115200,
2697         pbn_b1_4_115200,
2698         pbn_b1_8_115200,
2699         pbn_b1_16_115200,
2700
2701         pbn_b1_1_921600,
2702         pbn_b1_2_921600,
2703         pbn_b1_4_921600,
2704         pbn_b1_8_921600,
2705
2706         pbn_b1_2_1250000,
2707
2708         pbn_b1_bt_1_115200,
2709         pbn_b1_bt_2_115200,
2710         pbn_b1_bt_4_115200,
2711
2712         pbn_b1_bt_2_921600,
2713
2714         pbn_b1_1_1382400,
2715         pbn_b1_2_1382400,
2716         pbn_b1_4_1382400,
2717         pbn_b1_8_1382400,
2718
2719         pbn_b2_1_115200,
2720         pbn_b2_2_115200,
2721         pbn_b2_4_115200,
2722         pbn_b2_8_115200,
2723
2724         pbn_b2_1_460800,
2725         pbn_b2_4_460800,
2726         pbn_b2_8_460800,
2727         pbn_b2_16_460800,
2728
2729         pbn_b2_1_921600,
2730         pbn_b2_4_921600,
2731         pbn_b2_8_921600,
2732
2733         pbn_b2_8_1152000,
2734
2735         pbn_b2_bt_1_115200,
2736         pbn_b2_bt_2_115200,
2737         pbn_b2_bt_4_115200,
2738
2739         pbn_b2_bt_2_921600,
2740         pbn_b2_bt_4_921600,
2741
2742         pbn_b3_2_115200,
2743         pbn_b3_4_115200,
2744         pbn_b3_8_115200,
2745
2746         pbn_b4_bt_2_921600,
2747         pbn_b4_bt_4_921600,
2748         pbn_b4_bt_8_921600,
2749
2750         /*
2751          * Board-specific versions.
2752          */
2753         pbn_panacom,
2754         pbn_panacom2,
2755         pbn_panacom4,
2756         pbn_plx_romulus,
2757         pbn_oxsemi,
2758         pbn_oxsemi_1_4000000,
2759         pbn_oxsemi_2_4000000,
2760         pbn_oxsemi_4_4000000,
2761         pbn_oxsemi_8_4000000,
2762         pbn_intel_i960,
2763         pbn_sgi_ioc3,
2764         pbn_computone_4,
2765         pbn_computone_6,
2766         pbn_computone_8,
2767         pbn_sbsxrsio,
2768         pbn_exar_XR17C152,
2769         pbn_exar_XR17C154,
2770         pbn_exar_XR17C158,
2771         pbn_exar_XR17V352,
2772         pbn_exar_XR17V354,
2773         pbn_exar_XR17V358,
2774         pbn_exar_ibm_saturn,
2775         pbn_pasemi_1682M,
2776         pbn_ni8430_2,
2777         pbn_ni8430_4,
2778         pbn_ni8430_8,
2779         pbn_ni8430_16,
2780         pbn_ADDIDATA_PCIe_1_3906250,
2781         pbn_ADDIDATA_PCIe_2_3906250,
2782         pbn_ADDIDATA_PCIe_4_3906250,
2783         pbn_ADDIDATA_PCIe_8_3906250,
2784         pbn_ce4100_1_115200,
2785         pbn_byt,
2786         pbn_qrk,
2787         pbn_omegapci,
2788         pbn_NETMOS9900_2s_115200,
2789         pbn_brcm_trumanage,
2790         pbn_fintek_4,
2791         pbn_fintek_8,
2792         pbn_fintek_12,
2793 };
2794
2795 /*
2796  * uart_offset - the space between channels
2797  * reg_shift   - describes how the UART registers are mapped
2798  *               to PCI memory by the card.
2799  * For example IER register on SBS, Inc. PMC-OctPro is located at
2800  * offset 0x10 from the UART base, while UART_IER is defined as 1
2801  * in include/linux/serial_reg.h,
2802  * see first lines of serial_in() and serial_out() in 8250.c
2803 */
2804
2805 static struct pciserial_board pci_boards[] = {
2806         [pbn_default] = {
2807                 .flags          = FL_BASE0,
2808                 .num_ports      = 1,
2809                 .base_baud      = 115200,
2810                 .uart_offset    = 8,
2811         },
2812         [pbn_b0_1_115200] = {
2813                 .flags          = FL_BASE0,
2814                 .num_ports      = 1,
2815                 .base_baud      = 115200,
2816                 .uart_offset    = 8,
2817         },
2818         [pbn_b0_2_115200] = {
2819                 .flags          = FL_BASE0,
2820                 .num_ports      = 2,
2821                 .base_baud      = 115200,
2822                 .uart_offset    = 8,
2823         },
2824         [pbn_b0_4_115200] = {
2825                 .flags          = FL_BASE0,
2826                 .num_ports      = 4,
2827                 .base_baud      = 115200,
2828                 .uart_offset    = 8,
2829         },
2830         [pbn_b0_5_115200] = {
2831                 .flags          = FL_BASE0,
2832                 .num_ports      = 5,
2833                 .base_baud      = 115200,
2834                 .uart_offset    = 8,
2835         },
2836         [pbn_b0_8_115200] = {
2837                 .flags          = FL_BASE0,
2838                 .num_ports      = 8,
2839                 .base_baud      = 115200,
2840                 .uart_offset    = 8,
2841         },
2842         [pbn_b0_1_921600] = {
2843                 .flags          = FL_BASE0,
2844                 .num_ports      = 1,
2845                 .base_baud      = 921600,
2846                 .uart_offset    = 8,
2847         },
2848         [pbn_b0_2_921600] = {
2849                 .flags          = FL_BASE0,
2850                 .num_ports      = 2,
2851                 .base_baud      = 921600,
2852                 .uart_offset    = 8,
2853         },
2854         [pbn_b0_4_921600] = {
2855                 .flags          = FL_BASE0,
2856                 .num_ports      = 4,
2857                 .base_baud      = 921600,
2858                 .uart_offset    = 8,
2859         },
2860
2861         [pbn_b0_2_1130000] = {
2862                 .flags          = FL_BASE0,
2863                 .num_ports      = 2,
2864                 .base_baud      = 1130000,
2865                 .uart_offset    = 8,
2866         },
2867
2868         [pbn_b0_4_1152000] = {
2869                 .flags          = FL_BASE0,
2870                 .num_ports      = 4,
2871                 .base_baud      = 1152000,
2872                 .uart_offset    = 8,
2873         },
2874
2875         [pbn_b0_2_1152000_200] = {
2876                 .flags          = FL_BASE0,
2877                 .num_ports      = 2,
2878                 .base_baud      = 1152000,
2879                 .uart_offset    = 0x200,
2880         },
2881
2882         [pbn_b0_4_1152000_200] = {
2883                 .flags          = FL_BASE0,
2884                 .num_ports      = 4,
2885                 .base_baud      = 1152000,
2886                 .uart_offset    = 0x200,
2887         },
2888
2889         [pbn_b0_8_1152000_200] = {
2890                 .flags          = FL_BASE0,
2891                 .num_ports      = 8,
2892                 .base_baud      = 1152000,
2893                 .uart_offset    = 0x200,
2894         },
2895
2896         [pbn_b0_2_1843200] = {
2897                 .flags          = FL_BASE0,
2898                 .num_ports      = 2,
2899                 .base_baud      = 1843200,
2900                 .uart_offset    = 8,
2901         },
2902         [pbn_b0_4_1843200] = {
2903                 .flags          = FL_BASE0,
2904                 .num_ports      = 4,
2905                 .base_baud      = 1843200,
2906                 .uart_offset    = 8,
2907         },
2908
2909         [pbn_b0_2_1843200_200] = {
2910                 .flags          = FL_BASE0,
2911                 .num_ports      = 2,
2912                 .base_baud      = 1843200,
2913                 .uart_offset    = 0x200,
2914         },
2915         [pbn_b0_4_1843200_200] = {
2916                 .flags          = FL_BASE0,
2917                 .num_ports      = 4,
2918                 .base_baud      = 1843200,
2919                 .uart_offset    = 0x200,
2920         },
2921         [pbn_b0_8_1843200_200] = {
2922                 .flags          = FL_BASE0,
2923                 .num_ports      = 8,
2924                 .base_baud      = 1843200,
2925                 .uart_offset    = 0x200,
2926         },
2927         [pbn_b0_1_4000000] = {
2928                 .flags          = FL_BASE0,
2929                 .num_ports      = 1,
2930                 .base_baud      = 4000000,
2931                 .uart_offset    = 8,
2932         },
2933
2934         [pbn_b0_bt_1_115200] = {
2935                 .flags          = FL_BASE0|FL_BASE_BARS,
2936                 .num_ports      = 1,
2937                 .base_baud      = 115200,
2938                 .uart_offset    = 8,
2939         },
2940         [pbn_b0_bt_2_115200] = {
2941                 .flags          = FL_BASE0|FL_BASE_BARS,
2942                 .num_ports      = 2,
2943                 .base_baud      = 115200,
2944                 .uart_offset    = 8,
2945         },
2946         [pbn_b0_bt_4_115200] = {
2947                 .flags          = FL_BASE0|FL_BASE_BARS,
2948                 .num_ports      = 4,
2949                 .base_baud      = 115200,
2950                 .uart_offset    = 8,
2951         },
2952         [pbn_b0_bt_8_115200] = {
2953                 .flags          = FL_BASE0|FL_BASE_BARS,
2954                 .num_ports      = 8,
2955                 .base_baud      = 115200,
2956                 .uart_offset    = 8,
2957         },
2958
2959         [pbn_b0_bt_1_460800] = {
2960                 .flags          = FL_BASE0|FL_BASE_BARS,
2961                 .num_ports      = 1,
2962                 .base_baud      = 460800,
2963                 .uart_offset    = 8,
2964         },
2965         [pbn_b0_bt_2_460800] = {
2966                 .flags          = FL_BASE0|FL_BASE_BARS,
2967                 .num_ports      = 2,
2968                 .base_baud      = 460800,
2969                 .uart_offset    = 8,
2970         },
2971         [pbn_b0_bt_4_460800] = {
2972                 .flags          = FL_BASE0|FL_BASE_BARS,
2973                 .num_ports      = 4,
2974                 .base_baud      = 460800,
2975                 .uart_offset    = 8,
2976         },
2977
2978         [pbn_b0_bt_1_921600] = {
2979                 .flags          = FL_BASE0|FL_BASE_BARS,
2980                 .num_ports      = 1,
2981                 .base_baud      = 921600,
2982                 .uart_offset    = 8,
2983         },
2984         [pbn_b0_bt_2_921600] = {
2985                 .flags          = FL_BASE0|FL_BASE_BARS,
2986                 .num_ports      = 2,
2987                 .base_baud      = 921600,
2988                 .uart_offset    = 8,
2989         },
2990         [pbn_b0_bt_4_921600] = {
2991                 .flags          = FL_BASE0|FL_BASE_BARS,
2992                 .num_ports      = 4,
2993                 .base_baud      = 921600,
2994                 .uart_offset    = 8,
2995         },
2996         [pbn_b0_bt_8_921600] = {
2997                 .flags          = FL_BASE0|FL_BASE_BARS,
2998                 .num_ports      = 8,
2999                 .base_baud      = 921600,
3000                 .uart_offset    = 8,
3001         },
3002
3003         [pbn_b1_1_115200] = {
3004                 .flags          = FL_BASE1,
3005                 .num_ports      = 1,
3006                 .base_baud      = 115200,
3007                 .uart_offset    = 8,
3008         },
3009         [pbn_b1_2_115200] = {
3010                 .flags          = FL_BASE1,
3011                 .num_ports      = 2,
3012                 .base_baud      = 115200,
3013                 .uart_offset    = 8,
3014         },
3015         [pbn_b1_4_115200] = {
3016                 .flags          = FL_BASE1,
3017                 .num_ports      = 4,
3018                 .base_baud      = 115200,
3019                 .uart_offset    = 8,
3020         },
3021         [pbn_b1_8_115200] = {
3022                 .flags          = FL_BASE1,
3023                 .num_ports      = 8,
3024                 .base_baud      = 115200,
3025                 .uart_offset    = 8,
3026         },
3027         [pbn_b1_16_115200] = {
3028                 .flags          = FL_BASE1,
3029                 .num_ports      = 16,
3030                 .base_baud      = 115200,
3031                 .uart_offset    = 8,
3032         },
3033
3034         [pbn_b1_1_921600] = {
3035                 .flags          = FL_BASE1,
3036                 .num_ports      = 1,
3037                 .base_baud      = 921600,
3038                 .uart_offset    = 8,
3039         },
3040         [pbn_b1_2_921600] = {
3041                 .flags          = FL_BASE1,
3042                 .num_ports      = 2,
3043                 .base_baud      = 921600,
3044                 .uart_offset    = 8,
3045         },
3046         [pbn_b1_4_921600] = {
3047                 .flags          = FL_BASE1,
3048                 .num_ports      = 4,
3049                 .base_baud      = 921600,
3050                 .uart_offset    = 8,
3051         },
3052         [pbn_b1_8_921600] = {
3053                 .flags          = FL_BASE1,
3054                 .num_ports      = 8,
3055                 .base_baud      = 921600,
3056                 .uart_offset    = 8,
3057         },
3058         [pbn_b1_2_1250000] = {
3059                 .flags          = FL_BASE1,
3060                 .num_ports      = 2,
3061                 .base_baud      = 1250000,
3062                 .uart_offset    = 8,
3063         },
3064
3065         [pbn_b1_bt_1_115200] = {
3066                 .flags          = FL_BASE1|FL_BASE_BARS,
3067                 .num_ports      = 1,
3068                 .base_baud      = 115200,
3069                 .uart_offset    = 8,
3070         },
3071         [pbn_b1_bt_2_115200] = {
3072                 .flags          = FL_BASE1|FL_BASE_BARS,
3073                 .num_ports      = 2,
3074                 .base_baud      = 115200,
3075                 .uart_offset    = 8,
3076         },
3077         [pbn_b1_bt_4_115200] = {
3078                 .flags          = FL_BASE1|FL_BASE_BARS,
3079                 .num_ports      = 4,
3080                 .base_baud      = 115200,
3081                 .uart_offset    = 8,
3082         },
3083
3084         [pbn_b1_bt_2_921600] = {
3085                 .flags          = FL_BASE1|FL_BASE_BARS,
3086                 .num_ports      = 2,
3087                 .base_baud      = 921600,
3088                 .uart_offset    = 8,
3089         },
3090
3091         [pbn_b1_1_1382400] = {
3092                 .flags          = FL_BASE1,
3093                 .num_ports      = 1,
3094                 .base_baud      = 1382400,
3095                 .uart_offset    = 8,
3096         },
3097         [pbn_b1_2_1382400] = {
3098                 .flags          = FL_BASE1,
3099                 .num_ports      = 2,
3100                 .base_baud      = 1382400,
3101                 .uart_offset    = 8,
3102         },
3103         [pbn_b1_4_1382400] = {
3104                 .flags          = FL_BASE1,
3105                 .num_ports      = 4,
3106                 .base_baud      = 1382400,
3107                 .uart_offset    = 8,
3108         },
3109         [pbn_b1_8_1382400] = {
3110                 .flags          = FL_BASE1,
3111                 .num_ports      = 8,
3112                 .base_baud      = 1382400,
3113                 .uart_offset    = 8,
3114         },
3115
3116         [pbn_b2_1_115200] = {
3117                 .flags          = FL_BASE2,
3118                 .num_ports      = 1,
3119                 .base_baud      = 115200,
3120                 .uart_offset    = 8,
3121         },
3122         [pbn_b2_2_115200] = {
3123                 .flags          = FL_BASE2,
3124                 .num_ports      = 2,
3125                 .base_baud      = 115200,
3126                 .uart_offset    = 8,
3127         },
3128         [pbn_b2_4_115200] = {
3129                 .flags          = FL_BASE2,
3130                 .num_ports      = 4,
3131                 .base_baud      = 115200,
3132                 .uart_offset    = 8,
3133         },
3134         [pbn_b2_8_115200] = {
3135                 .flags          = FL_BASE2,
3136                 .num_ports      = 8,
3137                 .base_baud      = 115200,
3138                 .uart_offset    = 8,
3139         },
3140
3141         [pbn_b2_1_460800] = {
3142                 .flags          = FL_BASE2,
3143                 .num_ports      = 1,
3144                 .base_baud      = 460800,
3145                 .uart_offset    = 8,
3146         },
3147         [pbn_b2_4_460800] = {
3148                 .flags          = FL_BASE2,
3149                 .num_ports      = 4,
3150                 .base_baud      = 460800,
3151                 .uart_offset    = 8,
3152         },
3153         [pbn_b2_8_460800] = {
3154                 .flags          = FL_BASE2,
3155                 .num_ports      = 8,
3156                 .base_baud      = 460800,
3157                 .uart_offset    = 8,
3158         },
3159         [pbn_b2_16_460800] = {
3160                 .flags          = FL_BASE2,
3161                 .num_ports      = 16,
3162                 .base_baud      = 460800,
3163                 .uart_offset    = 8,
3164          },
3165
3166         [pbn_b2_1_921600] = {
3167                 .flags          = FL_BASE2,
3168                 .num_ports      = 1,
3169                 .base_baud      = 921600,
3170                 .uart_offset    = 8,
3171         },
3172         [pbn_b2_4_921600] = {
3173                 .flags          = FL_BASE2,
3174                 .num_ports      = 4,
3175                 .base_baud      = 921600,
3176                 .uart_offset    = 8,
3177         },
3178         [pbn_b2_8_921600] = {
3179                 .flags          = FL_BASE2,
3180                 .num_ports      = 8,
3181                 .base_baud      = 921600,
3182                 .uart_offset    = 8,
3183         },
3184
3185         [pbn_b2_8_1152000] = {
3186                 .flags          = FL_BASE2,
3187                 .num_ports      = 8,
3188                 .base_baud      = 1152000,
3189                 .uart_offset    = 8,
3190         },
3191
3192         [pbn_b2_bt_1_115200] = {
3193                 .flags          = FL_BASE2|FL_BASE_BARS,
3194                 .num_ports      = 1,
3195                 .base_baud      = 115200,
3196                 .uart_offset    = 8,
3197         },
3198         [pbn_b2_bt_2_115200] = {
3199                 .flags          = FL_BASE2|FL_BASE_BARS,
3200                 .num_ports      = 2,
3201                 .base_baud      = 115200,
3202                 .uart_offset    = 8,
3203         },
3204         [pbn_b2_bt_4_115200] = {
3205                 .flags          = FL_BASE2|FL_BASE_BARS,
3206                 .num_ports      = 4,
3207                 .base_baud      = 115200,
3208                 .uart_offset    = 8,
3209         },
3210
3211         [pbn_b2_bt_2_921600] = {
3212                 .flags          = FL_BASE2|FL_BASE_BARS,
3213                 .num_ports      = 2,
3214                 .base_baud      = 921600,
3215                 .uart_offset    = 8,
3216         },
3217         [pbn_b2_bt_4_921600] = {
3218                 .flags          = FL_BASE2|FL_BASE_BARS,
3219                 .num_ports      = 4,
3220                 .base_baud      = 921600,
3221                 .uart_offset    = 8,
3222         },
3223
3224         [pbn_b3_2_115200] = {
3225                 .flags          = FL_BASE3,
3226                 .num_ports      = 2,
3227                 .base_baud      = 115200,
3228                 .uart_offset    = 8,
3229         },
3230         [pbn_b3_4_115200] = {
3231                 .flags          = FL_BASE3,
3232                 .num_ports      = 4,
3233                 .base_baud      = 115200,
3234                 .uart_offset    = 8,
3235         },
3236         [pbn_b3_8_115200] = {
3237                 .flags          = FL_BASE3,
3238                 .num_ports      = 8,
3239                 .base_baud      = 115200,
3240                 .uart_offset    = 8,
3241         },
3242
3243         [pbn_b4_bt_2_921600] = {
3244                 .flags          = FL_BASE4,
3245                 .num_ports      = 2,
3246                 .base_baud      = 921600,
3247                 .uart_offset    = 8,
3248         },
3249         [pbn_b4_bt_4_921600] = {
3250                 .flags          = FL_BASE4,
3251                 .num_ports      = 4,
3252                 .base_baud      = 921600,
3253                 .uart_offset    = 8,
3254         },
3255         [pbn_b4_bt_8_921600] = {
3256                 .flags          = FL_BASE4,
3257                 .num_ports      = 8,
3258                 .base_baud      = 921600,
3259                 .uart_offset    = 8,
3260         },
3261
3262         /*
3263          * Entries following this are board-specific.
3264          */
3265
3266         /*
3267          * Panacom - IOMEM
3268          */
3269         [pbn_panacom] = {
3270                 .flags          = FL_BASE2,
3271                 .num_ports      = 2,
3272                 .base_baud      = 921600,
3273                 .uart_offset    = 0x400,
3274                 .reg_shift      = 7,
3275         },
3276         [pbn_panacom2] = {
3277                 .flags          = FL_BASE2|FL_BASE_BARS,
3278                 .num_ports      = 2,
3279                 .base_baud      = 921600,
3280                 .uart_offset    = 0x400,
3281                 .reg_shift      = 7,
3282         },
3283         [pbn_panacom4] = {
3284                 .flags          = FL_BASE2|FL_BASE_BARS,
3285                 .num_ports      = 4,
3286                 .base_baud      = 921600,
3287                 .uart_offset    = 0x400,
3288                 .reg_shift      = 7,
3289         },
3290
3291         /* I think this entry is broken - the first_offset looks wrong --rmk */
3292         [pbn_plx_romulus] = {
3293                 .flags          = FL_BASE2,
3294                 .num_ports      = 4,
3295                 .base_baud      = 921600,
3296                 .uart_offset    = 8 << 2,
3297                 .reg_shift      = 2,
3298                 .first_offset   = 0x03,
3299         },
3300
3301         /*
3302          * This board uses the size of PCI Base region 0 to
3303          * signal now many ports are available
3304          */
3305         [pbn_oxsemi] = {
3306                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3307                 .num_ports      = 32,
3308                 .base_baud      = 115200,
3309                 .uart_offset    = 8,
3310         },
3311         [pbn_oxsemi_1_4000000] = {
3312                 .flags          = FL_BASE0,
3313                 .num_ports      = 1,
3314                 .base_baud      = 4000000,
3315                 .uart_offset    = 0x200,
3316                 .first_offset   = 0x1000,
3317         },
3318         [pbn_oxsemi_2_4000000] = {
3319                 .flags          = FL_BASE0,
3320                 .num_ports      = 2,
3321                 .base_baud      = 4000000,
3322                 .uart_offset    = 0x200,
3323                 .first_offset   = 0x1000,
3324         },
3325         [pbn_oxsemi_4_4000000] = {
3326                 .flags          = FL_BASE0,
3327                 .num_ports      = 4,
3328                 .base_baud      = 4000000,
3329                 .uart_offset    = 0x200,
3330                 .first_offset   = 0x1000,
3331         },
3332         [pbn_oxsemi_8_4000000] = {
3333                 .flags          = FL_BASE0,
3334                 .num_ports      = 8,
3335                 .base_baud      = 4000000,
3336                 .uart_offset    = 0x200,
3337                 .first_offset   = 0x1000,
3338         },
3339
3340
3341         /*
3342          * EKF addition for i960 Boards form EKF with serial port.
3343          * Max 256 ports.
3344          */
3345         [pbn_intel_i960] = {
3346                 .flags          = FL_BASE0,
3347                 .num_ports      = 32,
3348                 .base_baud      = 921600,
3349                 .uart_offset    = 8 << 2,
3350                 .reg_shift      = 2,
3351                 .first_offset   = 0x10000,
3352         },
3353         [pbn_sgi_ioc3] = {
3354                 .flags          = FL_BASE0|FL_NOIRQ,
3355                 .num_ports      = 1,
3356                 .base_baud      = 458333,
3357                 .uart_offset    = 8,
3358                 .reg_shift      = 0,
3359                 .first_offset   = 0x20178,
3360         },
3361
3362         /*
3363          * Computone - uses IOMEM.
3364          */
3365         [pbn_computone_4] = {
3366                 .flags          = FL_BASE0,
3367                 .num_ports      = 4,
3368                 .base_baud      = 921600,
3369                 .uart_offset    = 0x40,
3370                 .reg_shift      = 2,
3371                 .first_offset   = 0x200,
3372         },
3373         [pbn_computone_6] = {
3374                 .flags          = FL_BASE0,
3375                 .num_ports      = 6,
3376                 .base_baud      = 921600,
3377                 .uart_offset    = 0x40,
3378                 .reg_shift      = 2,
3379                 .first_offset   = 0x200,
3380         },
3381         [pbn_computone_8] = {
3382                 .flags          = FL_BASE0,
3383                 .num_ports      = 8,
3384                 .base_baud      = 921600,
3385                 .uart_offset    = 0x40,
3386                 .reg_shift      = 2,
3387                 .first_offset   = 0x200,
3388         },
3389         [pbn_sbsxrsio] = {
3390                 .flags          = FL_BASE0,
3391                 .num_ports      = 8,
3392                 .base_baud      = 460800,
3393                 .uart_offset    = 256,
3394                 .reg_shift      = 4,
3395         },
3396         /*
3397          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3398          *  Only basic 16550A support.
3399          *  XR17C15[24] are not tested, but they should work.
3400          */
3401         [pbn_exar_XR17C152] = {
3402                 .flags          = FL_BASE0,
3403                 .num_ports      = 2,
3404                 .base_baud      = 921600,
3405                 .uart_offset    = 0x200,
3406         },
3407         [pbn_exar_XR17C154] = {
3408                 .flags          = FL_BASE0,
3409                 .num_ports      = 4,
3410                 .base_baud      = 921600,
3411                 .uart_offset    = 0x200,
3412         },
3413         [pbn_exar_XR17C158] = {
3414                 .flags          = FL_BASE0,
3415                 .num_ports      = 8,
3416                 .base_baud      = 921600,
3417                 .uart_offset    = 0x200,
3418         },
3419         [pbn_exar_XR17V352] = {
3420                 .flags          = FL_BASE0,
3421                 .num_ports      = 2,
3422                 .base_baud      = 7812500,
3423                 .uart_offset    = 0x400,
3424                 .reg_shift      = 0,
3425                 .first_offset   = 0,
3426         },
3427         [pbn_exar_XR17V354] = {
3428                 .flags          = FL_BASE0,
3429                 .num_ports      = 4,
3430                 .base_baud      = 7812500,
3431                 .uart_offset    = 0x400,
3432                 .reg_shift      = 0,
3433                 .first_offset   = 0,
3434         },
3435         [pbn_exar_XR17V358] = {
3436                 .flags          = FL_BASE0,
3437                 .num_ports      = 8,
3438                 .base_baud      = 7812500,
3439                 .uart_offset    = 0x400,
3440                 .reg_shift      = 0,
3441                 .first_offset   = 0,
3442         },
3443         [pbn_exar_ibm_saturn] = {
3444                 .flags          = FL_BASE0,
3445                 .num_ports      = 1,
3446                 .base_baud      = 921600,
3447                 .uart_offset    = 0x200,
3448         },
3449
3450         /*
3451          * PA Semi PWRficient PA6T-1682M on-chip UART
3452          */
3453         [pbn_pasemi_1682M] = {
3454                 .flags          = FL_BASE0,
3455                 .num_ports      = 1,
3456                 .base_baud      = 8333333,
3457         },
3458         /*
3459          * National Instruments 843x
3460          */
3461         [pbn_ni8430_16] = {
3462                 .flags          = FL_BASE0,
3463                 .num_ports      = 16,
3464                 .base_baud      = 3686400,
3465                 .uart_offset    = 0x10,
3466                 .first_offset   = 0x800,
3467         },
3468         [pbn_ni8430_8] = {
3469                 .flags          = FL_BASE0,
3470                 .num_ports      = 8,
3471                 .base_baud      = 3686400,
3472                 .uart_offset    = 0x10,
3473                 .first_offset   = 0x800,
3474         },
3475         [pbn_ni8430_4] = {
3476                 .flags          = FL_BASE0,
3477                 .num_ports      = 4,
3478                 .base_baud      = 3686400,
3479                 .uart_offset    = 0x10,
3480                 .first_offset   = 0x800,
3481         },
3482         [pbn_ni8430_2] = {
3483                 .flags          = FL_BASE0,
3484                 .num_ports      = 2,
3485                 .base_baud      = 3686400,
3486                 .uart_offset    = 0x10,
3487                 .first_offset   = 0x800,
3488         },
3489         /*
3490          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3491          */
3492         [pbn_ADDIDATA_PCIe_1_3906250] = {
3493                 .flags          = FL_BASE0,
3494                 .num_ports      = 1,
3495                 .base_baud      = 3906250,
3496                 .uart_offset    = 0x200,
3497                 .first_offset   = 0x1000,
3498         },
3499         [pbn_ADDIDATA_PCIe_2_3906250] = {
3500                 .flags          = FL_BASE0,
3501                 .num_ports      = 2,
3502                 .base_baud      = 3906250,
3503                 .uart_offset    = 0x200,
3504                 .first_offset   = 0x1000,
3505         },
3506         [pbn_ADDIDATA_PCIe_4_3906250] = {
3507                 .flags          = FL_BASE0,
3508                 .num_ports      = 4,
3509                 .base_baud      = 3906250,
3510                 .uart_offset    = 0x200,
3511                 .first_offset   = 0x1000,
3512         },
3513         [pbn_ADDIDATA_PCIe_8_3906250] = {
3514                 .flags          = FL_BASE0,
3515                 .num_ports      = 8,
3516                 .base_baud      = 3906250,
3517                 .uart_offset    = 0x200,
3518                 .first_offset   = 0x1000,
3519         },
3520         [pbn_ce4100_1_115200] = {
3521                 .flags          = FL_BASE_BARS,
3522                 .num_ports      = 2,
3523                 .base_baud      = 921600,
3524                 .reg_shift      = 2,
3525         },
3526         /*
3527          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3528          * but is overridden by byt_set_termios.
3529          */
3530         [pbn_byt] = {
3531                 .flags          = FL_BASE0,
3532                 .num_ports      = 1,
3533                 .base_baud      = 2764800,
3534                 .uart_offset    = 0x80,
3535                 .reg_shift      = 2,
3536         },
3537         [pbn_qrk] = {
3538                 .flags          = FL_BASE0,
3539                 .num_ports      = 1,
3540                 .base_baud      = 2764800,
3541                 .reg_shift      = 2,
3542         },
3543         [pbn_omegapci] = {
3544                 .flags          = FL_BASE0,
3545                 .num_ports      = 8,
3546                 .base_baud      = 115200,
3547                 .uart_offset    = 0x200,
3548         },
3549         [pbn_NETMOS9900_2s_115200] = {
3550                 .flags          = FL_BASE0,
3551                 .num_ports      = 2,
3552                 .base_baud      = 115200,
3553         },
3554         [pbn_brcm_trumanage] = {
3555                 .flags          = FL_BASE0,
3556                 .num_ports      = 1,
3557                 .reg_shift      = 2,
3558                 .base_baud      = 115200,
3559         },
3560         [pbn_fintek_4] = {
3561                 .num_ports      = 4,
3562                 .uart_offset    = 8,
3563                 .base_baud      = 115200,
3564                 .first_offset   = 0x40,
3565         },
3566         [pbn_fintek_8] = {
3567                 .num_ports      = 8,
3568                 .uart_offset    = 8,
3569                 .base_baud      = 115200,
3570                 .first_offset   = 0x40,
3571         },
3572         [pbn_fintek_12] = {
3573                 .num_ports      = 12,
3574                 .uart_offset    = 8,
3575                 .base_baud      = 115200,
3576                 .first_offset   = 0x40,
3577         },
3578 };
3579
3580 static const struct pci_device_id blacklist[] = {
3581         /* softmodems */
3582         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3583         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3584         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3585
3586         /* multi-io cards handled by parport_serial */
3587         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3588         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3589 };
3590
3591 /*
3592  * Given a complete unknown PCI device, try to use some heuristics to
3593  * guess what the configuration might be, based on the pitiful PCI
3594  * serial specs.  Returns 0 on success, 1 on failure.
3595  */
3596 static int
3597 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3598 {
3599         const struct pci_device_id *bldev;
3600         int num_iomem, num_port, first_port = -1, i;
3601
3602         /*
3603          * If it is not a communications device or the programming
3604          * interface is greater than 6, give up.
3605          *
3606          * (Should we try to make guesses for multiport serial devices
3607          * later?)
3608          */
3609         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3610              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3611             (dev->class & 0xff) > 6)
3612                 return -ENODEV;
3613
3614         /*
3615          * Do not access blacklisted devices that are known not to
3616          * feature serial ports or are handled by other modules.
3617          */
3618         for (bldev = blacklist;
3619              bldev < blacklist + ARRAY_SIZE(blacklist);
3620              bldev++) {
3621                 if (dev->vendor == bldev->vendor &&
3622                     dev->device == bldev->device)
3623                         return -ENODEV;
3624         }
3625
3626         num_iomem = num_port = 0;
3627         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3628                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3629                         num_port++;
3630                         if (first_port == -1)
3631                                 first_port = i;
3632                 }
3633                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3634                         num_iomem++;
3635         }
3636
3637         /*
3638          * If there is 1 or 0 iomem regions, and exactly one port,
3639          * use it.  We guess the number of ports based on the IO
3640          * region size.
3641          */
3642         if (num_iomem <= 1 && num_port == 1) {
3643                 board->flags = first_port;
3644                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3645                 return 0;
3646         }
3647
3648         /*
3649          * Now guess if we've got a board which indexes by BARs.
3650          * Each IO BAR should be 8 bytes, and they should follow
3651          * consecutively.
3652          */
3653         first_port = -1;
3654         num_port = 0;
3655         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3656                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3657                     pci_resource_len(dev, i) == 8 &&
3658                     (first_port == -1 || (first_port + num_port) == i)) {
3659                         num_port++;
3660                         if (first_port == -1)
3661                                 first_port = i;
3662                 }
3663         }
3664
3665         if (num_port > 1) {
3666                 board->flags = first_port | FL_BASE_BARS;
3667                 board->num_ports = num_port;
3668                 return 0;
3669         }
3670
3671         return -ENODEV;
3672 }
3673
3674 static inline int
3675 serial_pci_matches(const struct pciserial_board *board,
3676                    const struct pciserial_board *guessed)
3677 {
3678         return
3679             board->num_ports == guessed->num_ports &&
3680             board->base_baud == guessed->base_baud &&
3681             board->uart_offset == guessed->uart_offset &&
3682             board->reg_shift == guessed->reg_shift &&
3683             board->first_offset == guessed->first_offset;
3684 }
3685
3686 struct serial_private *
3687 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3688 {
3689         struct uart_8250_port uart;
3690         struct serial_private *priv;
3691         struct pci_serial_quirk *quirk;
3692         int rc, nr_ports, i;
3693
3694         nr_ports = board->num_ports;
3695
3696         /*
3697          * Find an init and setup quirks.
3698          */
3699         quirk = find_quirk(dev);
3700
3701         /*
3702          * Run the new-style initialization function.
3703          * The initialization function returns:
3704          *  <0  - error
3705          *   0  - use board->num_ports
3706          *  >0  - number of ports
3707          */
3708         if (quirk->init) {
3709                 rc = quirk->init(dev);
3710                 if (rc < 0) {
3711                         priv = ERR_PTR(rc);
3712                         goto err_out;
3713                 }
3714                 if (rc)
3715                         nr_ports = rc;
3716         }
3717
3718         priv = kzalloc(sizeof(struct serial_private) +
3719                        sizeof(unsigned int) * nr_ports,
3720                        GFP_KERNEL);
3721         if (!priv) {
3722                 priv = ERR_PTR(-ENOMEM);
3723                 goto err_deinit;
3724         }
3725
3726         priv->dev = dev;
3727         priv->quirk = quirk;
3728
3729         memset(&uart, 0, sizeof(uart));
3730         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3731         uart.port.uartclk = board->base_baud * 16;
3732         uart.port.irq = get_pci_irq(dev, board);
3733         uart.port.dev = &dev->dev;
3734
3735         for (i = 0; i < nr_ports; i++) {
3736                 if (quirk->setup(priv, board, &uart, i))
3737                         break;
3738
3739                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3740                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3741
3742                 priv->line[i] = serial8250_register_8250_port(&uart);
3743                 if (priv->line[i] < 0) {
3744                         dev_err(&dev->dev,
3745                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3746                                 uart.port.iobase, uart.port.irq,
3747                                 uart.port.iotype, priv->line[i]);
3748                         break;
3749                 }
3750         }
3751         priv->nr = i;
3752         return priv;
3753
3754 err_deinit:
3755         if (quirk->exit)
3756                 quirk->exit(dev);
3757 err_out:
3758         return priv;
3759 }
3760 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3761
3762 void pciserial_remove_ports(struct serial_private *priv)
3763 {
3764         struct pci_serial_quirk *quirk;
3765         int i;
3766
3767         for (i = 0; i < priv->nr; i++)
3768                 serial8250_unregister_port(priv->line[i]);
3769
3770         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3771                 if (priv->remapped_bar[i])
3772                         iounmap(priv->remapped_bar[i]);
3773                 priv->remapped_bar[i] = NULL;
3774         }
3775
3776         /*
3777          * Find the exit quirks.
3778          */
3779         quirk = find_quirk(priv->dev);
3780         if (quirk->exit)
3781                 quirk->exit(priv->dev);
3782
3783         kfree(priv);
3784 }
3785 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3786
3787 void pciserial_suspend_ports(struct serial_private *priv)
3788 {
3789         int i;
3790
3791         for (i = 0; i < priv->nr; i++)
3792                 if (priv->line[i] >= 0)
3793                         serial8250_suspend_port(priv->line[i]);
3794
3795         /*
3796          * Ensure that every init quirk is properly torn down
3797          */
3798         if (priv->quirk->exit)
3799                 priv->quirk->exit(priv->dev);
3800 }
3801 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3802
3803 void pciserial_resume_ports(struct serial_private *priv)
3804 {
3805         int i;
3806
3807         /*
3808          * Ensure that the board is correctly configured.
3809          */
3810         if (priv->quirk->init)
3811                 priv->quirk->init(priv->dev);
3812
3813         for (i = 0; i < priv->nr; i++)
3814                 if (priv->line[i] >= 0)
3815                         serial8250_resume_port(priv->line[i]);
3816 }
3817 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3818
3819 /*
3820  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
3821  * to the arrangement of serial ports on a PCI card.
3822  */
3823 static int
3824 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3825 {
3826         struct pci_serial_quirk *quirk;
3827         struct serial_private *priv;
3828         const struct pciserial_board *board;
3829         struct pciserial_board tmp;
3830         int rc;
3831
3832         quirk = find_quirk(dev);
3833         if (quirk->probe) {
3834                 rc = quirk->probe(dev);
3835                 if (rc)
3836                         return rc;
3837         }
3838
3839         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3840                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3841                         ent->driver_data);
3842                 return -EINVAL;
3843         }
3844
3845         board = &pci_boards[ent->driver_data];
3846
3847         rc = pci_enable_device(dev);
3848         pci_save_state(dev);
3849         if (rc)
3850                 return rc;
3851
3852         if (ent->driver_data == pbn_default) {
3853                 /*
3854                  * Use a copy of the pci_board entry for this;
3855                  * avoid changing entries in the table.
3856                  */
3857                 memcpy(&tmp, board, sizeof(struct pciserial_board));
3858                 board = &tmp;
3859
3860                 /*
3861                  * We matched one of our class entries.  Try to
3862                  * determine the parameters of this board.
3863                  */
3864                 rc = serial_pci_guess_board(dev, &tmp);
3865                 if (rc)
3866                         goto disable;
3867         } else {
3868                 /*
3869                  * We matched an explicit entry.  If we are able to
3870                  * detect this boards settings with our heuristic,
3871                  * then we no longer need this entry.
3872                  */
3873                 memcpy(&tmp, &pci_boards[pbn_default],
3874                        sizeof(struct pciserial_board));
3875                 rc = serial_pci_guess_board(dev, &tmp);
3876                 if (rc == 0 && serial_pci_matches(board, &tmp))
3877                         moan_device("Redundant entry in serial pci_table.",
3878                                     dev);
3879         }
3880
3881         priv = pciserial_init_ports(dev, board);
3882         if (!IS_ERR(priv)) {
3883                 pci_set_drvdata(dev, priv);
3884                 return 0;
3885         }
3886
3887         rc = PTR_ERR(priv);
3888
3889  disable:
3890         pci_disable_device(dev);
3891         return rc;
3892 }
3893
3894 static void pciserial_remove_one(struct pci_dev *dev)
3895 {
3896         struct serial_private *priv = pci_get_drvdata(dev);
3897
3898         pciserial_remove_ports(priv);
3899
3900         pci_disable_device(dev);
3901 }
3902
3903 #ifdef CONFIG_PM
3904 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3905 {
3906         struct serial_private *priv = pci_get_drvdata(dev);
3907
3908         if (priv)
3909                 pciserial_suspend_ports(priv);
3910
3911         pci_save_state(dev);
3912         pci_set_power_state(dev, pci_choose_state(dev, state));
3913         return 0;
3914 }
3915
3916 static int pciserial_resume_one(struct pci_dev *dev)
3917 {
3918         int err;
3919         struct serial_private *priv = pci_get_drvdata(dev);
3920
3921         pci_set_power_state(dev, PCI_D0);
3922         pci_restore_state(dev);
3923
3924         if (priv) {
3925                 /*
3926                  * The device may have been disabled.  Re-enable it.
3927                  */
3928                 err = pci_enable_device(dev);
3929                 /* FIXME: We cannot simply error out here */
3930                 if (err)
3931                         dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
3932                 pciserial_resume_ports(priv);
3933         }
3934         return 0;
3935 }
3936 #endif
3937
3938 static struct pci_device_id serial_pci_tbl[] = {
3939         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3940         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3941                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3942                 pbn_b2_8_921600 },
3943         /* Advantech also use 0x3618 and 0xf618 */
3944         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3945                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3946                 pbn_b0_4_921600 },
3947         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3948                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3949                 pbn_b0_4_921600 },
3950         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3951                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3952                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3953                 pbn_b1_8_1382400 },
3954         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3955                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3956                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3957                 pbn_b1_4_1382400 },
3958         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3959                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3960                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3961                 pbn_b1_2_1382400 },
3962         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3963                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3964                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3965                 pbn_b1_8_1382400 },
3966         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3967                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3968                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3969                 pbn_b1_4_1382400 },
3970         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3971                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3972                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3973                 pbn_b1_2_1382400 },
3974         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3975                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3976                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3977                 pbn_b1_8_921600 },
3978         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3979                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3980                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3981                 pbn_b1_8_921600 },
3982         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3983                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3984                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3985                 pbn_b1_4_921600 },
3986         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3987                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3988                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3989                 pbn_b1_4_921600 },
3990         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3991                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3992                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3993                 pbn_b1_2_921600 },
3994         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3995                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3996                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3997                 pbn_b1_8_921600 },
3998         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3999                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4000                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4001                 pbn_b1_8_921600 },
4002         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4003                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4004                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4005                 pbn_b1_4_921600 },
4006         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4007                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4008                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4009                 pbn_b1_2_1250000 },
4010         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4011                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4012                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4013                 pbn_b0_2_1843200 },
4014         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4015                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4016                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4017                 pbn_b0_4_1843200 },
4018         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4019                 PCI_VENDOR_ID_AFAVLAB,
4020                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4021                 pbn_b0_4_1152000 },
4022         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4023                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4024                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4025                 pbn_b0_2_1843200_200 },
4026         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4027                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4028                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4029                 pbn_b0_4_1843200_200 },
4030         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4031                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4032                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4033                 pbn_b0_8_1843200_200 },
4034         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4035                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4036                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4037                 pbn_b0_2_1843200_200 },
4038         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4039                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4040                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4041                 pbn_b0_4_1843200_200 },
4042         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4043                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4044                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4045                 pbn_b0_8_1843200_200 },
4046         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4047                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4048                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4049                 pbn_b0_2_1843200_200 },
4050         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4051                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4052                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4053                 pbn_b0_4_1843200_200 },
4054         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4055                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4056                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4057                 pbn_b0_8_1843200_200 },
4058         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4059                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4060                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4061                 pbn_b0_2_1843200_200 },
4062         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4063                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4064                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4065                 pbn_b0_4_1843200_200 },
4066         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4067                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4068                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4069                 pbn_b0_8_1843200_200 },
4070         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4071                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4072                 0, 0, pbn_exar_ibm_saturn },
4073
4074         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4075                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4076                 pbn_b2_bt_1_115200 },
4077         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4078                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4079                 pbn_b2_bt_2_115200 },
4080         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4082                 pbn_b2_bt_4_115200 },
4083         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4084                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085                 pbn_b2_bt_2_115200 },
4086         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4087                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088                 pbn_b2_bt_4_115200 },
4089         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4090                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091                 pbn_b2_8_115200 },
4092         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4093                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094                 pbn_b2_8_460800 },
4095         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4096                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097                 pbn_b2_8_115200 },
4098
4099         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4101                 pbn_b2_bt_2_115200 },
4102         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4104                 pbn_b2_bt_2_921600 },
4105         /*
4106          * VScom SPCOM800, from sl@s.pl
4107          */
4108         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4110                 pbn_b2_8_921600 },
4111         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4113                 pbn_b2_4_921600 },
4114         /* Unknown card - subdevice 0x1584 */
4115         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4116                 PCI_VENDOR_ID_PLX,
4117                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4118                 pbn_b2_4_115200 },
4119         /* Unknown card - subdevice 0x1588 */
4120         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4121                 PCI_VENDOR_ID_PLX,
4122                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4123                 pbn_b2_8_115200 },
4124         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4125                 PCI_SUBVENDOR_ID_KEYSPAN,
4126                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4127                 pbn_panacom },
4128         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4130                 pbn_panacom4 },
4131         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4132                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4133                 pbn_panacom2 },
4134         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4135                 PCI_VENDOR_ID_ESDGMBH,
4136                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4137                 pbn_b2_4_115200 },
4138         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4139                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4140                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4141                 pbn_b2_4_460800 },
4142         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4143                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4144                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4145                 pbn_b2_8_460800 },
4146         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4147                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4148                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4149                 pbn_b2_16_460800 },
4150         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4151                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4152                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4153                 pbn_b2_16_460800 },
4154         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4155                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4156                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4157                 pbn_b2_4_460800 },
4158         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4159                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4160                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4161                 pbn_b2_8_460800 },
4162         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4163                 PCI_SUBVENDOR_ID_EXSYS,
4164                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4165                 pbn_b2_4_115200 },
4166         /*
4167          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4168          * (Exoray@isys.ca)
4169          */
4170         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4171                 0x10b5, 0x106a, 0, 0,
4172                 pbn_plx_romulus },
4173         /*
4174          * Quatech cards. These actually have configurable clocks but for
4175          * now we just use the default.
4176          *
4177          * 100 series are RS232, 200 series RS422,
4178          */
4179         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4181                 pbn_b1_4_115200 },
4182         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184                 pbn_b1_2_115200 },
4185         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4187                 pbn_b2_2_115200 },
4188         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4190                 pbn_b1_2_115200 },
4191         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4193                 pbn_b2_2_115200 },
4194         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4196                 pbn_b1_4_115200 },
4197         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4198                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199                 pbn_b1_8_115200 },
4200         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4201                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4202                 pbn_b1_8_115200 },
4203         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4204                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4205                 pbn_b1_4_115200 },
4206         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4207                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208                 pbn_b1_2_115200 },
4209         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4210                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4211                 pbn_b1_4_115200 },
4212         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4213                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4214                 pbn_b1_2_115200 },
4215         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4217                 pbn_b2_4_115200 },
4218         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4220                 pbn_b2_2_115200 },
4221         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4223                 pbn_b2_1_115200 },
4224         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226                 pbn_b2_4_115200 },
4227         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4228                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4229                 pbn_b2_2_115200 },
4230         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4232                 pbn_b2_1_115200 },
4233         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235                 pbn_b0_8_115200 },
4236
4237         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4238                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4239                 0, 0,
4240                 pbn_b0_4_921600 },
4241         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4242                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4243                 0, 0,
4244                 pbn_b0_4_1152000 },
4245         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4246                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4247                 pbn_b0_bt_2_921600 },
4248
4249                 /*
4250                  * The below card is a little controversial since it is the
4251                  * subject of a PCI vendor/device ID clash.  (See
4252                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4253                  * For now just used the hex ID 0x950a.
4254                  */
4255         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4256                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4257                 0, 0, pbn_b0_2_115200 },
4258         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4259                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4260                 0, 0, pbn_b0_2_115200 },
4261         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4263                 pbn_b0_2_1130000 },
4264         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4265                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4266                 pbn_b0_1_921600 },
4267         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269                 pbn_b0_4_115200 },
4270         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272                 pbn_b0_bt_2_921600 },
4273         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4274                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4275                 pbn_b2_8_1152000 },
4276
4277         /*
4278          * Oxford Semiconductor Inc. Tornado PCI express device range.
4279          */
4280         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282                 pbn_b0_1_4000000 },
4283         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285                 pbn_b0_1_4000000 },
4286         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288                 pbn_oxsemi_1_4000000 },
4289         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291                 pbn_oxsemi_1_4000000 },
4292         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294                 pbn_b0_1_4000000 },
4295         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297                 pbn_b0_1_4000000 },
4298         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300                 pbn_oxsemi_1_4000000 },
4301         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303                 pbn_oxsemi_1_4000000 },
4304         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306                 pbn_b0_1_4000000 },
4307         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309                 pbn_b0_1_4000000 },
4310         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312                 pbn_b0_1_4000000 },
4313         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315                 pbn_b0_1_4000000 },
4316         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318                 pbn_oxsemi_2_4000000 },
4319         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321                 pbn_oxsemi_2_4000000 },
4322         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324                 pbn_oxsemi_4_4000000 },
4325         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327                 pbn_oxsemi_4_4000000 },
4328         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330                 pbn_oxsemi_8_4000000 },
4331         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333                 pbn_oxsemi_8_4000000 },
4334         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336                 pbn_oxsemi_1_4000000 },
4337         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339                 pbn_oxsemi_1_4000000 },
4340         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342                 pbn_oxsemi_1_4000000 },
4343         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345                 pbn_oxsemi_1_4000000 },
4346         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348                 pbn_oxsemi_1_4000000 },
4349         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351                 pbn_oxsemi_1_4000000 },
4352         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354                 pbn_oxsemi_1_4000000 },
4355         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4356                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357                 pbn_oxsemi_1_4000000 },
4358         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4359                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360                 pbn_oxsemi_1_4000000 },
4361         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4362                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363                 pbn_oxsemi_1_4000000 },
4364         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4365                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366                 pbn_oxsemi_1_4000000 },
4367         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4368                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369                 pbn_oxsemi_1_4000000 },
4370         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4371                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372                 pbn_oxsemi_1_4000000 },
4373         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4374                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375                 pbn_oxsemi_1_4000000 },
4376         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4377                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378                 pbn_oxsemi_1_4000000 },
4379         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4380                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381                 pbn_oxsemi_1_4000000 },
4382         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4383                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384                 pbn_oxsemi_1_4000000 },
4385         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387                 pbn_oxsemi_1_4000000 },
4388         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390                 pbn_oxsemi_1_4000000 },
4391         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4392                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393                 pbn_oxsemi_1_4000000 },
4394         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4395                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396                 pbn_oxsemi_1_4000000 },
4397         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4398                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399                 pbn_oxsemi_1_4000000 },
4400         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4401                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4402                 pbn_oxsemi_1_4000000 },
4403         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4404                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4405                 pbn_oxsemi_1_4000000 },
4406         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4407                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408                 pbn_oxsemi_1_4000000 },
4409         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4410                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411                 pbn_oxsemi_1_4000000 },
4412         /*
4413          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4414          */
4415         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4416                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4417                 pbn_oxsemi_1_4000000 },
4418         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4419                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4420                 pbn_oxsemi_2_4000000 },
4421         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4422                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4423                 pbn_oxsemi_4_4000000 },
4424         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4425                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4426                 pbn_oxsemi_8_4000000 },
4427
4428         /*
4429          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4430          */
4431         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4432                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4433                 pbn_oxsemi_2_4000000 },
4434
4435         /*
4436          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4437          * from skokodyn@yahoo.com
4438          */
4439         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4440                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4441                 pbn_sbsxrsio },
4442         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4443                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4444                 pbn_sbsxrsio },
4445         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4446                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4447                 pbn_sbsxrsio },
4448         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4449                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4450                 pbn_sbsxrsio },
4451
4452         /*
4453          * Digitan DS560-558, from jimd@esoft.com
4454          */
4455         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457                 pbn_b1_1_115200 },
4458
4459         /*
4460          * Titan Electronic cards
4461          *  The 400L and 800L have a custom setup quirk.
4462          */
4463         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465                 pbn_b0_1_921600 },
4466         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4467                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468                 pbn_b0_2_921600 },
4469         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471                 pbn_b0_4_921600 },
4472         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474                 pbn_b0_4_921600 },
4475         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477                 pbn_b1_1_921600 },
4478         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480                 pbn_b1_bt_2_921600 },
4481         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483                 pbn_b0_bt_4_921600 },
4484         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486                 pbn_b0_bt_8_921600 },
4487         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489                 pbn_b4_bt_2_921600 },
4490         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492                 pbn_b4_bt_4_921600 },
4493         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495                 pbn_b4_bt_8_921600 },
4496         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498                 pbn_b0_4_921600 },
4499         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501                 pbn_b0_4_921600 },
4502         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504                 pbn_b0_4_921600 },
4505         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507                 pbn_oxsemi_1_4000000 },
4508         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510                 pbn_oxsemi_2_4000000 },
4511         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513                 pbn_oxsemi_4_4000000 },
4514         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516                 pbn_oxsemi_8_4000000 },
4517         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519                 pbn_oxsemi_2_4000000 },
4520         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522                 pbn_oxsemi_2_4000000 },
4523         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525                 pbn_b0_bt_2_921600 },
4526         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4527                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528                 pbn_b0_4_921600 },
4529         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4530                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531                 pbn_b0_4_921600 },
4532         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4533                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534                 pbn_b0_4_921600 },
4535         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4536                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537                 pbn_b0_4_921600 },
4538
4539         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4540                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541                 pbn_b2_1_460800 },
4542         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544                 pbn_b2_1_460800 },
4545         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4546                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547                 pbn_b2_1_460800 },
4548         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4549                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550                 pbn_b2_bt_2_921600 },
4551         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553                 pbn_b2_bt_2_921600 },
4554         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4555                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556                 pbn_b2_bt_2_921600 },
4557         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4558                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559                 pbn_b2_bt_4_921600 },
4560         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562                 pbn_b2_bt_4_921600 },
4563         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4564                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565                 pbn_b2_bt_4_921600 },
4566         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568                 pbn_b0_1_921600 },
4569         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571                 pbn_b0_1_921600 },
4572         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574                 pbn_b0_1_921600 },
4575         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577                 pbn_b0_bt_2_921600 },
4578         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580                 pbn_b0_bt_2_921600 },
4581         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583                 pbn_b0_bt_2_921600 },
4584         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586                 pbn_b0_bt_4_921600 },
4587         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589                 pbn_b0_bt_4_921600 },
4590         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4591                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592                 pbn_b0_bt_4_921600 },
4593         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4594                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595                 pbn_b0_bt_8_921600 },
4596         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4597                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598                 pbn_b0_bt_8_921600 },
4599         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4600                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601                 pbn_b0_bt_8_921600 },
4602
4603         /*
4604          * Computone devices submitted by Doug McNash dmcnash@computone.com
4605          */
4606         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4607                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4608                 0, 0, pbn_computone_4 },
4609         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4610                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4611                 0, 0, pbn_computone_8 },
4612         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4613                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4614                 0, 0, pbn_computone_6 },
4615
4616         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4617                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618                 pbn_oxsemi },
4619         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4620                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4621                 pbn_b0_bt_1_921600 },
4622
4623         /*
4624          * SUNIX (TIMEDIA)
4625          */
4626         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4627                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4628                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4629                 pbn_b0_bt_1_921600 },
4630
4631         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4632                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4633                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4634                 pbn_b0_bt_1_921600 },
4635
4636         /*
4637          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4638          */
4639         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4640                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641                 pbn_b0_bt_8_115200 },
4642         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4643                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644                 pbn_b0_bt_8_115200 },
4645
4646         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4647                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648                 pbn_b0_bt_2_115200 },
4649         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4650                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651                 pbn_b0_bt_2_115200 },
4652         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4653                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654                 pbn_b0_bt_2_115200 },
4655         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4656                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657                 pbn_b0_bt_2_115200 },
4658         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4659                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660                 pbn_b0_bt_2_115200 },
4661         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4662                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663                 pbn_b0_bt_4_460800 },
4664         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4665                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666                 pbn_b0_bt_4_460800 },
4667         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4668                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669                 pbn_b0_bt_2_460800 },
4670         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4671                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672                 pbn_b0_bt_2_460800 },
4673         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4674                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675                 pbn_b0_bt_2_460800 },
4676         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4677                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678                 pbn_b0_bt_1_115200 },
4679         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4680                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681                 pbn_b0_bt_1_460800 },
4682
4683         /*
4684          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4685          * Cards are identified by their subsystem vendor IDs, which
4686          * (in hex) match the model number.
4687          *
4688          * Note that JC140x are RS422/485 cards which require ox950
4689          * ACR = 0x10, and as such are not currently fully supported.
4690          */
4691         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4692                 0x1204, 0x0004, 0, 0,
4693                 pbn_b0_4_921600 },
4694         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4695                 0x1208, 0x0004, 0, 0,
4696                 pbn_b0_4_921600 },
4697 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4698                 0x1402, 0x0002, 0, 0,
4699                 pbn_b0_2_921600 }, */
4700 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4701                 0x1404, 0x0004, 0, 0,
4702                 pbn_b0_4_921600 }, */
4703         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4704                 0x1208, 0x0004, 0, 0,
4705                 pbn_b0_4_921600 },
4706
4707         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4708                 0x1204, 0x0004, 0, 0,
4709                 pbn_b0_4_921600 },
4710         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4711                 0x1208, 0x0004, 0, 0,
4712                 pbn_b0_4_921600 },
4713         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4714                 0x1208, 0x0004, 0, 0,
4715                 pbn_b0_4_921600 },
4716         /*
4717          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4718          */
4719         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4720                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721                 pbn_b1_1_1382400 },
4722
4723         /*
4724          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4725          */
4726         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4727                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728                 pbn_b1_1_1382400 },
4729
4730         /*
4731          * RAStel 2 port modem, gerg@moreton.com.au
4732          */
4733         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735                 pbn_b2_bt_2_115200 },
4736
4737         /*
4738          * EKF addition for i960 Boards form EKF with serial port
4739          */
4740         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4741                 0xE4BF, PCI_ANY_ID, 0, 0,
4742                 pbn_intel_i960 },
4743
4744         /*
4745          * Xircom Cardbus/Ethernet combos
4746          */
4747         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4748                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749                 pbn_b0_1_115200 },
4750         /*
4751          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4752          */
4753         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4754                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755                 pbn_b0_1_115200 },
4756
4757         /*
4758          * Untested PCI modems, sent in from various folks...
4759          */
4760
4761         /*
4762          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4763          */
4764         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4765                 0x1048, 0x1500, 0, 0,
4766                 pbn_b1_1_115200 },
4767
4768         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4769                 0xFF00, 0, 0, 0,
4770                 pbn_sgi_ioc3 },
4771
4772         /*
4773          * HP Diva card
4774          */
4775         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4776                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4777                 pbn_b1_1_115200 },
4778         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4779                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780                 pbn_b0_5_115200 },
4781         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4782                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783                 pbn_b2_1_115200 },
4784
4785         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787                 pbn_b3_2_115200 },
4788         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4789                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790                 pbn_b3_4_115200 },
4791         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4792                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793                 pbn_b3_8_115200 },
4794
4795         /*
4796          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4797          */
4798         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4799                 PCI_ANY_ID, PCI_ANY_ID,
4800                 0,
4801                 0, pbn_exar_XR17C152 },
4802         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4803                 PCI_ANY_ID, PCI_ANY_ID,
4804                 0,
4805                 0, pbn_exar_XR17C154 },
4806         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4807                 PCI_ANY_ID, PCI_ANY_ID,
4808                 0,
4809                 0, pbn_exar_XR17C158 },
4810         /*
4811          * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4812          */
4813         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4814                 PCI_ANY_ID, PCI_ANY_ID,
4815                 0,
4816                 0, pbn_exar_XR17V352 },
4817         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4818                 PCI_ANY_ID, PCI_ANY_ID,
4819                 0,
4820                 0, pbn_exar_XR17V354 },
4821         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4822                 PCI_ANY_ID, PCI_ANY_ID,
4823                 0,
4824                 0, pbn_exar_XR17V358 },
4825
4826         /*
4827          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4828          */
4829         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4830                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831                 pbn_b0_1_115200 },
4832         /*
4833          * ITE
4834          */
4835         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4836                 PCI_ANY_ID, PCI_ANY_ID,
4837                 0, 0,
4838                 pbn_b1_bt_1_115200 },
4839
4840         /*
4841          * IntaShield IS-200
4842          */
4843         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4844                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
4845                 pbn_b2_2_115200 },
4846         /*
4847          * IntaShield IS-400
4848          */
4849         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4850                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
4851                 pbn_b2_4_115200 },
4852         /*
4853          * Perle PCI-RAS cards
4854          */
4855         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4856                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4857                 0, 0, pbn_b2_4_921600 },
4858         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4859                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4860                 0, 0, pbn_b2_8_921600 },
4861
4862         /*
4863          * Mainpine series cards: Fairly standard layout but fools
4864          * parts of the autodetect in some cases and uses otherwise
4865          * unmatched communications subclasses in the PCI Express case
4866          */
4867
4868         {       /* RockForceDUO */
4869                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4870                 PCI_VENDOR_ID_MAINPINE, 0x0200,
4871                 0, 0, pbn_b0_2_115200 },
4872         {       /* RockForceQUATRO */
4873                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4874                 PCI_VENDOR_ID_MAINPINE, 0x0300,
4875                 0, 0, pbn_b0_4_115200 },
4876         {       /* RockForceDUO+ */
4877                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4878                 PCI_VENDOR_ID_MAINPINE, 0x0400,
4879                 0, 0, pbn_b0_2_115200 },
4880         {       /* RockForceQUATRO+ */
4881                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4882                 PCI_VENDOR_ID_MAINPINE, 0x0500,
4883                 0, 0, pbn_b0_4_115200 },
4884         {       /* RockForce+ */
4885                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4886                 PCI_VENDOR_ID_MAINPINE, 0x0600,
4887                 0, 0, pbn_b0_2_115200 },
4888         {       /* RockForce+ */
4889                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4890                 PCI_VENDOR_ID_MAINPINE, 0x0700,
4891                 0, 0, pbn_b0_4_115200 },
4892         {       /* RockForceOCTO+ */
4893                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4894                 PCI_VENDOR_ID_MAINPINE, 0x0800,
4895                 0, 0, pbn_b0_8_115200 },
4896         {       /* RockForceDUO+ */
4897                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4898                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4899                 0, 0, pbn_b0_2_115200 },
4900         {       /* RockForceQUARTRO+ */
4901                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4902                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4903                 0, 0, pbn_b0_4_115200 },
4904         {       /* RockForceOCTO+ */
4905                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4906                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4907                 0, 0, pbn_b0_8_115200 },
4908         {       /* RockForceD1 */
4909                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4910                 PCI_VENDOR_ID_MAINPINE, 0x2000,
4911                 0, 0, pbn_b0_1_115200 },
4912         {       /* RockForceF1 */
4913                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4914                 PCI_VENDOR_ID_MAINPINE, 0x2100,
4915                 0, 0, pbn_b0_1_115200 },
4916         {       /* RockForceD2 */
4917                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4918                 PCI_VENDOR_ID_MAINPINE, 0x2200,
4919                 0, 0, pbn_b0_2_115200 },
4920         {       /* RockForceF2 */
4921                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4922                 PCI_VENDOR_ID_MAINPINE, 0x2300,
4923                 0, 0, pbn_b0_2_115200 },
4924         {       /* RockForceD4 */
4925                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4926                 PCI_VENDOR_ID_MAINPINE, 0x2400,
4927                 0, 0, pbn_b0_4_115200 },
4928         {       /* RockForceF4 */
4929                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4930                 PCI_VENDOR_ID_MAINPINE, 0x2500,
4931                 0, 0, pbn_b0_4_115200 },
4932         {       /* RockForceD8 */
4933                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4934                 PCI_VENDOR_ID_MAINPINE, 0x2600,
4935                 0, 0, pbn_b0_8_115200 },
4936         {       /* RockForceF8 */
4937                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4938                 PCI_VENDOR_ID_MAINPINE, 0x2700,
4939                 0, 0, pbn_b0_8_115200 },
4940         {       /* IQ Express D1 */
4941                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4942                 PCI_VENDOR_ID_MAINPINE, 0x3000,
4943                 0, 0, pbn_b0_1_115200 },
4944         {       /* IQ Express F1 */
4945                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4946                 PCI_VENDOR_ID_MAINPINE, 0x3100,
4947                 0, 0, pbn_b0_1_115200 },
4948         {       /* IQ Express D2 */
4949                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4950                 PCI_VENDOR_ID_MAINPINE, 0x3200,
4951                 0, 0, pbn_b0_2_115200 },
4952         {       /* IQ Express F2 */
4953                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4954                 PCI_VENDOR_ID_MAINPINE, 0x3300,
4955                 0, 0, pbn_b0_2_115200 },
4956         {       /* IQ Express D4 */
4957                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4958                 PCI_VENDOR_ID_MAINPINE, 0x3400,
4959                 0, 0, pbn_b0_4_115200 },
4960         {       /* IQ Express F4 */
4961                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4962                 PCI_VENDOR_ID_MAINPINE, 0x3500,
4963                 0, 0, pbn_b0_4_115200 },
4964         {       /* IQ Express D8 */
4965                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4966                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4967                 0, 0, pbn_b0_8_115200 },
4968         {       /* IQ Express F8 */
4969                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4970                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4971                 0, 0, pbn_b0_8_115200 },
4972
4973
4974         /*
4975          * PA Semi PA6T-1682M on-chip UART
4976          */
4977         {       PCI_VENDOR_ID_PASEMI, 0xa004,
4978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4979                 pbn_pasemi_1682M },
4980
4981         /*
4982          * National Instruments
4983          */
4984         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986                 pbn_b1_16_115200 },
4987         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4988                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989                 pbn_b1_8_115200 },
4990         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992                 pbn_b1_bt_4_115200 },
4993         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995                 pbn_b1_bt_2_115200 },
4996         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998                 pbn_b1_bt_4_115200 },
4999         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001                 pbn_b1_bt_2_115200 },
5002         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004                 pbn_b1_16_115200 },
5005         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007                 pbn_b1_8_115200 },
5008         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010                 pbn_b1_bt_4_115200 },
5011         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5013                 pbn_b1_bt_2_115200 },
5014         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016                 pbn_b1_bt_4_115200 },
5017         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5018                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5019                 pbn_b1_bt_2_115200 },
5020         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5022                 pbn_ni8430_2 },
5023         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5025                 pbn_ni8430_2 },
5026         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028                 pbn_ni8430_4 },
5029         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5030                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5031                 pbn_ni8430_4 },
5032         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5033                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5034                 pbn_ni8430_8 },
5035         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5037                 pbn_ni8430_8 },
5038         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5040                 pbn_ni8430_16 },
5041         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5043                 pbn_ni8430_16 },
5044         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5045                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5046                 pbn_ni8430_2 },
5047         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5048                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5049                 pbn_ni8430_2 },
5050         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5051                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5052                 pbn_ni8430_4 },
5053         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5054                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5055                 pbn_ni8430_4 },
5056
5057         /*
5058         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5059         */
5060         {       PCI_VENDOR_ID_ADDIDATA,
5061                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5062                 PCI_ANY_ID,
5063                 PCI_ANY_ID,
5064                 0,
5065                 0,
5066                 pbn_b0_4_115200 },
5067
5068         {       PCI_VENDOR_ID_ADDIDATA,
5069                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5070                 PCI_ANY_ID,
5071                 PCI_ANY_ID,
5072                 0,
5073                 0,
5074                 pbn_b0_2_115200 },
5075
5076         {       PCI_VENDOR_ID_ADDIDATA,
5077                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5078                 PCI_ANY_ID,
5079                 PCI_ANY_ID,
5080                 0,
5081                 0,
5082                 pbn_b0_1_115200 },
5083
5084         {       PCI_VENDOR_ID_AMCC,
5085                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5086                 PCI_ANY_ID,
5087                 PCI_ANY_ID,
5088                 0,
5089                 0,
5090                 pbn_b1_8_115200 },
5091
5092         {       PCI_VENDOR_ID_ADDIDATA,
5093                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5094                 PCI_ANY_ID,
5095                 PCI_ANY_ID,
5096                 0,
5097                 0,
5098                 pbn_b0_4_115200 },
5099
5100         {       PCI_VENDOR_ID_ADDIDATA,
5101                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5102                 PCI_ANY_ID,
5103                 PCI_ANY_ID,
5104                 0,
5105                 0,
5106                 pbn_b0_2_115200 },
5107
5108         {       PCI_VENDOR_ID_ADDIDATA,
5109                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5110                 PCI_ANY_ID,
5111                 PCI_ANY_ID,
5112                 0,
5113                 0,
5114                 pbn_b0_1_115200 },
5115
5116         {       PCI_VENDOR_ID_ADDIDATA,
5117                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5118                 PCI_ANY_ID,
5119                 PCI_ANY_ID,
5120                 0,
5121                 0,
5122                 pbn_b0_4_115200 },
5123
5124         {       PCI_VENDOR_ID_ADDIDATA,
5125                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5126                 PCI_ANY_ID,
5127                 PCI_ANY_ID,
5128                 0,
5129                 0,
5130                 pbn_b0_2_115200 },
5131
5132         {       PCI_VENDOR_ID_ADDIDATA,
5133                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5134                 PCI_ANY_ID,
5135                 PCI_ANY_ID,
5136                 0,
5137                 0,
5138                 pbn_b0_1_115200 },
5139
5140         {       PCI_VENDOR_ID_ADDIDATA,
5141                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5142                 PCI_ANY_ID,
5143                 PCI_ANY_ID,
5144                 0,
5145                 0,
5146                 pbn_b0_8_115200 },
5147
5148         {       PCI_VENDOR_ID_ADDIDATA,
5149                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5150                 PCI_ANY_ID,
5151                 PCI_ANY_ID,
5152                 0,
5153                 0,
5154                 pbn_ADDIDATA_PCIe_4_3906250 },
5155
5156         {       PCI_VENDOR_ID_ADDIDATA,
5157                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5158                 PCI_ANY_ID,
5159                 PCI_ANY_ID,
5160                 0,
5161                 0,
5162                 pbn_ADDIDATA_PCIe_2_3906250 },
5163
5164         {       PCI_VENDOR_ID_ADDIDATA,
5165                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5166                 PCI_ANY_ID,
5167                 PCI_ANY_ID,
5168                 0,
5169                 0,
5170                 pbn_ADDIDATA_PCIe_1_3906250 },
5171
5172         {       PCI_VENDOR_ID_ADDIDATA,
5173                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5174                 PCI_ANY_ID,
5175                 PCI_ANY_ID,
5176                 0,
5177                 0,
5178                 pbn_ADDIDATA_PCIe_8_3906250 },
5179
5180         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5181                 PCI_VENDOR_ID_IBM, 0x0299,
5182                 0, 0, pbn_b0_bt_2_115200 },
5183
5184         /*
5185          * other NetMos 9835 devices are most likely handled by the
5186          * parport_serial driver, check drivers/parport/parport_serial.c
5187          * before adding them here.
5188          */
5189
5190         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5191                 0xA000, 0x1000,
5192                 0, 0, pbn_b0_1_115200 },
5193
5194         /* the 9901 is a rebranded 9912 */
5195         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5196                 0xA000, 0x1000,
5197                 0, 0, pbn_b0_1_115200 },
5198
5199         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5200                 0xA000, 0x1000,
5201                 0, 0, pbn_b0_1_115200 },
5202
5203         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5204                 0xA000, 0x1000,
5205                 0, 0, pbn_b0_1_115200 },
5206
5207         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5208                 0xA000, 0x1000,
5209                 0, 0, pbn_b0_1_115200 },
5210
5211         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5212                 0xA000, 0x3002,
5213                 0, 0, pbn_NETMOS9900_2s_115200 },
5214
5215         /*
5216          * Best Connectivity and Rosewill PCI Multi I/O cards
5217          */
5218
5219         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5220                 0xA000, 0x1000,
5221                 0, 0, pbn_b0_1_115200 },
5222
5223         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5224                 0xA000, 0x3002,
5225                 0, 0, pbn_b0_bt_2_115200 },
5226
5227         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5228                 0xA000, 0x3004,
5229                 0, 0, pbn_b0_bt_4_115200 },
5230         /* Intel CE4100 */
5231         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5232                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5233                 pbn_ce4100_1_115200 },
5234         /* Intel BayTrail */
5235         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5236                 PCI_ANY_ID,  PCI_ANY_ID,
5237                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5238                 pbn_byt },
5239         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5240                 PCI_ANY_ID,  PCI_ANY_ID,
5241                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5242                 pbn_byt },
5243         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5244                 PCI_ANY_ID,  PCI_ANY_ID,
5245                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5246                 pbn_byt },
5247         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5248                 PCI_ANY_ID,  PCI_ANY_ID,
5249                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5250                 pbn_byt },
5251
5252         /*
5253          * Intel Quark x1000
5254          */
5255         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5257                 pbn_qrk },
5258         /*
5259          * Cronyx Omega PCI
5260          */
5261         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5263                 pbn_omegapci },
5264
5265         /*
5266          * Broadcom TruManage
5267          */
5268         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270                 pbn_brcm_trumanage },
5271
5272         /*
5273          * AgeStar as-prs2-009
5274          */
5275         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5276                 PCI_ANY_ID, PCI_ANY_ID,
5277                 0, 0, pbn_b0_bt_2_115200 },
5278
5279         /*
5280          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5281          * so not listed here.
5282          */
5283         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5284                 PCI_ANY_ID, PCI_ANY_ID,
5285                 0, 0, pbn_b0_bt_4_115200 },
5286
5287         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5288                 PCI_ANY_ID, PCI_ANY_ID,
5289                 0, 0, pbn_b0_bt_2_115200 },
5290
5291         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5292                 PCI_ANY_ID, PCI_ANY_ID,
5293                 0, 0, pbn_b0_bt_2_115200 },
5294
5295         /*
5296          * Commtech, Inc. Fastcom adapters
5297          */
5298         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5299                 PCI_ANY_ID, PCI_ANY_ID,
5300                 0,
5301                 0, pbn_b0_2_1152000_200 },
5302         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5303                 PCI_ANY_ID, PCI_ANY_ID,
5304                 0,
5305                 0, pbn_b0_4_1152000_200 },
5306         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5307                 PCI_ANY_ID, PCI_ANY_ID,
5308                 0,
5309                 0, pbn_b0_4_1152000_200 },
5310         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5311                 PCI_ANY_ID, PCI_ANY_ID,
5312                 0,
5313                 0, pbn_b0_8_1152000_200 },
5314         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5315                 PCI_ANY_ID, PCI_ANY_ID,
5316                 0,
5317                 0, pbn_exar_XR17V352 },
5318         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5319                 PCI_ANY_ID, PCI_ANY_ID,
5320                 0,
5321                 0, pbn_exar_XR17V354 },
5322         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5323                 PCI_ANY_ID, PCI_ANY_ID,
5324                 0,
5325                 0, pbn_exar_XR17V358 },
5326
5327         /* Fintek PCI serial cards */
5328         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5329         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5330         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5331
5332         /*
5333          * These entries match devices with class COMMUNICATION_SERIAL,
5334          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5335          */
5336         {       PCI_ANY_ID, PCI_ANY_ID,
5337                 PCI_ANY_ID, PCI_ANY_ID,
5338                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5339                 0xffff00, pbn_default },
5340         {       PCI_ANY_ID, PCI_ANY_ID,
5341                 PCI_ANY_ID, PCI_ANY_ID,
5342                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5343                 0xffff00, pbn_default },
5344         {       PCI_ANY_ID, PCI_ANY_ID,
5345                 PCI_ANY_ID, PCI_ANY_ID,
5346                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5347                 0xffff00, pbn_default },
5348         { 0, }
5349 };
5350
5351 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5352                                                 pci_channel_state_t state)
5353 {
5354         struct serial_private *priv = pci_get_drvdata(dev);
5355
5356         if (state == pci_channel_io_perm_failure)
5357                 return PCI_ERS_RESULT_DISCONNECT;
5358
5359         if (priv)
5360                 pciserial_suspend_ports(priv);
5361
5362         pci_disable_device(dev);
5363
5364         return PCI_ERS_RESULT_NEED_RESET;
5365 }
5366
5367 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5368 {
5369         int rc;
5370
5371         rc = pci_enable_device(dev);
5372
5373         if (rc)
5374                 return PCI_ERS_RESULT_DISCONNECT;
5375
5376         pci_restore_state(dev);
5377         pci_save_state(dev);
5378
5379         return PCI_ERS_RESULT_RECOVERED;
5380 }
5381
5382 static void serial8250_io_resume(struct pci_dev *dev)
5383 {
5384         struct serial_private *priv = pci_get_drvdata(dev);
5385
5386         if (priv)
5387                 pciserial_resume_ports(priv);
5388 }
5389
5390 static const struct pci_error_handlers serial8250_err_handler = {
5391         .error_detected = serial8250_io_error_detected,
5392         .slot_reset = serial8250_io_slot_reset,
5393         .resume = serial8250_io_resume,
5394 };
5395
5396 static struct pci_driver serial_pci_driver = {
5397         .name           = "serial",
5398         .probe          = pciserial_init_one,
5399         .remove         = pciserial_remove_one,
5400 #ifdef CONFIG_PM
5401         .suspend        = pciserial_suspend_one,
5402         .resume         = pciserial_resume_one,
5403 #endif
5404         .id_table       = serial_pci_tbl,
5405         .err_handler    = &serial8250_err_handler,
5406 };
5407
5408 module_pci_driver(serial_pci_driver);
5409
5410 MODULE_LICENSE("GPL");
5411 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5412 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);