drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18 #define SUPPORT_SYSRQ
  19 #endif
  20 #include <linux/kernel.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/slab.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/console.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/tty.h>
  28 #include <linux/tty_flip.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/dmi.h>
  32 #include <linux/nmi.h>
  33 #include <linux/delay.h>
  34
  35 #include <linux/debugfs.h>
  36 #include <linux/dmaengine.h>
  37 #include <linux/pch_dma.h>
  38
  39 enum {
  40         PCH_UART_HANDLED_RX_INT_SHIFT,
  41         PCH_UART_HANDLED_TX_INT_SHIFT,
  42         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  43         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  44         PCH_UART_HANDLED_MS_INT_SHIFT,
  45         PCH_UART_HANDLED_LS_INT_SHIFT,
  46 };
  47
  48 enum {
  49         PCH_UART_8LINE,
  50         PCH_UART_2LINE,
  51 };
  52
  53 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  54
  55 /* Set the max number of UART port
  56  * Intel EG20T PCH: 4 port
  57  * LAPIS Semiconductor ML7213 IOH: 3 port
  58  * LAPIS Semiconductor ML7223 IOH: 2 port
  59 */
  60 #define PCH_UART_NR     4
  61
  62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  64 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  65                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  66 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  67                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  69
  70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  71
  72 #define PCH_UART_RBR            0x00
  73 #define PCH_UART_THR            0x00
  74
  75 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  76                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  77 #define PCH_UART_IER_ERBFI      0x00000001
  78 #define PCH_UART_IER_ETBEI      0x00000002
  79 #define PCH_UART_IER_ELSI       0x00000004
  80 #define PCH_UART_IER_EDSSI      0x00000008
  81
  82 #define PCH_UART_IIR_IP                 0x00000001
  83 #define PCH_UART_IIR_IID                0x00000006
  84 #define PCH_UART_IIR_MSI                0x00000000
  85 #define PCH_UART_IIR_TRI                0x00000002
  86 #define PCH_UART_IIR_RRI                0x00000004
  87 #define PCH_UART_IIR_REI                0x00000006
  88 #define PCH_UART_IIR_TOI                0x00000008
  89 #define PCH_UART_IIR_FIFO256            0x00000020
  90 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  91 #define PCH_UART_IIR_FE                 0x000000C0
  92
  93 #define PCH_UART_FCR_FIFOE              0x00000001
  94 #define PCH_UART_FCR_RFR                0x00000002
  95 #define PCH_UART_FCR_TFR                0x00000004
  96 #define PCH_UART_FCR_DMS                0x00000008
  97 #define PCH_UART_FCR_FIFO256            0x00000020
  98 #define PCH_UART_FCR_RFTL               0x000000C0
  99
 100 #define PCH_UART_FCR_RFTL1              0x00000000
 101 #define PCH_UART_FCR_RFTL64             0x00000040
 102 #define PCH_UART_FCR_RFTL128            0x00000080
 103 #define PCH_UART_FCR_RFTL224            0x000000C0
 104 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
 105 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 106 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 107 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 108 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 109 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 110 #define PCH_UART_FCR_RFTL_SHIFT         6
 111
 112 #define PCH_UART_LCR_WLS        0x00000003
 113 #define PCH_UART_LCR_STB        0x00000004
 114 #define PCH_UART_LCR_PEN        0x00000008
 115 #define PCH_UART_LCR_EPS        0x00000010
 116 #define PCH_UART_LCR_SP         0x00000020
 117 #define PCH_UART_LCR_SB         0x00000040
 118 #define PCH_UART_LCR_DLAB       0x00000080
 119 #define PCH_UART_LCR_NP         0x00000000
 120 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 121 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 122 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 123 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 124                                 PCH_UART_LCR_SP)
 125
 126 #define PCH_UART_LCR_5BIT       0x00000000
 127 #define PCH_UART_LCR_6BIT       0x00000001
 128 #define PCH_UART_LCR_7BIT       0x00000002
 129 #define PCH_UART_LCR_8BIT       0x00000003
 130
 131 #define PCH_UART_MCR_DTR        0x00000001
 132 #define PCH_UART_MCR_RTS        0x00000002
 133 #define PCH_UART_MCR_OUT        0x0000000C
 134 #define PCH_UART_MCR_LOOP       0x00000010
 135 #define PCH_UART_MCR_AFE        0x00000020
 136
 137 #define PCH_UART_LSR_DR         0x00000001
 138 #define PCH_UART_LSR_ERR        (1<<7)
 139
 140 #define PCH_UART_MSR_DCTS       0x00000001
 141 #define PCH_UART_MSR_DDSR       0x00000002
 142 #define PCH_UART_MSR_TERI       0x00000004
 143 #define PCH_UART_MSR_DDCD       0x00000008
 144 #define PCH_UART_MSR_CTS        0x00000010
 145 #define PCH_UART_MSR_DSR        0x00000020
 146 #define PCH_UART_MSR_RI         0x00000040
 147 #define PCH_UART_MSR_DCD        0x00000080
 148 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 149                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 150
 151 #define PCH_UART_DLL            0x00
 152 #define PCH_UART_DLM            0x01
 153
 154 #define PCH_UART_BRCSR          0x0E
 155
 156 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 157 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 158 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 159 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 160 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 161
 162 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 163 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 164 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 165 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 166 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 167 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 168 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 169 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 170 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 171 #define PCH_UART_HAL_STB1               0
 172 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 173
 174 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 175 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 176 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 177                                         PCH_UART_HAL_CLR_RX_FIFO)
 178
 179 #define PCH_UART_HAL_DMA_MODE0          0
 180 #define PCH_UART_HAL_FIFO_DIS           0
 181 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 182 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 183                                         PCH_UART_FCR_FIFO256)
 184 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 185 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 186 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 187 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 188 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 189 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 190 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 191 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 192 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 193 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 194 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 195 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 196 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 197 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 198
 199 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 200 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 201 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 202 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 203 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 204
 205 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 206 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 207 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 208 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 209 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 210
 211 #define PCI_VENDOR_ID_ROHM              0x10DB
 212
 213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 214
 215 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 216 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 217 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 218 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 219 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 220
 221 struct pch_uart_buffer {
 222         unsigned char *buf;
 223         int size;
 224 };
 225
 226 struct eg20t_port {
 227         struct uart_port port;
 228         int port_type;
 229         void __iomem *membase;
 230         resource_size_t mapbase;
 231         unsigned int iobase;
 232         struct pci_dev *pdev;
 233         int fifo_size;
 234         int uartclk;
 235         int start_tx;
 236         int start_rx;
 237         int tx_empty;
 238         int trigger;
 239         int trigger_level;
 240         struct pch_uart_buffer rxbuf;
 241         unsigned int dmsr;
 242         unsigned int fcr;
 243         unsigned int mcr;
 244         unsigned int use_dma;
 245         struct dma_async_tx_descriptor  *desc_tx;
 246         struct dma_async_tx_descriptor  *desc_rx;
 247         struct pch_dma_slave            param_tx;
 248         struct pch_dma_slave            param_rx;
 249         struct dma_chan                 *chan_tx;
 250         struct dma_chan                 *chan_rx;
 251         struct scatterlist              *sg_tx_p;
 252         int                             nent;
 253         struct scatterlist              sg_rx;
 254         int                             tx_dma_use;
 255         void                            *rx_buf_virt;
 256         dma_addr_t                      rx_buf_dma;
 257
 258         struct dentry   *debugfs;
 259
 260         /* protect the eg20t_port private structure and io access to membase */
 261         spinlock_t lock;
 262 };
 263
 264 /**
 265  * struct pch_uart_driver_data - private data structure for UART-DMA
 266  * @port_type:                  The number of DMA channel
 267  * @line_no:                    UART port line number (0, 1, 2...)
 268  */
 269 struct pch_uart_driver_data {
 270         int port_type;
 271         int line_no;
 272 };
 273
 274 enum pch_uart_num_t {
 275         pch_et20t_uart0 = 0,
 276         pch_et20t_uart1,
 277         pch_et20t_uart2,
 278         pch_et20t_uart3,
 279         pch_ml7213_uart0,
 280         pch_ml7213_uart1,
 281         pch_ml7213_uart2,
 282         pch_ml7223_uart0,
 283         pch_ml7223_uart1,
 284         pch_ml7831_uart0,
 285         pch_ml7831_uart1,
 286 };
 287
 288 static struct pch_uart_driver_data drv_dat[] = {
 289         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 290         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 291         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 292         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 293         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 294         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 295         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 296         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 297         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 298         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 299         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 300 };
 301
 302 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 303 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 304 #endif
 305 static unsigned int default_baud = 9600;
 306 static unsigned int user_uartclk = 0;
 307 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 308 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 309 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 310 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 311
 312 #ifdef CONFIG_DEBUG_FS
 313
 314 #define PCH_REGS_BUFSIZE        1024
 315
 316
 317 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 318                                 size_t count, loff_t *ppos)
 319 {
 320         struct eg20t_port *priv = file->private_data;
 321         char *buf;
 322         u32 len = 0;
 323         ssize_t ret;
 324         unsigned char lcr;
 325
 326         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 327         if (!buf)
 328                 return 0;
 329
 330         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 331                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 332
 333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 334                         "=================================\n");
 335         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 336                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 337         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 338                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 339         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 340                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 341         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 342                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 343         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 344                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 345         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 346                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 347         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 348                         "BRCSR: \t0x%02x\n",
 349                         ioread8(priv->membase + PCH_UART_BRCSR));
 350
 351         lcr = ioread8(priv->membase + UART_LCR);
 352         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 353         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 354                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 355         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 356                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 357         iowrite8(lcr, priv->membase + UART_LCR);
 358
 359         if (len > PCH_REGS_BUFSIZE)
 360                 len = PCH_REGS_BUFSIZE;
 361
 362         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 363         kfree(buf);
 364         return ret;
 365 }
 366
 367 static const struct file_operations port_regs_ops = {
 368         .owner          = THIS_MODULE,
 369         .open           = simple_open,
 370         .read           = port_show_regs,
 371         .llseek         = default_llseek,
 372 };
 373 #endif  /* CONFIG_DEBUG_FS */
 374
 375 /* Return UART clock, checking for board specific clocks. */
 376 static int pch_uart_get_uartclk(void)
 377 {
 378         const char *cmp;
 379
 380         if (user_uartclk)
 381                 return user_uartclk;
 382
 383         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 384         if (cmp && strstr(cmp, "CM-iTC"))
 385                 return CMITC_UARTCLK;
 386
 387         cmp = dmi_get_system_info(DMI_BIOS_VERSION);
 388         if (cmp && strnstr(cmp, "FRI2", 4))
 389                 return FRI2_64_UARTCLK;
 390
 391         cmp = dmi_get_system_info(DMI_PRODUCT_NAME);
 392         if (cmp && strstr(cmp, "Fish River Island II"))
 393                 return FRI2_48_UARTCLK;
 394
 395         /* Kontron COMe-mTT10 (nanoETXexpress-TT) */
 396         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 397         if (cmp && (strstr(cmp, "COMe-mTT") ||
 398                     strstr(cmp, "nanoETXexpress-TT")))
 399                 return NTC1_UARTCLK;
 400
 401         return DEFAULT_UARTCLK;
 402 }
 403
 404 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 405                                           unsigned int flag)
 406 {
 407         u8 ier = ioread8(priv->membase + UART_IER);
 408         ier |= flag & PCH_UART_IER_MASK;
 409         iowrite8(ier, priv->membase + UART_IER);
 410 }
 411
 412 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 413                                            unsigned int flag)
 414 {
 415         u8 ier = ioread8(priv->membase + UART_IER);
 416         ier &= ~(flag & PCH_UART_IER_MASK);
 417         iowrite8(ier, priv->membase + UART_IER);
 418 }
 419
 420 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 421                                  unsigned int parity, unsigned int bits,
 422                                  unsigned int stb)
 423 {
 424         unsigned int dll, dlm, lcr;
 425         int div;
 426
 427         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 428         if (div < 0 || USHRT_MAX <= div) {
 429                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 430                 return -EINVAL;
 431         }
 432
 433         dll = (unsigned int)div & 0x00FFU;
 434         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 435
 436         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 437                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 438                 return -EINVAL;
 439         }
 440
 441         if (bits & ~PCH_UART_LCR_WLS) {
 442                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 443                 return -EINVAL;
 444         }
 445
 446         if (stb & ~PCH_UART_LCR_STB) {
 447                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 448                 return -EINVAL;
 449         }
 450
 451         lcr = parity;
 452         lcr |= bits;
 453         lcr |= stb;
 454
 455         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 456                  __func__, baud, div, lcr, jiffies);
 457         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 458         iowrite8(dll, priv->membase + PCH_UART_DLL);
 459         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 460         iowrite8(lcr, priv->membase + UART_LCR);
 461
 462         return 0;
 463 }
 464
 465 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 466                                     unsigned int flag)
 467 {
 468         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 469                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 470                         __func__, flag);
 471                 return -EINVAL;
 472         }
 473
 474         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 475         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 476                  priv->membase + UART_FCR);
 477         iowrite8(priv->fcr, priv->membase + UART_FCR);
 478
 479         return 0;
 480 }
 481
 482 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 483                                  unsigned int dmamode,
 484                                  unsigned int fifo_size, unsigned int trigger)
 485 {
 486         u8 fcr;
 487
 488         if (dmamode & ~PCH_UART_FCR_DMS) {
 489                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 490                         __func__, dmamode);
 491                 return -EINVAL;
 492         }
 493
 494         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 495                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 496                         __func__, fifo_size);
 497                 return -EINVAL;
 498         }
 499
 500         if (trigger & ~PCH_UART_FCR_RFTL) {
 501                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 502                         __func__, trigger);
 503                 return -EINVAL;
 504         }
 505
 506         switch (priv->fifo_size) {
 507         case 256:
 508                 priv->trigger_level =
 509                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 510                 break;
 511         case 64:
 512                 priv->trigger_level =
 513                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 514                 break;
 515         case 16:
 516                 priv->trigger_level =
 517                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 518                 break;
 519         default:
 520                 priv->trigger_level =
 521                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 522                 break;
 523         }
 524         fcr =
 525             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 526         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 527         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 528                  priv->membase + UART_FCR);
 529         iowrite8(fcr, priv->membase + UART_FCR);
 530         priv->fcr = fcr;
 531
 532         return 0;
 533 }
 534
 535 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 536 {
 537         unsigned int msr = ioread8(priv->membase + UART_MSR);
 538         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 539         return (u8)msr;
 540 }
 541
 542 static void pch_uart_hal_write(struct eg20t_port *priv,
 543                               const unsigned char *buf, int tx_size)
 544 {
 545         int i;
 546         unsigned int thr;
 547
 548         for (i = 0; i < tx_size;) {
 549                 thr = buf[i++];
 550                 iowrite8(thr, priv->membase + PCH_UART_THR);
 551         }
 552 }
 553
 554 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 555                              int rx_size)
 556 {
 557         int i;
 558         u8 rbr, lsr;
 559         struct uart_port *port = &priv->port;
 560
 561         lsr = ioread8(priv->membase + UART_LSR);
 562         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 563              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 564              lsr = ioread8(priv->membase + UART_LSR)) {
 565                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 566
 567                 if (lsr & UART_LSR_BI) {
 568                         port->icount.brk++;
 569                         if (uart_handle_break(port))
 570                                 continue;
 571                 }
 572                 if (port->sysrq) {
 573                         if (uart_handle_sysrq_char(port, rbr))
 574                                 continue;
 575                 }
 576
 577                 buf[i++] = rbr;
 578         }
 579         return i;
 580 }
 581
 582 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 583 {
 584         return ioread8(priv->membase + UART_IIR) &\
 585                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 586 }
 587
 588 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 589 {
 590         return ioread8(priv->membase + UART_LSR);
 591 }
 592
 593 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 594 {
 595         unsigned int lcr;
 596
 597         lcr = ioread8(priv->membase + UART_LCR);
 598         if (on)
 599                 lcr |= PCH_UART_LCR_SB;
 600         else
 601                 lcr &= ~PCH_UART_LCR_SB;
 602
 603         iowrite8(lcr, priv->membase + UART_LCR);
 604 }
 605
 606 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 607                    int size)
 608 {
 609         struct uart_port *port = &priv->port;
 610         struct tty_port *tport = &port->state->port;
 611
 612         tty_insert_flip_string(tport, buf, size);
 613         tty_flip_buffer_push(tport);
 614
 615         return 0;
 616 }
 617
 618 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 619 {
 620         int ret = 0;
 621         struct uart_port *port = &priv->port;
 622
 623         if (port->x_char) {
 624                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 625                         __func__, port->x_char, jiffies);
 626                 buf[0] = port->x_char;
 627                 port->x_char = 0;
 628                 ret = 1;
 629         }
 630
 631         return ret;
 632 }
 633
 634 static int dma_push_rx(struct eg20t_port *priv, int size)
 635 {
 636         struct tty_struct *tty;
 637         int room;
 638         struct uart_port *port = &priv->port;
 639         struct tty_port *tport = &port->state->port;
 640
 641         port = &priv->port;
 642         tty = tty_port_tty_get(tport);
 643         if (!tty) {
 644                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 645                 return 0;
 646         }
 647
 648         room = tty_buffer_request_room(tport, size);
 649
 650         if (room < size)
 651                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 652                          size - room);
 653         if (!room)
 654                 return room;
 655
 656         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 657
 658         port->icount.rx += room;
 659         tty_kref_put(tty);
 660
 661         return room;
 662 }
 663
 664 static void pch_free_dma(struct uart_port *port)
 665 {
 666         struct eg20t_port *priv;
 667         priv = container_of(port, struct eg20t_port, port);
 668
 669         if (priv->chan_tx) {
 670                 dma_release_channel(priv->chan_tx);
 671                 priv->chan_tx = NULL;
 672         }
 673         if (priv->chan_rx) {
 674                 dma_release_channel(priv->chan_rx);
 675                 priv->chan_rx = NULL;
 676         }
 677
 678         if (priv->rx_buf_dma) {
 679                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 680                                   priv->rx_buf_dma);
 681                 priv->rx_buf_virt = NULL;
 682                 priv->rx_buf_dma = 0;
 683         }
 684
 685         return;
 686 }
 687
 688 static bool filter(struct dma_chan *chan, void *slave)
 689 {
 690         struct pch_dma_slave *param = slave;
 691
 692         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 693                                                   chan->device->dev)) {
 694                 chan->private = param;
 695                 return true;
 696         } else {
 697                 return false;
 698         }
 699 }
 700
 701 static void pch_request_dma(struct uart_port *port)
 702 {
 703         dma_cap_mask_t mask;
 704         struct dma_chan *chan;
 705         struct pci_dev *dma_dev;
 706         struct pch_dma_slave *param;
 707         struct eg20t_port *priv =
 708                                 container_of(port, struct eg20t_port, port);
 709         dma_cap_zero(mask);
 710         dma_cap_set(DMA_SLAVE, mask);
 711
 712         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 713                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 714                                                                 information */
 715         /* Set Tx DMA */
 716         param = &priv->param_tx;
 717         param->dma_dev = &dma_dev->dev;
 718         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 719
 720         param->tx_reg = port->mapbase + UART_TX;
 721         chan = dma_request_channel(mask, filter, param);
 722         if (!chan) {
 723                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 724                         __func__);
 725                 return;
 726         }
 727         priv->chan_tx = chan;
 728
 729         /* Set Rx DMA */
 730         param = &priv->param_rx;
 731         param->dma_dev = &dma_dev->dev;
 732         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 733
 734         param->rx_reg = port->mapbase + UART_RX;
 735         chan = dma_request_channel(mask, filter, param);
 736         if (!chan) {
 737                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 738                         __func__);
 739                 dma_release_channel(priv->chan_tx);
 740                 priv->chan_tx = NULL;
 741                 return;
 742         }
 743
 744         /* Get Consistent memory for DMA */
 745         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 746                                     &priv->rx_buf_dma, GFP_KERNEL);
 747         priv->chan_rx = chan;
 748 }
 749
 750 static void pch_dma_rx_complete(void *arg)
 751 {
 752         struct eg20t_port *priv = arg;
 753         struct uart_port *port = &priv->port;
 754         int count;
 755
 756         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 757         count = dma_push_rx(priv, priv->trigger_level);
 758         if (count)
 759                 tty_flip_buffer_push(&port->state->port);
 760         async_tx_ack(priv->desc_rx);
 761         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 762                                             PCH_UART_HAL_RX_ERR_INT);
 763 }
 764
 765 static void pch_dma_tx_complete(void *arg)
 766 {
 767         struct eg20t_port *priv = arg;
 768         struct uart_port *port = &priv->port;
 769         struct circ_buf *xmit = &port->state->xmit;
 770         struct scatterlist *sg = priv->sg_tx_p;
 771         int i;
 772
 773         for (i = 0; i < priv->nent; i++, sg++) {
 774                 xmit->tail += sg_dma_len(sg);
 775                 port->icount.tx += sg_dma_len(sg);
 776         }
 777         xmit->tail &= UART_XMIT_SIZE - 1;
 778         async_tx_ack(priv->desc_tx);
 779         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 780         priv->tx_dma_use = 0;
 781         priv->nent = 0;
 782         kfree(priv->sg_tx_p);
 783         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 784 }
 785
 786 static int pop_tx(struct eg20t_port *priv, int size)
 787 {
 788         int count = 0;
 789         struct uart_port *port = &priv->port;
 790         struct circ_buf *xmit = &port->state->xmit;
 791
 792         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 793                 goto pop_tx_end;
 794
 795         do {
 796                 int cnt_to_end =
 797                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 798                 int sz = min(size - count, cnt_to_end);
 799                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 800                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 801                 count += sz;
 802         } while (!uart_circ_empty(xmit) && count < size);
 803
 804 pop_tx_end:
 805         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 806                  count, size - count, jiffies);
 807
 808         return count;
 809 }
 810
 811 static int handle_rx_to(struct eg20t_port *priv)
 812 {
 813         struct pch_uart_buffer *buf;
 814         int rx_size;
 815         int ret;
 816         if (!priv->start_rx) {
 817                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 818                                                      PCH_UART_HAL_RX_ERR_INT);
 819                 return 0;
 820         }
 821         buf = &priv->rxbuf;
 822         do {
 823                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 824                 ret = push_rx(priv, buf->buf, rx_size);
 825                 if (ret)
 826                         return 0;
 827         } while (rx_size == buf->size);
 828
 829         return PCH_UART_HANDLED_RX_INT;
 830 }
 831
 832 static int handle_rx(struct eg20t_port *priv)
 833 {
 834         return handle_rx_to(priv);
 835 }
 836
 837 static int dma_handle_rx(struct eg20t_port *priv)
 838 {
 839         struct uart_port *port = &priv->port;
 840         struct dma_async_tx_descriptor *desc;
 841         struct scatterlist *sg;
 842
 843         priv = container_of(port, struct eg20t_port, port);
 844         sg = &priv->sg_rx;
 845
 846         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 847
 848         sg_dma_len(sg) = priv->trigger_level;
 849
 850         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 851                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 852                      ~PAGE_MASK);
 853
 854         sg_dma_address(sg) = priv->rx_buf_dma;
 855
 856         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 857                         sg, 1, DMA_DEV_TO_MEM,
 858                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 859
 860         if (!desc)
 861                 return 0;
 862
 863         priv->desc_rx = desc;
 864         desc->callback = pch_dma_rx_complete;
 865         desc->callback_param = priv;
 866         desc->tx_submit(desc);
 867         dma_async_issue_pending(priv->chan_rx);
 868
 869         return PCH_UART_HANDLED_RX_INT;
 870 }
 871
 872 static unsigned int handle_tx(struct eg20t_port *priv)
 873 {
 874         struct uart_port *port = &priv->port;
 875         struct circ_buf *xmit = &port->state->xmit;
 876         int fifo_size;
 877         int tx_size;
 878         int size;
 879         int tx_empty;
 880
 881         if (!priv->start_tx) {
 882                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 883                         __func__, jiffies);
 884                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 885                 priv->tx_empty = 1;
 886                 return 0;
 887         }
 888
 889         fifo_size = max(priv->fifo_size, 1);
 890         tx_empty = 1;
 891         if (pop_tx_x(priv, xmit->buf)) {
 892                 pch_uart_hal_write(priv, xmit->buf, 1);
 893                 port->icount.tx++;
 894                 tx_empty = 0;
 895                 fifo_size--;
 896         }
 897         size = min(xmit->head - xmit->tail, fifo_size);
 898         if (size < 0)
 899                 size = fifo_size;
 900
 901         tx_size = pop_tx(priv, size);
 902         if (tx_size > 0) {
 903                 port->icount.tx += tx_size;
 904                 tx_empty = 0;
 905         }
 906
 907         priv->tx_empty = tx_empty;
 908
 909         if (tx_empty) {
 910                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 911                 uart_write_wakeup(port);
 912         }
 913
 914         return PCH_UART_HANDLED_TX_INT;
 915 }
 916
 917 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 918 {
 919         struct uart_port *port = &priv->port;
 920         struct circ_buf *xmit = &port->state->xmit;
 921         struct scatterlist *sg;
 922         int nent;
 923         int fifo_size;
 924         int tx_empty;
 925         struct dma_async_tx_descriptor *desc;
 926         int num;
 927         int i;
 928         int bytes;
 929         int size;
 930         int rem;
 931
 932         if (!priv->start_tx) {
 933                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 934                         __func__, jiffies);
 935                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 936                 priv->tx_empty = 1;
 937                 return 0;
 938         }
 939
 940         if (priv->tx_dma_use) {
 941                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 942                         __func__, jiffies);
 943                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 944                 priv->tx_empty = 1;
 945                 return 0;
 946         }
 947
 948         fifo_size = max(priv->fifo_size, 1);
 949         tx_empty = 1;
 950         if (pop_tx_x(priv, xmit->buf)) {
 951                 pch_uart_hal_write(priv, xmit->buf, 1);
 952                 port->icount.tx++;
 953                 tx_empty = 0;
 954                 fifo_size--;
 955         }
 956
 957         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 958                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 959                              xmit->tail, UART_XMIT_SIZE));
 960         if (!bytes) {
 961                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 962                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 963                 uart_write_wakeup(port);
 964                 return 0;
 965         }
 966
 967         if (bytes > fifo_size) {
 968                 num = bytes / fifo_size + 1;
 969                 size = fifo_size;
 970                 rem = bytes % fifo_size;
 971         } else {
 972                 num = 1;
 973                 size = bytes;
 974                 rem = bytes;
 975         }
 976
 977         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 978                 __func__, num, size, rem);
 979
 980         priv->tx_dma_use = 1;
 981
 982         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 983         if (!priv->sg_tx_p) {
 984                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
 985                 return 0;
 986         }
 987
 988         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 989         sg = priv->sg_tx_p;
 990
 991         for (i = 0; i < num; i++, sg++) {
 992                 if (i == (num - 1))
 993                         sg_set_page(sg, virt_to_page(xmit->buf),
 994                                     rem, fifo_size * i);
 995                 else
 996                         sg_set_page(sg, virt_to_page(xmit->buf),
 997                                     size, fifo_size * i);
 998         }
 999
1000         sg = priv->sg_tx_p;
1001         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1002         if (!nent) {
1003                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1004                 return 0;
1005         }
1006         priv->nent = nent;
1007
1008         for (i = 0; i < nent; i++, sg++) {
1009                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1010                               fifo_size * i;
1011                 sg_dma_address(sg) = (sg_dma_address(sg) &
1012                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1013                 if (i == (nent - 1))
1014                         sg_dma_len(sg) = rem;
1015                 else
1016                         sg_dma_len(sg) = size;
1017         }
1018
1019         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1020                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1021                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1022         if (!desc) {
1023                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1024                         __func__);
1025                 return 0;
1026         }
1027         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1028         priv->desc_tx = desc;
1029         desc->callback = pch_dma_tx_complete;
1030         desc->callback_param = priv;
1031
1032         desc->tx_submit(desc);
1033
1034         dma_async_issue_pending(priv->chan_tx);
1035
1036         return PCH_UART_HANDLED_TX_INT;
1037 }
1038
1039 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1040 {
1041         struct uart_port *port = &priv->port;
1042         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1043         char   *error_msg[5] = {};
1044         int    i = 0;
1045
1046         if (lsr & PCH_UART_LSR_ERR)
1047                 error_msg[i++] = "Error data in FIFO\n";
1048
1049         if (lsr & UART_LSR_FE) {
1050                 port->icount.frame++;
1051                 error_msg[i++] = "  Framing Error\n";
1052         }
1053
1054         if (lsr & UART_LSR_PE) {
1055                 port->icount.parity++;
1056                 error_msg[i++] = "  Parity Error\n";
1057         }
1058
1059         if (lsr & UART_LSR_OE) {
1060                 port->icount.overrun++;
1061                 error_msg[i++] = "  Overrun Error\n";
1062         }
1063
1064         if (tty == NULL) {
1065                 for (i = 0; error_msg[i] != NULL; i++)
1066                         dev_err(&priv->pdev->dev, error_msg[i]);
1067         }
1068 }
1069
1070 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1071 {
1072         struct eg20t_port *priv = dev_id;
1073         unsigned int handled;
1074         u8 lsr;
1075         int ret = 0;
1076         unsigned char iid;
1077         unsigned long flags;
1078         int next = 1;
1079         u8 msr;
1080
1081         spin_lock_irqsave(&priv->lock, flags);
1082         handled = 0;
1083         while (next) {
1084                 iid = pch_uart_hal_get_iid(priv);
1085                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1086                         break;
1087                 switch (iid) {
1088                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1089                         lsr = pch_uart_hal_get_line_status(priv);
1090                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1091                                                 UART_LSR_PE | UART_LSR_OE)) {
1092                                 pch_uart_err_ir(priv, lsr);
1093                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1094                         } else {
1095                                 ret = PCH_UART_HANDLED_LS_INT;
1096                         }
1097                         break;
1098                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1099                         if (priv->use_dma) {
1100                                 pch_uart_hal_disable_interrupt(priv,
1101                                                 PCH_UART_HAL_RX_INT |
1102                                                 PCH_UART_HAL_RX_ERR_INT);
1103                                 ret = dma_handle_rx(priv);
1104                                 if (!ret)
1105                                         pch_uart_hal_enable_interrupt(priv,
1106                                                 PCH_UART_HAL_RX_INT |
1107                                                 PCH_UART_HAL_RX_ERR_INT);
1108                         } else {
1109                                 ret = handle_rx(priv);
1110                         }
1111                         break;
1112                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1113                                                    (FIFO Timeout) */
1114                         ret = handle_rx_to(priv);
1115                         break;
1116                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1117                                                    Empty */
1118                         if (priv->use_dma)
1119                                 ret = dma_handle_tx(priv);
1120                         else
1121                                 ret = handle_tx(priv);
1122                         break;
1123                 case PCH_UART_IID_MS:   /* Modem Status */
1124                         msr = pch_uart_hal_get_modem(priv);
1125                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1126                                      means final interrupt */
1127                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1128                                 break;
1129                         ret |= PCH_UART_HANDLED_MS_INT;
1130                         break;
1131                 default:        /* Never junp to this label */
1132                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1133                                 iid, jiffies);
1134                         ret = -1;
1135                         next = 0;
1136                         break;
1137                 }
1138                 handled |= (unsigned int)ret;
1139         }
1140
1141         spin_unlock_irqrestore(&priv->lock, flags);
1142         return IRQ_RETVAL(handled);
1143 }
1144
1145 /* This function tests whether the transmitter fifo and shifter for the port
1146                                                 described by 'port' is empty. */
1147 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1148 {
1149         struct eg20t_port *priv;
1150
1151         priv = container_of(port, struct eg20t_port, port);
1152         if (priv->tx_empty)
1153                 return TIOCSER_TEMT;
1154         else
1155                 return 0;
1156 }
1157
1158 /* Returns the current state of modem control inputs. */
1159 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1160 {
1161         struct eg20t_port *priv;
1162         u8 modem;
1163         unsigned int ret = 0;
1164
1165         priv = container_of(port, struct eg20t_port, port);
1166         modem = pch_uart_hal_get_modem(priv);
1167
1168         if (modem & UART_MSR_DCD)
1169                 ret |= TIOCM_CAR;
1170
1171         if (modem & UART_MSR_RI)
1172                 ret |= TIOCM_RNG;
1173
1174         if (modem & UART_MSR_DSR)
1175                 ret |= TIOCM_DSR;
1176
1177         if (modem & UART_MSR_CTS)
1178                 ret |= TIOCM_CTS;
1179
1180         return ret;
1181 }
1182
1183 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1184 {
1185         u32 mcr = 0;
1186         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1187
1188         if (mctrl & TIOCM_DTR)
1189                 mcr |= UART_MCR_DTR;
1190         if (mctrl & TIOCM_RTS)
1191                 mcr |= UART_MCR_RTS;
1192         if (mctrl & TIOCM_LOOP)
1193                 mcr |= UART_MCR_LOOP;
1194
1195         if (priv->mcr & UART_MCR_AFE)
1196                 mcr |= UART_MCR_AFE;
1197
1198         if (mctrl)
1199                 iowrite8(mcr, priv->membase + UART_MCR);
1200 }
1201
1202 static void pch_uart_stop_tx(struct uart_port *port)
1203 {
1204         struct eg20t_port *priv;
1205         priv = container_of(port, struct eg20t_port, port);
1206         priv->start_tx = 0;
1207         priv->tx_dma_use = 0;
1208 }
1209
1210 static void pch_uart_start_tx(struct uart_port *port)
1211 {
1212         struct eg20t_port *priv;
1213
1214         priv = container_of(port, struct eg20t_port, port);
1215
1216         if (priv->use_dma) {
1217                 if (priv->tx_dma_use) {
1218                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1219                                 __func__);
1220                         return;
1221                 }
1222         }
1223
1224         priv->start_tx = 1;
1225         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1226 }
1227
1228 static void pch_uart_stop_rx(struct uart_port *port)
1229 {
1230         struct eg20t_port *priv;
1231         priv = container_of(port, struct eg20t_port, port);
1232         priv->start_rx = 0;
1233         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1234                                              PCH_UART_HAL_RX_ERR_INT);
1235 }
1236
1237 /* Enable the modem status interrupts. */
1238 static void pch_uart_enable_ms(struct uart_port *port)
1239 {
1240         struct eg20t_port *priv;
1241         priv = container_of(port, struct eg20t_port, port);
1242         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1243 }
1244
1245 /* Control the transmission of a break signal. */
1246 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1247 {
1248         struct eg20t_port *priv;
1249         unsigned long flags;
1250
1251         priv = container_of(port, struct eg20t_port, port);
1252         spin_lock_irqsave(&priv->lock, flags);
1253         pch_uart_hal_set_break(priv, ctl);
1254         spin_unlock_irqrestore(&priv->lock, flags);
1255 }
1256
1257 /* Grab any interrupt resources and initialise any low level driver state. */
1258 static int pch_uart_startup(struct uart_port *port)
1259 {
1260         struct eg20t_port *priv;
1261         int ret;
1262         int fifo_size;
1263         int trigger_level;
1264
1265         priv = container_of(port, struct eg20t_port, port);
1266         priv->tx_empty = 1;
1267
1268         if (port->uartclk)
1269                 priv->uartclk = port->uartclk;
1270         else
1271                 port->uartclk = priv->uartclk;
1272
1273         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1274         ret = pch_uart_hal_set_line(priv, default_baud,
1275                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1276                               PCH_UART_HAL_STB1);
1277         if (ret)
1278                 return ret;
1279
1280         switch (priv->fifo_size) {
1281         case 256:
1282                 fifo_size = PCH_UART_HAL_FIFO256;
1283                 break;
1284         case 64:
1285                 fifo_size = PCH_UART_HAL_FIFO64;
1286                 break;
1287         case 16:
1288                 fifo_size = PCH_UART_HAL_FIFO16;
1289                 break;
1290         case 1:
1291         default:
1292                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1293                 break;
1294         }
1295
1296         switch (priv->trigger) {
1297         case PCH_UART_HAL_TRIGGER1:
1298                 trigger_level = 1;
1299                 break;
1300         case PCH_UART_HAL_TRIGGER_L:
1301                 trigger_level = priv->fifo_size / 4;
1302                 break;
1303         case PCH_UART_HAL_TRIGGER_M:
1304                 trigger_level = priv->fifo_size / 2;
1305                 break;
1306         case PCH_UART_HAL_TRIGGER_H:
1307         default:
1308                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1309                 break;
1310         }
1311
1312         priv->trigger_level = trigger_level;
1313         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1314                                     fifo_size, priv->trigger);
1315         if (ret < 0)
1316                 return ret;
1317
1318         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1319                         KBUILD_MODNAME, priv);
1320         if (ret < 0)
1321                 return ret;
1322
1323         if (priv->use_dma)
1324                 pch_request_dma(port);
1325
1326         priv->start_rx = 1;
1327         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1328                                             PCH_UART_HAL_RX_ERR_INT);
1329         uart_update_timeout(port, CS8, default_baud);
1330
1331         return 0;
1332 }
1333
1334 static void pch_uart_shutdown(struct uart_port *port)
1335 {
1336         struct eg20t_port *priv;
1337         int ret;
1338
1339         priv = container_of(port, struct eg20t_port, port);
1340         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1341         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1342         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1343                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1344         if (ret)
1345                 dev_err(priv->port.dev,
1346                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1347
1348         pch_free_dma(port);
1349
1350         free_irq(priv->port.irq, priv);
1351 }
1352
1353 /* Change the port parameters, including word length, parity, stop
1354  *bits.  Update read_status_mask and ignore_status_mask to indicate
1355  *the types of events we are interested in receiving.  */
1356 static void pch_uart_set_termios(struct uart_port *port,
1357                                  struct ktermios *termios, struct ktermios *old)
1358 {
1359         int baud;
1360         int rtn;
1361         unsigned int parity, bits, stb;
1362         struct eg20t_port *priv;
1363         unsigned long flags;
1364
1365         priv = container_of(port, struct eg20t_port, port);
1366         switch (termios->c_cflag & CSIZE) {
1367         case CS5:
1368                 bits = PCH_UART_HAL_5BIT;
1369                 break;
1370         case CS6:
1371                 bits = PCH_UART_HAL_6BIT;
1372                 break;
1373         case CS7:
1374                 bits = PCH_UART_HAL_7BIT;
1375                 break;
1376         default:                /* CS8 */
1377                 bits = PCH_UART_HAL_8BIT;
1378                 break;
1379         }
1380         if (termios->c_cflag & CSTOPB)
1381                 stb = PCH_UART_HAL_STB2;
1382         else
1383                 stb = PCH_UART_HAL_STB1;
1384
1385         if (termios->c_cflag & PARENB) {
1386                 if (termios->c_cflag & PARODD)
1387                         parity = PCH_UART_HAL_PARITY_ODD;
1388                 else
1389                         parity = PCH_UART_HAL_PARITY_EVEN;
1390
1391         } else
1392                 parity = PCH_UART_HAL_PARITY_NONE;
1393
1394         /* Only UART0 has auto hardware flow function */
1395         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1396                 priv->mcr |= UART_MCR_AFE;
1397         else
1398                 priv->mcr &= ~UART_MCR_AFE;
1399
1400         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1401
1402         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1403
1404         spin_lock_irqsave(&priv->lock, flags);
1405         spin_lock(&port->lock);
1406
1407         uart_update_timeout(port, termios->c_cflag, baud);
1408         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1409         if (rtn)
1410                 goto out;
1411
1412         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1413         /* Don't rewrite B0 */
1414         if (tty_termios_baud_rate(termios))
1415                 tty_termios_encode_baud_rate(termios, baud, baud);
1416
1417 out:
1418         spin_unlock(&port->lock);
1419         spin_unlock_irqrestore(&priv->lock, flags);
1420 }
1421
1422 static const char *pch_uart_type(struct uart_port *port)
1423 {
1424         return KBUILD_MODNAME;
1425 }
1426
1427 static void pch_uart_release_port(struct uart_port *port)
1428 {
1429         struct eg20t_port *priv;
1430
1431         priv = container_of(port, struct eg20t_port, port);
1432         pci_iounmap(priv->pdev, priv->membase);
1433         pci_release_regions(priv->pdev);
1434 }
1435
1436 static int pch_uart_request_port(struct uart_port *port)
1437 {
1438         struct eg20t_port *priv;
1439         int ret;
1440         void __iomem *membase;
1441
1442         priv = container_of(port, struct eg20t_port, port);
1443         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1444         if (ret < 0)
1445                 return -EBUSY;
1446
1447         membase = pci_iomap(priv->pdev, 1, 0);
1448         if (!membase) {
1449                 pci_release_regions(priv->pdev);
1450                 return -EBUSY;
1451         }
1452         priv->membase = port->membase = membase;
1453
1454         return 0;
1455 }
1456
1457 static void pch_uart_config_port(struct uart_port *port, int type)
1458 {
1459         struct eg20t_port *priv;
1460
1461         priv = container_of(port, struct eg20t_port, port);
1462         if (type & UART_CONFIG_TYPE) {
1463                 port->type = priv->port_type;
1464                 pch_uart_request_port(port);
1465         }
1466 }
1467
1468 static int pch_uart_verify_port(struct uart_port *port,
1469                                 struct serial_struct *serinfo)
1470 {
1471         struct eg20t_port *priv;
1472
1473         priv = container_of(port, struct eg20t_port, port);
1474         if (serinfo->flags & UPF_LOW_LATENCY) {
1475                 dev_info(priv->port.dev,
1476                         "PCH UART : Use PIO Mode (without DMA)\n");
1477                 priv->use_dma = 0;
1478                 serinfo->flags &= ~UPF_LOW_LATENCY;
1479         } else {
1480 #ifndef CONFIG_PCH_DMA
1481                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1482                         __func__);
1483                 return -EOPNOTSUPP;
1484 #endif
1485                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1486                 if (!priv->use_dma)
1487                         pch_request_dma(port);
1488                 priv->use_dma = 1;
1489         }
1490
1491         return 0;
1492 }
1493
1494 static struct uart_ops pch_uart_ops = {
1495         .tx_empty = pch_uart_tx_empty,
1496         .set_mctrl = pch_uart_set_mctrl,
1497         .get_mctrl = pch_uart_get_mctrl,
1498         .stop_tx = pch_uart_stop_tx,
1499         .start_tx = pch_uart_start_tx,
1500         .stop_rx = pch_uart_stop_rx,
1501         .enable_ms = pch_uart_enable_ms,
1502         .break_ctl = pch_uart_break_ctl,
1503         .startup = pch_uart_startup,
1504         .shutdown = pch_uart_shutdown,
1505         .set_termios = pch_uart_set_termios,
1506 /*      .pm             = pch_uart_pm,          Not supported yet */
1507 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1508         .type = pch_uart_type,
1509         .release_port = pch_uart_release_port,
1510         .request_port = pch_uart_request_port,
1511         .config_port = pch_uart_config_port,
1512         .verify_port = pch_uart_verify_port
1513 };
1514
1515 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1516
1517 /*
1518  *      Wait for transmitter & holding register to empty
1519  */
1520 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1521 {
1522         unsigned int status, tmout = 10000;
1523
1524         /* Wait up to 10ms for the character(s) to be sent. */
1525         for (;;) {
1526                 status = ioread8(up->membase + UART_LSR);
1527
1528                 if ((status & bits) == bits)
1529                         break;
1530                 if (--tmout == 0)
1531                         break;
1532                 udelay(1);
1533         }
1534
1535         /* Wait up to 1s for flow control if necessary */
1536         if (up->port.flags & UPF_CONS_FLOW) {
1537                 unsigned int tmout;
1538                 for (tmout = 1000000; tmout; tmout--) {
1539                         unsigned int msr = ioread8(up->membase + UART_MSR);
1540                         if (msr & UART_MSR_CTS)
1541                                 break;
1542                         udelay(1);
1543                         touch_nmi_watchdog();
1544                 }
1545         }
1546 }
1547
1548 static void pch_console_putchar(struct uart_port *port, int ch)
1549 {
1550         struct eg20t_port *priv =
1551                 container_of(port, struct eg20t_port, port);
1552
1553         wait_for_xmitr(priv, UART_LSR_THRE);
1554         iowrite8(ch, priv->membase + PCH_UART_THR);
1555 }
1556
1557 /*
1558  *      Print a string to the serial port trying not to disturb
1559  *      any possible real use of the port...
1560  *
1561  *      The console_lock must be held when we get here.
1562  */
1563 static void
1564 pch_console_write(struct console *co, const char *s, unsigned int count)
1565 {
1566         struct eg20t_port *priv;
1567         unsigned long flags;
1568         int priv_locked = 1;
1569         int port_locked = 1;
1570         u8 ier;
1571
1572         priv = pch_uart_ports[co->index];
1573
1574         touch_nmi_watchdog();
1575
1576         local_irq_save(flags);
1577         if (priv->port.sysrq) {
1578                 /* call to uart_handle_sysrq_char already took the priv lock */
1579                 priv_locked = 0;
1580                 /* serial8250_handle_port() already took the port lock */
1581                 port_locked = 0;
1582         } else if (oops_in_progress) {
1583                 priv_locked = spin_trylock(&priv->lock);
1584                 port_locked = spin_trylock(&priv->port.lock);
1585         } else {
1586                 spin_lock(&priv->lock);
1587                 spin_lock(&priv->port.lock);
1588         }
1589
1590         /*
1591          *      First save the IER then disable the interrupts
1592          */
1593         ier = ioread8(priv->membase + UART_IER);
1594
1595         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1596
1597         uart_console_write(&priv->port, s, count, pch_console_putchar);
1598
1599         /*
1600          *      Finally, wait for transmitter to become empty
1601          *      and restore the IER
1602          */
1603         wait_for_xmitr(priv, BOTH_EMPTY);
1604         iowrite8(ier, priv->membase + UART_IER);
1605
1606         if (port_locked)
1607                 spin_unlock(&priv->port.lock);
1608         if (priv_locked)
1609                 spin_unlock(&priv->lock);
1610         local_irq_restore(flags);
1611 }
1612
1613 static int __init pch_console_setup(struct console *co, char *options)
1614 {
1615         struct uart_port *port;
1616         int baud = default_baud;
1617         int bits = 8;
1618         int parity = 'n';
1619         int flow = 'n';
1620
1621         /*
1622          * Check whether an invalid uart number has been specified, and
1623          * if so, search for the first available port that does have
1624          * console support.
1625          */
1626         if (co->index >= PCH_UART_NR)
1627                 co->index = 0;
1628         port = &pch_uart_ports[co->index]->port;
1629
1630         if (!port || (!port->iobase && !port->membase))
1631                 return -ENODEV;
1632
1633         port->uartclk = pch_uart_get_uartclk();
1634
1635         if (options)
1636                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1637
1638         return uart_set_options(port, co, baud, parity, bits, flow);
1639 }
1640
1641 static struct uart_driver pch_uart_driver;
1642
1643 static struct console pch_console = {
1644         .name           = PCH_UART_DRIVER_DEVICE,
1645         .write          = pch_console_write,
1646         .device         = uart_console_device,
1647         .setup          = pch_console_setup,
1648         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1649         .index          = -1,
1650         .data           = &pch_uart_driver,
1651 };
1652
1653 #define PCH_CONSOLE     (&pch_console)
1654 #else
1655 #define PCH_CONSOLE     NULL
1656 #endif
1657
1658 static struct uart_driver pch_uart_driver = {
1659         .owner = THIS_MODULE,
1660         .driver_name = KBUILD_MODNAME,
1661         .dev_name = PCH_UART_DRIVER_DEVICE,
1662         .major = 0,
1663         .minor = 0,
1664         .nr = PCH_UART_NR,
1665         .cons = PCH_CONSOLE,
1666 };
1667
1668 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1669                                              const struct pci_device_id *id)
1670 {
1671         struct eg20t_port *priv;
1672         int ret;
1673         unsigned int iobase;
1674         unsigned int mapbase;
1675         unsigned char *rxbuf;
1676         int fifosize;
1677         int port_type;
1678         struct pch_uart_driver_data *board;
1679         char name[32];  /* for debugfs file name */
1680
1681         board = &drv_dat[id->driver_data];
1682         port_type = board->port_type;
1683
1684         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1685         if (priv == NULL)
1686                 goto init_port_alloc_err;
1687
1688         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1689         if (!rxbuf)
1690                 goto init_port_free_txbuf;
1691
1692         switch (port_type) {
1693         case PORT_UNKNOWN:
1694                 fifosize = 256; /* EG20T/ML7213: UART0 */
1695                 break;
1696         case PORT_8250:
1697                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1698                 break;
1699         default:
1700                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1701                 goto init_port_hal_free;
1702         }
1703
1704         pci_enable_msi(pdev);
1705         pci_set_master(pdev);
1706
1707         spin_lock_init(&priv->lock);
1708
1709         iobase = pci_resource_start(pdev, 0);
1710         mapbase = pci_resource_start(pdev, 1);
1711         priv->mapbase = mapbase;
1712         priv->iobase = iobase;
1713         priv->pdev = pdev;
1714         priv->tx_empty = 1;
1715         priv->rxbuf.buf = rxbuf;
1716         priv->rxbuf.size = PAGE_SIZE;
1717
1718         priv->fifo_size = fifosize;
1719         priv->uartclk = pch_uart_get_uartclk();
1720         priv->port_type = PORT_MAX_8250 + port_type + 1;
1721         priv->port.dev = &pdev->dev;
1722         priv->port.iobase = iobase;
1723         priv->port.membase = NULL;
1724         priv->port.mapbase = mapbase;
1725         priv->port.irq = pdev->irq;
1726         priv->port.iotype = UPIO_PORT;
1727         priv->port.ops = &pch_uart_ops;
1728         priv->port.flags = UPF_BOOT_AUTOCONF;
1729         priv->port.fifosize = fifosize;
1730         priv->port.line = board->line_no;
1731         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1732
1733         spin_lock_init(&priv->port.lock);
1734
1735         pci_set_drvdata(pdev, priv);
1736         priv->trigger_level = 1;
1737         priv->fcr = 0;
1738
1739 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1740         pch_uart_ports[board->line_no] = priv;
1741 #endif
1742         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1743         if (ret < 0)
1744                 goto init_port_hal_free;
1745
1746 #ifdef CONFIG_DEBUG_FS
1747         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1748         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1749                                 NULL, priv, &port_regs_ops);
1750 #endif
1751
1752         return priv;
1753
1754 init_port_hal_free:
1755 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1756         pch_uart_ports[board->line_no] = NULL;
1757 #endif
1758         free_page((unsigned long)rxbuf);
1759 init_port_free_txbuf:
1760         kfree(priv);
1761 init_port_alloc_err:
1762
1763         return NULL;
1764 }
1765
1766 static void pch_uart_exit_port(struct eg20t_port *priv)
1767 {
1768
1769 #ifdef CONFIG_DEBUG_FS
1770         if (priv->debugfs)
1771                 debugfs_remove(priv->debugfs);
1772 #endif
1773         uart_remove_one_port(&pch_uart_driver, &priv->port);
1774         pci_set_drvdata(priv->pdev, NULL);
1775         free_page((unsigned long)priv->rxbuf.buf);
1776 }
1777
1778 static void pch_uart_pci_remove(struct pci_dev *pdev)
1779 {
1780         struct eg20t_port *priv = pci_get_drvdata(pdev);
1781
1782         pci_disable_msi(pdev);
1783
1784 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1785         pch_uart_ports[priv->port.line] = NULL;
1786 #endif
1787         pch_uart_exit_port(priv);
1788         pci_disable_device(pdev);
1789         kfree(priv);
1790         return;
1791 }
1792 #ifdef CONFIG_PM
1793 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1794 {
1795         struct eg20t_port *priv = pci_get_drvdata(pdev);
1796
1797         uart_suspend_port(&pch_uart_driver, &priv->port);
1798
1799         pci_save_state(pdev);
1800         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1801         return 0;
1802 }
1803
1804 static int pch_uart_pci_resume(struct pci_dev *pdev)
1805 {
1806         struct eg20t_port *priv = pci_get_drvdata(pdev);
1807         int ret;
1808
1809         pci_set_power_state(pdev, PCI_D0);
1810         pci_restore_state(pdev);
1811
1812         ret = pci_enable_device(pdev);
1813         if (ret) {
1814                 dev_err(&pdev->dev,
1815                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1816                 return ret;
1817         }
1818
1819         uart_resume_port(&pch_uart_driver, &priv->port);
1820
1821         return 0;
1822 }
1823 #else
1824 #define pch_uart_pci_suspend NULL
1825 #define pch_uart_pci_resume NULL
1826 #endif
1827
1828 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1829         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1830          .driver_data = pch_et20t_uart0},
1831         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1832          .driver_data = pch_et20t_uart1},
1833         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1834          .driver_data = pch_et20t_uart2},
1835         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1836          .driver_data = pch_et20t_uart3},
1837         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1838          .driver_data = pch_ml7213_uart0},
1839         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1840          .driver_data = pch_ml7213_uart1},
1841         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1842          .driver_data = pch_ml7213_uart2},
1843         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1844          .driver_data = pch_ml7223_uart0},
1845         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1846          .driver_data = pch_ml7223_uart1},
1847         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1848          .driver_data = pch_ml7831_uart0},
1849         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1850          .driver_data = pch_ml7831_uart1},
1851         {0,},
1852 };
1853
1854 static int pch_uart_pci_probe(struct pci_dev *pdev,
1855                                         const struct pci_device_id *id)
1856 {
1857         int ret;
1858         struct eg20t_port *priv;
1859
1860         ret = pci_enable_device(pdev);
1861         if (ret < 0)
1862                 goto probe_error;
1863
1864         priv = pch_uart_init_port(pdev, id);
1865         if (!priv) {
1866                 ret = -EBUSY;
1867                 goto probe_disable_device;
1868         }
1869         pci_set_drvdata(pdev, priv);
1870
1871         return ret;
1872
1873 probe_disable_device:
1874         pci_disable_msi(pdev);
1875         pci_disable_device(pdev);
1876 probe_error:
1877         return ret;
1878 }
1879
1880 static struct pci_driver pch_uart_pci_driver = {
1881         .name = "pch_uart",
1882         .id_table = pch_uart_pci_id,
1883         .probe = pch_uart_pci_probe,
1884         .remove = pch_uart_pci_remove,
1885         .suspend = pch_uart_pci_suspend,
1886         .resume = pch_uart_pci_resume,
1887 };
1888
1889 static int __init pch_uart_module_init(void)
1890 {
1891         int ret;
1892
1893         /* register as UART driver */
1894         ret = uart_register_driver(&pch_uart_driver);
1895         if (ret < 0)
1896                 return ret;
1897
1898         /* register as PCI driver */
1899         ret = pci_register_driver(&pch_uart_pci_driver);
1900         if (ret < 0)
1901                 uart_unregister_driver(&pch_uart_driver);
1902
1903         return ret;
1904 }
1905 module_init(pch_uart_module_init);
1906
1907 static void __exit pch_uart_module_exit(void)
1908 {
1909         pci_unregister_driver(&pch_uart_pci_driver);
1910         uart_unregister_driver(&pch_uart_driver);
1911 }
1912 module_exit(pch_uart_module_exit);
1913
1914 MODULE_LICENSE("GPL v2");
1915 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1916 module_param(default_baud, uint, S_IRUGO);
1917 MODULE_PARM_DESC(default_baud,
1918                  "Default BAUD for initial driver state and console (default 9600)");
1919 module_param(user_uartclk, uint, S_IRUGO);
1920 MODULE_PARM_DESC(user_uartclk,
1921                  "Override UART default or board specific UART clock");