drivers/usb/chipidea/core.c

   1 /*
   2  * core.c - ChipIdea USB IP core family device controller
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 /*
  14  * Description: ChipIdea USB IP core family device controller
  15  *
  16  * This driver is composed of several blocks:
  17  * - HW:     hardware interface
  18  * - DBG:    debug facilities (optional)
  19  * - UTIL:   utilities
  20  * - ISR:    interrupts handling
  21  * - ENDPT:  endpoint operations (Gadget API)
  22  * - GADGET: gadget operations (Gadget API)
  23  * - BUS:    bus glue code, bus abstraction layer
  24  *
  25  * Compile Options
  26  * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
  27  * - STALL_IN:  non-empty bulk-in pipes cannot be halted
  28  *              if defined mass storage compliance succeeds but with warnings
  29  *              => case 4: Hi >  Dn
  30  *              => case 5: Hi >  Di
  31  *              => case 8: Hi <> Do
  32  *              if undefined usbtest 13 fails
  33  * - TRACE:     enable function tracing (depends on DEBUG)
  34  *
  35  * Main Features
  36  * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37  * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38  * - Normal & LPM support
  39  *
  40  * USBTEST Report
  41  * - OK: 0-12, 13 (STALL_IN defined) & 14
  42  * - Not Supported: 15 & 16 (ISO)
  43  *
  44  * TODO List
  45  * - Suspend & Remote Wakeup
  46  */
  47 #include <linux/delay.h>
  48 #include <linux/device.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/extcon.h>
  51 #include <linux/phy/phy.h>
  52 #include <linux/platform_device.h>
  53 #include <linux/module.h>
  54 #include <linux/idr.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/io.h>
  57 #include <linux/kernel.h>
  58 #include <linux/slab.h>
  59 #include <linux/pm_runtime.h>
  60 #include <linux/usb/ch9.h>
  61 #include <linux/usb/gadget.h>
  62 #include <linux/usb/otg.h>
  63 #include <linux/usb/chipidea.h>
  64 #include <linux/usb/of.h>
  65 #include <linux/of.h>
  66 #include <linux/phy.h>
  67 #include <linux/regulator/consumer.h>
  68 #include <linux/usb/ehci_def.h>
  69
  70 #include "ci.h"
  71 #include "udc.h"
  72 #include "bits.h"
  73 #include "host.h"
  74 #include "otg.h"
  75 #include "otg_fsm.h"
  76
  77 /* Controller register map */
  78 static const u8 ci_regs_nolpm[] = {
  79         [CAP_CAPLENGTH]         = 0x00U,
  80         [CAP_HCCPARAMS]         = 0x08U,
  81         [CAP_DCCPARAMS]         = 0x24U,
  82         [CAP_TESTMODE]          = 0x38U,
  83         [OP_USBCMD]             = 0x00U,
  84         [OP_USBSTS]             = 0x04U,
  85         [OP_USBINTR]            = 0x08U,
  86         [OP_DEVICEADDR]         = 0x14U,
  87         [OP_ENDPTLISTADDR]      = 0x18U,
  88         [OP_TTCTRL]             = 0x1CU,
  89         [OP_BURSTSIZE]          = 0x20U,
  90         [OP_PORTSC]             = 0x44U,
  91         [OP_DEVLC]              = 0x84U,
  92         [OP_OTGSC]              = 0x64U,
  93         [OP_USBMODE]            = 0x68U,
  94         [OP_ENDPTSETUPSTAT]     = 0x6CU,
  95         [OP_ENDPTPRIME]         = 0x70U,
  96         [OP_ENDPTFLUSH]         = 0x74U,
  97         [OP_ENDPTSTAT]          = 0x78U,
  98         [OP_ENDPTCOMPLETE]      = 0x7CU,
  99         [OP_ENDPTCTRL]          = 0x80U,
 100 };
 101
 102 static const u8 ci_regs_lpm[] = {
 103         [CAP_CAPLENGTH]         = 0x00U,
 104         [CAP_HCCPARAMS]         = 0x08U,
 105         [CAP_DCCPARAMS]         = 0x24U,
 106         [CAP_TESTMODE]          = 0xFCU,
 107         [OP_USBCMD]             = 0x00U,
 108         [OP_USBSTS]             = 0x04U,
 109         [OP_USBINTR]            = 0x08U,
 110         [OP_DEVICEADDR]         = 0x14U,
 111         [OP_ENDPTLISTADDR]      = 0x18U,
 112         [OP_TTCTRL]             = 0x1CU,
 113         [OP_BURSTSIZE]          = 0x20U,
 114         [OP_PORTSC]             = 0x44U,
 115         [OP_DEVLC]              = 0x84U,
 116         [OP_OTGSC]              = 0xC4U,
 117         [OP_USBMODE]            = 0xC8U,
 118         [OP_ENDPTSETUPSTAT]     = 0xD8U,
 119         [OP_ENDPTPRIME]         = 0xDCU,
 120         [OP_ENDPTFLUSH]         = 0xE0U,
 121         [OP_ENDPTSTAT]          = 0xE4U,
 122         [OP_ENDPTCOMPLETE]      = 0xE8U,
 123         [OP_ENDPTCTRL]          = 0xECU,
 124 };
 125
 126 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
 127 {
 128         int i;
 129
 130         for (i = 0; i < OP_ENDPTCTRL; i++)
 131                 ci->hw_bank.regmap[i] =
 132                         (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
 133                         (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
 134
 135         for (; i <= OP_LAST; i++)
 136                 ci->hw_bank.regmap[i] = ci->hw_bank.op +
 137                         4 * (i - OP_ENDPTCTRL) +
 138                         (is_lpm
 139                          ? ci_regs_lpm[OP_ENDPTCTRL]
 140                          : ci_regs_nolpm[OP_ENDPTCTRL]);
 141
 142 }
 143
 144 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
 145 {
 146         int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
 147         enum ci_revision rev = CI_REVISION_UNKNOWN;
 148
 149         if (ver == 0x2) {
 150                 rev = hw_read_id_reg(ci, ID_ID, REVISION)
 151                         >> __ffs(REVISION);
 152                 rev += CI_REVISION_20;
 153         } else if (ver == 0x0) {
 154                 rev = CI_REVISION_1X;
 155         }
 156
 157         return rev;
 158 }
 159
 160 /**
 161  * hw_read_intr_enable: returns interrupt enable register
 162  *
 163  * @ci: the controller
 164  *
 165  * This function returns register data
 166  */
 167 u32 hw_read_intr_enable(struct ci_hdrc *ci)
 168 {
 169         return hw_read(ci, OP_USBINTR, ~0);
 170 }
 171
 172 /**
 173  * hw_read_intr_status: returns interrupt status register
 174  *
 175  * @ci: the controller
 176  *
 177  * This function returns register data
 178  */
 179 u32 hw_read_intr_status(struct ci_hdrc *ci)
 180 {
 181         return hw_read(ci, OP_USBSTS, ~0);
 182 }
 183
 184 /**
 185  * hw_port_test_set: writes port test mode (execute without interruption)
 186  * @mode: new value
 187  *
 188  * This function returns an error code
 189  */
 190 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
 191 {
 192         const u8 TEST_MODE_MAX = 7;
 193
 194         if (mode > TEST_MODE_MAX)
 195                 return -EINVAL;
 196
 197         hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
 198         return 0;
 199 }
 200
 201 /**
 202  * hw_port_test_get: reads port test mode value
 203  *
 204  * @ci: the controller
 205  *
 206  * This function returns port test mode value
 207  */
 208 u8 hw_port_test_get(struct ci_hdrc *ci)
 209 {
 210         return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
 211 }
 212
 213 static void hw_wait_phy_stable(void)
 214 {
 215         /*
 216          * The phy needs some delay to output the stable status from low
 217          * power mode. And for OTGSC, the status inputs are debounced
 218          * using a 1 ms time constant, so, delay 2ms for controller to get
 219          * the stable status, like vbus and id when the phy leaves low power.
 220          */
 221         usleep_range(2000, 2500);
 222 }
 223
 224 /* The PHY enters/leaves low power mode */
 225 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
 226 {
 227         enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
 228         bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
 229
 230         if (enable && !lpm)
 231                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 232                                 PORTSC_PHCD(ci->hw_bank.lpm));
 233         else if (!enable && lpm)
 234                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 235                                 0);
 236 }
 237
 238 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
 239 {
 240         u32 reg;
 241
 242         /* bank is a module variable */
 243         ci->hw_bank.abs = base;
 244
 245         ci->hw_bank.cap = ci->hw_bank.abs;
 246         ci->hw_bank.cap += ci->platdata->capoffset;
 247         ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
 248
 249         hw_alloc_regmap(ci, false);
 250         reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
 251                 __ffs(HCCPARAMS_LEN);
 252         ci->hw_bank.lpm  = reg;
 253         if (reg)
 254                 hw_alloc_regmap(ci, !!reg);
 255         ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
 256         ci->hw_bank.size += OP_LAST;
 257         ci->hw_bank.size /= sizeof(u32);
 258
 259         reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
 260                 __ffs(DCCPARAMS_DEN);
 261         ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
 262
 263         if (ci->hw_ep_max > ENDPT_MAX)
 264                 return -ENODEV;
 265
 266         ci_hdrc_enter_lpm(ci, false);
 267
 268         /* Disable all interrupts bits */
 269         hw_write(ci, OP_USBINTR, 0xffffffff, 0);
 270
 271         /* Clear all interrupts status bits*/
 272         hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
 273
 274         ci->rev = ci_get_revision(ci);
 275
 276         dev_dbg(ci->dev,
 277                 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
 278                 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
 279
 280         /* setup lock mode ? */
 281
 282         /* ENDPTSETUPSTAT is '0' by default */
 283
 284         /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
 285
 286         return 0;
 287 }
 288
 289 static void hw_phymode_configure(struct ci_hdrc *ci)
 290 {
 291         u32 portsc, lpm, sts = 0;
 292
 293         switch (ci->platdata->phy_mode) {
 294         case USBPHY_INTERFACE_MODE_UTMI:
 295                 portsc = PORTSC_PTS(PTS_UTMI);
 296                 lpm = DEVLC_PTS(PTS_UTMI);
 297                 break;
 298         case USBPHY_INTERFACE_MODE_UTMIW:
 299                 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
 300                 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
 301                 break;
 302         case USBPHY_INTERFACE_MODE_ULPI:
 303                 portsc = PORTSC_PTS(PTS_ULPI);
 304                 lpm = DEVLC_PTS(PTS_ULPI);
 305                 break;
 306         case USBPHY_INTERFACE_MODE_SERIAL:
 307                 portsc = PORTSC_PTS(PTS_SERIAL);
 308                 lpm = DEVLC_PTS(PTS_SERIAL);
 309                 sts = 1;
 310                 break;
 311         case USBPHY_INTERFACE_MODE_HSIC:
 312                 portsc = PORTSC_PTS(PTS_HSIC);
 313                 lpm = DEVLC_PTS(PTS_HSIC);
 314                 break;
 315         default:
 316                 return;
 317         }
 318
 319         if (ci->hw_bank.lpm) {
 320                 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
 321                 if (sts)
 322                         hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
 323         } else {
 324                 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
 325                 if (sts)
 326                         hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
 327         }
 328 }
 329
 330 /**
 331  * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
 332  * interfaces
 333  * @ci: the controller
 334  *
 335  * This function returns an error code if the phy failed to init
 336  */
 337 static int _ci_usb_phy_init(struct ci_hdrc *ci)
 338 {
 339         int ret;
 340
 341         if (ci->phy) {
 342                 ret = phy_init(ci->phy);
 343                 if (ret)
 344                         return ret;
 345
 346                 ret = phy_power_on(ci->phy);
 347                 if (ret) {
 348                         phy_exit(ci->phy);
 349                         return ret;
 350                 }
 351         } else {
 352                 ret = usb_phy_init(ci->usb_phy);
 353         }
 354
 355         return ret;
 356 }
 357
 358 /**
 359  * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
 360  * interfaces
 361  * @ci: the controller
 362  */
 363 static void ci_usb_phy_exit(struct ci_hdrc *ci)
 364 {
 365         if (ci->phy) {
 366                 phy_power_off(ci->phy);
 367                 phy_exit(ci->phy);
 368         } else {
 369                 usb_phy_shutdown(ci->usb_phy);
 370         }
 371 }
 372
 373 /**
 374  * ci_usb_phy_init: initialize phy according to different phy type
 375  * @ci: the controller
 376  *
 377  * This function returns an error code if usb_phy_init has failed
 378  */
 379 static int ci_usb_phy_init(struct ci_hdrc *ci)
 380 {
 381         int ret;
 382
 383         switch (ci->platdata->phy_mode) {
 384         case USBPHY_INTERFACE_MODE_UTMI:
 385         case USBPHY_INTERFACE_MODE_UTMIW:
 386         case USBPHY_INTERFACE_MODE_HSIC:
 387                 ret = _ci_usb_phy_init(ci);
 388                 if (!ret)
 389                         hw_wait_phy_stable();
 390                 else
 391                         return ret;
 392                 hw_phymode_configure(ci);
 393                 break;
 394         case USBPHY_INTERFACE_MODE_ULPI:
 395         case USBPHY_INTERFACE_MODE_SERIAL:
 396                 hw_phymode_configure(ci);
 397                 ret = _ci_usb_phy_init(ci);
 398                 if (ret)
 399                         return ret;
 400                 break;
 401         default:
 402                 ret = _ci_usb_phy_init(ci);
 403                 if (!ret)
 404                         hw_wait_phy_stable();
 405         }
 406
 407         return ret;
 408 }
 409
 410
 411 /**
 412  * ci_platform_configure: do controller configure
 413  * @ci: the controller
 414  *
 415  */
 416 void ci_platform_configure(struct ci_hdrc *ci)
 417 {
 418         bool is_device_mode, is_host_mode;
 419
 420         is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
 421         is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
 422
 423         if (is_device_mode &&
 424                 (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING))
 425                 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
 426
 427         if (is_host_mode &&
 428                 (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING))
 429                 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
 430
 431         if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
 432                 if (ci->hw_bank.lpm)
 433                         hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
 434                 else
 435                         hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
 436         }
 437
 438         if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
 439                 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
 440
 441         hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
 442
 443         if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
 444                 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
 445                         ci->platdata->ahb_burst_config);
 446
 447         /* override burst size, take effect only when ahb_burst_config is 0 */
 448         if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
 449                 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
 450                         hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
 451                         ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
 452
 453                 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
 454                         hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
 455                                 ci->platdata->rx_burst_size);
 456         }
 457 }
 458
 459 /**
 460  * hw_controller_reset: do controller reset
 461  * @ci: the controller
 462   *
 463  * This function returns an error code
 464  */
 465 static int hw_controller_reset(struct ci_hdrc *ci)
 466 {
 467         int count = 0;
 468
 469         hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
 470         while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
 471                 udelay(10);
 472                 if (count++ > 1000)
 473                         return -ETIMEDOUT;
 474         }
 475
 476         return 0;
 477 }
 478
 479 /**
 480  * hw_device_reset: resets chip (execute without interruption)
 481  * @ci: the controller
 482  *
 483  * This function returns an error code
 484  */
 485 int hw_device_reset(struct ci_hdrc *ci)
 486 {
 487         int ret;
 488
 489         /* should flush & stop before reset */
 490         hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
 491         hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
 492
 493         ret = hw_controller_reset(ci);
 494         if (ret) {
 495                 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
 496                 return ret;
 497         }
 498
 499         if (ci->platdata->notify_event)
 500                 ci->platdata->notify_event(ci,
 501                         CI_HDRC_CONTROLLER_RESET_EVENT);
 502
 503         /* USBMODE should be configured step by step */
 504         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
 505         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
 506         /* HW >= 2.3 */
 507         hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
 508
 509         if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
 510                 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
 511                 pr_err("lpm = %i", ci->hw_bank.lpm);
 512                 return -ENODEV;
 513         }
 514
 515         ci_platform_configure(ci);
 516
 517         return 0;
 518 }
 519
 520 /**
 521  * hw_wait_reg: wait the register value
 522  *
 523  * Sometimes, it needs to wait register value before going on.
 524  * Eg, when switch to device mode, the vbus value should be lower
 525  * than OTGSC_BSV before connects to host.
 526  *
 527  * @ci: the controller
 528  * @reg: register index
 529  * @mask: mast bit
 530  * @value: the bit value to wait
 531  * @timeout_ms: timeout in millisecond
 532  *
 533  * This function returns an error code if timeout
 534  */
 535 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
 536                                 u32 value, unsigned int timeout_ms)
 537 {
 538         unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
 539
 540         while (hw_read(ci, reg, mask) != value) {
 541                 if (time_after(jiffies, elapse)) {
 542                         dev_err(ci->dev, "timeout waiting for %08x in %d\n",
 543                                         mask, reg);
 544                         return -ETIMEDOUT;
 545                 }
 546                 msleep(20);
 547         }
 548
 549         return 0;
 550 }
 551
 552 static irqreturn_t ci_irq(int irq, void *data)
 553 {
 554         struct ci_hdrc *ci = data;
 555         irqreturn_t ret = IRQ_NONE;
 556         u32 otgsc = 0;
 557
 558         if (ci->in_lpm) {
 559                 disable_irq_nosync(irq);
 560                 ci->wakeup_int = true;
 561                 pm_runtime_get(ci->dev);
 562                 return IRQ_HANDLED;
 563         }
 564
 565         if (ci->is_otg) {
 566                 otgsc = hw_read_otgsc(ci, ~0);
 567                 if (ci_otg_is_fsm_mode(ci)) {
 568                         ret = ci_otg_fsm_irq(ci);
 569                         if (ret == IRQ_HANDLED)
 570                                 return ret;
 571                 }
 572         }
 573
 574         /*
 575          * Handle id change interrupt, it indicates device/host function
 576          * switch.
 577          */
 578         if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
 579                 ci->id_event = true;
 580                 /* Clear ID change irq status */
 581                 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
 582                 ci_otg_queue_work(ci);
 583                 return IRQ_HANDLED;
 584         }
 585
 586         /*
 587          * Handle vbus change interrupt, it indicates device connection
 588          * and disconnection events.
 589          */
 590         if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
 591                 ci->b_sess_valid_event = true;
 592                 /* Clear BSV irq */
 593                 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
 594                 ci_otg_queue_work(ci);
 595                 return IRQ_HANDLED;
 596         }
 597
 598         /* Handle device/host interrupt */
 599         if (ci->role != CI_ROLE_END)
 600                 ret = ci_role(ci)->irq(ci);
 601
 602         return ret;
 603 }
 604
 605 static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event,
 606                             void *ptr)
 607 {
 608         struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, nb);
 609         struct ci_hdrc *ci = vbus->ci;
 610
 611         if (event)
 612                 vbus->state = true;
 613         else
 614                 vbus->state = false;
 615
 616         vbus->changed = true;
 617
 618         ci_irq(ci->irq, ci);
 619         return NOTIFY_DONE;
 620 }
 621
 622 static int ci_id_notifier(struct notifier_block *nb, unsigned long event,
 623                           void *ptr)
 624 {
 625         struct ci_hdrc_cable *id = container_of(nb, struct ci_hdrc_cable, nb);
 626         struct ci_hdrc *ci = id->ci;
 627
 628         if (event)
 629                 id->state = false;
 630         else
 631                 id->state = true;
 632
 633         id->changed = true;
 634
 635         ci_irq(ci->irq, ci);
 636         return NOTIFY_DONE;
 637 }
 638
 639 static int ci_get_platdata(struct device *dev,
 640                 struct ci_hdrc_platform_data *platdata)
 641 {
 642         struct extcon_dev *ext_vbus, *ext_id;
 643         struct ci_hdrc_cable *cable;
 644         int ret;
 645
 646         if (!platdata->phy_mode)
 647                 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
 648
 649         if (!platdata->dr_mode)
 650                 platdata->dr_mode = usb_get_dr_mode(dev);
 651
 652         if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
 653                 platdata->dr_mode = USB_DR_MODE_OTG;
 654
 655         if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
 656                 /* Get the vbus regulator */
 657                 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
 658                 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
 659                         return -EPROBE_DEFER;
 660                 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
 661                         /* no vbus regulator is needed */
 662                         platdata->reg_vbus = NULL;
 663                 } else if (IS_ERR(platdata->reg_vbus)) {
 664                         dev_err(dev, "Getting regulator error: %ld\n",
 665                                 PTR_ERR(platdata->reg_vbus));
 666                         return PTR_ERR(platdata->reg_vbus);
 667                 }
 668                 /* Get TPL support */
 669                 if (!platdata->tpl_support)
 670                         platdata->tpl_support =
 671                                 of_usb_host_tpl_support(dev->of_node);
 672         }
 673
 674         if (platdata->dr_mode == USB_DR_MODE_OTG) {
 675                 /* We can support HNP and SRP of OTG 2.0 */
 676                 platdata->ci_otg_caps.otg_rev = 0x0200;
 677                 platdata->ci_otg_caps.hnp_support = true;
 678                 platdata->ci_otg_caps.srp_support = true;
 679
 680                 /* Update otg capabilities by DT properties */
 681                 ret = of_usb_update_otg_caps(dev->of_node,
 682                                         &platdata->ci_otg_caps);
 683                 if (ret)
 684                         return ret;
 685         }
 686
 687         if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
 688                 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
 689
 690         if (of_find_property(dev->of_node, "phy-clkgate-delay-us", NULL))
 691                 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
 692                                      &platdata->phy_clkgate_delay_us);
 693
 694         platdata->itc_setting = 1;
 695         if (of_find_property(dev->of_node, "itc-setting", NULL)) {
 696                 ret = of_property_read_u32(dev->of_node, "itc-setting",
 697                         &platdata->itc_setting);
 698                 if (ret) {
 699                         dev_err(dev,
 700                                 "failed to get itc-setting\n");
 701                         return ret;
 702                 }
 703         }
 704
 705         if (of_find_property(dev->of_node, "ahb-burst-config", NULL)) {
 706                 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
 707                         &platdata->ahb_burst_config);
 708                 if (ret) {
 709                         dev_err(dev,
 710                                 "failed to get ahb-burst-config\n");
 711                         return ret;
 712                 }
 713                 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
 714         }
 715
 716         if (of_find_property(dev->of_node, "tx-burst-size-dword", NULL)) {
 717                 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
 718                         &platdata->tx_burst_size);
 719                 if (ret) {
 720                         dev_err(dev,
 721                                 "failed to get tx-burst-size-dword\n");
 722                         return ret;
 723                 }
 724                 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
 725         }
 726
 727         if (of_find_property(dev->of_node, "rx-burst-size-dword", NULL)) {
 728                 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
 729                         &platdata->rx_burst_size);
 730                 if (ret) {
 731                         dev_err(dev,
 732                                 "failed to get rx-burst-size-dword\n");
 733                         return ret;
 734                 }
 735                 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
 736         }
 737
 738         ext_id = ERR_PTR(-ENODEV);
 739         ext_vbus = ERR_PTR(-ENODEV);
 740         if (of_property_read_bool(dev->of_node, "extcon")) {
 741                 /* Each one of them is not mandatory */
 742                 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
 743                 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
 744                         return PTR_ERR(ext_vbus);
 745
 746                 ext_id = extcon_get_edev_by_phandle(dev, 1);
 747                 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
 748                         return PTR_ERR(ext_id);
 749         }
 750
 751         cable = &platdata->vbus_extcon;
 752         cable->nb.notifier_call = ci_vbus_notifier;
 753         cable->edev = ext_vbus;
 754
 755         if (!IS_ERR(ext_vbus)) {
 756                 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB);
 757                 if (ret)
 758                         cable->state = true;
 759                 else
 760                         cable->state = false;
 761         }
 762
 763         cable = &platdata->id_extcon;
 764         cable->nb.notifier_call = ci_id_notifier;
 765         cable->edev = ext_id;
 766
 767         if (!IS_ERR(ext_id)) {
 768                 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB_HOST);
 769                 if (ret)
 770                         cable->state = false;
 771                 else
 772                         cable->state = true;
 773         }
 774         return 0;
 775 }
 776
 777 static int ci_extcon_register(struct ci_hdrc *ci)
 778 {
 779         struct ci_hdrc_cable *id, *vbus;
 780         int ret;
 781
 782         id = &ci->platdata->id_extcon;
 783         id->ci = ci;
 784         if (!IS_ERR(id->edev)) {
 785                 ret = extcon_register_notifier(id->edev, EXTCON_USB_HOST,
 786                                                &id->nb);
 787                 if (ret < 0) {
 788                         dev_err(ci->dev, "register ID failed\n");
 789                         return ret;
 790                 }
 791         }
 792
 793         vbus = &ci->platdata->vbus_extcon;
 794         vbus->ci = ci;
 795         if (!IS_ERR(vbus->edev)) {
 796                 ret = extcon_register_notifier(vbus->edev, EXTCON_USB,
 797                                                &vbus->nb);
 798                 if (ret < 0) {
 799                         extcon_unregister_notifier(id->edev, EXTCON_USB_HOST,
 800                                                    &id->nb);
 801                         dev_err(ci->dev, "register VBUS failed\n");
 802                         return ret;
 803                 }
 804         }
 805
 806         return 0;
 807 }
 808
 809 static void ci_extcon_unregister(struct ci_hdrc *ci)
 810 {
 811         struct ci_hdrc_cable *cable;
 812
 813         cable = &ci->platdata->id_extcon;
 814         if (!IS_ERR(cable->edev))
 815                 extcon_unregister_notifier(cable->edev, EXTCON_USB_HOST,
 816                                            &cable->nb);
 817
 818         cable = &ci->platdata->vbus_extcon;
 819         if (!IS_ERR(cable->edev))
 820                 extcon_unregister_notifier(cable->edev, EXTCON_USB, &cable->nb);
 821 }
 822
 823 static DEFINE_IDA(ci_ida);
 824
 825 struct platform_device *ci_hdrc_add_device(struct device *dev,
 826                         struct resource *res, int nres,
 827                         struct ci_hdrc_platform_data *platdata)
 828 {
 829         struct platform_device *pdev;
 830         int id, ret;
 831
 832         ret = ci_get_platdata(dev, platdata);
 833         if (ret)
 834                 return ERR_PTR(ret);
 835
 836         id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
 837         if (id < 0)
 838                 return ERR_PTR(id);
 839
 840         pdev = platform_device_alloc("ci_hdrc", id);
 841         if (!pdev) {
 842                 ret = -ENOMEM;
 843                 goto put_id;
 844         }
 845
 846         pdev->dev.parent = dev;
 847         pdev->dev.dma_mask = dev->dma_mask;
 848         pdev->dev.dma_parms = dev->dma_parms;
 849         dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
 850
 851         ret = platform_device_add_resources(pdev, res, nres);
 852         if (ret)
 853                 goto err;
 854
 855         ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
 856         if (ret)
 857                 goto err;
 858
 859         ret = platform_device_add(pdev);
 860         if (ret)
 861                 goto err;
 862
 863         return pdev;
 864
 865 err:
 866         platform_device_put(pdev);
 867 put_id:
 868         ida_simple_remove(&ci_ida, id);
 869         return ERR_PTR(ret);
 870 }
 871 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
 872
 873 void ci_hdrc_remove_device(struct platform_device *pdev)
 874 {
 875         int id = pdev->id;
 876         platform_device_unregister(pdev);
 877         ida_simple_remove(&ci_ida, id);
 878 }
 879 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
 880
 881 static inline void ci_role_destroy(struct ci_hdrc *ci)
 882 {
 883         ci_hdrc_gadget_destroy(ci);
 884         ci_hdrc_host_destroy(ci);
 885         if (ci->is_otg)
 886                 ci_hdrc_otg_destroy(ci);
 887 }
 888
 889 static void ci_get_otg_capable(struct ci_hdrc *ci)
 890 {
 891         if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
 892                 ci->is_otg = false;
 893         else
 894                 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
 895                                 DCCPARAMS_DC | DCCPARAMS_HC)
 896                                         == (DCCPARAMS_DC | DCCPARAMS_HC));
 897         if (ci->is_otg) {
 898                 dev_dbg(ci->dev, "It is OTG capable controller\n");
 899                 /* Disable and clear all OTG irq */
 900                 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
 901                                                         OTGSC_INT_STATUS_BITS);
 902         }
 903 }
 904
 905 static int ci_hdrc_probe(struct platform_device *pdev)
 906 {
 907         struct device   *dev = &pdev->dev;
 908         struct ci_hdrc  *ci;
 909         struct resource *res;
 910         void __iomem    *base;
 911         int             ret;
 912         enum usb_dr_mode dr_mode;
 913
 914         if (!dev_get_platdata(dev)) {
 915                 dev_err(dev, "platform data missing\n");
 916                 return -ENODEV;
 917         }
 918
 919         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 920         base = devm_ioremap_resource(dev, res);
 921         if (IS_ERR(base))
 922                 return PTR_ERR(base);
 923
 924         ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
 925         if (!ci)
 926                 return -ENOMEM;
 927
 928         ci->dev = dev;
 929         ci->platdata = dev_get_platdata(dev);
 930         ci->imx28_write_fix = !!(ci->platdata->flags &
 931                 CI_HDRC_IMX28_WRITE_FIX);
 932         ci->supports_runtime_pm = !!(ci->platdata->flags &
 933                 CI_HDRC_SUPPORTS_RUNTIME_PM);
 934
 935         ret = hw_device_init(ci, base);
 936         if (ret < 0) {
 937                 dev_err(dev, "can't initialize hardware\n");
 938                 return -ENODEV;
 939         }
 940
 941         if (ci->platdata->phy) {
 942                 ci->phy = ci->platdata->phy;
 943         } else if (ci->platdata->usb_phy) {
 944                 ci->usb_phy = ci->platdata->usb_phy;
 945         } else {
 946                 ci->phy = devm_phy_get(dev->parent, "usb-phy");
 947                 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
 948
 949                 /* if both generic PHY and USB PHY layers aren't enabled */
 950                 if (PTR_ERR(ci->phy) == -ENOSYS &&
 951                                 PTR_ERR(ci->usb_phy) == -ENXIO)
 952                         return -ENXIO;
 953
 954                 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
 955                         return -EPROBE_DEFER;
 956
 957                 if (IS_ERR(ci->phy))
 958                         ci->phy = NULL;
 959                 else if (IS_ERR(ci->usb_phy))
 960                         ci->usb_phy = NULL;
 961         }
 962
 963         ret = ci_usb_phy_init(ci);
 964         if (ret) {
 965                 dev_err(dev, "unable to init phy: %d\n", ret);
 966                 return ret;
 967         }
 968
 969         ci->hw_bank.phys = res->start;
 970
 971         ci->irq = platform_get_irq(pdev, 0);
 972         if (ci->irq < 0) {
 973                 dev_err(dev, "missing IRQ\n");
 974                 ret = ci->irq;
 975                 goto deinit_phy;
 976         }
 977
 978         ci_get_otg_capable(ci);
 979
 980         dr_mode = ci->platdata->dr_mode;
 981         /* initialize role(s) before the interrupt is requested */
 982         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
 983                 ret = ci_hdrc_host_init(ci);
 984                 if (ret)
 985                         dev_info(dev, "doesn't support host\n");
 986         }
 987
 988         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
 989                 ret = ci_hdrc_gadget_init(ci);
 990                 if (ret)
 991                         dev_info(dev, "doesn't support gadget\n");
 992         }
 993
 994         if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
 995                 dev_err(dev, "no supported roles\n");
 996                 ret = -ENODEV;
 997                 goto deinit_phy;
 998         }
 999
1000         if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1001                 ret = ci_hdrc_otg_init(ci);
1002                 if (ret) {
1003                         dev_err(dev, "init otg fails, ret = %d\n", ret);
1004                         goto stop;
1005                 }
1006         }
1007
1008         if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1009                 if (ci->is_otg) {
1010                         ci->role = ci_otg_role(ci);
1011                         /* Enable ID change irq */
1012                         hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1013                 } else {
1014                         /*
1015                          * If the controller is not OTG capable, but support
1016                          * role switch, the defalt role is gadget, and the
1017                          * user can switch it through debugfs.
1018                          */
1019                         ci->role = CI_ROLE_GADGET;
1020                 }
1021         } else {
1022                 ci->role = ci->roles[CI_ROLE_HOST]
1023                         ? CI_ROLE_HOST
1024                         : CI_ROLE_GADGET;
1025         }
1026
1027         if (!ci_otg_is_fsm_mode(ci)) {
1028                 /* only update vbus status for peripheral */
1029                 if (ci->role == CI_ROLE_GADGET)
1030                         ci_handle_vbus_change(ci);
1031
1032                 ret = ci_role_start(ci, ci->role);
1033                 if (ret) {
1034                         dev_err(dev, "can't start %s role\n",
1035                                                 ci_role(ci)->name);
1036                         goto stop;
1037                 }
1038         }
1039
1040         platform_set_drvdata(pdev, ci);
1041         ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1042                         ci->platdata->name, ci);
1043         if (ret)
1044                 goto stop;
1045
1046         ret = ci_extcon_register(ci);
1047         if (ret)
1048                 goto stop;
1049
1050         if (ci->supports_runtime_pm) {
1051                 pm_runtime_set_active(&pdev->dev);
1052                 pm_runtime_enable(&pdev->dev);
1053                 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1054                 pm_runtime_mark_last_busy(ci->dev);
1055                 pm_runtime_use_autosuspend(&pdev->dev);
1056         }
1057
1058         if (ci_otg_is_fsm_mode(ci))
1059                 ci_hdrc_otg_fsm_start(ci);
1060
1061         device_set_wakeup_capable(&pdev->dev, true);
1062
1063         ret = dbg_create_files(ci);
1064         if (!ret)
1065                 return 0;
1066
1067         ci_extcon_unregister(ci);
1068 stop:
1069         ci_role_destroy(ci);
1070 deinit_phy:
1071         ci_usb_phy_exit(ci);
1072
1073         return ret;
1074 }
1075
1076 static int ci_hdrc_remove(struct platform_device *pdev)
1077 {
1078         struct ci_hdrc *ci = platform_get_drvdata(pdev);
1079
1080         if (ci->supports_runtime_pm) {
1081                 pm_runtime_get_sync(&pdev->dev);
1082                 pm_runtime_disable(&pdev->dev);
1083                 pm_runtime_put_noidle(&pdev->dev);
1084         }
1085
1086         dbg_remove_files(ci);
1087         ci_extcon_unregister(ci);
1088         ci_role_destroy(ci);
1089         ci_hdrc_enter_lpm(ci, true);
1090         ci_usb_phy_exit(ci);
1091
1092         return 0;
1093 }
1094
1095 #ifdef CONFIG_PM
1096 /* Prepare wakeup by SRP before suspend */
1097 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1098 {
1099         if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1100                                 !hw_read_otgsc(ci, OTGSC_ID)) {
1101                 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1102                                                                 PORTSC_PP);
1103                 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1104                                                                 PORTSC_WKCN);
1105         }
1106 }
1107
1108 /* Handle SRP when wakeup by data pulse */
1109 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1110 {
1111         if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1112                 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1113                 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1114                         ci->fsm.a_srp_det = 1;
1115                         ci->fsm.a_bus_drop = 0;
1116                 } else {
1117                         ci->fsm.id = 1;
1118                 }
1119                 ci_otg_queue_work(ci);
1120         }
1121 }
1122
1123 static void ci_controller_suspend(struct ci_hdrc *ci)
1124 {
1125         disable_irq(ci->irq);
1126         ci_hdrc_enter_lpm(ci, true);
1127         if (ci->platdata->phy_clkgate_delay_us)
1128                 usleep_range(ci->platdata->phy_clkgate_delay_us,
1129                              ci->platdata->phy_clkgate_delay_us + 50);
1130         usb_phy_set_suspend(ci->usb_phy, 1);
1131         ci->in_lpm = true;
1132         enable_irq(ci->irq);
1133 }
1134
1135 static int ci_controller_resume(struct device *dev)
1136 {
1137         struct ci_hdrc *ci = dev_get_drvdata(dev);
1138
1139         dev_dbg(dev, "at %s\n", __func__);
1140
1141         if (!ci->in_lpm) {
1142                 WARN_ON(1);
1143                 return 0;
1144         }
1145
1146         ci_hdrc_enter_lpm(ci, false);
1147         if (ci->usb_phy) {
1148                 usb_phy_set_suspend(ci->usb_phy, 0);
1149                 usb_phy_set_wakeup(ci->usb_phy, false);
1150                 hw_wait_phy_stable();
1151         }
1152
1153         ci->in_lpm = false;
1154         if (ci->wakeup_int) {
1155                 ci->wakeup_int = false;
1156                 pm_runtime_mark_last_busy(ci->dev);
1157                 pm_runtime_put_autosuspend(ci->dev);
1158                 enable_irq(ci->irq);
1159                 if (ci_otg_is_fsm_mode(ci))
1160                         ci_otg_fsm_wakeup_by_srp(ci);
1161         }
1162
1163         return 0;
1164 }
1165
1166 #ifdef CONFIG_PM_SLEEP
1167 static int ci_suspend(struct device *dev)
1168 {
1169         struct ci_hdrc *ci = dev_get_drvdata(dev);
1170
1171         if (ci->wq)
1172                 flush_workqueue(ci->wq);
1173         /*
1174          * Controller needs to be active during suspend, otherwise the core
1175          * may run resume when the parent is at suspend if other driver's
1176          * suspend fails, it occurs before parent's suspend has not started,
1177          * but the core suspend has finished.
1178          */
1179         if (ci->in_lpm)
1180                 pm_runtime_resume(dev);
1181
1182         if (ci->in_lpm) {
1183                 WARN_ON(1);
1184                 return 0;
1185         }
1186
1187         if (device_may_wakeup(dev)) {
1188                 if (ci_otg_is_fsm_mode(ci))
1189                         ci_otg_fsm_suspend_for_srp(ci);
1190
1191                 usb_phy_set_wakeup(ci->usb_phy, true);
1192                 enable_irq_wake(ci->irq);
1193         }
1194
1195         ci_controller_suspend(ci);
1196
1197         return 0;
1198 }
1199
1200 static int ci_resume(struct device *dev)
1201 {
1202         struct ci_hdrc *ci = dev_get_drvdata(dev);
1203         int ret;
1204
1205         if (device_may_wakeup(dev))
1206                 disable_irq_wake(ci->irq);
1207
1208         ret = ci_controller_resume(dev);
1209         if (ret)
1210                 return ret;
1211
1212         if (ci->supports_runtime_pm) {
1213                 pm_runtime_disable(dev);
1214                 pm_runtime_set_active(dev);
1215                 pm_runtime_enable(dev);
1216         }
1217
1218         return ret;
1219 }
1220 #endif /* CONFIG_PM_SLEEP */
1221
1222 static int ci_runtime_suspend(struct device *dev)
1223 {
1224         struct ci_hdrc *ci = dev_get_drvdata(dev);
1225
1226         dev_dbg(dev, "at %s\n", __func__);
1227
1228         if (ci->in_lpm) {
1229                 WARN_ON(1);
1230                 return 0;
1231         }
1232
1233         if (ci_otg_is_fsm_mode(ci))
1234                 ci_otg_fsm_suspend_for_srp(ci);
1235
1236         usb_phy_set_wakeup(ci->usb_phy, true);
1237         ci_controller_suspend(ci);
1238
1239         return 0;
1240 }
1241
1242 static int ci_runtime_resume(struct device *dev)
1243 {
1244         return ci_controller_resume(dev);
1245 }
1246
1247 #endif /* CONFIG_PM */
1248 static const struct dev_pm_ops ci_pm_ops = {
1249         SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1250         SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1251 };
1252
1253 static struct platform_driver ci_hdrc_driver = {
1254         .probe  = ci_hdrc_probe,
1255         .remove = ci_hdrc_remove,
1256         .driver = {
1257                 .name   = "ci_hdrc",
1258                 .pm     = &ci_pm_ops,
1259         },
1260 };
1261
1262 static int __init ci_hdrc_platform_register(void)
1263 {
1264         ci_hdrc_host_driver_init();
1265         return platform_driver_register(&ci_hdrc_driver);
1266 }
1267 module_init(ci_hdrc_platform_register);
1268
1269 static void __exit ci_hdrc_platform_unregister(void)
1270 {
1271         platform_driver_unregister(&ci_hdrc_driver);
1272 }
1273 module_exit(ci_hdrc_platform_unregister);
1274
1275 MODULE_ALIAS("platform:ci_hdrc");
1276 MODULE_LICENSE("GPL v2");
1277 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1278 MODULE_DESCRIPTION("ChipIdea HDRC Driver");