drivers/usb/chipidea/core.c

   1 /*
   2  * core.c - ChipIdea USB IP core family device controller
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 /*
  14  * Description: ChipIdea USB IP core family device controller
  15  *
  16  * This driver is composed of several blocks:
  17  * - HW:     hardware interface
  18  * - DBG:    debug facilities (optional)
  19  * - UTIL:   utilities
  20  * - ISR:    interrupts handling
  21  * - ENDPT:  endpoint operations (Gadget API)
  22  * - GADGET: gadget operations (Gadget API)
  23  * - BUS:    bus glue code, bus abstraction layer
  24  *
  25  * Compile Options
  26  * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
  27  * - STALL_IN:  non-empty bulk-in pipes cannot be halted
  28  *              if defined mass storage compliance succeeds but with warnings
  29  *              => case 4: Hi >  Dn
  30  *              => case 5: Hi >  Di
  31  *              => case 8: Hi <> Do
  32  *              if undefined usbtest 13 fails
  33  * - TRACE:     enable function tracing (depends on DEBUG)
  34  *
  35  * Main Features
  36  * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37  * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38  * - Normal & LPM support
  39  *
  40  * USBTEST Report
  41  * - OK: 0-12, 13 (STALL_IN defined) & 14
  42  * - Not Supported: 15 & 16 (ISO)
  43  *
  44  * TODO List
  45  * - Suspend & Remote Wakeup
  46  */
  47 #include <linux/delay.h>
  48 #include <linux/device.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/extcon.h>
  51 #include <linux/phy/phy.h>
  52 #include <linux/platform_device.h>
  53 #include <linux/module.h>
  54 #include <linux/idr.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/io.h>
  57 #include <linux/kernel.h>
  58 #include <linux/slab.h>
  59 #include <linux/pm_runtime.h>
  60 #include <linux/usb/ch9.h>
  61 #include <linux/usb/gadget.h>
  62 #include <linux/usb/otg.h>
  63 #include <linux/usb/chipidea.h>
  64 #include <linux/usb/of.h>
  65 #include <linux/of.h>
  66 #include <linux/phy.h>
  67 #include <linux/regulator/consumer.h>
  68 #include <linux/usb/ehci_def.h>
  69
  70 #include "ci.h"
  71 #include "udc.h"
  72 #include "bits.h"
  73 #include "host.h"
  74 #include "debug.h"
  75 #include "otg.h"
  76 #include "otg_fsm.h"
  77
  78 /* Controller register map */
  79 static const u8 ci_regs_nolpm[] = {
  80         [CAP_CAPLENGTH]         = 0x00U,
  81         [CAP_HCCPARAMS]         = 0x08U,
  82         [CAP_DCCPARAMS]         = 0x24U,
  83         [CAP_TESTMODE]          = 0x38U,
  84         [OP_USBCMD]             = 0x00U,
  85         [OP_USBSTS]             = 0x04U,
  86         [OP_USBINTR]            = 0x08U,
  87         [OP_DEVICEADDR]         = 0x14U,
  88         [OP_ENDPTLISTADDR]      = 0x18U,
  89         [OP_TTCTRL]             = 0x1CU,
  90         [OP_BURSTSIZE]          = 0x20U,
  91         [OP_PORTSC]             = 0x44U,
  92         [OP_DEVLC]              = 0x84U,
  93         [OP_OTGSC]              = 0x64U,
  94         [OP_USBMODE]            = 0x68U,
  95         [OP_ENDPTSETUPSTAT]     = 0x6CU,
  96         [OP_ENDPTPRIME]         = 0x70U,
  97         [OP_ENDPTFLUSH]         = 0x74U,
  98         [OP_ENDPTSTAT]          = 0x78U,
  99         [OP_ENDPTCOMPLETE]      = 0x7CU,
 100         [OP_ENDPTCTRL]          = 0x80U,
 101 };
 102
 103 static const u8 ci_regs_lpm[] = {
 104         [CAP_CAPLENGTH]         = 0x00U,
 105         [CAP_HCCPARAMS]         = 0x08U,
 106         [CAP_DCCPARAMS]         = 0x24U,
 107         [CAP_TESTMODE]          = 0xFCU,
 108         [OP_USBCMD]             = 0x00U,
 109         [OP_USBSTS]             = 0x04U,
 110         [OP_USBINTR]            = 0x08U,
 111         [OP_DEVICEADDR]         = 0x14U,
 112         [OP_ENDPTLISTADDR]      = 0x18U,
 113         [OP_TTCTRL]             = 0x1CU,
 114         [OP_BURSTSIZE]          = 0x20U,
 115         [OP_PORTSC]             = 0x44U,
 116         [OP_DEVLC]              = 0x84U,
 117         [OP_OTGSC]              = 0xC4U,
 118         [OP_USBMODE]            = 0xC8U,
 119         [OP_ENDPTSETUPSTAT]     = 0xD8U,
 120         [OP_ENDPTPRIME]         = 0xDCU,
 121         [OP_ENDPTFLUSH]         = 0xE0U,
 122         [OP_ENDPTSTAT]          = 0xE4U,
 123         [OP_ENDPTCOMPLETE]      = 0xE8U,
 124         [OP_ENDPTCTRL]          = 0xECU,
 125 };
 126
 127 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
 128 {
 129         int i;
 130
 131         for (i = 0; i < OP_ENDPTCTRL; i++)
 132                 ci->hw_bank.regmap[i] =
 133                         (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
 134                         (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
 135
 136         for (; i <= OP_LAST; i++)
 137                 ci->hw_bank.regmap[i] = ci->hw_bank.op +
 138                         4 * (i - OP_ENDPTCTRL) +
 139                         (is_lpm
 140                          ? ci_regs_lpm[OP_ENDPTCTRL]
 141                          : ci_regs_nolpm[OP_ENDPTCTRL]);
 142
 143 }
 144
 145 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
 146 {
 147         int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
 148         enum ci_revision rev = CI_REVISION_UNKNOWN;
 149
 150         if (ver == 0x2) {
 151                 rev = hw_read_id_reg(ci, ID_ID, REVISION)
 152                         >> __ffs(REVISION);
 153                 rev += CI_REVISION_20;
 154         } else if (ver == 0x0) {
 155                 rev = CI_REVISION_1X;
 156         }
 157
 158         return rev;
 159 }
 160
 161 /**
 162  * hw_read_intr_enable: returns interrupt enable register
 163  *
 164  * @ci: the controller
 165  *
 166  * This function returns register data
 167  */
 168 u32 hw_read_intr_enable(struct ci_hdrc *ci)
 169 {
 170         return hw_read(ci, OP_USBINTR, ~0);
 171 }
 172
 173 /**
 174  * hw_read_intr_status: returns interrupt status register
 175  *
 176  * @ci: the controller
 177  *
 178  * This function returns register data
 179  */
 180 u32 hw_read_intr_status(struct ci_hdrc *ci)
 181 {
 182         return hw_read(ci, OP_USBSTS, ~0);
 183 }
 184
 185 /**
 186  * hw_port_test_set: writes port test mode (execute without interruption)
 187  * @mode: new value
 188  *
 189  * This function returns an error code
 190  */
 191 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
 192 {
 193         const u8 TEST_MODE_MAX = 7;
 194
 195         if (mode > TEST_MODE_MAX)
 196                 return -EINVAL;
 197
 198         hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
 199         return 0;
 200 }
 201
 202 /**
 203  * hw_port_test_get: reads port test mode value
 204  *
 205  * @ci: the controller
 206  *
 207  * This function returns port test mode value
 208  */
 209 u8 hw_port_test_get(struct ci_hdrc *ci)
 210 {
 211         return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
 212 }
 213
 214 static void hw_wait_phy_stable(void)
 215 {
 216         /*
 217          * The phy needs some delay to output the stable status from low
 218          * power mode. And for OTGSC, the status inputs are debounced
 219          * using a 1 ms time constant, so, delay 2ms for controller to get
 220          * the stable status, like vbus and id when the phy leaves low power.
 221          */
 222         usleep_range(2000, 2500);
 223 }
 224
 225 /* The PHY enters/leaves low power mode */
 226 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
 227 {
 228         enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
 229         bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
 230
 231         if (enable && !lpm)
 232                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 233                                 PORTSC_PHCD(ci->hw_bank.lpm));
 234         else if (!enable && lpm)
 235                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 236                                 0);
 237 }
 238
 239 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
 240 {
 241         u32 reg;
 242
 243         /* bank is a module variable */
 244         ci->hw_bank.abs = base;
 245
 246         ci->hw_bank.cap = ci->hw_bank.abs;
 247         ci->hw_bank.cap += ci->platdata->capoffset;
 248         ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
 249
 250         hw_alloc_regmap(ci, false);
 251         reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
 252                 __ffs(HCCPARAMS_LEN);
 253         ci->hw_bank.lpm  = reg;
 254         if (reg)
 255                 hw_alloc_regmap(ci, !!reg);
 256         ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
 257         ci->hw_bank.size += OP_LAST;
 258         ci->hw_bank.size /= sizeof(u32);
 259
 260         reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
 261                 __ffs(DCCPARAMS_DEN);
 262         ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
 263
 264         if (ci->hw_ep_max > ENDPT_MAX)
 265                 return -ENODEV;
 266
 267         ci_hdrc_enter_lpm(ci, false);
 268
 269         /* Disable all interrupts bits */
 270         hw_write(ci, OP_USBINTR, 0xffffffff, 0);
 271
 272         /* Clear all interrupts status bits*/
 273         hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
 274
 275         ci->rev = ci_get_revision(ci);
 276
 277         dev_dbg(ci->dev,
 278                 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
 279                 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
 280
 281         /* setup lock mode ? */
 282
 283         /* ENDPTSETUPSTAT is '0' by default */
 284
 285         /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
 286
 287         return 0;
 288 }
 289
 290 static void hw_phymode_configure(struct ci_hdrc *ci)
 291 {
 292         u32 portsc, lpm, sts = 0;
 293
 294         switch (ci->platdata->phy_mode) {
 295         case USBPHY_INTERFACE_MODE_UTMI:
 296                 portsc = PORTSC_PTS(PTS_UTMI);
 297                 lpm = DEVLC_PTS(PTS_UTMI);
 298                 break;
 299         case USBPHY_INTERFACE_MODE_UTMIW:
 300                 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
 301                 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
 302                 break;
 303         case USBPHY_INTERFACE_MODE_ULPI:
 304                 portsc = PORTSC_PTS(PTS_ULPI);
 305                 lpm = DEVLC_PTS(PTS_ULPI);
 306                 break;
 307         case USBPHY_INTERFACE_MODE_SERIAL:
 308                 portsc = PORTSC_PTS(PTS_SERIAL);
 309                 lpm = DEVLC_PTS(PTS_SERIAL);
 310                 sts = 1;
 311                 break;
 312         case USBPHY_INTERFACE_MODE_HSIC:
 313                 portsc = PORTSC_PTS(PTS_HSIC);
 314                 lpm = DEVLC_PTS(PTS_HSIC);
 315                 break;
 316         default:
 317                 return;
 318         }
 319
 320         if (ci->hw_bank.lpm) {
 321                 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
 322                 if (sts)
 323                         hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
 324         } else {
 325                 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
 326                 if (sts)
 327                         hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
 328         }
 329 }
 330
 331 /**
 332  * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
 333  * interfaces
 334  * @ci: the controller
 335  *
 336  * This function returns an error code if the phy failed to init
 337  */
 338 static int _ci_usb_phy_init(struct ci_hdrc *ci)
 339 {
 340         int ret;
 341
 342         if (ci->phy) {
 343                 ret = phy_init(ci->phy);
 344                 if (ret)
 345                         return ret;
 346
 347                 ret = phy_power_on(ci->phy);
 348                 if (ret) {
 349                         phy_exit(ci->phy);
 350                         return ret;
 351                 }
 352         } else {
 353                 ret = usb_phy_init(ci->usb_phy);
 354         }
 355
 356         return ret;
 357 }
 358
 359 /**
 360  * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
 361  * interfaces
 362  * @ci: the controller
 363  */
 364 static void ci_usb_phy_exit(struct ci_hdrc *ci)
 365 {
 366         if (ci->phy) {
 367                 phy_power_off(ci->phy);
 368                 phy_exit(ci->phy);
 369         } else {
 370                 usb_phy_shutdown(ci->usb_phy);
 371         }
 372 }
 373
 374 /**
 375  * ci_usb_phy_init: initialize phy according to different phy type
 376  * @ci: the controller
 377  *
 378  * This function returns an error code if usb_phy_init has failed
 379  */
 380 static int ci_usb_phy_init(struct ci_hdrc *ci)
 381 {
 382         int ret;
 383
 384         switch (ci->platdata->phy_mode) {
 385         case USBPHY_INTERFACE_MODE_UTMI:
 386         case USBPHY_INTERFACE_MODE_UTMIW:
 387         case USBPHY_INTERFACE_MODE_HSIC:
 388                 ret = _ci_usb_phy_init(ci);
 389                 if (!ret)
 390                         hw_wait_phy_stable();
 391                 else
 392                         return ret;
 393                 hw_phymode_configure(ci);
 394                 break;
 395         case USBPHY_INTERFACE_MODE_ULPI:
 396         case USBPHY_INTERFACE_MODE_SERIAL:
 397                 hw_phymode_configure(ci);
 398                 ret = _ci_usb_phy_init(ci);
 399                 if (ret)
 400                         return ret;
 401                 break;
 402         default:
 403                 ret = _ci_usb_phy_init(ci);
 404                 if (!ret)
 405                         hw_wait_phy_stable();
 406         }
 407
 408         return ret;
 409 }
 410
 411
 412 /**
 413  * ci_platform_configure: do controller configure
 414  * @ci: the controller
 415  *
 416  */
 417 void ci_platform_configure(struct ci_hdrc *ci)
 418 {
 419         bool is_device_mode, is_host_mode;
 420
 421         is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
 422         is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
 423
 424         if (is_device_mode &&
 425                 (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING))
 426                 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
 427
 428         if (is_host_mode &&
 429                 (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING))
 430                 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
 431
 432         if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
 433                 if (ci->hw_bank.lpm)
 434                         hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
 435                 else
 436                         hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
 437         }
 438
 439         if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
 440                 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
 441
 442         hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
 443
 444         if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
 445                 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
 446                         ci->platdata->ahb_burst_config);
 447
 448         /* override burst size, take effect only when ahb_burst_config is 0 */
 449         if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
 450                 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
 451                         hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
 452                         ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
 453
 454                 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
 455                         hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
 456                                 ci->platdata->rx_burst_size);
 457         }
 458 }
 459
 460 /**
 461  * hw_controller_reset: do controller reset
 462  * @ci: the controller
 463   *
 464  * This function returns an error code
 465  */
 466 static int hw_controller_reset(struct ci_hdrc *ci)
 467 {
 468         int count = 0;
 469
 470         hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
 471         while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
 472                 udelay(10);
 473                 if (count++ > 1000)
 474                         return -ETIMEDOUT;
 475         }
 476
 477         return 0;
 478 }
 479
 480 /**
 481  * hw_device_reset: resets chip (execute without interruption)
 482  * @ci: the controller
 483  *
 484  * This function returns an error code
 485  */
 486 int hw_device_reset(struct ci_hdrc *ci)
 487 {
 488         int ret;
 489
 490         /* should flush & stop before reset */
 491         hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
 492         hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
 493
 494         ret = hw_controller_reset(ci);
 495         if (ret) {
 496                 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
 497                 return ret;
 498         }
 499
 500         if (ci->platdata->notify_event)
 501                 ci->platdata->notify_event(ci,
 502                         CI_HDRC_CONTROLLER_RESET_EVENT);
 503
 504         /* USBMODE should be configured step by step */
 505         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
 506         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
 507         /* HW >= 2.3 */
 508         hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
 509
 510         if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
 511                 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
 512                 pr_err("lpm = %i", ci->hw_bank.lpm);
 513                 return -ENODEV;
 514         }
 515
 516         ci_platform_configure(ci);
 517
 518         return 0;
 519 }
 520
 521 /**
 522  * hw_wait_reg: wait the register value
 523  *
 524  * Sometimes, it needs to wait register value before going on.
 525  * Eg, when switch to device mode, the vbus value should be lower
 526  * than OTGSC_BSV before connects to host.
 527  *
 528  * @ci: the controller
 529  * @reg: register index
 530  * @mask: mast bit
 531  * @value: the bit value to wait
 532  * @timeout_ms: timeout in millisecond
 533  *
 534  * This function returns an error code if timeout
 535  */
 536 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
 537                                 u32 value, unsigned int timeout_ms)
 538 {
 539         unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
 540
 541         while (hw_read(ci, reg, mask) != value) {
 542                 if (time_after(jiffies, elapse)) {
 543                         dev_err(ci->dev, "timeout waiting for %08x in %d\n",
 544                                         mask, reg);
 545                         return -ETIMEDOUT;
 546                 }
 547                 msleep(20);
 548         }
 549
 550         return 0;
 551 }
 552
 553 static irqreturn_t ci_irq(int irq, void *data)
 554 {
 555         struct ci_hdrc *ci = data;
 556         irqreturn_t ret = IRQ_NONE;
 557         u32 otgsc = 0;
 558
 559         if (ci->in_lpm) {
 560                 disable_irq_nosync(irq);
 561                 ci->wakeup_int = true;
 562                 pm_runtime_get(ci->dev);
 563                 return IRQ_HANDLED;
 564         }
 565
 566         if (ci->is_otg) {
 567                 otgsc = hw_read_otgsc(ci, ~0);
 568                 if (ci_otg_is_fsm_mode(ci)) {
 569                         ret = ci_otg_fsm_irq(ci);
 570                         if (ret == IRQ_HANDLED)
 571                                 return ret;
 572                 }
 573         }
 574
 575         /*
 576          * Handle id change interrupt, it indicates device/host function
 577          * switch.
 578          */
 579         if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
 580                 ci->id_event = true;
 581                 /* Clear ID change irq status */
 582                 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
 583                 ci_otg_queue_work(ci);
 584                 return IRQ_HANDLED;
 585         }
 586
 587         /*
 588          * Handle vbus change interrupt, it indicates device connection
 589          * and disconnection events.
 590          */
 591         if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
 592                 ci->b_sess_valid_event = true;
 593                 /* Clear BSV irq */
 594                 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
 595                 ci_otg_queue_work(ci);
 596                 return IRQ_HANDLED;
 597         }
 598
 599         /* Handle device/host interrupt */
 600         if (ci->role != CI_ROLE_END)
 601                 ret = ci_role(ci)->irq(ci);
 602
 603         return ret;
 604 }
 605
 606 static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event,
 607                             void *ptr)
 608 {
 609         struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, nb);
 610         struct ci_hdrc *ci = vbus->ci;
 611
 612         if (event)
 613                 vbus->state = true;
 614         else
 615                 vbus->state = false;
 616
 617         vbus->changed = true;
 618
 619         ci_irq(ci->irq, ci);
 620         return NOTIFY_DONE;
 621 }
 622
 623 static int ci_id_notifier(struct notifier_block *nb, unsigned long event,
 624                           void *ptr)
 625 {
 626         struct ci_hdrc_cable *id = container_of(nb, struct ci_hdrc_cable, nb);
 627         struct ci_hdrc *ci = id->ci;
 628
 629         if (event)
 630                 id->state = false;
 631         else
 632                 id->state = true;
 633
 634         id->changed = true;
 635
 636         ci_irq(ci->irq, ci);
 637         return NOTIFY_DONE;
 638 }
 639
 640 static int ci_get_platdata(struct device *dev,
 641                 struct ci_hdrc_platform_data *platdata)
 642 {
 643         struct extcon_dev *ext_vbus, *ext_id;
 644         struct ci_hdrc_cable *cable;
 645         int ret;
 646
 647         if (!platdata->phy_mode)
 648                 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
 649
 650         if (!platdata->dr_mode)
 651                 platdata->dr_mode = usb_get_dr_mode(dev);
 652
 653         if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
 654                 platdata->dr_mode = USB_DR_MODE_OTG;
 655
 656         if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
 657                 /* Get the vbus regulator */
 658                 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
 659                 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
 660                         return -EPROBE_DEFER;
 661                 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
 662                         /* no vbus regulator is needed */
 663                         platdata->reg_vbus = NULL;
 664                 } else if (IS_ERR(platdata->reg_vbus)) {
 665                         dev_err(dev, "Getting regulator error: %ld\n",
 666                                 PTR_ERR(platdata->reg_vbus));
 667                         return PTR_ERR(platdata->reg_vbus);
 668                 }
 669                 /* Get TPL support */
 670                 if (!platdata->tpl_support)
 671                         platdata->tpl_support =
 672                                 of_usb_host_tpl_support(dev->of_node);
 673         }
 674
 675         if (platdata->dr_mode == USB_DR_MODE_OTG) {
 676                 /* We can support HNP and SRP of OTG 2.0 */
 677                 platdata->ci_otg_caps.otg_rev = 0x0200;
 678                 platdata->ci_otg_caps.hnp_support = true;
 679                 platdata->ci_otg_caps.srp_support = true;
 680
 681                 /* Update otg capabilities by DT properties */
 682                 ret = of_usb_update_otg_caps(dev->of_node,
 683                                         &platdata->ci_otg_caps);
 684                 if (ret)
 685                         return ret;
 686         }
 687
 688         if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
 689                 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
 690
 691         if (of_find_property(dev->of_node, "phy-clkgate-delay-us", NULL))
 692                 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
 693                                      &platdata->phy_clkgate_delay_us);
 694
 695         platdata->itc_setting = 1;
 696         if (of_find_property(dev->of_node, "itc-setting", NULL)) {
 697                 ret = of_property_read_u32(dev->of_node, "itc-setting",
 698                         &platdata->itc_setting);
 699                 if (ret) {
 700                         dev_err(dev,
 701                                 "failed to get itc-setting\n");
 702                         return ret;
 703                 }
 704         }
 705
 706         if (of_find_property(dev->of_node, "ahb-burst-config", NULL)) {
 707                 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
 708                         &platdata->ahb_burst_config);
 709                 if (ret) {
 710                         dev_err(dev,
 711                                 "failed to get ahb-burst-config\n");
 712                         return ret;
 713                 }
 714                 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
 715         }
 716
 717         if (of_find_property(dev->of_node, "tx-burst-size-dword", NULL)) {
 718                 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
 719                         &platdata->tx_burst_size);
 720                 if (ret) {
 721                         dev_err(dev,
 722                                 "failed to get tx-burst-size-dword\n");
 723                         return ret;
 724                 }
 725                 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
 726         }
 727
 728         if (of_find_property(dev->of_node, "rx-burst-size-dword", NULL)) {
 729                 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
 730                         &platdata->rx_burst_size);
 731                 if (ret) {
 732                         dev_err(dev,
 733                                 "failed to get rx-burst-size-dword\n");
 734                         return ret;
 735                 }
 736                 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
 737         }
 738
 739         ext_id = ERR_PTR(-ENODEV);
 740         ext_vbus = ERR_PTR(-ENODEV);
 741         if (of_property_read_bool(dev->of_node, "extcon")) {
 742                 /* Each one of them is not mandatory */
 743                 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
 744                 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
 745                         return PTR_ERR(ext_vbus);
 746
 747                 ext_id = extcon_get_edev_by_phandle(dev, 1);
 748                 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
 749                         return PTR_ERR(ext_id);
 750         }
 751
 752         cable = &platdata->vbus_extcon;
 753         cable->nb.notifier_call = ci_vbus_notifier;
 754         cable->edev = ext_vbus;
 755
 756         if (!IS_ERR(ext_vbus)) {
 757                 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB);
 758                 if (ret)
 759                         cable->state = true;
 760                 else
 761                         cable->state = false;
 762         }
 763
 764         cable = &platdata->id_extcon;
 765         cable->nb.notifier_call = ci_id_notifier;
 766         cable->edev = ext_id;
 767
 768         if (!IS_ERR(ext_id)) {
 769                 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB_HOST);
 770                 if (ret)
 771                         cable->state = false;
 772                 else
 773                         cable->state = true;
 774         }
 775         return 0;
 776 }
 777
 778 static int ci_extcon_register(struct ci_hdrc *ci)
 779 {
 780         struct ci_hdrc_cable *id, *vbus;
 781         int ret;
 782
 783         id = &ci->platdata->id_extcon;
 784         id->ci = ci;
 785         if (!IS_ERR(id->edev)) {
 786                 ret = extcon_register_notifier(id->edev, EXTCON_USB_HOST,
 787                                                &id->nb);
 788                 if (ret < 0) {
 789                         dev_err(ci->dev, "register ID failed\n");
 790                         return ret;
 791                 }
 792         }
 793
 794         vbus = &ci->platdata->vbus_extcon;
 795         vbus->ci = ci;
 796         if (!IS_ERR(vbus->edev)) {
 797                 ret = extcon_register_notifier(vbus->edev, EXTCON_USB,
 798                                                &vbus->nb);
 799                 if (ret < 0) {
 800                         extcon_unregister_notifier(id->edev, EXTCON_USB_HOST,
 801                                                    &id->nb);
 802                         dev_err(ci->dev, "register VBUS failed\n");
 803                         return ret;
 804                 }
 805         }
 806
 807         return 0;
 808 }
 809
 810 static void ci_extcon_unregister(struct ci_hdrc *ci)
 811 {
 812         struct ci_hdrc_cable *cable;
 813
 814         cable = &ci->platdata->id_extcon;
 815         if (!IS_ERR(cable->edev))
 816                 extcon_unregister_notifier(cable->edev, EXTCON_USB_HOST,
 817                                            &cable->nb);
 818
 819         cable = &ci->platdata->vbus_extcon;
 820         if (!IS_ERR(cable->edev))
 821                 extcon_unregister_notifier(cable->edev, EXTCON_USB, &cable->nb);
 822 }
 823
 824 static DEFINE_IDA(ci_ida);
 825
 826 struct platform_device *ci_hdrc_add_device(struct device *dev,
 827                         struct resource *res, int nres,
 828                         struct ci_hdrc_platform_data *platdata)
 829 {
 830         struct platform_device *pdev;
 831         int id, ret;
 832
 833         ret = ci_get_platdata(dev, platdata);
 834         if (ret)
 835                 return ERR_PTR(ret);
 836
 837         id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
 838         if (id < 0)
 839                 return ERR_PTR(id);
 840
 841         pdev = platform_device_alloc("ci_hdrc", id);
 842         if (!pdev) {
 843                 ret = -ENOMEM;
 844                 goto put_id;
 845         }
 846
 847         pdev->dev.parent = dev;
 848         pdev->dev.dma_mask = dev->dma_mask;
 849         pdev->dev.dma_parms = dev->dma_parms;
 850         dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
 851
 852         ret = platform_device_add_resources(pdev, res, nres);
 853         if (ret)
 854                 goto err;
 855
 856         ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
 857         if (ret)
 858                 goto err;
 859
 860         ret = platform_device_add(pdev);
 861         if (ret)
 862                 goto err;
 863
 864         return pdev;
 865
 866 err:
 867         platform_device_put(pdev);
 868 put_id:
 869         ida_simple_remove(&ci_ida, id);
 870         return ERR_PTR(ret);
 871 }
 872 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
 873
 874 void ci_hdrc_remove_device(struct platform_device *pdev)
 875 {
 876         int id = pdev->id;
 877         platform_device_unregister(pdev);
 878         ida_simple_remove(&ci_ida, id);
 879 }
 880 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
 881
 882 static inline void ci_role_destroy(struct ci_hdrc *ci)
 883 {
 884         ci_hdrc_gadget_destroy(ci);
 885         ci_hdrc_host_destroy(ci);
 886         if (ci->is_otg)
 887                 ci_hdrc_otg_destroy(ci);
 888 }
 889
 890 static void ci_get_otg_capable(struct ci_hdrc *ci)
 891 {
 892         if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
 893                 ci->is_otg = false;
 894         else
 895                 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
 896                                 DCCPARAMS_DC | DCCPARAMS_HC)
 897                                         == (DCCPARAMS_DC | DCCPARAMS_HC));
 898         if (ci->is_otg) {
 899                 dev_dbg(ci->dev, "It is OTG capable controller\n");
 900                 /* Disable and clear all OTG irq */
 901                 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
 902                                                         OTGSC_INT_STATUS_BITS);
 903         }
 904 }
 905
 906 static int ci_hdrc_probe(struct platform_device *pdev)
 907 {
 908         struct device   *dev = &pdev->dev;
 909         struct ci_hdrc  *ci;
 910         struct resource *res;
 911         void __iomem    *base;
 912         int             ret;
 913         enum usb_dr_mode dr_mode;
 914
 915         if (!dev_get_platdata(dev)) {
 916                 dev_err(dev, "platform data missing\n");
 917                 return -ENODEV;
 918         }
 919
 920         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 921         base = devm_ioremap_resource(dev, res);
 922         if (IS_ERR(base))
 923                 return PTR_ERR(base);
 924
 925         ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
 926         if (!ci)
 927                 return -ENOMEM;
 928
 929         ci->dev = dev;
 930         ci->platdata = dev_get_platdata(dev);
 931         ci->imx28_write_fix = !!(ci->platdata->flags &
 932                 CI_HDRC_IMX28_WRITE_FIX);
 933         ci->supports_runtime_pm = !!(ci->platdata->flags &
 934                 CI_HDRC_SUPPORTS_RUNTIME_PM);
 935
 936         ret = hw_device_init(ci, base);
 937         if (ret < 0) {
 938                 dev_err(dev, "can't initialize hardware\n");
 939                 return -ENODEV;
 940         }
 941
 942         if (ci->platdata->phy) {
 943                 ci->phy = ci->platdata->phy;
 944         } else if (ci->platdata->usb_phy) {
 945                 ci->usb_phy = ci->platdata->usb_phy;
 946         } else {
 947                 ci->phy = devm_phy_get(dev->parent, "usb-phy");
 948                 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
 949
 950                 /* if both generic PHY and USB PHY layers aren't enabled */
 951                 if (PTR_ERR(ci->phy) == -ENOSYS &&
 952                                 PTR_ERR(ci->usb_phy) == -ENXIO)
 953                         return -ENXIO;
 954
 955                 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
 956                         return -EPROBE_DEFER;
 957
 958                 if (IS_ERR(ci->phy))
 959                         ci->phy = NULL;
 960                 else if (IS_ERR(ci->usb_phy))
 961                         ci->usb_phy = NULL;
 962         }
 963
 964         ret = ci_usb_phy_init(ci);
 965         if (ret) {
 966                 dev_err(dev, "unable to init phy: %d\n", ret);
 967                 return ret;
 968         }
 969
 970         ci->hw_bank.phys = res->start;
 971
 972         ci->irq = platform_get_irq(pdev, 0);
 973         if (ci->irq < 0) {
 974                 dev_err(dev, "missing IRQ\n");
 975                 ret = ci->irq;
 976                 goto deinit_phy;
 977         }
 978
 979         ci_get_otg_capable(ci);
 980
 981         dr_mode = ci->platdata->dr_mode;
 982         /* initialize role(s) before the interrupt is requested */
 983         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
 984                 ret = ci_hdrc_host_init(ci);
 985                 if (ret)
 986                         dev_info(dev, "doesn't support host\n");
 987         }
 988
 989         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
 990                 ret = ci_hdrc_gadget_init(ci);
 991                 if (ret)
 992                         dev_info(dev, "doesn't support gadget\n");
 993         }
 994
 995         if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
 996                 dev_err(dev, "no supported roles\n");
 997                 ret = -ENODEV;
 998                 goto deinit_phy;
 999         }
1000
1001         if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1002                 ret = ci_hdrc_otg_init(ci);
1003                 if (ret) {
1004                         dev_err(dev, "init otg fails, ret = %d\n", ret);
1005                         goto stop;
1006                 }
1007         }
1008
1009         if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1010                 if (ci->is_otg) {
1011                         ci->role = ci_otg_role(ci);
1012                         /* Enable ID change irq */
1013                         hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1014                 } else {
1015                         /*
1016                          * If the controller is not OTG capable, but support
1017                          * role switch, the defalt role is gadget, and the
1018                          * user can switch it through debugfs.
1019                          */
1020                         ci->role = CI_ROLE_GADGET;
1021                 }
1022         } else {
1023                 ci->role = ci->roles[CI_ROLE_HOST]
1024                         ? CI_ROLE_HOST
1025                         : CI_ROLE_GADGET;
1026         }
1027
1028         if (!ci_otg_is_fsm_mode(ci)) {
1029                 /* only update vbus status for peripheral */
1030                 if (ci->role == CI_ROLE_GADGET)
1031                         ci_handle_vbus_change(ci);
1032
1033                 ret = ci_role_start(ci, ci->role);
1034                 if (ret) {
1035                         dev_err(dev, "can't start %s role\n",
1036                                                 ci_role(ci)->name);
1037                         goto stop;
1038                 }
1039         }
1040
1041         platform_set_drvdata(pdev, ci);
1042         ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1043                         ci->platdata->name, ci);
1044         if (ret)
1045                 goto stop;
1046
1047         ret = ci_extcon_register(ci);
1048         if (ret)
1049                 goto stop;
1050
1051         if (ci->supports_runtime_pm) {
1052                 pm_runtime_set_active(&pdev->dev);
1053                 pm_runtime_enable(&pdev->dev);
1054                 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1055                 pm_runtime_mark_last_busy(ci->dev);
1056                 pm_runtime_use_autosuspend(&pdev->dev);
1057         }
1058
1059         if (ci_otg_is_fsm_mode(ci))
1060                 ci_hdrc_otg_fsm_start(ci);
1061
1062         device_set_wakeup_capable(&pdev->dev, true);
1063
1064         ret = dbg_create_files(ci);
1065         if (!ret)
1066                 return 0;
1067
1068         ci_extcon_unregister(ci);
1069 stop:
1070         ci_role_destroy(ci);
1071 deinit_phy:
1072         ci_usb_phy_exit(ci);
1073
1074         return ret;
1075 }
1076
1077 static int ci_hdrc_remove(struct platform_device *pdev)
1078 {
1079         struct ci_hdrc *ci = platform_get_drvdata(pdev);
1080
1081         if (ci->supports_runtime_pm) {
1082                 pm_runtime_get_sync(&pdev->dev);
1083                 pm_runtime_disable(&pdev->dev);
1084                 pm_runtime_put_noidle(&pdev->dev);
1085         }
1086
1087         dbg_remove_files(ci);
1088         ci_extcon_unregister(ci);
1089         ci_role_destroy(ci);
1090         ci_hdrc_enter_lpm(ci, true);
1091         ci_usb_phy_exit(ci);
1092
1093         return 0;
1094 }
1095
1096 #ifdef CONFIG_PM
1097 /* Prepare wakeup by SRP before suspend */
1098 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1099 {
1100         if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1101                                 !hw_read_otgsc(ci, OTGSC_ID)) {
1102                 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1103                                                                 PORTSC_PP);
1104                 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1105                                                                 PORTSC_WKCN);
1106         }
1107 }
1108
1109 /* Handle SRP when wakeup by data pulse */
1110 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1111 {
1112         if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1113                 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1114                 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1115                         ci->fsm.a_srp_det = 1;
1116                         ci->fsm.a_bus_drop = 0;
1117                 } else {
1118                         ci->fsm.id = 1;
1119                 }
1120                 ci_otg_queue_work(ci);
1121         }
1122 }
1123
1124 static void ci_controller_suspend(struct ci_hdrc *ci)
1125 {
1126         disable_irq(ci->irq);
1127         ci_hdrc_enter_lpm(ci, true);
1128         if (ci->platdata->phy_clkgate_delay_us)
1129                 usleep_range(ci->platdata->phy_clkgate_delay_us,
1130                              ci->platdata->phy_clkgate_delay_us + 50);
1131         usb_phy_set_suspend(ci->usb_phy, 1);
1132         ci->in_lpm = true;
1133         enable_irq(ci->irq);
1134 }
1135
1136 static int ci_controller_resume(struct device *dev)
1137 {
1138         struct ci_hdrc *ci = dev_get_drvdata(dev);
1139
1140         dev_dbg(dev, "at %s\n", __func__);
1141
1142         if (!ci->in_lpm) {
1143                 WARN_ON(1);
1144                 return 0;
1145         }
1146
1147         ci_hdrc_enter_lpm(ci, false);
1148         if (ci->usb_phy) {
1149                 usb_phy_set_suspend(ci->usb_phy, 0);
1150                 usb_phy_set_wakeup(ci->usb_phy, false);
1151                 hw_wait_phy_stable();
1152         }
1153
1154         ci->in_lpm = false;
1155         if (ci->wakeup_int) {
1156                 ci->wakeup_int = false;
1157                 pm_runtime_mark_last_busy(ci->dev);
1158                 pm_runtime_put_autosuspend(ci->dev);
1159                 enable_irq(ci->irq);
1160                 if (ci_otg_is_fsm_mode(ci))
1161                         ci_otg_fsm_wakeup_by_srp(ci);
1162         }
1163
1164         return 0;
1165 }
1166
1167 #ifdef CONFIG_PM_SLEEP
1168 static int ci_suspend(struct device *dev)
1169 {
1170         struct ci_hdrc *ci = dev_get_drvdata(dev);
1171
1172         if (ci->wq)
1173                 flush_workqueue(ci->wq);
1174         /*
1175          * Controller needs to be active during suspend, otherwise the core
1176          * may run resume when the parent is at suspend if other driver's
1177          * suspend fails, it occurs before parent's suspend has not started,
1178          * but the core suspend has finished.
1179          */
1180         if (ci->in_lpm)
1181                 pm_runtime_resume(dev);
1182
1183         if (ci->in_lpm) {
1184                 WARN_ON(1);
1185                 return 0;
1186         }
1187
1188         if (device_may_wakeup(dev)) {
1189                 if (ci_otg_is_fsm_mode(ci))
1190                         ci_otg_fsm_suspend_for_srp(ci);
1191
1192                 usb_phy_set_wakeup(ci->usb_phy, true);
1193                 enable_irq_wake(ci->irq);
1194         }
1195
1196         ci_controller_suspend(ci);
1197
1198         return 0;
1199 }
1200
1201 static int ci_resume(struct device *dev)
1202 {
1203         struct ci_hdrc *ci = dev_get_drvdata(dev);
1204         int ret;
1205
1206         if (device_may_wakeup(dev))
1207                 disable_irq_wake(ci->irq);
1208
1209         ret = ci_controller_resume(dev);
1210         if (ret)
1211                 return ret;
1212
1213         if (ci->supports_runtime_pm) {
1214                 pm_runtime_disable(dev);
1215                 pm_runtime_set_active(dev);
1216                 pm_runtime_enable(dev);
1217         }
1218
1219         return ret;
1220 }
1221 #endif /* CONFIG_PM_SLEEP */
1222
1223 static int ci_runtime_suspend(struct device *dev)
1224 {
1225         struct ci_hdrc *ci = dev_get_drvdata(dev);
1226
1227         dev_dbg(dev, "at %s\n", __func__);
1228
1229         if (ci->in_lpm) {
1230                 WARN_ON(1);
1231                 return 0;
1232         }
1233
1234         if (ci_otg_is_fsm_mode(ci))
1235                 ci_otg_fsm_suspend_for_srp(ci);
1236
1237         usb_phy_set_wakeup(ci->usb_phy, true);
1238         ci_controller_suspend(ci);
1239
1240         return 0;
1241 }
1242
1243 static int ci_runtime_resume(struct device *dev)
1244 {
1245         return ci_controller_resume(dev);
1246 }
1247
1248 #endif /* CONFIG_PM */
1249 static const struct dev_pm_ops ci_pm_ops = {
1250         SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1251         SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1252 };
1253
1254 static struct platform_driver ci_hdrc_driver = {
1255         .probe  = ci_hdrc_probe,
1256         .remove = ci_hdrc_remove,
1257         .driver = {
1258                 .name   = "ci_hdrc",
1259                 .pm     = &ci_pm_ops,
1260         },
1261 };
1262
1263 static int __init ci_hdrc_platform_register(void)
1264 {
1265         ci_hdrc_host_driver_init();
1266         return platform_driver_register(&ci_hdrc_driver);
1267 }
1268 module_init(ci_hdrc_platform_register);
1269
1270 static void __exit ci_hdrc_platform_unregister(void)
1271 {
1272         platform_driver_unregister(&ci_hdrc_driver);
1273 }
1274 module_exit(ci_hdrc_platform_unregister);
1275
1276 MODULE_ALIAS("platform:ci_hdrc");
1277 MODULE_LICENSE("GPL v2");
1278 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1279 MODULE_DESCRIPTION("ChipIdea HDRC Driver");