include/linux/nvme.h

   1 /*
   2  * Definitions for the NVM Express interface
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #ifndef _LINUX_NVME_H
  20 #define _LINUX_NVME_H
  21
  22 #include <linux/types.h>
  23
  24 struct nvme_bar {
  25         __u64                   cap;    /* Controller Capabilities */
  26         __u32                   vs;     /* Version */
  27         __u32                   intms;  /* Interrupt Mask Set */
  28         __u32                   intmc;  /* Interrupt Mask Clear */
  29         __u32                   cc;     /* Controller Configuration */
  30         __u32                   rsvd1;  /* Reserved */
  31         __u32                   csts;   /* Controller Status */
  32         __u32                   rsvd2;  /* Reserved */
  33         __u32                   aqa;    /* Admin Queue Attributes */
  34         __u64                   asq;    /* Admin SQ Base Address */
  35         __u64                   acq;    /* Admin CQ Base Address */
  36 };
  37
  38 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
  39
  40 enum {
  41         NVME_CC_ENABLE          = 1 << 0,
  42         NVME_CC_CSS_NVM         = 0 << 4,
  43         NVME_CC_MPS_SHIFT       = 7,
  44         NVME_CC_ARB_RR          = 0 << 11,
  45         NVME_CC_ARB_WRRU        = 1 << 11,
  46         NVME_CC_ARB_VS          = 7 << 11,
  47         NVME_CC_SHN_NONE        = 0 << 14,
  48         NVME_CC_SHN_NORMAL      = 1 << 14,
  49         NVME_CC_SHN_ABRUPT      = 2 << 14,
  50         NVME_CC_IOSQES          = 6 << 16,
  51         NVME_CC_IOCQES          = 4 << 20,
  52         NVME_CSTS_RDY           = 1 << 0,
  53         NVME_CSTS_CFS           = 1 << 1,
  54         NVME_CSTS_SHST_NORMAL   = 0 << 2,
  55         NVME_CSTS_SHST_OCCUR    = 1 << 2,
  56         NVME_CSTS_SHST_CMPLT    = 2 << 2,
  57 };
  58
  59 #define NVME_VS(major, minor)   (major << 16 | minor)
  60
  61 struct nvme_id_ctrl {
  62         __le16                  vid;
  63         __le16                  ssvid;
  64         char                    sn[20];
  65         char                    mn[40];
  66         char                    fr[8];
  67         __le32                  nn;
  68         __u8                    rab;
  69         __u8                    rsvd77[178];
  70         __le16                  oacs;
  71         __u8                    acl;
  72         __u8                    aerl;
  73         __u8                    frmw;
  74         __u8                    lpa;
  75         __u8                    elpe;
  76         __u8                    npss;
  77         __u8                    rsvd264[248];
  78         __le64                  psd[32];
  79         __le16                  oncs;
  80         __le16                  fuses;
  81         __u8                    fna;
  82         __u8                    vwc;
  83         __le16                  awun;
  84         __le16                  awupf;
  85         __u8                    rsvd778[246];
  86         __u8                    cmdset[2048];
  87         __u8                    vs[1024];
  88 };
  89
  90 struct nvme_lbaf {
  91         __le16                  ms;
  92         __u8                    ds;
  93         __u8                    rp;
  94 };
  95
  96 struct nvme_id_ns {
  97         __le64                  nsze;
  98         __le64                  ncap;
  99         __le64                  nuse;
 100         __u8                    nsfeat;
 101         __u8                    nlbaf;
 102         __u8                    flbas;
 103         __u8                    mc;
 104         __u8                    dpc;
 105         __u8                    dps;
 106         __u8                    rsvd30[98];
 107         struct nvme_lbaf        lbaf[16];
 108         __u8                    rsvd192[192];
 109         __u8                    vs[3712];
 110 };
 111
 112 enum {
 113         NVME_NS_FEAT_THIN       = 1 << 0,
 114         NVME_LBAF_RP_BEST       = 0,
 115         NVME_LBAF_RP_BETTER     = 1,
 116         NVME_LBAF_RP_GOOD       = 2,
 117         NVME_LBAF_RP_DEGRADED   = 3,
 118 };
 119
 120 struct nvme_lba_range_type {
 121         __u8                    type;
 122         __u8                    attributes;
 123         __u8                    rsvd2[14];
 124         __u64                   slba;
 125         __u64                   nlb;
 126         __u8                    guid[16];
 127         __u8                    rsvd48[16];
 128 };
 129
 130 enum {
 131         NVME_LBART_TYPE_FS      = 0x01,
 132         NVME_LBART_TYPE_RAID    = 0x02,
 133         NVME_LBART_TYPE_CACHE   = 0x03,
 134         NVME_LBART_TYPE_SWAP    = 0x04,
 135
 136         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 137         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 138 };
 139
 140 /* I/O commands */
 141
 142 enum nvme_opcode {
 143         nvme_cmd_flush          = 0x00,
 144         nvme_cmd_write          = 0x01,
 145         nvme_cmd_read           = 0x02,
 146         nvme_cmd_write_uncor    = 0x04,
 147         nvme_cmd_compare        = 0x05,
 148         nvme_cmd_dsm            = 0x09,
 149 };
 150
 151 struct nvme_common_command {
 152         __u8                    opcode;
 153         __u8                    flags;
 154         __u16                   command_id;
 155         __le32                  nsid;
 156         __u64                   rsvd2;
 157         __le64                  metadata;
 158         __le64                  prp1;
 159         __le64                  prp2;
 160         __u32                   rsvd10[6];
 161 };
 162
 163 struct nvme_rw_command {
 164         __u8                    opcode;
 165         __u8                    flags;
 166         __u16                   command_id;
 167         __le32                  nsid;
 168         __u64                   rsvd2;
 169         __le64                  metadata;
 170         __le64                  prp1;
 171         __le64                  prp2;
 172         __le64                  slba;
 173         __le16                  length;
 174         __le16                  control;
 175         __le32                  dsmgmt;
 176         __le32                  reftag;
 177         __le16                  apptag;
 178         __le16                  appmask;
 179 };
 180
 181 enum {
 182         NVME_RW_LR                      = 1 << 15,
 183         NVME_RW_FUA                     = 1 << 14,
 184         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 185         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 186         NVME_RW_DSM_FREQ_RARE           = 2,
 187         NVME_RW_DSM_FREQ_READS          = 3,
 188         NVME_RW_DSM_FREQ_WRITES         = 4,
 189         NVME_RW_DSM_FREQ_RW             = 5,
 190         NVME_RW_DSM_FREQ_ONCE           = 6,
 191         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 192         NVME_RW_DSM_FREQ_TEMP           = 8,
 193         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 194         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 195         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 196         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 197         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 198         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 199 };
 200
 201 /* Admin commands */
 202
 203 enum nvme_admin_opcode {
 204         nvme_admin_delete_sq            = 0x00,
 205         nvme_admin_create_sq            = 0x01,
 206         nvme_admin_get_log_page         = 0x02,
 207         nvme_admin_delete_cq            = 0x04,
 208         nvme_admin_create_cq            = 0x05,
 209         nvme_admin_identify             = 0x06,
 210         nvme_admin_abort_cmd            = 0x08,
 211         nvme_admin_set_features         = 0x09,
 212         nvme_admin_get_features         = 0x0a,
 213         nvme_admin_async_event          = 0x0c,
 214         nvme_admin_activate_fw          = 0x10,
 215         nvme_admin_download_fw          = 0x11,
 216         nvme_admin_format_nvm           = 0x80,
 217         nvme_admin_security_send        = 0x81,
 218         nvme_admin_security_recv        = 0x82,
 219 };
 220
 221 enum {
 222         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 223         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 224         NVME_SQ_PRIO_URGENT     = (0 << 1),
 225         NVME_SQ_PRIO_HIGH       = (1 << 1),
 226         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 227         NVME_SQ_PRIO_LOW        = (3 << 1),
 228         NVME_FEAT_ARBITRATION   = 0x01,
 229         NVME_FEAT_POWER_MGMT    = 0x02,
 230         NVME_FEAT_LBA_RANGE     = 0x03,
 231         NVME_FEAT_TEMP_THRESH   = 0x04,
 232         NVME_FEAT_ERR_RECOVERY  = 0x05,
 233         NVME_FEAT_VOLATILE_WC   = 0x06,
 234         NVME_FEAT_NUM_QUEUES    = 0x07,
 235         NVME_FEAT_IRQ_COALESCE  = 0x08,
 236         NVME_FEAT_IRQ_CONFIG    = 0x09,
 237         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 238         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 239         NVME_FEAT_SW_PROGRESS   = 0x0c,
 240 };
 241
 242 struct nvme_identify {
 243         __u8                    opcode;
 244         __u8                    flags;
 245         __u16                   command_id;
 246         __le32                  nsid;
 247         __u64                   rsvd2[2];
 248         __le64                  prp1;
 249         __le64                  prp2;
 250         __le32                  cns;
 251         __u32                   rsvd11[5];
 252 };
 253
 254 struct nvme_features {
 255         __u8                    opcode;
 256         __u8                    flags;
 257         __u16                   command_id;
 258         __le32                  nsid;
 259         __u64                   rsvd2[2];
 260         __le64                  prp1;
 261         __le64                  prp2;
 262         __le32                  fid;
 263         __le32                  dword11;
 264         __u32                   rsvd12[4];
 265 };
 266
 267 struct nvme_create_cq {
 268         __u8                    opcode;
 269         __u8                    flags;
 270         __u16                   command_id;
 271         __u32                   rsvd1[5];
 272         __le64                  prp1;
 273         __u64                   rsvd8;
 274         __le16                  cqid;
 275         __le16                  qsize;
 276         __le16                  cq_flags;
 277         __le16                  irq_vector;
 278         __u32                   rsvd12[4];
 279 };
 280
 281 struct nvme_create_sq {
 282         __u8                    opcode;
 283         __u8                    flags;
 284         __u16                   command_id;
 285         __u32                   rsvd1[5];
 286         __le64                  prp1;
 287         __u64                   rsvd8;
 288         __le16                  sqid;
 289         __le16                  qsize;
 290         __le16                  sq_flags;
 291         __le16                  cqid;
 292         __u32                   rsvd12[4];
 293 };
 294
 295 struct nvme_delete_queue {
 296         __u8                    opcode;
 297         __u8                    flags;
 298         __u16                   command_id;
 299         __u32                   rsvd1[9];
 300         __le16                  qid;
 301         __u16                   rsvd10;
 302         __u32                   rsvd11[5];
 303 };
 304
 305 struct nvme_download_firmware {
 306         __u8                    opcode;
 307         __u8                    flags;
 308         __u16                   command_id;
 309         __u32                   rsvd1[5];
 310         __le64                  prp1;
 311         __le64                  prp2;
 312         __le32                  numd;
 313         __le32                  offset;
 314         __u32                   rsvd12[4];
 315 };
 316
 317 struct nvme_command {
 318         union {
 319                 struct nvme_common_command common;
 320                 struct nvme_rw_command rw;
 321                 struct nvme_identify identify;
 322                 struct nvme_features features;
 323                 struct nvme_create_cq create_cq;
 324                 struct nvme_create_sq create_sq;
 325                 struct nvme_delete_queue delete_queue;
 326                 struct nvme_download_firmware dlfw;
 327         };
 328 };
 329
 330 enum {
 331         NVME_SC_SUCCESS                 = 0x0,
 332         NVME_SC_INVALID_OPCODE          = 0x1,
 333         NVME_SC_INVALID_FIELD           = 0x2,
 334         NVME_SC_CMDID_CONFLICT          = 0x3,
 335         NVME_SC_DATA_XFER_ERROR         = 0x4,
 336         NVME_SC_POWER_LOSS              = 0x5,
 337         NVME_SC_INTERNAL                = 0x6,
 338         NVME_SC_ABORT_REQ               = 0x7,
 339         NVME_SC_ABORT_QUEUE             = 0x8,
 340         NVME_SC_FUSED_FAIL              = 0x9,
 341         NVME_SC_FUSED_MISSING           = 0xa,
 342         NVME_SC_INVALID_NS              = 0xb,
 343         NVME_SC_LBA_RANGE               = 0x80,
 344         NVME_SC_CAP_EXCEEDED            = 0x81,
 345         NVME_SC_NS_NOT_READY            = 0x82,
 346         NVME_SC_CQ_INVALID              = 0x100,
 347         NVME_SC_QID_INVALID             = 0x101,
 348         NVME_SC_QUEUE_SIZE              = 0x102,
 349         NVME_SC_ABORT_LIMIT             = 0x103,
 350         NVME_SC_ABORT_MISSING           = 0x104,
 351         NVME_SC_ASYNC_LIMIT             = 0x105,
 352         NVME_SC_FIRMWARE_SLOT           = 0x106,
 353         NVME_SC_FIRMWARE_IMAGE          = 0x107,
 354         NVME_SC_INVALID_VECTOR          = 0x108,
 355         NVME_SC_INVALID_LOG_PAGE        = 0x109,
 356         NVME_SC_INVALID_FORMAT          = 0x10a,
 357         NVME_SC_BAD_ATTRIBUTES          = 0x180,
 358         NVME_SC_WRITE_FAULT             = 0x280,
 359         NVME_SC_READ_ERROR              = 0x281,
 360         NVME_SC_GUARD_CHECK             = 0x282,
 361         NVME_SC_APPTAG_CHECK            = 0x283,
 362         NVME_SC_REFTAG_CHECK            = 0x284,
 363         NVME_SC_COMPARE_FAILED          = 0x285,
 364         NVME_SC_ACCESS_DENIED           = 0x286,
 365 };
 366
 367 struct nvme_completion {
 368         __le32  result;         /* Used by admin commands to return data */
 369         __u32   rsvd;
 370         __le16  sq_head;        /* how much of this queue may be reclaimed */
 371         __le16  sq_id;          /* submission queue that generated this entry */
 372         __u16   command_id;     /* of the command which completed */
 373         __le16  status;         /* did the command fail, and if so, why? */
 374 };
 375
 376 struct nvme_user_io {
 377         __u8    opcode;
 378         __u8    flags;
 379         __u16   control;
 380         __u16   nblocks;
 381         __u16   rsvd;
 382         __u64   metadata;
 383         __u64   addr;
 384         __u64   slba;
 385         __u32   dsmgmt;
 386         __u32   reftag;
 387         __u16   apptag;
 388         __u16   appmask;
 389 };
 390
 391 struct nvme_dlfw {
 392         __u64   addr;
 393         __u32   length; /* In dwords */
 394         __u32   offset; /* In dwords */
 395 };
 396
 397 #define NVME_IOCTL_IDENTIFY_NS  _IOW('N', 0x40, struct nvme_id_ns)
 398 #define NVME_IOCTL_IDENTIFY_CTRL _IOW('N', 0x41, struct nvme_id_ctrl)
 399 #define NVME_IOCTL_GET_RANGE_TYPE _IOW('N', 0x42, struct nvme_lba_range_type)
 400 #define NVME_IOCTL_SUBMIT_IO    _IOW('N', 0x43, struct nvme_user_io)
 401 #define NVME_IOCTL_DOWNLOAD_FW  _IOW('N', 0x44, struct nvme_dlfw)
 402 #define NVME_IOCTL_ACTIVATE_FW  _IO('N', 0x45)
 403
 404 #endif /* _LINUX_NVME_H */