sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #endif
  58 #include <sound/core.h>
  59 #include <sound/initval.h>
  60 #include <sound/hdaudio.h>
  61 #include <sound/hda_i915.h>
  62 #include <linux/vgaarb.h>
  63 #include <linux/vga_switcheroo.h>
  64 #include <linux/firmware.h>
  65 #include "hda_codec.h"
  66 #include "hda_controller.h"
  67 #include "hda_intel.h"
  68
  69 #define CREATE_TRACE_POINTS
  70 #include "hda_intel_trace.h"
  71
  72 /* position fix mode */
  73 enum {
  74         POS_FIX_AUTO,
  75         POS_FIX_LPIB,
  76         POS_FIX_POSBUF,
  77         POS_FIX_VIACOMBO,
  78         POS_FIX_COMBO,
  79 };
  80
  81 /* Defines for ATI HD Audio support in SB450 south bridge */
  82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  84
  85 /* Defines for Nvidia HDA support */
  86 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  87 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  88 #define NVIDIA_HDA_ISTRM_COH          0x4d
  89 #define NVIDIA_HDA_OSTRM_COH          0x4c
  90 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  91
  92 /* Defines for Intel SCH HDA snoop control */
  93 #define INTEL_SCH_HDA_DEVC      0x78
  94 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  95
  96 /* Define IN stream 0 FIFO size offset in VIA controller */
  97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  98 /* Define VIA HD Audio Device ID*/
  99 #define VIA_HDAC_DEVICE_ID              0x3288
 100
 101 /* max number of SDs */
 102 /* ICH, ATI and VIA have 4 playback and 4 capture */
 103 #define ICH6_NUM_CAPTURE        4
 104 #define ICH6_NUM_PLAYBACK       4
 105
 106 /* ULI has 6 playback and 5 capture */
 107 #define ULI_NUM_CAPTURE         5
 108 #define ULI_NUM_PLAYBACK        6
 109
 110 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 111 #define ATIHDMI_NUM_CAPTURE     0
 112 #define ATIHDMI_NUM_PLAYBACK    8
 113
 114 /* TERA has 4 playback and 3 capture */
 115 #define TERA_NUM_CAPTURE        3
 116 #define TERA_NUM_PLAYBACK       4
 117
 118
 119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 122 static char *model[SNDRV_CARDS];
 123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 126 static int probe_only[SNDRV_CARDS];
 127 static int jackpoll_ms[SNDRV_CARDS];
 128 static bool single_cmd;
 129 static int enable_msi = -1;
 130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 131 static char *patch[SNDRV_CARDS];
 132 #endif
 133 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 135                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 136 #endif
 137
 138 module_param_array(index, int, NULL, 0444);
 139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 140 module_param_array(id, charp, NULL, 0444);
 141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 142 module_param_array(enable, bool, NULL, 0444);
 143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 144 module_param_array(model, charp, NULL, 0444);
 145 MODULE_PARM_DESC(model, "Use the given board model.");
 146 module_param_array(position_fix, int, NULL, 0444);
 147 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 148                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 149 module_param_array(bdl_pos_adj, int, NULL, 0644);
 150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 151 module_param_array(probe_mask, int, NULL, 0444);
 152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 153 module_param_array(probe_only, int, NULL, 0444);
 154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 155 module_param_array(jackpoll_ms, int, NULL, 0444);
 156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 157 module_param(single_cmd, bool, 0444);
 158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 159                  "(for debugging only).");
 160 module_param(enable_msi, bint, 0444);
 161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 162 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 163 module_param_array(patch, charp, NULL, 0444);
 164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 165 #endif
 166 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 167 module_param_array(beep_mode, bool, NULL, 0444);
 168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 169                             "(0=off, 1=on) (default=1).");
 170 #endif
 171
 172 #ifdef CONFIG_PM
 173 static int param_set_xint(const char *val, const struct kernel_param *kp);
 174 static const struct kernel_param_ops param_ops_xint = {
 175         .set = param_set_xint,
 176         .get = param_get_int,
 177 };
 178 #define param_check_xint param_check_int
 179
 180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 181 module_param(power_save, xint, 0644);
 182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 183                  "(in second, 0 = disable).");
 184
 185 /* reset the HD-audio controller in power save mode.
 186  * this may give more power-saving, but will take longer time to
 187  * wake up.
 188  */
 189 static bool power_save_controller = 1;
 190 module_param(power_save_controller, bool, 0644);
 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 192 #else
 193 #define power_save      0
 194 #endif /* CONFIG_PM */
 195
 196 static int align_buffer_size = -1;
 197 module_param(align_buffer_size, bint, 0644);
 198 MODULE_PARM_DESC(align_buffer_size,
 199                 "Force buffer and period sizes to be multiple of 128 bytes.");
 200
 201 #ifdef CONFIG_X86
 202 static int hda_snoop = -1;
 203 module_param_named(snoop, hda_snoop, bint, 0444);
 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 205 #else
 206 #define hda_snoop               true
 207 #endif
 208
 209
 210 MODULE_LICENSE("GPL");
 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 212                          "{Intel, ICH6M},"
 213                          "{Intel, ICH7},"
 214                          "{Intel, ESB2},"
 215                          "{Intel, ICH8},"
 216                          "{Intel, ICH9},"
 217                          "{Intel, ICH10},"
 218                          "{Intel, PCH},"
 219                          "{Intel, CPT},"
 220                          "{Intel, PPT},"
 221                          "{Intel, LPT},"
 222                          "{Intel, LPT_LP},"
 223                          "{Intel, WPT_LP},"
 224                          "{Intel, SPT},"
 225                          "{Intel, SPT_LP},"
 226                          "{Intel, HPT},"
 227                          "{Intel, PBG},"
 228                          "{Intel, SCH},"
 229                          "{ATI, SB450},"
 230                          "{ATI, SB600},"
 231                          "{ATI, RS600},"
 232                          "{ATI, RS690},"
 233                          "{ATI, RS780},"
 234                          "{ATI, R600},"
 235                          "{ATI, RV630},"
 236                          "{ATI, RV610},"
 237                          "{ATI, RV670},"
 238                          "{ATI, RV635},"
 239                          "{ATI, RV620},"
 240                          "{ATI, RV770},"
 241                          "{VIA, VT8251},"
 242                          "{VIA, VT8237A},"
 243                          "{SiS, SIS966},"
 244                          "{ULI, M5461}}");
 245 MODULE_DESCRIPTION("Intel HDA driver");
 246
 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 249 #define SUPPORT_VGA_SWITCHEROO
 250 #endif
 251 #endif
 252
 253
 254 /*
 255  */
 256
 257 /* driver types */
 258 enum {
 259         AZX_DRIVER_ICH,
 260         AZX_DRIVER_PCH,
 261         AZX_DRIVER_SCH,
 262         AZX_DRIVER_HDMI,
 263         AZX_DRIVER_ATI,
 264         AZX_DRIVER_ATIHDMI,
 265         AZX_DRIVER_ATIHDMI_NS,
 266         AZX_DRIVER_VIA,
 267         AZX_DRIVER_SIS,
 268         AZX_DRIVER_ULI,
 269         AZX_DRIVER_NVIDIA,
 270         AZX_DRIVER_TERA,
 271         AZX_DRIVER_CTX,
 272         AZX_DRIVER_CTHDA,
 273         AZX_DRIVER_CMEDIA,
 274         AZX_DRIVER_GENERIC,
 275         AZX_NUM_DRIVERS, /* keep this as last entry */
 276 };
 277
 278 #define azx_get_snoop_type(chip) \
 279         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 281
 282 /* quirks for old Intel chipsets */
 283 #define AZX_DCAPS_INTEL_ICH \
 284         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 285
 286 /* quirks for Intel PCH */
 287 #define AZX_DCAPS_INTEL_PCH_NOPM \
 288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 289          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
 290
 291 #define AZX_DCAPS_INTEL_PCH \
 292         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 293
 294 #define AZX_DCAPS_INTEL_HASWELL \
 295         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 296          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 297          AZX_DCAPS_SNOOP_TYPE(SCH))
 298
 299 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 300 #define AZX_DCAPS_INTEL_BROADWELL \
 301         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 302          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 303          AZX_DCAPS_SNOOP_TYPE(SCH))
 304
 305 #define AZX_DCAPS_INTEL_BAYTRAIL \
 306         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 307
 308 #define AZX_DCAPS_INTEL_BRASWELL \
 309         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 310
 311 #define AZX_DCAPS_INTEL_SKYLAKE \
 312         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 313          AZX_DCAPS_I915_POWERWELL)
 314
 315 /* quirks for ATI SB / AMD Hudson */
 316 #define AZX_DCAPS_PRESET_ATI_SB \
 317         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 318          AZX_DCAPS_SNOOP_TYPE(ATI))
 319
 320 /* quirks for ATI/AMD HDMI */
 321 #define AZX_DCAPS_PRESET_ATI_HDMI \
 322         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 323          AZX_DCAPS_NO_MSI64)
 324
 325 /* quirks for ATI HDMI with snoop off */
 326 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 327         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 328
 329 /* quirks for Nvidia */
 330 #define AZX_DCAPS_PRESET_NVIDIA \
 331         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 332          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 333          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 334
 335 #define AZX_DCAPS_PRESET_CTHDA \
 336         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 337          AZX_DCAPS_NO_64BIT |\
 338          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 339
 340 /*
 341  * VGA-switcher support
 342  */
 343 #ifdef SUPPORT_VGA_SWITCHEROO
 344 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 345 #else
 346 #define use_vga_switcheroo(chip)        0
 347 #endif
 348
 349 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 350                                         ((pci)->device == 0x0c0c) || \
 351                                         ((pci)->device == 0x0d0c) || \
 352                                         ((pci)->device == 0x160c))
 353
 354 static char *driver_short_names[] = {
 355         [AZX_DRIVER_ICH] = "HDA Intel",
 356         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 357         [AZX_DRIVER_SCH] = "HDA Intel MID",
 358         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 359         [AZX_DRIVER_ATI] = "HDA ATI SB",
 360         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 361         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 362         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 363         [AZX_DRIVER_SIS] = "HDA SIS966",
 364         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 365         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 366         [AZX_DRIVER_TERA] = "HDA Teradici",
 367         [AZX_DRIVER_CTX] = "HDA Creative",
 368         [AZX_DRIVER_CTHDA] = "HDA Creative",
 369         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 370         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 371 };
 372
 373 #ifdef CONFIG_X86
 374 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 375 {
 376         int pages;
 377
 378         if (azx_snoop(chip))
 379                 return;
 380         if (!dmab || !dmab->area || !dmab->bytes)
 381                 return;
 382
 383 #ifdef CONFIG_SND_DMA_SGBUF
 384         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 385                 struct snd_sg_buf *sgbuf = dmab->private_data;
 386                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 387                         return; /* deal with only CORB/RIRB buffers */
 388                 if (on)
 389                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 390                 else
 391                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 392                 return;
 393         }
 394 #endif
 395
 396         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 397         if (on)
 398                 set_memory_wc((unsigned long)dmab->area, pages);
 399         else
 400                 set_memory_wb((unsigned long)dmab->area, pages);
 401 }
 402
 403 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 404                                  bool on)
 405 {
 406         __mark_pages_wc(chip, buf, on);
 407 }
 408 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 409                                    struct snd_pcm_substream *substream, bool on)
 410 {
 411         if (azx_dev->wc_marked != on) {
 412                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 413                 azx_dev->wc_marked = on;
 414         }
 415 }
 416 #else
 417 /* NOP for other archs */
 418 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 419                                  bool on)
 420 {
 421 }
 422 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 423                                    struct snd_pcm_substream *substream, bool on)
 424 {
 425 }
 426 #endif
 427
 428 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 429
 430 /*
 431  * initialize the PCI registers
 432  */
 433 /* update bits in a PCI register byte */
 434 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 435                             unsigned char mask, unsigned char val)
 436 {
 437         unsigned char data;
 438
 439         pci_read_config_byte(pci, reg, &data);
 440         data &= ~mask;
 441         data |= (val & mask);
 442         pci_write_config_byte(pci, reg, data);
 443 }
 444
 445 static void azx_init_pci(struct azx *chip)
 446 {
 447         int snoop_type = azx_get_snoop_type(chip);
 448
 449         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 450          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 451          * Ensuring these bits are 0 clears playback static on some HD Audio
 452          * codecs.
 453          * The PCI register TCSEL is defined in the Intel manuals.
 454          */
 455         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 456                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 457                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 458         }
 459
 460         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 461          * we need to enable snoop.
 462          */
 463         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 464                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 465                         azx_snoop(chip));
 466                 update_pci_byte(chip->pci,
 467                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 468                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 469         }
 470
 471         /* For NVIDIA HDA, enable snoop */
 472         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 473                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 474                         azx_snoop(chip));
 475                 update_pci_byte(chip->pci,
 476                                 NVIDIA_HDA_TRANSREG_ADDR,
 477                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 478                 update_pci_byte(chip->pci,
 479                                 NVIDIA_HDA_ISTRM_COH,
 480                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 481                 update_pci_byte(chip->pci,
 482                                 NVIDIA_HDA_OSTRM_COH,
 483                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 484         }
 485
 486         /* Enable SCH/PCH snoop if needed */
 487         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 488                 unsigned short snoop;
 489                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 490                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 491                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 492                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 493                         if (!azx_snoop(chip))
 494                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 495                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 496                         pci_read_config_word(chip->pci,
 497                                 INTEL_SCH_HDA_DEVC, &snoop);
 498                 }
 499                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 500                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 501                         "Disabled" : "Enabled");
 502         }
 503 }
 504
 505 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 506 {
 507         struct hdac_bus *bus = azx_bus(chip);
 508
 509         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 510                 snd_hdac_set_codec_wakeup(bus, true);
 511         azx_init_chip(chip, full_reset);
 512         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 513                 snd_hdac_set_codec_wakeup(bus, false);
 514 }
 515
 516 /* calculate runtime delay from LPIB */
 517 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 518                                    unsigned int pos)
 519 {
 520         struct snd_pcm_substream *substream = azx_dev->core.substream;
 521         int stream = substream->stream;
 522         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 523         int delay;
 524
 525         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 526                 delay = pos - lpib_pos;
 527         else
 528                 delay = lpib_pos - pos;
 529         if (delay < 0) {
 530                 if (delay >= azx_dev->core.delay_negative_threshold)
 531                         delay = 0;
 532                 else
 533                         delay += azx_dev->core.bufsize;
 534         }
 535
 536         if (delay >= azx_dev->core.period_bytes) {
 537                 dev_info(chip->card->dev,
 538                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 539                          delay, azx_dev->core.period_bytes);
 540                 delay = 0;
 541                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 542                 chip->get_delay[stream] = NULL;
 543         }
 544
 545         return bytes_to_frames(substream->runtime, delay);
 546 }
 547
 548 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 549
 550 /* called from IRQ */
 551 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 552 {
 553         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 554         int ok;
 555
 556         ok = azx_position_ok(chip, azx_dev);
 557         if (ok == 1) {
 558                 azx_dev->irq_pending = 0;
 559                 return ok;
 560         } else if (ok == 0) {
 561                 /* bogus IRQ, process it later */
 562                 azx_dev->irq_pending = 1;
 563                 schedule_work(&hda->irq_pending_work);
 564         }
 565         return 0;
 566 }
 567
 568 /* Enable/disable i915 display power for the link */
 569 static int azx_intel_link_power(struct azx *chip, bool enable)
 570 {
 571         struct hdac_bus *bus = azx_bus(chip);
 572
 573         return snd_hdac_display_power(bus, enable);
 574 }
 575
 576 /*
 577  * Check whether the current DMA position is acceptable for updating
 578  * periods.  Returns non-zero if it's OK.
 579  *
 580  * Many HD-audio controllers appear pretty inaccurate about
 581  * the update-IRQ timing.  The IRQ is issued before actually the
 582  * data is processed.  So, we need to process it afterwords in a
 583  * workqueue.
 584  */
 585 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 586 {
 587         struct snd_pcm_substream *substream = azx_dev->core.substream;
 588         int stream = substream->stream;
 589         u32 wallclk;
 590         unsigned int pos;
 591
 592         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 593         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 594                 return -1;      /* bogus (too early) interrupt */
 595
 596         if (chip->get_position[stream])
 597                 pos = chip->get_position[stream](chip, azx_dev);
 598         else { /* use the position buffer as default */
 599                 pos = azx_get_pos_posbuf(chip, azx_dev);
 600                 if (!pos || pos == (u32)-1) {
 601                         dev_info(chip->card->dev,
 602                                  "Invalid position buffer, using LPIB read method instead.\n");
 603                         chip->get_position[stream] = azx_get_pos_lpib;
 604                         if (chip->get_position[0] == azx_get_pos_lpib &&
 605                             chip->get_position[1] == azx_get_pos_lpib)
 606                                 azx_bus(chip)->use_posbuf = false;
 607                         pos = azx_get_pos_lpib(chip, azx_dev);
 608                         chip->get_delay[stream] = NULL;
 609                 } else {
 610                         chip->get_position[stream] = azx_get_pos_posbuf;
 611                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 612                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 613                 }
 614         }
 615
 616         if (pos >= azx_dev->core.bufsize)
 617                 pos = 0;
 618
 619         if (WARN_ONCE(!azx_dev->core.period_bytes,
 620                       "hda-intel: zero azx_dev->period_bytes"))
 621                 return -1; /* this shouldn't happen! */
 622         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 623             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 624                 /* NG - it's below the first next period boundary */
 625                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
 626         azx_dev->core.start_wallclk += wallclk;
 627         return 1; /* OK, it's fine */
 628 }
 629
 630 /*
 631  * The work for pending PCM period updates.
 632  */
 633 static void azx_irq_pending_work(struct work_struct *work)
 634 {
 635         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 636         struct azx *chip = &hda->chip;
 637         struct hdac_bus *bus = azx_bus(chip);
 638         struct hdac_stream *s;
 639         int pending, ok;
 640
 641         if (!hda->irq_pending_warned) {
 642                 dev_info(chip->card->dev,
 643                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 644                          chip->card->number);
 645                 hda->irq_pending_warned = 1;
 646         }
 647
 648         for (;;) {
 649                 pending = 0;
 650                 spin_lock_irq(&bus->reg_lock);
 651                 list_for_each_entry(s, &bus->stream_list, list) {
 652                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 653                         if (!azx_dev->irq_pending ||
 654                             !s->substream ||
 655                             !s->running)
 656                                 continue;
 657                         ok = azx_position_ok(chip, azx_dev);
 658                         if (ok > 0) {
 659                                 azx_dev->irq_pending = 0;
 660                                 spin_unlock(&bus->reg_lock);
 661                                 snd_pcm_period_elapsed(s->substream);
 662                                 spin_lock(&bus->reg_lock);
 663                         } else if (ok < 0) {
 664                                 pending = 0;    /* too early */
 665                         } else
 666                                 pending++;
 667                 }
 668                 spin_unlock_irq(&bus->reg_lock);
 669                 if (!pending)
 670                         return;
 671                 msleep(1);
 672         }
 673 }
 674
 675 /* clear irq_pending flags and assure no on-going workq */
 676 static void azx_clear_irq_pending(struct azx *chip)
 677 {
 678         struct hdac_bus *bus = azx_bus(chip);
 679         struct hdac_stream *s;
 680
 681         spin_lock_irq(&bus->reg_lock);
 682         list_for_each_entry(s, &bus->stream_list, list) {
 683                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 684                 azx_dev->irq_pending = 0;
 685         }
 686         spin_unlock_irq(&bus->reg_lock);
 687 }
 688
 689 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 690 {
 691         struct hdac_bus *bus = azx_bus(chip);
 692
 693         if (request_irq(chip->pci->irq, azx_interrupt,
 694                         chip->msi ? 0 : IRQF_SHARED,
 695                         KBUILD_MODNAME, chip)) {
 696                 dev_err(chip->card->dev,
 697                         "unable to grab IRQ %d, disabling device\n",
 698                         chip->pci->irq);
 699                 if (do_disconnect)
 700                         snd_card_disconnect(chip->card);
 701                 return -1;
 702         }
 703         bus->irq = chip->pci->irq;
 704         pci_intx(chip->pci, !chip->msi);
 705         return 0;
 706 }
 707
 708 /* get the current DMA position with correction on VIA chips */
 709 static unsigned int azx_via_get_position(struct azx *chip,
 710                                          struct azx_dev *azx_dev)
 711 {
 712         unsigned int link_pos, mini_pos, bound_pos;
 713         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 714         unsigned int fifo_size;
 715
 716         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 717         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 718                 /* Playback, no problem using link position */
 719                 return link_pos;
 720         }
 721
 722         /* Capture */
 723         /* For new chipset,
 724          * use mod to get the DMA position just like old chipset
 725          */
 726         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 727         mod_dma_pos %= azx_dev->core.period_bytes;
 728
 729         /* azx_dev->fifo_size can't get FIFO size of in stream.
 730          * Get from base address + offset.
 731          */
 732         fifo_size = readw(azx_bus(chip)->remap_addr +
 733                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 734
 735         if (azx_dev->insufficient) {
 736                 /* Link position never gather than FIFO size */
 737                 if (link_pos <= fifo_size)
 738                         return 0;
 739
 740                 azx_dev->insufficient = 0;
 741         }
 742
 743         if (link_pos <= fifo_size)
 744                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 745         else
 746                 mini_pos = link_pos - fifo_size;
 747
 748         /* Find nearest previous boudary */
 749         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 750         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 751         if (mod_link_pos >= fifo_size)
 752                 bound_pos = link_pos - mod_link_pos;
 753         else if (mod_dma_pos >= mod_mini_pos)
 754                 bound_pos = mini_pos - mod_mini_pos;
 755         else {
 756                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 757                 if (bound_pos >= azx_dev->core.bufsize)
 758                         bound_pos = 0;
 759         }
 760
 761         /* Calculate real DMA position we want */
 762         return bound_pos + mod_dma_pos;
 763 }
 764
 765 #ifdef CONFIG_PM
 766 static DEFINE_MUTEX(card_list_lock);
 767 static LIST_HEAD(card_list);
 768
 769 static void azx_add_card_list(struct azx *chip)
 770 {
 771         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 772         mutex_lock(&card_list_lock);
 773         list_add(&hda->list, &card_list);
 774         mutex_unlock(&card_list_lock);
 775 }
 776
 777 static void azx_del_card_list(struct azx *chip)
 778 {
 779         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 780         mutex_lock(&card_list_lock);
 781         list_del_init(&hda->list);
 782         mutex_unlock(&card_list_lock);
 783 }
 784
 785 /* trigger power-save check at writing parameter */
 786 static int param_set_xint(const char *val, const struct kernel_param *kp)
 787 {
 788         struct hda_intel *hda;
 789         struct azx *chip;
 790         int prev = power_save;
 791         int ret = param_set_int(val, kp);
 792
 793         if (ret || prev == power_save)
 794                 return ret;
 795
 796         mutex_lock(&card_list_lock);
 797         list_for_each_entry(hda, &card_list, list) {
 798                 chip = &hda->chip;
 799                 if (!hda->probe_continued || chip->disabled)
 800                         continue;
 801                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 802         }
 803         mutex_unlock(&card_list_lock);
 804         return 0;
 805 }
 806 #else
 807 #define azx_add_card_list(chip) /* NOP */
 808 #define azx_del_card_list(chip) /* NOP */
 809 #endif /* CONFIG_PM */
 810
 811 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
 812  * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
 813  * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
 814  * BCLK = CDCLK * M / N
 815  * The values will be lost when the display power well is disabled and need to
 816  * be restored to avoid abnormal playback speed.
 817  */
 818 static void haswell_set_bclk(struct hda_intel *hda)
 819 {
 820         struct azx *chip = &hda->chip;
 821         int cdclk_freq;
 822         unsigned int bclk_m, bclk_n;
 823
 824         if (!hda->need_i915_power)
 825                 return;
 826
 827         cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
 828         switch (cdclk_freq) {
 829         case 337500:
 830                 bclk_m = 16;
 831                 bclk_n = 225;
 832                 break;
 833
 834         case 450000:
 835         default: /* default CDCLK 450MHz */
 836                 bclk_m = 4;
 837                 bclk_n = 75;
 838                 break;
 839
 840         case 540000:
 841                 bclk_m = 4;
 842                 bclk_n = 90;
 843                 break;
 844
 845         case 675000:
 846                 bclk_m = 8;
 847                 bclk_n = 225;
 848                 break;
 849         }
 850
 851         azx_writew(chip, HSW_EM4, bclk_m);
 852         azx_writew(chip, HSW_EM5, bclk_n);
 853 }
 854
 855 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 856 /*
 857  * power management
 858  */
 859 static int azx_suspend(struct device *dev)
 860 {
 861         struct snd_card *card = dev_get_drvdata(dev);
 862         struct azx *chip;
 863         struct hda_intel *hda;
 864         struct hdac_bus *bus;
 865
 866         if (!card)
 867                 return 0;
 868
 869         chip = card->private_data;
 870         hda = container_of(chip, struct hda_intel, chip);
 871         if (chip->disabled || hda->init_failed || !chip->running)
 872                 return 0;
 873
 874         bus = azx_bus(chip);
 875         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 876         azx_clear_irq_pending(chip);
 877         azx_stop_chip(chip);
 878         azx_enter_link_reset(chip);
 879         if (bus->irq >= 0) {
 880                 free_irq(bus->irq, chip);
 881                 bus->irq = -1;
 882         }
 883
 884         if (chip->msi)
 885                 pci_disable_msi(chip->pci);
 886         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 887                 && hda->need_i915_power)
 888                 snd_hdac_display_power(bus, false);
 889
 890         trace_azx_suspend(chip);
 891         return 0;
 892 }
 893
 894 static int azx_resume(struct device *dev)
 895 {
 896         struct pci_dev *pci = to_pci_dev(dev);
 897         struct snd_card *card = dev_get_drvdata(dev);
 898         struct azx *chip;
 899         struct hda_intel *hda;
 900
 901         if (!card)
 902                 return 0;
 903
 904         chip = card->private_data;
 905         hda = container_of(chip, struct hda_intel, chip);
 906         if (chip->disabled || hda->init_failed || !chip->running)
 907                 return 0;
 908
 909         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 910                 && hda->need_i915_power) {
 911                 snd_hdac_display_power(azx_bus(chip), true);
 912                 haswell_set_bclk(hda);
 913         }
 914         if (chip->msi)
 915                 if (pci_enable_msi(pci) < 0)
 916                         chip->msi = 0;
 917         if (azx_acquire_irq(chip, 1) < 0)
 918                 return -EIO;
 919         azx_init_pci(chip);
 920
 921         hda_intel_init_chip(chip, true);
 922
 923         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 924
 925         trace_azx_resume(chip);
 926         return 0;
 927 }
 928 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 929
 930 #ifdef CONFIG_PM
 931 static int azx_runtime_suspend(struct device *dev)
 932 {
 933         struct snd_card *card = dev_get_drvdata(dev);
 934         struct azx *chip;
 935         struct hda_intel *hda;
 936
 937         if (!card)
 938                 return 0;
 939
 940         chip = card->private_data;
 941         hda = container_of(chip, struct hda_intel, chip);
 942         if (chip->disabled || hda->init_failed)
 943                 return 0;
 944
 945         if (!azx_has_pm_runtime(chip))
 946                 return 0;
 947
 948         /* enable controller wake up event */
 949         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
 950                   STATESTS_INT_MASK);
 951
 952         azx_stop_chip(chip);
 953         azx_enter_link_reset(chip);
 954         azx_clear_irq_pending(chip);
 955         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 956                 && hda->need_i915_power)
 957                 snd_hdac_display_power(azx_bus(chip), false);
 958
 959         trace_azx_runtime_suspend(chip);
 960         return 0;
 961 }
 962
 963 static int azx_runtime_resume(struct device *dev)
 964 {
 965         struct snd_card *card = dev_get_drvdata(dev);
 966         struct azx *chip;
 967         struct hda_intel *hda;
 968         struct hdac_bus *bus;
 969         struct hda_codec *codec;
 970         int status;
 971
 972         if (!card)
 973                 return 0;
 974
 975         chip = card->private_data;
 976         hda = container_of(chip, struct hda_intel, chip);
 977         if (chip->disabled || hda->init_failed)
 978                 return 0;
 979
 980         if (!azx_has_pm_runtime(chip))
 981                 return 0;
 982
 983         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 984                 bus = azx_bus(chip);
 985                 if (hda->need_i915_power) {
 986                         snd_hdac_display_power(bus, true);
 987                         haswell_set_bclk(hda);
 988                 } else {
 989                         /* toggle codec wakeup bit for STATESTS read */
 990                         snd_hdac_set_codec_wakeup(bus, true);
 991                         snd_hdac_set_codec_wakeup(bus, false);
 992                 }
 993         }
 994
 995         /* Read STATESTS before controller reset */
 996         status = azx_readw(chip, STATESTS);
 997
 998         azx_init_pci(chip);
 999         hda_intel_init_chip(chip, true);
1000
1001         if (status) {
1002                 list_for_each_codec(codec, &chip->bus)
1003                         if (status & (1 << codec->addr))
1004                                 schedule_delayed_work(&codec->jackpoll_work,
1005                                                       codec->jackpoll_interval);
1006         }
1007
1008         /* disable controller Wake Up event*/
1009         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1010                         ~STATESTS_INT_MASK);
1011
1012         trace_azx_runtime_resume(chip);
1013         return 0;
1014 }
1015
1016 static int azx_runtime_idle(struct device *dev)
1017 {
1018         struct snd_card *card = dev_get_drvdata(dev);
1019         struct azx *chip;
1020         struct hda_intel *hda;
1021
1022         if (!card)
1023                 return 0;
1024
1025         chip = card->private_data;
1026         hda = container_of(chip, struct hda_intel, chip);
1027         if (chip->disabled || hda->init_failed)
1028                 return 0;
1029
1030         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1031             azx_bus(chip)->codec_powered || !chip->running)
1032                 return -EBUSY;
1033
1034         return 0;
1035 }
1036
1037 static const struct dev_pm_ops azx_pm = {
1038         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1039         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1040 };
1041
1042 #define AZX_PM_OPS      &azx_pm
1043 #else
1044 #define AZX_PM_OPS      NULL
1045 #endif /* CONFIG_PM */
1046
1047
1048 static int azx_probe_continue(struct azx *chip);
1049
1050 #ifdef SUPPORT_VGA_SWITCHEROO
1051 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1052
1053 static void azx_vs_set_state(struct pci_dev *pci,
1054                              enum vga_switcheroo_state state)
1055 {
1056         struct snd_card *card = pci_get_drvdata(pci);
1057         struct azx *chip = card->private_data;
1058         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1059         bool disabled;
1060
1061         wait_for_completion(&hda->probe_wait);
1062         if (hda->init_failed)
1063                 return;
1064
1065         disabled = (state == VGA_SWITCHEROO_OFF);
1066         if (chip->disabled == disabled)
1067                 return;
1068
1069         if (!hda->probe_continued) {
1070                 chip->disabled = disabled;
1071                 if (!disabled) {
1072                         dev_info(chip->card->dev,
1073                                  "Start delayed initialization\n");
1074                         if (azx_probe_continue(chip) < 0) {
1075                                 dev_err(chip->card->dev, "initialization error\n");
1076                                 hda->init_failed = true;
1077                         }
1078                 }
1079         } else {
1080                 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1081                          disabled ? "Disabling" : "Enabling");
1082                 if (disabled) {
1083                         pm_runtime_put_sync_suspend(card->dev);
1084                         azx_suspend(card->dev);
1085                         /* when we get suspended by vga switcheroo we end up in D3cold,
1086                          * however we have no ACPI handle, so pci/acpi can't put us there,
1087                          * put ourselves there */
1088                         pci->current_state = PCI_D3cold;
1089                         chip->disabled = true;
1090                         if (snd_hda_lock_devices(&chip->bus))
1091                                 dev_warn(chip->card->dev,
1092                                          "Cannot lock devices!\n");
1093                 } else {
1094                         snd_hda_unlock_devices(&chip->bus);
1095                         pm_runtime_get_noresume(card->dev);
1096                         chip->disabled = false;
1097                         azx_resume(card->dev);
1098                 }
1099         }
1100 }
1101
1102 static bool azx_vs_can_switch(struct pci_dev *pci)
1103 {
1104         struct snd_card *card = pci_get_drvdata(pci);
1105         struct azx *chip = card->private_data;
1106         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1107
1108         wait_for_completion(&hda->probe_wait);
1109         if (hda->init_failed)
1110                 return false;
1111         if (chip->disabled || !hda->probe_continued)
1112                 return true;
1113         if (snd_hda_lock_devices(&chip->bus))
1114                 return false;
1115         snd_hda_unlock_devices(&chip->bus);
1116         return true;
1117 }
1118
1119 static void init_vga_switcheroo(struct azx *chip)
1120 {
1121         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1122         struct pci_dev *p = get_bound_vga(chip->pci);
1123         if (p) {
1124                 dev_info(chip->card->dev,
1125                          "Handle VGA-switcheroo audio client\n");
1126                 hda->use_vga_switcheroo = 1;
1127                 pci_dev_put(p);
1128         }
1129 }
1130
1131 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1132         .set_gpu_state = azx_vs_set_state,
1133         .can_switch = azx_vs_can_switch,
1134 };
1135
1136 static int register_vga_switcheroo(struct azx *chip)
1137 {
1138         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1139         int err;
1140
1141         if (!hda->use_vga_switcheroo)
1142                 return 0;
1143         /* FIXME: currently only handling DIS controller
1144          * is there any machine with two switchable HDMI audio controllers?
1145          */
1146         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1147                                                     VGA_SWITCHEROO_DIS,
1148                                                     hda->probe_continued);
1149         if (err < 0)
1150                 return err;
1151         hda->vga_switcheroo_registered = 1;
1152
1153         /* register as an optimus hdmi audio power domain */
1154         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1155                                                          &hda->hdmi_pm_domain);
1156         return 0;
1157 }
1158 #else
1159 #define init_vga_switcheroo(chip)               /* NOP */
1160 #define register_vga_switcheroo(chip)           0
1161 #define check_hdmi_disabled(pci)        false
1162 #endif /* SUPPORT_VGA_SWITCHER */
1163
1164 /*
1165  * destructor
1166  */
1167 static int azx_free(struct azx *chip)
1168 {
1169         struct pci_dev *pci = chip->pci;
1170         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1171         struct hdac_bus *bus = azx_bus(chip);
1172
1173         if (azx_has_pm_runtime(chip) && chip->running)
1174                 pm_runtime_get_noresume(&pci->dev);
1175
1176         azx_del_card_list(chip);
1177
1178         hda->init_failed = 1; /* to be sure */
1179         complete_all(&hda->probe_wait);
1180
1181         if (use_vga_switcheroo(hda)) {
1182                 if (chip->disabled && hda->probe_continued)
1183                         snd_hda_unlock_devices(&chip->bus);
1184                 if (hda->vga_switcheroo_registered)
1185                         vga_switcheroo_unregister_client(chip->pci);
1186         }
1187
1188         if (bus->chip_init) {
1189                 azx_clear_irq_pending(chip);
1190                 azx_stop_all_streams(chip);
1191                 azx_stop_chip(chip);
1192         }
1193
1194         if (bus->irq >= 0)
1195                 free_irq(bus->irq, (void*)chip);
1196         if (chip->msi)
1197                 pci_disable_msi(chip->pci);
1198         iounmap(bus->remap_addr);
1199
1200         azx_free_stream_pages(chip);
1201         azx_free_streams(chip);
1202         snd_hdac_bus_exit(bus);
1203
1204         if (chip->region_requested)
1205                 pci_release_regions(chip->pci);
1206
1207         pci_disable_device(chip->pci);
1208 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1209         release_firmware(chip->fw);
1210 #endif
1211
1212         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1213                 if (hda->need_i915_power)
1214                         snd_hdac_display_power(bus, false);
1215                 snd_hdac_i915_exit(bus);
1216         }
1217         kfree(hda);
1218
1219         return 0;
1220 }
1221
1222 static int azx_dev_disconnect(struct snd_device *device)
1223 {
1224         struct azx *chip = device->device_data;
1225
1226         chip->bus.shutdown = 1;
1227         return 0;
1228 }
1229
1230 static int azx_dev_free(struct snd_device *device)
1231 {
1232         return azx_free(device->device_data);
1233 }
1234
1235 #ifdef SUPPORT_VGA_SWITCHEROO
1236 /*
1237  * Check of disabled HDMI controller by vga-switcheroo
1238  */
1239 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1240 {
1241         struct pci_dev *p;
1242
1243         /* check only discrete GPU */
1244         switch (pci->vendor) {
1245         case PCI_VENDOR_ID_ATI:
1246         case PCI_VENDOR_ID_AMD:
1247         case PCI_VENDOR_ID_NVIDIA:
1248                 if (pci->devfn == 1) {
1249                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1250                                                         pci->bus->number, 0);
1251                         if (p) {
1252                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1253                                         return p;
1254                                 pci_dev_put(p);
1255                         }
1256                 }
1257                 break;
1258         }
1259         return NULL;
1260 }
1261
1262 static bool check_hdmi_disabled(struct pci_dev *pci)
1263 {
1264         bool vga_inactive = false;
1265         struct pci_dev *p = get_bound_vga(pci);
1266
1267         if (p) {
1268                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1269                         vga_inactive = true;
1270                 pci_dev_put(p);
1271         }
1272         return vga_inactive;
1273 }
1274 #endif /* SUPPORT_VGA_SWITCHEROO */
1275
1276 /*
1277  * white/black-listing for position_fix
1278  */
1279 static struct snd_pci_quirk position_fix_list[] = {
1280         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1281         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1282         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1283         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1284         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1285         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1286         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1287         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1288         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1289         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1290         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1291         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1292         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1293         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1294         {}
1295 };
1296
1297 static int check_position_fix(struct azx *chip, int fix)
1298 {
1299         const struct snd_pci_quirk *q;
1300
1301         switch (fix) {
1302         case POS_FIX_AUTO:
1303         case POS_FIX_LPIB:
1304         case POS_FIX_POSBUF:
1305         case POS_FIX_VIACOMBO:
1306         case POS_FIX_COMBO:
1307                 return fix;
1308         }
1309
1310         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1311         if (q) {
1312                 dev_info(chip->card->dev,
1313                          "position_fix set to %d for device %04x:%04x\n",
1314                          q->value, q->subvendor, q->subdevice);
1315                 return q->value;
1316         }
1317
1318         /* Check VIA/ATI HD Audio Controller exist */
1319         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1320                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1321                 return POS_FIX_VIACOMBO;
1322         }
1323         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1324                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1325                 return POS_FIX_LPIB;
1326         }
1327         return POS_FIX_AUTO;
1328 }
1329
1330 static void assign_position_fix(struct azx *chip, int fix)
1331 {
1332         static azx_get_pos_callback_t callbacks[] = {
1333                 [POS_FIX_AUTO] = NULL,
1334                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1335                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1336                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1337                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1338         };
1339
1340         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1341
1342         /* combo mode uses LPIB only for playback */
1343         if (fix == POS_FIX_COMBO)
1344                 chip->get_position[1] = NULL;
1345
1346         if (fix == POS_FIX_POSBUF &&
1347             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1348                 chip->get_delay[0] = chip->get_delay[1] =
1349                         azx_get_delay_from_lpib;
1350         }
1351
1352 }
1353
1354 /*
1355  * black-lists for probe_mask
1356  */
1357 static struct snd_pci_quirk probe_mask_list[] = {
1358         /* Thinkpad often breaks the controller communication when accessing
1359          * to the non-working (or non-existing) modem codec slot.
1360          */
1361         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1362         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1363         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1364         /* broken BIOS */
1365         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1366         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1367         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1368         /* forced codec slots */
1369         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1370         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1371         /* WinFast VP200 H (Teradici) user reported broken communication */
1372         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1373         {}
1374 };
1375
1376 #define AZX_FORCE_CODEC_MASK    0x100
1377
1378 static void check_probe_mask(struct azx *chip, int dev)
1379 {
1380         const struct snd_pci_quirk *q;
1381
1382         chip->codec_probe_mask = probe_mask[dev];
1383         if (chip->codec_probe_mask == -1) {
1384                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1385                 if (q) {
1386                         dev_info(chip->card->dev,
1387                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1388                                  q->value, q->subvendor, q->subdevice);
1389                         chip->codec_probe_mask = q->value;
1390                 }
1391         }
1392
1393         /* check forced option */
1394         if (chip->codec_probe_mask != -1 &&
1395             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1396                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1397                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1398                          (int)azx_bus(chip)->codec_mask);
1399         }
1400 }
1401
1402 /*
1403  * white/black-list for enable_msi
1404  */
1405 static struct snd_pci_quirk msi_black_list[] = {
1406         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1407         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1408         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1409         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1410         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1411         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1412         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1413         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1414         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1415         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1416         {}
1417 };
1418
1419 static void check_msi(struct azx *chip)
1420 {
1421         const struct snd_pci_quirk *q;
1422
1423         if (enable_msi >= 0) {
1424                 chip->msi = !!enable_msi;
1425                 return;
1426         }
1427         chip->msi = 1;  /* enable MSI as default */
1428         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1429         if (q) {
1430                 dev_info(chip->card->dev,
1431                          "msi for device %04x:%04x set to %d\n",
1432                          q->subvendor, q->subdevice, q->value);
1433                 chip->msi = q->value;
1434                 return;
1435         }
1436
1437         /* NVidia chipsets seem to cause troubles with MSI */
1438         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1439                 dev_info(chip->card->dev, "Disabling MSI\n");
1440                 chip->msi = 0;
1441         }
1442 }
1443
1444 /* check the snoop mode availability */
1445 static void azx_check_snoop_available(struct azx *chip)
1446 {
1447         int snoop = hda_snoop;
1448
1449         if (snoop >= 0) {
1450                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1451                          snoop ? "snoop" : "non-snoop");
1452                 chip->snoop = snoop;
1453                 return;
1454         }
1455
1456         snoop = true;
1457         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1458             chip->driver_type == AZX_DRIVER_VIA) {
1459                 /* force to non-snoop mode for a new VIA controller
1460                  * when BIOS is set
1461                  */
1462                 u8 val;
1463                 pci_read_config_byte(chip->pci, 0x42, &val);
1464                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1465                         snoop = false;
1466         }
1467
1468         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1469                 snoop = false;
1470
1471         chip->snoop = snoop;
1472         if (!snoop)
1473                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1474 }
1475
1476 static void azx_probe_work(struct work_struct *work)
1477 {
1478         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1479         azx_probe_continue(&hda->chip);
1480 }
1481
1482 /*
1483  * constructor
1484  */
1485 static const struct hdac_io_ops pci_hda_io_ops;
1486 static const struct hda_controller_ops pci_hda_ops;
1487
1488 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1489                       int dev, unsigned int driver_caps,
1490                       struct azx **rchip)
1491 {
1492         static struct snd_device_ops ops = {
1493                 .dev_disconnect = azx_dev_disconnect,
1494                 .dev_free = azx_dev_free,
1495         };
1496         struct hda_intel *hda;
1497         struct azx *chip;
1498         int err;
1499
1500         *rchip = NULL;
1501
1502         err = pci_enable_device(pci);
1503         if (err < 0)
1504                 return err;
1505
1506         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1507         if (!hda) {
1508                 pci_disable_device(pci);
1509                 return -ENOMEM;
1510         }
1511
1512         chip = &hda->chip;
1513         mutex_init(&chip->open_mutex);
1514         chip->card = card;
1515         chip->pci = pci;
1516         chip->ops = &pci_hda_ops;
1517         chip->driver_caps = driver_caps;
1518         chip->driver_type = driver_caps & 0xff;
1519         check_msi(chip);
1520         chip->dev_index = dev;
1521         chip->jackpoll_ms = jackpoll_ms;
1522         INIT_LIST_HEAD(&chip->pcm_list);
1523         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1524         INIT_LIST_HEAD(&hda->list);
1525         init_vga_switcheroo(chip);
1526         init_completion(&hda->probe_wait);
1527
1528         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1529
1530         check_probe_mask(chip, dev);
1531
1532         chip->single_cmd = single_cmd;
1533         azx_check_snoop_available(chip);
1534
1535         if (bdl_pos_adj[dev] < 0) {
1536                 switch (chip->driver_type) {
1537                 case AZX_DRIVER_ICH:
1538                 case AZX_DRIVER_PCH:
1539                         bdl_pos_adj[dev] = 1;
1540                         break;
1541                 default:
1542                         bdl_pos_adj[dev] = 32;
1543                         break;
1544                 }
1545         }
1546         chip->bdl_pos_adj = bdl_pos_adj;
1547
1548         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1549         if (err < 0) {
1550                 kfree(hda);
1551                 pci_disable_device(pci);
1552                 return err;
1553         }
1554
1555         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1556         if (err < 0) {
1557                 dev_err(card->dev, "Error creating device [card]!\n");
1558                 azx_free(chip);
1559                 return err;
1560         }
1561
1562         /* continue probing in work context as may trigger request module */
1563         INIT_WORK(&hda->probe_work, azx_probe_work);
1564
1565         *rchip = chip;
1566
1567         return 0;
1568 }
1569
1570 static int azx_first_init(struct azx *chip)
1571 {
1572         int dev = chip->dev_index;
1573         struct pci_dev *pci = chip->pci;
1574         struct snd_card *card = chip->card;
1575         struct hdac_bus *bus = azx_bus(chip);
1576         int err;
1577         unsigned short gcap;
1578         unsigned int dma_bits = 64;
1579
1580 #if BITS_PER_LONG != 64
1581         /* Fix up base address on ULI M5461 */
1582         if (chip->driver_type == AZX_DRIVER_ULI) {
1583                 u16 tmp3;
1584                 pci_read_config_word(pci, 0x40, &tmp3);
1585                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1586                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1587         }
1588 #endif
1589
1590         err = pci_request_regions(pci, "ICH HD audio");
1591         if (err < 0)
1592                 return err;
1593         chip->region_requested = 1;
1594
1595         bus->addr = pci_resource_start(pci, 0);
1596         bus->remap_addr = pci_ioremap_bar(pci, 0);
1597         if (bus->remap_addr == NULL) {
1598                 dev_err(card->dev, "ioremap error\n");
1599                 return -ENXIO;
1600         }
1601
1602         if (chip->msi) {
1603                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1604                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1605                         pci->no_64bit_msi = true;
1606                 }
1607                 if (pci_enable_msi(pci) < 0)
1608                         chip->msi = 0;
1609         }
1610
1611         if (azx_acquire_irq(chip, 0) < 0)
1612                 return -EBUSY;
1613
1614         pci_set_master(pci);
1615         synchronize_irq(bus->irq);
1616
1617         gcap = azx_readw(chip, GCAP);
1618         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1619
1620         /* AMD devices support 40 or 48bit DMA, take the safe one */
1621         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1622                 dma_bits = 40;
1623
1624         /* disable SB600 64bit support for safety */
1625         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1626                 struct pci_dev *p_smbus;
1627                 dma_bits = 40;
1628                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1629                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1630                                          NULL);
1631                 if (p_smbus) {
1632                         if (p_smbus->revision < 0x30)
1633                                 gcap &= ~AZX_GCAP_64OK;
1634                         pci_dev_put(p_smbus);
1635                 }
1636         }
1637
1638         /* disable 64bit DMA address on some devices */
1639         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1640                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1641                 gcap &= ~AZX_GCAP_64OK;
1642         }
1643
1644         /* disable buffer size rounding to 128-byte multiples if supported */
1645         if (align_buffer_size >= 0)
1646                 chip->align_buffer_size = !!align_buffer_size;
1647         else {
1648                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1649                         chip->align_buffer_size = 0;
1650                 else
1651                         chip->align_buffer_size = 1;
1652         }
1653
1654         /* allow 64bit DMA address if supported by H/W */
1655         if (!(gcap & AZX_GCAP_64OK))
1656                 dma_bits = 32;
1657         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1658                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1659         } else {
1660                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1661                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1662         }
1663
1664         /* read number of streams from GCAP register instead of using
1665          * hardcoded value
1666          */
1667         chip->capture_streams = (gcap >> 8) & 0x0f;
1668         chip->playback_streams = (gcap >> 12) & 0x0f;
1669         if (!chip->playback_streams && !chip->capture_streams) {
1670                 /* gcap didn't give any info, switching to old method */
1671
1672                 switch (chip->driver_type) {
1673                 case AZX_DRIVER_ULI:
1674                         chip->playback_streams = ULI_NUM_PLAYBACK;
1675                         chip->capture_streams = ULI_NUM_CAPTURE;
1676                         break;
1677                 case AZX_DRIVER_ATIHDMI:
1678                 case AZX_DRIVER_ATIHDMI_NS:
1679                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1680                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1681                         break;
1682                 case AZX_DRIVER_GENERIC:
1683                 default:
1684                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1685                         chip->capture_streams = ICH6_NUM_CAPTURE;
1686                         break;
1687                 }
1688         }
1689         chip->capture_index_offset = 0;
1690         chip->playback_index_offset = chip->capture_streams;
1691         chip->num_streams = chip->playback_streams + chip->capture_streams;
1692
1693         /* initialize streams */
1694         err = azx_init_streams(chip);
1695         if (err < 0)
1696                 return err;
1697
1698         err = azx_alloc_stream_pages(chip);
1699         if (err < 0)
1700                 return err;
1701
1702         /* initialize chip */
1703         azx_init_pci(chip);
1704
1705         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1706                 struct hda_intel *hda;
1707
1708                 hda = container_of(chip, struct hda_intel, chip);
1709                 haswell_set_bclk(hda);
1710         }
1711
1712         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1713
1714         /* codec detection */
1715         if (!azx_bus(chip)->codec_mask) {
1716                 dev_err(card->dev, "no codecs found!\n");
1717                 return -ENODEV;
1718         }
1719
1720         strcpy(card->driver, "HDA-Intel");
1721         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1722                 sizeof(card->shortname));
1723         snprintf(card->longname, sizeof(card->longname),
1724                  "%s at 0x%lx irq %i",
1725                  card->shortname, bus->addr, bus->irq);
1726
1727         return 0;
1728 }
1729
1730 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1731 /* callback from request_firmware_nowait() */
1732 static void azx_firmware_cb(const struct firmware *fw, void *context)
1733 {
1734         struct snd_card *card = context;
1735         struct azx *chip = card->private_data;
1736         struct pci_dev *pci = chip->pci;
1737
1738         if (!fw) {
1739                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1740                 goto error;
1741         }
1742
1743         chip->fw = fw;
1744         if (!chip->disabled) {
1745                 /* continue probing */
1746                 if (azx_probe_continue(chip))
1747                         goto error;
1748         }
1749         return; /* OK */
1750
1751  error:
1752         snd_card_free(card);
1753         pci_set_drvdata(pci, NULL);
1754 }
1755 #endif
1756
1757 /*
1758  * HDA controller ops.
1759  */
1760
1761 /* PCI register access. */
1762 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1763 {
1764         writel(value, addr);
1765 }
1766
1767 static u32 pci_azx_readl(u32 __iomem *addr)
1768 {
1769         return readl(addr);
1770 }
1771
1772 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1773 {
1774         writew(value, addr);
1775 }
1776
1777 static u16 pci_azx_readw(u16 __iomem *addr)
1778 {
1779         return readw(addr);
1780 }
1781
1782 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1783 {
1784         writeb(value, addr);
1785 }
1786
1787 static u8 pci_azx_readb(u8 __iomem *addr)
1788 {
1789         return readb(addr);
1790 }
1791
1792 static int disable_msi_reset_irq(struct azx *chip)
1793 {
1794         struct hdac_bus *bus = azx_bus(chip);
1795         int err;
1796
1797         free_irq(bus->irq, chip);
1798         bus->irq = -1;
1799         pci_disable_msi(chip->pci);
1800         chip->msi = 0;
1801         err = azx_acquire_irq(chip, 1);
1802         if (err < 0)
1803                 return err;
1804
1805         return 0;
1806 }
1807
1808 /* DMA page allocation helpers.  */
1809 static int dma_alloc_pages(struct hdac_bus *bus,
1810                            int type,
1811                            size_t size,
1812                            struct snd_dma_buffer *buf)
1813 {
1814         struct azx *chip = bus_to_azx(bus);
1815         int err;
1816
1817         err = snd_dma_alloc_pages(type,
1818                                   bus->dev,
1819                                   size, buf);
1820         if (err < 0)
1821                 return err;
1822         mark_pages_wc(chip, buf, true);
1823         return 0;
1824 }
1825
1826 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1827 {
1828         struct azx *chip = bus_to_azx(bus);
1829
1830         mark_pages_wc(chip, buf, false);
1831         snd_dma_free_pages(buf);
1832 }
1833
1834 static int substream_alloc_pages(struct azx *chip,
1835                                  struct snd_pcm_substream *substream,
1836                                  size_t size)
1837 {
1838         struct azx_dev *azx_dev = get_azx_dev(substream);
1839         int ret;
1840
1841         mark_runtime_wc(chip, azx_dev, substream, false);
1842         ret = snd_pcm_lib_malloc_pages(substream, size);
1843         if (ret < 0)
1844                 return ret;
1845         mark_runtime_wc(chip, azx_dev, substream, true);
1846         return 0;
1847 }
1848
1849 static int substream_free_pages(struct azx *chip,
1850                                 struct snd_pcm_substream *substream)
1851 {
1852         struct azx_dev *azx_dev = get_azx_dev(substream);
1853         mark_runtime_wc(chip, azx_dev, substream, false);
1854         return snd_pcm_lib_free_pages(substream);
1855 }
1856
1857 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1858                              struct vm_area_struct *area)
1859 {
1860 #ifdef CONFIG_X86
1861         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1862         struct azx *chip = apcm->chip;
1863         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1864                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1865 #endif
1866 }
1867
1868 static const struct hdac_io_ops pci_hda_io_ops = {
1869         .reg_writel = pci_azx_writel,
1870         .reg_readl = pci_azx_readl,
1871         .reg_writew = pci_azx_writew,
1872         .reg_readw = pci_azx_readw,
1873         .reg_writeb = pci_azx_writeb,
1874         .reg_readb = pci_azx_readb,
1875         .dma_alloc_pages = dma_alloc_pages,
1876         .dma_free_pages = dma_free_pages,
1877 };
1878
1879 static const struct hda_controller_ops pci_hda_ops = {
1880         .disable_msi_reset_irq = disable_msi_reset_irq,
1881         .substream_alloc_pages = substream_alloc_pages,
1882         .substream_free_pages = substream_free_pages,
1883         .pcm_mmap_prepare = pcm_mmap_prepare,
1884         .position_check = azx_position_check,
1885         .link_power = azx_intel_link_power,
1886 };
1887
1888 static int azx_probe(struct pci_dev *pci,
1889                      const struct pci_device_id *pci_id)
1890 {
1891         static int dev;
1892         struct snd_card *card;
1893         struct hda_intel *hda;
1894         struct azx *chip;
1895         bool schedule_probe;
1896         int err;
1897
1898         if (dev >= SNDRV_CARDS)
1899                 return -ENODEV;
1900         if (!enable[dev]) {
1901                 dev++;
1902                 return -ENOENT;
1903         }
1904
1905         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1906                            0, &card);
1907         if (err < 0) {
1908                 dev_err(&pci->dev, "Error creating card!\n");
1909                 return err;
1910         }
1911
1912         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1913         if (err < 0)
1914                 goto out_free;
1915         card->private_data = chip;
1916         hda = container_of(chip, struct hda_intel, chip);
1917
1918         pci_set_drvdata(pci, card);
1919
1920         err = register_vga_switcheroo(chip);
1921         if (err < 0) {
1922                 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1923                 goto out_free;
1924         }
1925
1926         if (check_hdmi_disabled(pci)) {
1927                 dev_info(card->dev, "VGA controller is disabled\n");
1928                 dev_info(card->dev, "Delaying initialization\n");
1929                 chip->disabled = true;
1930         }
1931
1932         schedule_probe = !chip->disabled;
1933
1934 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1935         if (patch[dev] && *patch[dev]) {
1936                 dev_info(card->dev, "Applying patch firmware '%s'\n",
1937                          patch[dev]);
1938                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1939                                               &pci->dev, GFP_KERNEL, card,
1940                                               azx_firmware_cb);
1941                 if (err < 0)
1942                         goto out_free;
1943                 schedule_probe = false; /* continued in azx_firmware_cb() */
1944         }
1945 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1946
1947 #ifndef CONFIG_SND_HDA_I915
1948         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1949                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1950 #endif
1951
1952         if (schedule_probe)
1953                 schedule_work(&hda->probe_work);
1954
1955         dev++;
1956         if (chip->disabled)
1957                 complete_all(&hda->probe_wait);
1958         return 0;
1959
1960 out_free:
1961         snd_card_free(card);
1962         return err;
1963 }
1964
1965 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1966 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1967         [AZX_DRIVER_NVIDIA] = 8,
1968         [AZX_DRIVER_TERA] = 1,
1969 };
1970
1971 static int azx_probe_continue(struct azx *chip)
1972 {
1973         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1974         struct hdac_bus *bus = azx_bus(chip);
1975         struct pci_dev *pci = chip->pci;
1976         int dev = chip->dev_index;
1977         int err;
1978
1979         hda->probe_continued = 1;
1980
1981         /* Request display power well for the HDA controller or codec. For
1982          * Haswell/Broadwell, both the display HDA controller and codec need
1983          * this power. For other platforms, like Baytrail/Braswell, only the
1984          * display codec needs the power and it can be released after probe.
1985          */
1986         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1987                 /* HSW/BDW controllers need this power */
1988                 if (CONTROLLER_IN_GPU(pci))
1989                         hda->need_i915_power = 1;
1990
1991                 err = snd_hdac_i915_init(bus);
1992                 if (err < 0) {
1993                         /* if the controller is bound only with HDMI/DP
1994                          * (for HSW and BDW), we need to abort the probe;
1995                          * for other chips, still continue probing as other
1996                          * codecs can be on the same link.
1997                          */
1998                         if (CONTROLLER_IN_GPU(pci))
1999                                 goto out_free;
2000                         else
2001                                 goto skip_i915;
2002                 }
2003
2004                 err = snd_hdac_display_power(bus, true);
2005                 if (err < 0) {
2006                         dev_err(chip->card->dev,
2007                                 "Cannot turn on display power on i915\n");
2008                         goto i915_power_fail;
2009                 }
2010         }
2011
2012  skip_i915:
2013         err = azx_first_init(chip);
2014         if (err < 0)
2015                 goto out_free;
2016
2017 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2018         chip->beep_mode = beep_mode[dev];
2019 #endif
2020
2021         /* create codec instances */
2022         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2023         if (err < 0)
2024                 goto out_free;
2025
2026 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2027         if (chip->fw) {
2028                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2029                                          chip->fw->data);
2030                 if (err < 0)
2031                         goto out_free;
2032 #ifndef CONFIG_PM
2033                 release_firmware(chip->fw); /* no longer needed */
2034                 chip->fw = NULL;
2035 #endif
2036         }
2037 #endif
2038         if ((probe_only[dev] & 1) == 0) {
2039                 err = azx_codec_configure(chip);
2040                 if (err < 0)
2041                         goto out_free;
2042         }
2043
2044         err = snd_card_register(chip->card);
2045         if (err < 0)
2046                 goto out_free;
2047
2048         chip->running = 1;
2049         azx_add_card_list(chip);
2050         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2051         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2052                 pm_runtime_put_noidle(&pci->dev);
2053
2054 out_free:
2055         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2056                 && !hda->need_i915_power)
2057                 snd_hdac_display_power(bus, false);
2058
2059 i915_power_fail:
2060         if (err < 0)
2061                 hda->init_failed = 1;
2062         complete_all(&hda->probe_wait);
2063         return err;
2064 }
2065
2066 static void azx_remove(struct pci_dev *pci)
2067 {
2068         struct snd_card *card = pci_get_drvdata(pci);
2069
2070         if (card)
2071                 snd_card_free(card);
2072 }
2073
2074 static void azx_shutdown(struct pci_dev *pci)
2075 {
2076         struct snd_card *card = pci_get_drvdata(pci);
2077         struct azx *chip;
2078
2079         if (!card)
2080                 return;
2081         chip = card->private_data;
2082         if (chip && chip->running)
2083                 azx_stop_chip(chip);
2084 }
2085
2086 /* PCI IDs */
2087 static const struct pci_device_id azx_ids[] = {
2088         /* CPT */
2089         { PCI_DEVICE(0x8086, 0x1c20),
2090           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2091         /* PBG */
2092         { PCI_DEVICE(0x8086, 0x1d20),
2093           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2094         /* Panther Point */
2095         { PCI_DEVICE(0x8086, 0x1e20),
2096           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2097         /* Lynx Point */
2098         { PCI_DEVICE(0x8086, 0x8c20),
2099           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2100         /* 9 Series */
2101         { PCI_DEVICE(0x8086, 0x8ca0),
2102           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2103         /* Wellsburg */
2104         { PCI_DEVICE(0x8086, 0x8d20),
2105           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2106         { PCI_DEVICE(0x8086, 0x8d21),
2107           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2108         /* Lynx Point-LP */
2109         { PCI_DEVICE(0x8086, 0x9c20),
2110           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2111         /* Lynx Point-LP */
2112         { PCI_DEVICE(0x8086, 0x9c21),
2113           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2114         /* Wildcat Point-LP */
2115         { PCI_DEVICE(0x8086, 0x9ca0),
2116           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2117         /* Sunrise Point */
2118         { PCI_DEVICE(0x8086, 0xa170),
2119           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2120         /* Sunrise Point-LP */
2121         { PCI_DEVICE(0x8086, 0x9d70),
2122           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2123         /* Haswell */
2124         { PCI_DEVICE(0x8086, 0x0a0c),
2125           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2126         { PCI_DEVICE(0x8086, 0x0c0c),
2127           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2128         { PCI_DEVICE(0x8086, 0x0d0c),
2129           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2130         /* Broadwell */
2131         { PCI_DEVICE(0x8086, 0x160c),
2132           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2133         /* 5 Series/3400 */
2134         { PCI_DEVICE(0x8086, 0x3b56),
2135           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2136         /* Poulsbo */
2137         { PCI_DEVICE(0x8086, 0x811b),
2138           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2139         /* Oaktrail */
2140         { PCI_DEVICE(0x8086, 0x080a),
2141           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2142         /* BayTrail */
2143         { PCI_DEVICE(0x8086, 0x0f04),
2144           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2145         /* Braswell */
2146         { PCI_DEVICE(0x8086, 0x2284),
2147           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2148         /* ICH6 */
2149         { PCI_DEVICE(0x8086, 0x2668),
2150           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2151         /* ICH7 */
2152         { PCI_DEVICE(0x8086, 0x27d8),
2153           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2154         /* ESB2 */
2155         { PCI_DEVICE(0x8086, 0x269a),
2156           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2157         /* ICH8 */
2158         { PCI_DEVICE(0x8086, 0x284b),
2159           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2160         /* ICH9 */
2161         { PCI_DEVICE(0x8086, 0x293e),
2162           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2163         /* ICH9 */
2164         { PCI_DEVICE(0x8086, 0x293f),
2165           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2166         /* ICH10 */
2167         { PCI_DEVICE(0x8086, 0x3a3e),
2168           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2169         /* ICH10 */
2170         { PCI_DEVICE(0x8086, 0x3a6e),
2171           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2172         /* Generic Intel */
2173         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2174           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2175           .class_mask = 0xffffff,
2176           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2177         /* ATI SB 450/600/700/800/900 */
2178         { PCI_DEVICE(0x1002, 0x437b),
2179           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2180         { PCI_DEVICE(0x1002, 0x4383),
2181           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2182         /* AMD Hudson */
2183         { PCI_DEVICE(0x1022, 0x780d),
2184           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2185         /* ATI HDMI */
2186         { PCI_DEVICE(0x1002, 0x1308),
2187           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2188         { PCI_DEVICE(0x1002, 0x157a),
2189           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2190         { PCI_DEVICE(0x1002, 0x793b),
2191           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2192         { PCI_DEVICE(0x1002, 0x7919),
2193           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2194         { PCI_DEVICE(0x1002, 0x960f),
2195           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2196         { PCI_DEVICE(0x1002, 0x970f),
2197           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2198         { PCI_DEVICE(0x1002, 0x9840),
2199           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2200         { PCI_DEVICE(0x1002, 0xaa00),
2201           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2202         { PCI_DEVICE(0x1002, 0xaa08),
2203           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2204         { PCI_DEVICE(0x1002, 0xaa10),
2205           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2206         { PCI_DEVICE(0x1002, 0xaa18),
2207           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2208         { PCI_DEVICE(0x1002, 0xaa20),
2209           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2210         { PCI_DEVICE(0x1002, 0xaa28),
2211           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2212         { PCI_DEVICE(0x1002, 0xaa30),
2213           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2214         { PCI_DEVICE(0x1002, 0xaa38),
2215           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2216         { PCI_DEVICE(0x1002, 0xaa40),
2217           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2218         { PCI_DEVICE(0x1002, 0xaa48),
2219           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2220         { PCI_DEVICE(0x1002, 0xaa50),
2221           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2222         { PCI_DEVICE(0x1002, 0xaa58),
2223           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2224         { PCI_DEVICE(0x1002, 0xaa60),
2225           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2226         { PCI_DEVICE(0x1002, 0xaa68),
2227           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2228         { PCI_DEVICE(0x1002, 0xaa80),
2229           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2230         { PCI_DEVICE(0x1002, 0xaa88),
2231           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2232         { PCI_DEVICE(0x1002, 0xaa90),
2233           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2234         { PCI_DEVICE(0x1002, 0xaa98),
2235           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2236         { PCI_DEVICE(0x1002, 0x9902),
2237           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2238         { PCI_DEVICE(0x1002, 0xaaa0),
2239           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2240         { PCI_DEVICE(0x1002, 0xaaa8),
2241           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2242         { PCI_DEVICE(0x1002, 0xaab0),
2243           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2244         { PCI_DEVICE(0x1002, 0xaac0),
2245           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2246         { PCI_DEVICE(0x1002, 0xaac8),
2247           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2248         { PCI_DEVICE(0x1002, 0xaad8),
2249           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2250         { PCI_DEVICE(0x1002, 0xaae8),
2251           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2252         /* VIA VT8251/VT8237A */
2253         { PCI_DEVICE(0x1106, 0x3288),
2254           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2255         /* VIA GFX VT7122/VX900 */
2256         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2257         /* VIA GFX VT6122/VX11 */
2258         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2259         /* SIS966 */
2260         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2261         /* ULI M5461 */
2262         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2263         /* NVIDIA MCP */
2264         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2265           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2266           .class_mask = 0xffffff,
2267           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2268         /* Teradici */
2269         { PCI_DEVICE(0x6549, 0x1200),
2270           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2271         { PCI_DEVICE(0x6549, 0x2200),
2272           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2273         /* Creative X-Fi (CA0110-IBG) */
2274         /* CTHDA chips */
2275         { PCI_DEVICE(0x1102, 0x0010),
2276           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2277         { PCI_DEVICE(0x1102, 0x0012),
2278           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2279 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2280         /* the following entry conflicts with snd-ctxfi driver,
2281          * as ctxfi driver mutates from HD-audio to native mode with
2282          * a special command sequence.
2283          */
2284         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2285           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2286           .class_mask = 0xffffff,
2287           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2288           AZX_DCAPS_NO_64BIT |
2289           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2290 #else
2291         /* this entry seems still valid -- i.e. without emu20kx chip */
2292         { PCI_DEVICE(0x1102, 0x0009),
2293           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2294           AZX_DCAPS_NO_64BIT |
2295           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2296 #endif
2297         /* CM8888 */
2298         { PCI_DEVICE(0x13f6, 0x5011),
2299           .driver_data = AZX_DRIVER_CMEDIA |
2300           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2301         /* Vortex86MX */
2302         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2303         /* VMware HDAudio */
2304         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2305         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2306         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2307           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2308           .class_mask = 0xffffff,
2309           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2310         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2311           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2312           .class_mask = 0xffffff,
2313           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2314         { 0, }
2315 };
2316 MODULE_DEVICE_TABLE(pci, azx_ids);
2317
2318 /* pci_driver definition */
2319 static struct pci_driver azx_driver = {
2320         .name = KBUILD_MODNAME,
2321         .id_table = azx_ids,
2322         .probe = azx_probe,
2323         .remove = azx_remove,
2324         .shutdown = azx_shutdown,
2325         .driver = {
2326                 .pm = AZX_PM_OPS,
2327         },
2328 };
2329
2330 module_pci_driver(azx_driver);