sound/soc/codecs/arizona.c

   1 /*
   2  * arizona.c - Wolfson Arizona class device shared support
   3  *
   4  * Copyright 2012 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/gcd.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <sound/pcm.h>
  18 #include <sound/pcm_params.h>
  19 #include <sound/tlv.h>
  20
  21 #include <linux/mfd/arizona/core.h>
  22 #include <linux/mfd/arizona/registers.h>
  23
  24 #include "arizona.h"
  25
  26 #define ARIZONA_AIF_BCLK_CTRL                   0x00
  27 #define ARIZONA_AIF_TX_PIN_CTRL                 0x01
  28 #define ARIZONA_AIF_RX_PIN_CTRL                 0x02
  29 #define ARIZONA_AIF_RATE_CTRL                   0x03
  30 #define ARIZONA_AIF_FORMAT                      0x04
  31 #define ARIZONA_AIF_TX_BCLK_RATE                0x05
  32 #define ARIZONA_AIF_RX_BCLK_RATE                0x06
  33 #define ARIZONA_AIF_FRAME_CTRL_1                0x07
  34 #define ARIZONA_AIF_FRAME_CTRL_2                0x08
  35 #define ARIZONA_AIF_FRAME_CTRL_3                0x09
  36 #define ARIZONA_AIF_FRAME_CTRL_4                0x0A
  37 #define ARIZONA_AIF_FRAME_CTRL_5                0x0B
  38 #define ARIZONA_AIF_FRAME_CTRL_6                0x0C
  39 #define ARIZONA_AIF_FRAME_CTRL_7                0x0D
  40 #define ARIZONA_AIF_FRAME_CTRL_8                0x0E
  41 #define ARIZONA_AIF_FRAME_CTRL_9                0x0F
  42 #define ARIZONA_AIF_FRAME_CTRL_10               0x10
  43 #define ARIZONA_AIF_FRAME_CTRL_11               0x11
  44 #define ARIZONA_AIF_FRAME_CTRL_12               0x12
  45 #define ARIZONA_AIF_FRAME_CTRL_13               0x13
  46 #define ARIZONA_AIF_FRAME_CTRL_14               0x14
  47 #define ARIZONA_AIF_FRAME_CTRL_15               0x15
  48 #define ARIZONA_AIF_FRAME_CTRL_16               0x16
  49 #define ARIZONA_AIF_FRAME_CTRL_17               0x17
  50 #define ARIZONA_AIF_FRAME_CTRL_18               0x18
  51 #define ARIZONA_AIF_TX_ENABLES                  0x19
  52 #define ARIZONA_AIF_RX_ENABLES                  0x1A
  53 #define ARIZONA_AIF_FORCE_WRITE                 0x1B
  54
  55 #define ARIZONA_FLL_VCO_CORNER 141900000
  56 #define ARIZONA_FLL_MAX_FREF   13500000
  57 #define ARIZONA_FLL_MIN_FVCO   90000000
  58 #define ARIZONA_FLL_MAX_FRATIO 16
  59 #define ARIZONA_FLL_MAX_REFDIV 8
  60 #define ARIZONA_FLL_MIN_OUTDIV 2
  61 #define ARIZONA_FLL_MAX_OUTDIV 7
  62
  63 #define ARIZONA_FMT_DSP_MODE_A          0
  64 #define ARIZONA_FMT_DSP_MODE_B          1
  65 #define ARIZONA_FMT_I2S_MODE            2
  66 #define ARIZONA_FMT_LEFT_JUSTIFIED_MODE 3
  67
  68 #define arizona_fll_err(_fll, fmt, ...) \
  69         dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  70 #define arizona_fll_warn(_fll, fmt, ...) \
  71         dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  72 #define arizona_fll_dbg(_fll, fmt, ...) \
  73         dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  74
  75 #define arizona_aif_err(_dai, fmt, ...) \
  76         dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  77 #define arizona_aif_warn(_dai, fmt, ...) \
  78         dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  79 #define arizona_aif_dbg(_dai, fmt, ...) \
  80         dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  81
  82 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
  83                           struct snd_kcontrol *kcontrol,
  84                           int event)
  85 {
  86         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  87         struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
  88         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
  89         bool manual_ena = false;
  90         int val;
  91
  92         switch (arizona->type) {
  93         case WM5102:
  94                 switch (arizona->rev) {
  95                 case 0:
  96                         break;
  97                 default:
  98                         manual_ena = true;
  99                         break;
 100                 }
 101         default:
 102                 break;
 103         }
 104
 105         switch (event) {
 106         case SND_SOC_DAPM_PRE_PMU:
 107                 if (!priv->spk_ena && manual_ena) {
 108                         regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
 109                         priv->spk_ena_pending = true;
 110                 }
 111                 break;
 112         case SND_SOC_DAPM_POST_PMU:
 113                 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
 114                 if (val & ARIZONA_SPK_OVERHEAT_STS) {
 115                         dev_crit(arizona->dev,
 116                                  "Speaker not enabled due to temperature\n");
 117                         return -EBUSY;
 118                 }
 119
 120                 regmap_update_bits_async(arizona->regmap,
 121                                          ARIZONA_OUTPUT_ENABLES_1,
 122                                          1 << w->shift, 1 << w->shift);
 123
 124                 if (priv->spk_ena_pending) {
 125                         msleep(75);
 126                         regmap_write_async(arizona->regmap, 0x4f5, 0xda);
 127                         priv->spk_ena_pending = false;
 128                         priv->spk_ena++;
 129                 }
 130                 break;
 131         case SND_SOC_DAPM_PRE_PMD:
 132                 if (manual_ena) {
 133                         priv->spk_ena--;
 134                         if (!priv->spk_ena)
 135                                 regmap_write_async(arizona->regmap,
 136                                                    0x4f5, 0x25a);
 137                 }
 138
 139                 regmap_update_bits_async(arizona->regmap,
 140                                          ARIZONA_OUTPUT_ENABLES_1,
 141                                          1 << w->shift, 0);
 142                 break;
 143         case SND_SOC_DAPM_POST_PMD:
 144                 if (manual_ena) {
 145                         if (!priv->spk_ena)
 146                                 regmap_write_async(arizona->regmap,
 147                                                    0x4f5, 0x0da);
 148                 }
 149                 break;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static irqreturn_t arizona_thermal_warn(int irq, void *data)
 156 {
 157         struct arizona *arizona = data;
 158         unsigned int val;
 159         int ret;
 160
 161         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
 162                           &val);
 163         if (ret != 0) {
 164                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
 165                         ret);
 166         } else if (val & ARIZONA_SPK_OVERHEAT_WARN_STS) {
 167                 dev_crit(arizona->dev, "Thermal warning\n");
 168         }
 169
 170         return IRQ_HANDLED;
 171 }
 172
 173 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
 174 {
 175         struct arizona *arizona = data;
 176         unsigned int val;
 177         int ret;
 178
 179         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
 180                           &val);
 181         if (ret != 0) {
 182                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
 183                         ret);
 184         } else if (val & ARIZONA_SPK_OVERHEAT_STS) {
 185                 dev_crit(arizona->dev, "Thermal shutdown\n");
 186                 ret = regmap_update_bits(arizona->regmap,
 187                                          ARIZONA_OUTPUT_ENABLES_1,
 188                                          ARIZONA_OUT4L_ENA |
 189                                          ARIZONA_OUT4R_ENA, 0);
 190                 if (ret != 0)
 191                         dev_crit(arizona->dev,
 192                                  "Failed to disable speaker outputs: %d\n",
 193                                  ret);
 194         }
 195
 196         return IRQ_HANDLED;
 197 }
 198
 199 static const struct snd_soc_dapm_widget arizona_spkl =
 200         SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
 201                            ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
 202                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
 203
 204 static const struct snd_soc_dapm_widget arizona_spkr =
 205         SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
 206                            ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
 207                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
 208
 209 int arizona_init_spk(struct snd_soc_codec *codec)
 210 {
 211         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 212         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 213         struct arizona *arizona = priv->arizona;
 214         int ret;
 215
 216         ret = snd_soc_dapm_new_controls(dapm, &arizona_spkl, 1);
 217         if (ret != 0)
 218                 return ret;
 219
 220         switch (arizona->type) {
 221         case WM8997:
 222                 break;
 223         default:
 224                 ret = snd_soc_dapm_new_controls(dapm, &arizona_spkr, 1);
 225                 if (ret != 0)
 226                         return ret;
 227                 break;
 228         }
 229
 230         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN,
 231                                   "Thermal warning", arizona_thermal_warn,
 232                                   arizona);
 233         if (ret != 0)
 234                 dev_err(arizona->dev,
 235                         "Failed to get thermal warning IRQ: %d\n",
 236                         ret);
 237
 238         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT,
 239                                   "Thermal shutdown", arizona_thermal_shutdown,
 240                                   arizona);
 241         if (ret != 0)
 242                 dev_err(arizona->dev,
 243                         "Failed to get thermal shutdown IRQ: %d\n",
 244                         ret);
 245
 246         return 0;
 247 }
 248 EXPORT_SYMBOL_GPL(arizona_init_spk);
 249
 250 static const struct snd_soc_dapm_route arizona_mono_routes[] = {
 251         { "OUT1R", NULL, "OUT1L" },
 252         { "OUT2R", NULL, "OUT2L" },
 253         { "OUT3R", NULL, "OUT3L" },
 254         { "OUT4R", NULL, "OUT4L" },
 255         { "OUT5R", NULL, "OUT5L" },
 256         { "OUT6R", NULL, "OUT6L" },
 257 };
 258
 259 int arizona_init_mono(struct snd_soc_codec *codec)
 260 {
 261         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 262         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 263         struct arizona *arizona = priv->arizona;
 264         int i;
 265
 266         for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) {
 267                 if (arizona->pdata.out_mono[i])
 268                         snd_soc_dapm_add_routes(dapm,
 269                                                 &arizona_mono_routes[i], 1);
 270         }
 271
 272         return 0;
 273 }
 274 EXPORT_SYMBOL_GPL(arizona_init_mono);
 275
 276 int arizona_init_gpio(struct snd_soc_codec *codec)
 277 {
 278         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 279         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 280         struct arizona *arizona = priv->arizona;
 281         int i;
 282
 283         switch (arizona->type) {
 284         case WM5110:
 285         case WM8280:
 286                 snd_soc_dapm_disable_pin(dapm, "DRC2 Signal Activity");
 287                 break;
 288         default:
 289                 break;
 290         }
 291
 292         snd_soc_dapm_disable_pin(dapm, "DRC1 Signal Activity");
 293
 294         for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
 295                 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
 296                 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
 297                         snd_soc_dapm_enable_pin(dapm, "DRC1 Signal Activity");
 298                         break;
 299                 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
 300                         snd_soc_dapm_enable_pin(dapm, "DRC2 Signal Activity");
 301                         break;
 302                 default:
 303                         break;
 304                 }
 305         }
 306
 307         return 0;
 308 }
 309 EXPORT_SYMBOL_GPL(arizona_init_gpio);
 310
 311 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
 312         "None",
 313         "Tone Generator 1",
 314         "Tone Generator 2",
 315         "Haptics",
 316         "AEC",
 317         "Mic Mute Mixer",
 318         "Noise Generator",
 319         "IN1L",
 320         "IN1R",
 321         "IN2L",
 322         "IN2R",
 323         "IN3L",
 324         "IN3R",
 325         "IN4L",
 326         "IN4R",
 327         "AIF1RX1",
 328         "AIF1RX2",
 329         "AIF1RX3",
 330         "AIF1RX4",
 331         "AIF1RX5",
 332         "AIF1RX6",
 333         "AIF1RX7",
 334         "AIF1RX8",
 335         "AIF2RX1",
 336         "AIF2RX2",
 337         "AIF2RX3",
 338         "AIF2RX4",
 339         "AIF2RX5",
 340         "AIF2RX6",
 341         "AIF3RX1",
 342         "AIF3RX2",
 343         "SLIMRX1",
 344         "SLIMRX2",
 345         "SLIMRX3",
 346         "SLIMRX4",
 347         "SLIMRX5",
 348         "SLIMRX6",
 349         "SLIMRX7",
 350         "SLIMRX8",
 351         "EQ1",
 352         "EQ2",
 353         "EQ3",
 354         "EQ4",
 355         "DRC1L",
 356         "DRC1R",
 357         "DRC2L",
 358         "DRC2R",
 359         "LHPF1",
 360         "LHPF2",
 361         "LHPF3",
 362         "LHPF4",
 363         "DSP1.1",
 364         "DSP1.2",
 365         "DSP1.3",
 366         "DSP1.4",
 367         "DSP1.5",
 368         "DSP1.6",
 369         "DSP2.1",
 370         "DSP2.2",
 371         "DSP2.3",
 372         "DSP2.4",
 373         "DSP2.5",
 374         "DSP2.6",
 375         "DSP3.1",
 376         "DSP3.2",
 377         "DSP3.3",
 378         "DSP3.4",
 379         "DSP3.5",
 380         "DSP3.6",
 381         "DSP4.1",
 382         "DSP4.2",
 383         "DSP4.3",
 384         "DSP4.4",
 385         "DSP4.5",
 386         "DSP4.6",
 387         "ASRC1L",
 388         "ASRC1R",
 389         "ASRC2L",
 390         "ASRC2R",
 391         "ISRC1INT1",
 392         "ISRC1INT2",
 393         "ISRC1INT3",
 394         "ISRC1INT4",
 395         "ISRC1DEC1",
 396         "ISRC1DEC2",
 397         "ISRC1DEC3",
 398         "ISRC1DEC4",
 399         "ISRC2INT1",
 400         "ISRC2INT2",
 401         "ISRC2INT3",
 402         "ISRC2INT4",
 403         "ISRC2DEC1",
 404         "ISRC2DEC2",
 405         "ISRC2DEC3",
 406         "ISRC2DEC4",
 407         "ISRC3INT1",
 408         "ISRC3INT2",
 409         "ISRC3INT3",
 410         "ISRC3INT4",
 411         "ISRC3DEC1",
 412         "ISRC3DEC2",
 413         "ISRC3DEC3",
 414         "ISRC3DEC4",
 415 };
 416 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
 417
 418 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
 419         0x00,  /* None */
 420         0x04,  /* Tone */
 421         0x05,
 422         0x06,  /* Haptics */
 423         0x08,  /* AEC */
 424         0x0c,  /* Noise mixer */
 425         0x0d,  /* Comfort noise */
 426         0x10,  /* IN1L */
 427         0x11,
 428         0x12,
 429         0x13,
 430         0x14,
 431         0x15,
 432         0x16,
 433         0x17,
 434         0x20,  /* AIF1RX1 */
 435         0x21,
 436         0x22,
 437         0x23,
 438         0x24,
 439         0x25,
 440         0x26,
 441         0x27,
 442         0x28,  /* AIF2RX1 */
 443         0x29,
 444         0x2a,
 445         0x2b,
 446         0x2c,
 447         0x2d,
 448         0x30,  /* AIF3RX1 */
 449         0x31,
 450         0x38,  /* SLIMRX1 */
 451         0x39,
 452         0x3a,
 453         0x3b,
 454         0x3c,
 455         0x3d,
 456         0x3e,
 457         0x3f,
 458         0x50,  /* EQ1 */
 459         0x51,
 460         0x52,
 461         0x53,
 462         0x58,  /* DRC1L */
 463         0x59,
 464         0x5a,
 465         0x5b,
 466         0x60,  /* LHPF1 */
 467         0x61,
 468         0x62,
 469         0x63,
 470         0x68,  /* DSP1.1 */
 471         0x69,
 472         0x6a,
 473         0x6b,
 474         0x6c,
 475         0x6d,
 476         0x70,  /* DSP2.1 */
 477         0x71,
 478         0x72,
 479         0x73,
 480         0x74,
 481         0x75,
 482         0x78,  /* DSP3.1 */
 483         0x79,
 484         0x7a,
 485         0x7b,
 486         0x7c,
 487         0x7d,
 488         0x80,  /* DSP4.1 */
 489         0x81,
 490         0x82,
 491         0x83,
 492         0x84,
 493         0x85,
 494         0x90,  /* ASRC1L */
 495         0x91,
 496         0x92,
 497         0x93,
 498         0xa0,  /* ISRC1INT1 */
 499         0xa1,
 500         0xa2,
 501         0xa3,
 502         0xa4,  /* ISRC1DEC1 */
 503         0xa5,
 504         0xa6,
 505         0xa7,
 506         0xa8,  /* ISRC2DEC1 */
 507         0xa9,
 508         0xaa,
 509         0xab,
 510         0xac,  /* ISRC2INT1 */
 511         0xad,
 512         0xae,
 513         0xaf,
 514         0xb0,  /* ISRC3DEC1 */
 515         0xb1,
 516         0xb2,
 517         0xb3,
 518         0xb4,  /* ISRC3INT1 */
 519         0xb5,
 520         0xb6,
 521         0xb7,
 522 };
 523 EXPORT_SYMBOL_GPL(arizona_mixer_values);
 524
 525 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
 526 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
 527
 528 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
 529         "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
 530 };
 531 EXPORT_SYMBOL_GPL(arizona_rate_text);
 532
 533 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
 534         0, 1, 2, 8,
 535 };
 536 EXPORT_SYMBOL_GPL(arizona_rate_val);
 537
 538
 539 const struct soc_enum arizona_isrc_fsh[] = {
 540         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1,
 541                               ARIZONA_ISRC1_FSH_SHIFT, 0xf,
 542                               ARIZONA_RATE_ENUM_SIZE,
 543                               arizona_rate_text, arizona_rate_val),
 544         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1,
 545                               ARIZONA_ISRC2_FSH_SHIFT, 0xf,
 546                               ARIZONA_RATE_ENUM_SIZE,
 547                               arizona_rate_text, arizona_rate_val),
 548         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1,
 549                               ARIZONA_ISRC3_FSH_SHIFT, 0xf,
 550                               ARIZONA_RATE_ENUM_SIZE,
 551                               arizona_rate_text, arizona_rate_val),
 552 };
 553 EXPORT_SYMBOL_GPL(arizona_isrc_fsh);
 554
 555 const struct soc_enum arizona_isrc_fsl[] = {
 556         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
 557                               ARIZONA_ISRC1_FSL_SHIFT, 0xf,
 558                               ARIZONA_RATE_ENUM_SIZE,
 559                               arizona_rate_text, arizona_rate_val),
 560         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
 561                               ARIZONA_ISRC2_FSL_SHIFT, 0xf,
 562                               ARIZONA_RATE_ENUM_SIZE,
 563                               arizona_rate_text, arizona_rate_val),
 564         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
 565                               ARIZONA_ISRC3_FSL_SHIFT, 0xf,
 566                               ARIZONA_RATE_ENUM_SIZE,
 567                               arizona_rate_text, arizona_rate_val),
 568 };
 569 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
 570
 571 const struct soc_enum arizona_asrc_rate1 =
 572         SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1,
 573                               ARIZONA_ASRC_RATE1_SHIFT, 0xf,
 574                               ARIZONA_RATE_ENUM_SIZE - 1,
 575                               arizona_rate_text, arizona_rate_val);
 576 EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
 577
 578 static const char *arizona_vol_ramp_text[] = {
 579         "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
 580         "15ms/6dB", "30ms/6dB",
 581 };
 582
 583 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp,
 584                      ARIZONA_INPUT_VOLUME_RAMP,
 585                      ARIZONA_IN_VD_RAMP_SHIFT,
 586                      arizona_vol_ramp_text);
 587 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
 588
 589 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp,
 590                      ARIZONA_INPUT_VOLUME_RAMP,
 591                      ARIZONA_IN_VI_RAMP_SHIFT,
 592                      arizona_vol_ramp_text);
 593 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
 594
 595 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp,
 596                      ARIZONA_OUTPUT_VOLUME_RAMP,
 597                      ARIZONA_OUT_VD_RAMP_SHIFT,
 598                      arizona_vol_ramp_text);
 599 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
 600
 601 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
 602                      ARIZONA_OUTPUT_VOLUME_RAMP,
 603                      ARIZONA_OUT_VI_RAMP_SHIFT,
 604                      arizona_vol_ramp_text);
 605 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
 606
 607 static const char *arizona_lhpf_mode_text[] = {
 608         "Low-pass", "High-pass"
 609 };
 610
 611 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode,
 612                      ARIZONA_HPLPF1_1,
 613                      ARIZONA_LHPF1_MODE_SHIFT,
 614                      arizona_lhpf_mode_text);
 615 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
 616
 617 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode,
 618                      ARIZONA_HPLPF2_1,
 619                      ARIZONA_LHPF2_MODE_SHIFT,
 620                      arizona_lhpf_mode_text);
 621 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
 622
 623 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode,
 624                      ARIZONA_HPLPF3_1,
 625                      ARIZONA_LHPF3_MODE_SHIFT,
 626                      arizona_lhpf_mode_text);
 627 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
 628
 629 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
 630                      ARIZONA_HPLPF4_1,
 631                      ARIZONA_LHPF4_MODE_SHIFT,
 632                      arizona_lhpf_mode_text);
 633 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
 634
 635 static const char *arizona_ng_hold_text[] = {
 636         "30ms", "120ms", "250ms", "500ms",
 637 };
 638
 639 SOC_ENUM_SINGLE_DECL(arizona_ng_hold,
 640                      ARIZONA_NOISE_GATE_CONTROL,
 641                      ARIZONA_NGATE_HOLD_SHIFT,
 642                      arizona_ng_hold_text);
 643 EXPORT_SYMBOL_GPL(arizona_ng_hold);
 644
 645 static const char * const arizona_in_hpf_cut_text[] = {
 646         "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
 647 };
 648
 649 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum,
 650                      ARIZONA_HPF_CONTROL,
 651                      ARIZONA_IN_HPF_CUT_SHIFT,
 652                      arizona_in_hpf_cut_text);
 653 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum);
 654
 655 static const char * const arizona_in_dmic_osr_text[] = {
 656         "1.536MHz", "3.072MHz", "6.144MHz", "768kHz",
 657 };
 658
 659 const struct soc_enum arizona_in_dmic_osr[] = {
 660         SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
 661                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 662                         arizona_in_dmic_osr_text),
 663         SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
 664                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 665                         arizona_in_dmic_osr_text),
 666         SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
 667                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 668                         arizona_in_dmic_osr_text),
 669         SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
 670                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 671                         arizona_in_dmic_osr_text),
 672 };
 673 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
 674
 675 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
 676 {
 677         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 678         unsigned int val;
 679         int i;
 680
 681         if (ena)
 682                 val = ARIZONA_IN_VU;
 683         else
 684                 val = 0;
 685
 686         for (i = 0; i < priv->num_inputs; i++)
 687                 snd_soc_update_bits(codec,
 688                                     ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
 689                                     ARIZONA_IN_VU, val);
 690 }
 691
 692 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
 693                   int event)
 694 {
 695         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 696         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 697         unsigned int reg;
 698
 699         if (w->shift % 2)
 700                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
 701         else
 702                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
 703
 704         switch (event) {
 705         case SND_SOC_DAPM_PRE_PMU:
 706                 priv->in_pending++;
 707                 break;
 708         case SND_SOC_DAPM_POST_PMU:
 709                 snd_soc_update_bits(codec, reg, ARIZONA_IN1L_MUTE, 0);
 710
 711                 /* If this is the last input pending then allow VU */
 712                 priv->in_pending--;
 713                 if (priv->in_pending == 0) {
 714                         msleep(1);
 715                         arizona_in_set_vu(codec, 1);
 716                 }
 717                 break;
 718         case SND_SOC_DAPM_PRE_PMD:
 719                 snd_soc_update_bits(codec, reg,
 720                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
 721                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
 722                 break;
 723         case SND_SOC_DAPM_POST_PMD:
 724                 /* Disable volume updates if no inputs are enabled */
 725                 reg = snd_soc_read(codec, ARIZONA_INPUT_ENABLES);
 726                 if (reg == 0)
 727                         arizona_in_set_vu(codec, 0);
 728         }
 729
 730         return 0;
 731 }
 732 EXPORT_SYMBOL_GPL(arizona_in_ev);
 733
 734 int arizona_out_ev(struct snd_soc_dapm_widget *w,
 735                    struct snd_kcontrol *kcontrol,
 736                    int event)
 737 {
 738         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 739         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 740
 741         switch (event) {
 742         case SND_SOC_DAPM_PRE_PMU:
 743                 switch (w->shift) {
 744                 case ARIZONA_OUT1L_ENA_SHIFT:
 745                 case ARIZONA_OUT1R_ENA_SHIFT:
 746                 case ARIZONA_OUT2L_ENA_SHIFT:
 747                 case ARIZONA_OUT2R_ENA_SHIFT:
 748                 case ARIZONA_OUT3L_ENA_SHIFT:
 749                 case ARIZONA_OUT3R_ENA_SHIFT:
 750                         priv->out_up_pending++;
 751                         priv->out_up_delay += 17;
 752                         break;
 753                 default:
 754                         break;
 755                 }
 756                 break;
 757         case SND_SOC_DAPM_POST_PMU:
 758                 switch (w->shift) {
 759                 case ARIZONA_OUT1L_ENA_SHIFT:
 760                 case ARIZONA_OUT1R_ENA_SHIFT:
 761                 case ARIZONA_OUT2L_ENA_SHIFT:
 762                 case ARIZONA_OUT2R_ENA_SHIFT:
 763                 case ARIZONA_OUT3L_ENA_SHIFT:
 764                 case ARIZONA_OUT3R_ENA_SHIFT:
 765                         priv->out_up_pending--;
 766                         if (!priv->out_up_pending) {
 767                                 msleep(priv->out_up_delay);
 768                                 priv->out_up_delay = 0;
 769                         }
 770                         break;
 771
 772                 default:
 773                         break;
 774                 }
 775                 break;
 776         case SND_SOC_DAPM_PRE_PMD:
 777                 switch (w->shift) {
 778                 case ARIZONA_OUT1L_ENA_SHIFT:
 779                 case ARIZONA_OUT1R_ENA_SHIFT:
 780                 case ARIZONA_OUT2L_ENA_SHIFT:
 781                 case ARIZONA_OUT2R_ENA_SHIFT:
 782                 case ARIZONA_OUT3L_ENA_SHIFT:
 783                 case ARIZONA_OUT3R_ENA_SHIFT:
 784                         priv->out_down_pending++;
 785                         priv->out_down_delay++;
 786                         break;
 787                 default:
 788                         break;
 789                 }
 790                 break;
 791         case SND_SOC_DAPM_POST_PMD:
 792                 switch (w->shift) {
 793                 case ARIZONA_OUT1L_ENA_SHIFT:
 794                 case ARIZONA_OUT1R_ENA_SHIFT:
 795                 case ARIZONA_OUT2L_ENA_SHIFT:
 796                 case ARIZONA_OUT2R_ENA_SHIFT:
 797                 case ARIZONA_OUT3L_ENA_SHIFT:
 798                 case ARIZONA_OUT3R_ENA_SHIFT:
 799                         priv->out_down_pending--;
 800                         if (!priv->out_down_pending) {
 801                                 msleep(priv->out_down_delay);
 802                                 priv->out_down_delay = 0;
 803                         }
 804                         break;
 805                 default:
 806                         break;
 807                 }
 808                 break;
 809         }
 810
 811         return 0;
 812 }
 813 EXPORT_SYMBOL_GPL(arizona_out_ev);
 814
 815 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
 816                    struct snd_kcontrol *kcontrol,
 817                    int event)
 818 {
 819         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 820         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 821         struct arizona *arizona = priv->arizona;
 822         unsigned int mask = 1 << w->shift;
 823         unsigned int val;
 824
 825         switch (event) {
 826         case SND_SOC_DAPM_POST_PMU:
 827                 val = mask;
 828                 break;
 829         case SND_SOC_DAPM_PRE_PMD:
 830                 val = 0;
 831                 break;
 832         case SND_SOC_DAPM_PRE_PMU:
 833         case SND_SOC_DAPM_POST_PMD:
 834                 return arizona_out_ev(w, kcontrol, event);
 835         default:
 836                 return -EINVAL;
 837         }
 838
 839         /* Store the desired state for the HP outputs */
 840         priv->arizona->hp_ena &= ~mask;
 841         priv->arizona->hp_ena |= val;
 842
 843         /* Force off if HPDET clamp is active */
 844         if (priv->arizona->hpdet_clamp)
 845                 val = 0;
 846
 847         regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
 848                                  mask, val);
 849
 850         return arizona_out_ev(w, kcontrol, event);
 851 }
 852 EXPORT_SYMBOL_GPL(arizona_hp_ev);
 853
 854 static int arizona_dvfs_enable(struct snd_soc_codec *codec)
 855 {
 856         const struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 857         struct arizona *arizona = priv->arizona;
 858         int ret;
 859
 860         ret = regulator_set_voltage(arizona->dcvdd, 1800000, 1800000);
 861         if (ret) {
 862                 dev_err(codec->dev, "Failed to boost DCVDD: %d\n", ret);
 863                 return ret;
 864         }
 865
 866         ret = regmap_update_bits(arizona->regmap,
 867                                  ARIZONA_DYNAMIC_FREQUENCY_SCALING_1,
 868                                  ARIZONA_SUBSYS_MAX_FREQ,
 869                                  ARIZONA_SUBSYS_MAX_FREQ);
 870         if (ret) {
 871                 dev_err(codec->dev, "Failed to enable subsys max: %d\n", ret);
 872                 regulator_set_voltage(arizona->dcvdd, 1200000, 1800000);
 873                 return ret;
 874         }
 875
 876         return 0;
 877 }
 878
 879 static int arizona_dvfs_disable(struct snd_soc_codec *codec)
 880 {
 881         const struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 882         struct arizona *arizona = priv->arizona;
 883         int ret;
 884
 885         ret = regmap_update_bits(arizona->regmap,
 886                                  ARIZONA_DYNAMIC_FREQUENCY_SCALING_1,
 887                                  ARIZONA_SUBSYS_MAX_FREQ, 0);
 888         if (ret) {
 889                 dev_err(codec->dev, "Failed to disable subsys max: %d\n", ret);
 890                 return ret;
 891         }
 892
 893         ret = regulator_set_voltage(arizona->dcvdd, 1200000, 1800000);
 894         if (ret) {
 895                 dev_err(codec->dev, "Failed to unboost DCVDD: %d\n", ret);
 896                 return ret;
 897         }
 898
 899         return 0;
 900 }
 901
 902 int arizona_dvfs_up(struct snd_soc_codec *codec, unsigned int flags)
 903 {
 904         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 905         int ret = 0;
 906
 907         mutex_lock(&priv->dvfs_lock);
 908
 909         if (!priv->dvfs_cached && !priv->dvfs_reqs) {
 910                 ret = arizona_dvfs_enable(codec);
 911                 if (ret)
 912                         goto err;
 913         }
 914
 915         priv->dvfs_reqs |= flags;
 916 err:
 917         mutex_unlock(&priv->dvfs_lock);
 918         return ret;
 919 }
 920 EXPORT_SYMBOL_GPL(arizona_dvfs_up);
 921
 922 int arizona_dvfs_down(struct snd_soc_codec *codec, unsigned int flags)
 923 {
 924         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 925         unsigned int old_reqs;
 926         int ret = 0;
 927
 928         mutex_lock(&priv->dvfs_lock);
 929
 930         old_reqs = priv->dvfs_reqs;
 931         priv->dvfs_reqs &= ~flags;
 932
 933         if (!priv->dvfs_cached && old_reqs && !priv->dvfs_reqs)
 934                 ret = arizona_dvfs_disable(codec);
 935
 936         mutex_unlock(&priv->dvfs_lock);
 937         return ret;
 938 }
 939 EXPORT_SYMBOL_GPL(arizona_dvfs_down);
 940
 941 int arizona_dvfs_sysclk_ev(struct snd_soc_dapm_widget *w,
 942                            struct snd_kcontrol *kcontrol, int event)
 943 {
 944         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 945         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 946         int ret = 0;
 947
 948         mutex_lock(&priv->dvfs_lock);
 949
 950         switch (event) {
 951         case SND_SOC_DAPM_POST_PMU:
 952                 if (priv->dvfs_reqs)
 953                         ret = arizona_dvfs_enable(codec);
 954
 955                 priv->dvfs_cached = false;
 956                 break;
 957         case SND_SOC_DAPM_PRE_PMD:
 958                 /* We must ensure DVFS is disabled before the codec goes into
 959                  * suspend so that we are never in an illegal state of DVFS
 960                  * enabled without enough DCVDD
 961                  */
 962                 priv->dvfs_cached = true;
 963
 964                 if (priv->dvfs_reqs)
 965                         ret = arizona_dvfs_disable(codec);
 966                 break;
 967         default:
 968                 break;
 969         }
 970
 971         mutex_unlock(&priv->dvfs_lock);
 972         return ret;
 973 }
 974 EXPORT_SYMBOL_GPL(arizona_dvfs_sysclk_ev);
 975
 976 void arizona_init_dvfs(struct arizona_priv *priv)
 977 {
 978         mutex_init(&priv->dvfs_lock);
 979 }
 980 EXPORT_SYMBOL_GPL(arizona_init_dvfs);
 981
 982 static unsigned int arizona_sysclk_48k_rates[] = {
 983         6144000,
 984         12288000,
 985         24576000,
 986         49152000,
 987         73728000,
 988         98304000,
 989         147456000,
 990 };
 991
 992 static unsigned int arizona_sysclk_44k1_rates[] = {
 993         5644800,
 994         11289600,
 995         22579200,
 996         45158400,
 997         67737600,
 998         90316800,
 999         135475200,
1000 };
1001
1002 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
1003                              unsigned int freq)
1004 {
1005         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1006         unsigned int reg;
1007         unsigned int *rates;
1008         int ref, div, refclk;
1009
1010         switch (clk) {
1011         case ARIZONA_CLK_OPCLK:
1012                 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
1013                 refclk = priv->sysclk;
1014                 break;
1015         case ARIZONA_CLK_ASYNC_OPCLK:
1016                 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
1017                 refclk = priv->asyncclk;
1018                 break;
1019         default:
1020                 return -EINVAL;
1021         }
1022
1023         if (refclk % 8000)
1024                 rates = arizona_sysclk_44k1_rates;
1025         else
1026                 rates = arizona_sysclk_48k_rates;
1027
1028         for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
1029                      rates[ref] <= refclk; ref++) {
1030                 div = 1;
1031                 while (rates[ref] / div >= freq && div < 32) {
1032                         if (rates[ref] / div == freq) {
1033                                 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
1034                                         freq);
1035                                 snd_soc_update_bits(codec, reg,
1036                                                     ARIZONA_OPCLK_DIV_MASK |
1037                                                     ARIZONA_OPCLK_SEL_MASK,
1038                                                     (div <<
1039                                                      ARIZONA_OPCLK_DIV_SHIFT) |
1040                                                     ref);
1041                                 return 0;
1042                         }
1043                         div++;
1044                 }
1045         }
1046
1047         dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
1048         return -EINVAL;
1049 }
1050
1051 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1052                        int source, unsigned int freq, int dir)
1053 {
1054         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1055         struct arizona *arizona = priv->arizona;
1056         char *name;
1057         unsigned int reg;
1058         unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
1059         unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
1060         unsigned int *clk;
1061
1062         switch (clk_id) {
1063         case ARIZONA_CLK_SYSCLK:
1064                 name = "SYSCLK";
1065                 reg = ARIZONA_SYSTEM_CLOCK_1;
1066                 clk = &priv->sysclk;
1067                 mask |= ARIZONA_SYSCLK_FRAC;
1068                 break;
1069         case ARIZONA_CLK_ASYNCCLK:
1070                 name = "ASYNCCLK";
1071                 reg = ARIZONA_ASYNC_CLOCK_1;
1072                 clk = &priv->asyncclk;
1073                 break;
1074         case ARIZONA_CLK_OPCLK:
1075         case ARIZONA_CLK_ASYNC_OPCLK:
1076                 return arizona_set_opclk(codec, clk_id, freq);
1077         default:
1078                 return -EINVAL;
1079         }
1080
1081         switch (freq) {
1082         case  5644800:
1083         case  6144000:
1084                 break;
1085         case 11289600:
1086         case 12288000:
1087                 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1088                 break;
1089         case 22579200:
1090         case 24576000:
1091                 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1092                 break;
1093         case 45158400:
1094         case 49152000:
1095                 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1096                 break;
1097         case 67737600:
1098         case 73728000:
1099                 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1100                 break;
1101         case 90316800:
1102         case 98304000:
1103                 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1104                 break;
1105         case 135475200:
1106         case 147456000:
1107                 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1108                 break;
1109         case 0:
1110                 dev_dbg(arizona->dev, "%s cleared\n", name);
1111                 *clk = freq;
1112                 return 0;
1113         default:
1114                 return -EINVAL;
1115         }
1116
1117         *clk = freq;
1118
1119         if (freq % 6144000)
1120                 val |= ARIZONA_SYSCLK_FRAC;
1121
1122         dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
1123
1124         return regmap_update_bits(arizona->regmap, reg, mask, val);
1125 }
1126 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
1127
1128 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1129 {
1130         struct snd_soc_codec *codec = dai->codec;
1131         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1132         struct arizona *arizona = priv->arizona;
1133         int lrclk, bclk, mode, base;
1134
1135         base = dai->driver->base;
1136
1137         lrclk = 0;
1138         bclk = 0;
1139
1140         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1141         case SND_SOC_DAIFMT_DSP_A:
1142                 mode = ARIZONA_FMT_DSP_MODE_A;
1143                 break;
1144         case SND_SOC_DAIFMT_DSP_B:
1145                 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK)
1146                                 != SND_SOC_DAIFMT_CBM_CFM) {
1147                         arizona_aif_err(dai, "DSP_B not valid in slave mode\n");
1148                         return -EINVAL;
1149                 }
1150                 mode = ARIZONA_FMT_DSP_MODE_B;
1151                 break;
1152         case SND_SOC_DAIFMT_I2S:
1153                 mode = ARIZONA_FMT_I2S_MODE;
1154                 break;
1155         case SND_SOC_DAIFMT_LEFT_J:
1156                 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK)
1157                                 != SND_SOC_DAIFMT_CBM_CFM) {
1158                         arizona_aif_err(dai, "LEFT_J not valid in slave mode\n");
1159                         return -EINVAL;
1160                 }
1161                 mode = ARIZONA_FMT_LEFT_JUSTIFIED_MODE;
1162                 break;
1163         default:
1164                 arizona_aif_err(dai, "Unsupported DAI format %d\n",
1165                                 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1166                 return -EINVAL;
1167         }
1168
1169         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1170         case SND_SOC_DAIFMT_CBS_CFS:
1171                 break;
1172         case SND_SOC_DAIFMT_CBS_CFM:
1173                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
1174                 break;
1175         case SND_SOC_DAIFMT_CBM_CFS:
1176                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
1177                 break;
1178         case SND_SOC_DAIFMT_CBM_CFM:
1179                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
1180                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
1181                 break;
1182         default:
1183                 arizona_aif_err(dai, "Unsupported master mode %d\n",
1184                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1185                 return -EINVAL;
1186         }
1187
1188         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1189         case SND_SOC_DAIFMT_NB_NF:
1190                 break;
1191         case SND_SOC_DAIFMT_IB_IF:
1192                 bclk |= ARIZONA_AIF1_BCLK_INV;
1193                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
1194                 break;
1195         case SND_SOC_DAIFMT_IB_NF:
1196                 bclk |= ARIZONA_AIF1_BCLK_INV;
1197                 break;
1198         case SND_SOC_DAIFMT_NB_IF:
1199                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
1200                 break;
1201         default:
1202                 return -EINVAL;
1203         }
1204
1205         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
1206                                  ARIZONA_AIF1_BCLK_INV |
1207                                  ARIZONA_AIF1_BCLK_MSTR,
1208                                  bclk);
1209         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
1210                                  ARIZONA_AIF1TX_LRCLK_INV |
1211                                  ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
1212         regmap_update_bits_async(arizona->regmap,
1213                                  base + ARIZONA_AIF_RX_PIN_CTRL,
1214                                  ARIZONA_AIF1RX_LRCLK_INV |
1215                                  ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
1216         regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
1217                            ARIZONA_AIF1_FMT_MASK, mode);
1218
1219         return 0;
1220 }
1221
1222 static const int arizona_48k_bclk_rates[] = {
1223         -1,
1224         48000,
1225         64000,
1226         96000,
1227         128000,
1228         192000,
1229         256000,
1230         384000,
1231         512000,
1232         768000,
1233         1024000,
1234         1536000,
1235         2048000,
1236         3072000,
1237         4096000,
1238         6144000,
1239         8192000,
1240         12288000,
1241         24576000,
1242 };
1243
1244 static const unsigned int arizona_48k_rates[] = {
1245         12000,
1246         24000,
1247         48000,
1248         96000,
1249         192000,
1250         384000,
1251         768000,
1252         4000,
1253         8000,
1254         16000,
1255         32000,
1256         64000,
1257         128000,
1258         256000,
1259         512000,
1260 };
1261
1262 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
1263         .count  = ARRAY_SIZE(arizona_48k_rates),
1264         .list   = arizona_48k_rates,
1265 };
1266
1267 static const int arizona_44k1_bclk_rates[] = {
1268         -1,
1269         44100,
1270         58800,
1271         88200,
1272         117600,
1273         177640,
1274         235200,
1275         352800,
1276         470400,
1277         705600,
1278         940800,
1279         1411200,
1280         1881600,
1281         2822400,
1282         3763200,
1283         5644800,
1284         7526400,
1285         11289600,
1286         22579200,
1287 };
1288
1289 static const unsigned int arizona_44k1_rates[] = {
1290         11025,
1291         22050,
1292         44100,
1293         88200,
1294         176400,
1295         352800,
1296         705600,
1297 };
1298
1299 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
1300         .count  = ARRAY_SIZE(arizona_44k1_rates),
1301         .list   = arizona_44k1_rates,
1302 };
1303
1304 static int arizona_sr_vals[] = {
1305         0,
1306         12000,
1307         24000,
1308         48000,
1309         96000,
1310         192000,
1311         384000,
1312         768000,
1313         0,
1314         11025,
1315         22050,
1316         44100,
1317         88200,
1318         176400,
1319         352800,
1320         705600,
1321         4000,
1322         8000,
1323         16000,
1324         32000,
1325         64000,
1326         128000,
1327         256000,
1328         512000,
1329 };
1330
1331 static int arizona_startup(struct snd_pcm_substream *substream,
1332                            struct snd_soc_dai *dai)
1333 {
1334         struct snd_soc_codec *codec = dai->codec;
1335         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1336         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1337         const struct snd_pcm_hw_constraint_list *constraint;
1338         unsigned int base_rate;
1339
1340         switch (dai_priv->clk) {
1341         case ARIZONA_CLK_SYSCLK:
1342                 base_rate = priv->sysclk;
1343                 break;
1344         case ARIZONA_CLK_ASYNCCLK:
1345                 base_rate = priv->asyncclk;
1346                 break;
1347         default:
1348                 return 0;
1349         }
1350
1351         if (base_rate == 0)
1352                 return 0;
1353
1354         if (base_rate % 8000)
1355                 constraint = &arizona_44k1_constraint;
1356         else
1357                 constraint = &arizona_48k_constraint;
1358
1359         return snd_pcm_hw_constraint_list(substream->runtime, 0,
1360                                           SNDRV_PCM_HW_PARAM_RATE,
1361                                           constraint);
1362 }
1363
1364 static void arizona_wm5102_set_dac_comp(struct snd_soc_codec *codec,
1365                                         unsigned int rate)
1366 {
1367         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1368         struct arizona *arizona = priv->arizona;
1369         struct reg_default dac_comp[] = {
1370                 { 0x80, 0x3 },
1371                 { ARIZONA_DAC_COMP_1, 0 },
1372                 { ARIZONA_DAC_COMP_2, 0 },
1373                 { 0x80, 0x0 },
1374         };
1375
1376         mutex_lock(&arizona->dac_comp_lock);
1377
1378         dac_comp[1].def = arizona->dac_comp_coeff;
1379         if (rate >= 176400)
1380                 dac_comp[2].def = arizona->dac_comp_enabled;
1381
1382         mutex_unlock(&arizona->dac_comp_lock);
1383
1384         regmap_multi_reg_write(arizona->regmap,
1385                                dac_comp,
1386                                ARRAY_SIZE(dac_comp));
1387 }
1388
1389 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1390                                   struct snd_pcm_hw_params *params,
1391                                   struct snd_soc_dai *dai)
1392 {
1393         struct snd_soc_codec *codec = dai->codec;
1394         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1395         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1396         int base = dai->driver->base;
1397         int i, sr_val, ret;
1398
1399         /*
1400          * We will need to be more flexible than this in future,
1401          * currently we use a single sample rate for SYSCLK.
1402          */
1403         for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1404                 if (arizona_sr_vals[i] == params_rate(params))
1405                         break;
1406         if (i == ARRAY_SIZE(arizona_sr_vals)) {
1407                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1408                                 params_rate(params));
1409                 return -EINVAL;
1410         }
1411         sr_val = i;
1412
1413         switch (priv->arizona->type) {
1414         case WM5102:
1415         case WM8997:
1416                 if (arizona_sr_vals[sr_val] >= 88200)
1417                         ret = arizona_dvfs_up(codec, ARIZONA_DVFS_SR1_RQ);
1418                 else
1419                         ret = arizona_dvfs_down(codec, ARIZONA_DVFS_SR1_RQ);
1420
1421                 if (ret) {
1422                         arizona_aif_err(dai, "Failed to change DVFS %d\n", ret);
1423                         return ret;
1424                 }
1425                 break;
1426         default:
1427                 break;
1428         }
1429
1430         switch (dai_priv->clk) {
1431         case ARIZONA_CLK_SYSCLK:
1432                 switch (priv->arizona->type) {
1433                 case WM5102:
1434                         arizona_wm5102_set_dac_comp(codec,
1435                                                     params_rate(params));
1436                         break;
1437                 default:
1438                         break;
1439                 }
1440
1441                 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1442                                     ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1443                 if (base)
1444                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1445                                             ARIZONA_AIF1_RATE_MASK, 0);
1446                 break;
1447         case ARIZONA_CLK_ASYNCCLK:
1448                 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1449                                     ARIZONA_ASYNC_SAMPLE_RATE_1_MASK, sr_val);
1450                 if (base)
1451                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1452                                             ARIZONA_AIF1_RATE_MASK,
1453                                             8 << ARIZONA_AIF1_RATE_SHIFT);
1454                 break;
1455         default:
1456                 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1457                 return -EINVAL;
1458         }
1459
1460         return 0;
1461 }
1462
1463 static bool arizona_aif_cfg_changed(struct snd_soc_codec *codec,
1464                                     int base, int bclk, int lrclk, int frame)
1465 {
1466         int val;
1467
1468         val = snd_soc_read(codec, base + ARIZONA_AIF_BCLK_CTRL);
1469         if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK))
1470                 return true;
1471
1472         val = snd_soc_read(codec, base + ARIZONA_AIF_TX_BCLK_RATE);
1473         if (lrclk != (val & ARIZONA_AIF1TX_BCPF_MASK))
1474                 return true;
1475
1476         val = snd_soc_read(codec, base + ARIZONA_AIF_FRAME_CTRL_1);
1477         if (frame != (val & (ARIZONA_AIF1TX_WL_MASK |
1478                              ARIZONA_AIF1TX_SLOT_LEN_MASK)))
1479                 return true;
1480
1481         return false;
1482 }
1483
1484 static int arizona_hw_params(struct snd_pcm_substream *substream,
1485                              struct snd_pcm_hw_params *params,
1486                              struct snd_soc_dai *dai)
1487 {
1488         struct snd_soc_codec *codec = dai->codec;
1489         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1490         struct arizona *arizona = priv->arizona;
1491         int base = dai->driver->base;
1492         const int *rates;
1493         int i, ret, val;
1494         int channels = params_channels(params);
1495         int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1496         int tdm_width = arizona->tdm_width[dai->id - 1];
1497         int tdm_slots = arizona->tdm_slots[dai->id - 1];
1498         int bclk, lrclk, wl, frame, bclk_target;
1499         bool reconfig;
1500         unsigned int aif_tx_state, aif_rx_state;
1501
1502         if (params_rate(params) % 8000)
1503                 rates = &arizona_44k1_bclk_rates[0];
1504         else
1505                 rates = &arizona_48k_bclk_rates[0];
1506
1507         wl = snd_pcm_format_width(params_format(params));
1508
1509         if (tdm_slots) {
1510                 arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n",
1511                                 tdm_slots, tdm_width);
1512                 bclk_target = tdm_slots * tdm_width * params_rate(params);
1513                 channels = tdm_slots;
1514         } else {
1515                 bclk_target = snd_soc_params_to_bclk(params);
1516                 tdm_width = wl;
1517         }
1518
1519         if (chan_limit && chan_limit < channels) {
1520                 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1521                 bclk_target /= channels;
1522                 bclk_target *= chan_limit;
1523         }
1524
1525         /* Force multiple of 2 channels for I2S mode */
1526         val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1527         val &= ARIZONA_AIF1_FMT_MASK;
1528         if ((channels & 1) && (val == ARIZONA_FMT_I2S_MODE)) {
1529                 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1530                 bclk_target /= channels;
1531                 bclk_target *= channels + 1;
1532         }
1533
1534         for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1535                 if (rates[i] >= bclk_target &&
1536                     rates[i] % params_rate(params) == 0) {
1537                         bclk = i;
1538                         break;
1539                 }
1540         }
1541         if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1542                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1543                                 params_rate(params));
1544                 return -EINVAL;
1545         }
1546
1547         lrclk = rates[bclk] / params_rate(params);
1548
1549         arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1550                         rates[bclk], rates[bclk] / lrclk);
1551
1552         frame = wl << ARIZONA_AIF1TX_WL_SHIFT | tdm_width;
1553
1554         reconfig = arizona_aif_cfg_changed(codec, base, bclk, lrclk, frame);
1555
1556         if (reconfig) {
1557                 /* Save AIF TX/RX state */
1558                 aif_tx_state = snd_soc_read(codec,
1559                                             base + ARIZONA_AIF_TX_ENABLES);
1560                 aif_rx_state = snd_soc_read(codec,
1561                                             base + ARIZONA_AIF_RX_ENABLES);
1562                 /* Disable AIF TX/RX before reconfiguring it */
1563                 regmap_update_bits_async(arizona->regmap,
1564                                     base + ARIZONA_AIF_TX_ENABLES, 0xff, 0x0);
1565                 regmap_update_bits(arizona->regmap,
1566                                     base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0);
1567         }
1568
1569         ret = arizona_hw_params_rate(substream, params, dai);
1570         if (ret != 0)
1571                 goto restore_aif;
1572
1573         if (reconfig) {
1574                 regmap_update_bits_async(arizona->regmap,
1575                                          base + ARIZONA_AIF_BCLK_CTRL,
1576                                          ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1577                 regmap_update_bits_async(arizona->regmap,
1578                                          base + ARIZONA_AIF_TX_BCLK_RATE,
1579                                          ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1580                 regmap_update_bits_async(arizona->regmap,
1581                                          base + ARIZONA_AIF_RX_BCLK_RATE,
1582                                          ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1583                 regmap_update_bits_async(arizona->regmap,
1584                                          base + ARIZONA_AIF_FRAME_CTRL_1,
1585                                          ARIZONA_AIF1TX_WL_MASK |
1586                                          ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1587                 regmap_update_bits(arizona->regmap,
1588                                    base + ARIZONA_AIF_FRAME_CTRL_2,
1589                                    ARIZONA_AIF1RX_WL_MASK |
1590                                    ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1591         }
1592
1593 restore_aif:
1594         if (reconfig) {
1595                 /* Restore AIF TX/RX state */
1596                 regmap_update_bits_async(arizona->regmap,
1597                                          base + ARIZONA_AIF_TX_ENABLES,
1598                                          0xff, aif_tx_state);
1599                 regmap_update_bits(arizona->regmap,
1600                                    base + ARIZONA_AIF_RX_ENABLES,
1601                                    0xff, aif_rx_state);
1602         }
1603         return ret;
1604 }
1605
1606 static const char *arizona_dai_clk_str(int clk_id)
1607 {
1608         switch (clk_id) {
1609         case ARIZONA_CLK_SYSCLK:
1610                 return "SYSCLK";
1611         case ARIZONA_CLK_ASYNCCLK:
1612                 return "ASYNCCLK";
1613         default:
1614                 return "Unknown clock";
1615         }
1616 }
1617
1618 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1619                                   int clk_id, unsigned int freq, int dir)
1620 {
1621         struct snd_soc_codec *codec = dai->codec;
1622         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1623         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1624         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1625         struct snd_soc_dapm_route routes[2];
1626
1627         switch (clk_id) {
1628         case ARIZONA_CLK_SYSCLK:
1629         case ARIZONA_CLK_ASYNCCLK:
1630                 break;
1631         default:
1632                 return -EINVAL;
1633         }
1634
1635         if (clk_id == dai_priv->clk)
1636                 return 0;
1637
1638         if (dai->active) {
1639                 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1640                         dai->id);
1641                 return -EBUSY;
1642         }
1643
1644         dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1645                 arizona_dai_clk_str(clk_id));
1646
1647         memset(&routes, 0, sizeof(routes));
1648         routes[0].sink = dai->driver->capture.stream_name;
1649         routes[1].sink = dai->driver->playback.stream_name;
1650
1651         routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1652         routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1653         snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
1654
1655         routes[0].source = arizona_dai_clk_str(clk_id);
1656         routes[1].source = arizona_dai_clk_str(clk_id);
1657         snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1658
1659         dai_priv->clk = clk_id;
1660
1661         return snd_soc_dapm_sync(dapm);
1662 }
1663
1664 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1665 {
1666         struct snd_soc_codec *codec = dai->codec;
1667         int base = dai->driver->base;
1668         unsigned int reg;
1669
1670         if (tristate)
1671                 reg = ARIZONA_AIF1_TRI;
1672         else
1673                 reg = 0;
1674
1675         return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1676                                    ARIZONA_AIF1_TRI, reg);
1677 }
1678
1679 static void arizona_set_channels_to_mask(struct snd_soc_dai *dai,
1680                                          unsigned int base,
1681                                          int channels, unsigned int mask)
1682 {
1683         struct snd_soc_codec *codec = dai->codec;
1684         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1685         struct arizona *arizona = priv->arizona;
1686         int slot, i;
1687
1688         for (i = 0; i < channels; ++i) {
1689                 slot = ffs(mask) - 1;
1690                 if (slot < 0)
1691                         return;
1692
1693                 regmap_write(arizona->regmap, base + i, slot);
1694
1695                 mask &= ~(1 << slot);
1696         }
1697
1698         if (mask)
1699                 arizona_aif_warn(dai, "Too many channels in TDM mask\n");
1700 }
1701
1702 static int arizona_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1703                                 unsigned int rx_mask, int slots, int slot_width)
1704 {
1705         struct snd_soc_codec *codec = dai->codec;
1706         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1707         struct arizona *arizona = priv->arizona;
1708         int base = dai->driver->base;
1709         int rx_max_chan = dai->driver->playback.channels_max;
1710         int tx_max_chan = dai->driver->capture.channels_max;
1711
1712         /* Only support TDM for the physical AIFs */
1713         if (dai->id > ARIZONA_MAX_AIF)
1714                 return -ENOTSUPP;
1715
1716         if (slots == 0) {
1717                 tx_mask = (1 << tx_max_chan) - 1;
1718                 rx_mask = (1 << rx_max_chan) - 1;
1719         }
1720
1721         arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3,
1722                                      tx_max_chan, tx_mask);
1723         arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11,
1724                                      rx_max_chan, rx_mask);
1725
1726         arizona->tdm_width[dai->id - 1] = slot_width;
1727         arizona->tdm_slots[dai->id - 1] = slots;
1728
1729         return 0;
1730 }
1731
1732 const struct snd_soc_dai_ops arizona_dai_ops = {
1733         .startup = arizona_startup,
1734         .set_fmt = arizona_set_fmt,
1735         .set_tdm_slot = arizona_set_tdm_slot,
1736         .hw_params = arizona_hw_params,
1737         .set_sysclk = arizona_dai_set_sysclk,
1738         .set_tristate = arizona_set_tristate,
1739 };
1740 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1741
1742 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1743         .startup = arizona_startup,
1744         .hw_params = arizona_hw_params_rate,
1745         .set_sysclk = arizona_dai_set_sysclk,
1746 };
1747 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1748
1749 int arizona_init_dai(struct arizona_priv *priv, int id)
1750 {
1751         struct arizona_dai_priv *dai_priv = &priv->dai[id];
1752
1753         dai_priv->clk = ARIZONA_CLK_SYSCLK;
1754
1755         return 0;
1756 }
1757 EXPORT_SYMBOL_GPL(arizona_init_dai);
1758
1759 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
1760 {
1761         struct arizona_fll *fll = data;
1762
1763         arizona_fll_dbg(fll, "clock OK\n");
1764
1765         complete(&fll->ok);
1766
1767         return IRQ_HANDLED;
1768 }
1769
1770 static struct {
1771         unsigned int min;
1772         unsigned int max;
1773         u16 fratio;
1774         int ratio;
1775 } fll_fratios[] = {
1776         {       0,    64000, 4, 16 },
1777         {   64000,   128000, 3,  8 },
1778         {  128000,   256000, 2,  4 },
1779         {  256000,  1000000, 1,  2 },
1780         { 1000000, 13500000, 0,  1 },
1781 };
1782
1783 static struct {
1784         unsigned int min;
1785         unsigned int max;
1786         u16 gain;
1787 } fll_gains[] = {
1788         {       0,   256000, 0 },
1789         {  256000,  1000000, 2 },
1790         { 1000000, 13500000, 4 },
1791 };
1792
1793 struct arizona_fll_cfg {
1794         int n;
1795         int theta;
1796         int lambda;
1797         int refdiv;
1798         int outdiv;
1799         int fratio;
1800         int gain;
1801 };
1802
1803 static int arizona_validate_fll(struct arizona_fll *fll,
1804                                 unsigned int Fref,
1805                                 unsigned int Fout)
1806 {
1807         unsigned int Fvco_min;
1808
1809         if (fll->fout && Fout != fll->fout) {
1810                 arizona_fll_err(fll,
1811                                 "Can't change output on active FLL\n");
1812                 return -EINVAL;
1813         }
1814
1815         if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
1816                 arizona_fll_err(fll,
1817                                 "Can't scale %dMHz in to <=13.5MHz\n",
1818                                 Fref);
1819                 return -EINVAL;
1820         }
1821
1822         Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult;
1823         if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) {
1824                 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1825                                 Fout);
1826                 return -EINVAL;
1827         }
1828
1829         return 0;
1830 }
1831
1832 static int arizona_find_fratio(unsigned int Fref, int *fratio)
1833 {
1834         int i;
1835
1836         /* Find an appropriate FLL_FRATIO */
1837         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1838                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1839                         if (fratio)
1840                                 *fratio = fll_fratios[i].fratio;
1841                         return fll_fratios[i].ratio;
1842                 }
1843         }
1844
1845         return -EINVAL;
1846 }
1847
1848 static int arizona_calc_fratio(struct arizona_fll *fll,
1849                                struct arizona_fll_cfg *cfg,
1850                                unsigned int target,
1851                                unsigned int Fref, bool sync)
1852 {
1853         int init_ratio, ratio;
1854         int refdiv, div;
1855
1856         /* Fref must be <=13.5MHz, find initial refdiv */
1857         div = 1;
1858         cfg->refdiv = 0;
1859         while (Fref > ARIZONA_FLL_MAX_FREF) {
1860                 div *= 2;
1861                 Fref /= 2;
1862                 cfg->refdiv++;
1863
1864                 if (div > ARIZONA_FLL_MAX_REFDIV)
1865                         return -EINVAL;
1866         }
1867
1868         /* Find an appropriate FLL_FRATIO */
1869         init_ratio = arizona_find_fratio(Fref, &cfg->fratio);
1870         if (init_ratio < 0) {
1871                 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1872                                 Fref);
1873                 return init_ratio;
1874         }
1875
1876         switch (fll->arizona->type) {
1877         case WM5110:
1878         case WM8280:
1879                 if (fll->arizona->rev < 3 || sync)
1880                         return init_ratio;
1881                 break;
1882         default:
1883                 return init_ratio;
1884         }
1885
1886         cfg->fratio = init_ratio - 1;
1887
1888         /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1889         refdiv = cfg->refdiv;
1890
1891         while (div <= ARIZONA_FLL_MAX_REFDIV) {
1892                 for (ratio = init_ratio; ratio <= ARIZONA_FLL_MAX_FRATIO;
1893                      ratio++) {
1894                         if ((ARIZONA_FLL_VCO_CORNER / 2) /
1895                             (fll->vco_mult * ratio) < Fref)
1896                                 break;
1897
1898                         if (target % (ratio * Fref)) {
1899                                 cfg->refdiv = refdiv;
1900                                 cfg->fratio = ratio - 1;
1901                                 return ratio;
1902                         }
1903                 }
1904
1905                 for (ratio = init_ratio - 1; ratio > 0; ratio--) {
1906                         if (target % (ratio * Fref)) {
1907                                 cfg->refdiv = refdiv;
1908                                 cfg->fratio = ratio - 1;
1909                                 return ratio;
1910                         }
1911                 }
1912
1913                 div *= 2;
1914                 Fref /= 2;
1915                 refdiv++;
1916                 init_ratio = arizona_find_fratio(Fref, NULL);
1917         }
1918
1919         arizona_fll_warn(fll, "Falling back to integer mode operation\n");
1920         return cfg->fratio + 1;
1921 }
1922
1923 static int arizona_calc_fll(struct arizona_fll *fll,
1924                             struct arizona_fll_cfg *cfg,
1925                             unsigned int Fref, bool sync)
1926 {
1927         unsigned int target, div, gcd_fll;
1928         int i, ratio;
1929
1930         arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout);
1931
1932         /* Fvco should be over the targt; don't check the upper bound */
1933         div = ARIZONA_FLL_MIN_OUTDIV;
1934         while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) {
1935                 div++;
1936                 if (div > ARIZONA_FLL_MAX_OUTDIV)
1937                         return -EINVAL;
1938         }
1939         target = fll->fout * div / fll->vco_mult;
1940         cfg->outdiv = div;
1941
1942         arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1943
1944         /* Find an appropriate FLL_FRATIO and refdiv */
1945         ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync);
1946         if (ratio < 0)
1947                 return ratio;
1948
1949         /* Apply the division for our remaining calculations */
1950         Fref = Fref / (1 << cfg->refdiv);
1951
1952         cfg->n = target / (ratio * Fref);
1953
1954         if (target % (ratio * Fref)) {
1955                 gcd_fll = gcd(target, ratio * Fref);
1956                 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1957
1958                 cfg->theta = (target - (cfg->n * ratio * Fref))
1959                         / gcd_fll;
1960                 cfg->lambda = (ratio * Fref) / gcd_fll;
1961         } else {
1962                 cfg->theta = 0;
1963                 cfg->lambda = 0;
1964         }
1965
1966         /* Round down to 16bit range with cost of accuracy lost.
1967          * Denominator must be bigger than numerator so we only
1968          * take care of it.
1969          */
1970         while (cfg->lambda >= (1 << 16)) {
1971                 cfg->theta >>= 1;
1972                 cfg->lambda >>= 1;
1973         }
1974
1975         for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1976                 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1977                         cfg->gain = fll_gains[i].gain;
1978                         break;
1979                 }
1980         }
1981         if (i == ARRAY_SIZE(fll_gains)) {
1982                 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1983                                 Fref);
1984                 return -EINVAL;
1985         }
1986
1987         arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1988                         cfg->n, cfg->theta, cfg->lambda);
1989         arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1990                         cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1991         arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1992
1993         return 0;
1994
1995 }
1996
1997 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1998                               struct arizona_fll_cfg *cfg, int source,
1999                               bool sync)
2000 {
2001         regmap_update_bits_async(arizona->regmap, base + 3,
2002                                  ARIZONA_FLL1_THETA_MASK, cfg->theta);
2003         regmap_update_bits_async(arizona->regmap, base + 4,
2004                                  ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
2005         regmap_update_bits_async(arizona->regmap, base + 5,
2006                                  ARIZONA_FLL1_FRATIO_MASK,
2007                                  cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
2008         regmap_update_bits_async(arizona->regmap, base + 6,
2009                                  ARIZONA_FLL1_CLK_REF_DIV_MASK |
2010                                  ARIZONA_FLL1_CLK_REF_SRC_MASK,
2011                                  cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
2012                                  source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
2013
2014         if (sync) {
2015                 regmap_update_bits(arizona->regmap, base + 0x7,
2016                                    ARIZONA_FLL1_GAIN_MASK,
2017                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
2018         } else {
2019                 regmap_update_bits(arizona->regmap, base + 0x5,
2020                                    ARIZONA_FLL1_OUTDIV_MASK,
2021                                    cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
2022                 regmap_update_bits(arizona->regmap, base + 0x9,
2023                                    ARIZONA_FLL1_GAIN_MASK,
2024                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
2025         }
2026
2027         regmap_update_bits_async(arizona->regmap, base + 2,
2028                                  ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
2029                                  ARIZONA_FLL1_CTRL_UPD | cfg->n);
2030 }
2031
2032 static int arizona_is_enabled_fll(struct arizona_fll *fll)
2033 {
2034         struct arizona *arizona = fll->arizona;
2035         unsigned int reg;
2036         int ret;
2037
2038         ret = regmap_read(arizona->regmap, fll->base + 1, &reg);
2039         if (ret != 0) {
2040                 arizona_fll_err(fll, "Failed to read current state: %d\n",
2041                                 ret);
2042                 return ret;
2043         }
2044
2045         return reg & ARIZONA_FLL1_ENA;
2046 }
2047
2048 static int arizona_enable_fll(struct arizona_fll *fll)
2049 {
2050         struct arizona *arizona = fll->arizona;
2051         unsigned long time_left;
2052         bool use_sync = false;
2053         int already_enabled = arizona_is_enabled_fll(fll);
2054         struct arizona_fll_cfg cfg;
2055
2056         if (already_enabled < 0)
2057                 return already_enabled;
2058
2059         if (already_enabled) {
2060                 /* Facilitate smooth refclk across the transition */
2061                 regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x7,
2062                                          ARIZONA_FLL1_GAIN_MASK, 0);
2063                 regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,
2064                                          ARIZONA_FLL1_FREERUN,
2065                                          ARIZONA_FLL1_FREERUN);
2066         }
2067
2068         /*
2069          * If we have both REFCLK and SYNCCLK then enable both,
2070          * otherwise apply the SYNCCLK settings to REFCLK.
2071          */
2072         if (fll->ref_src >= 0 && fll->ref_freq &&
2073             fll->ref_src != fll->sync_src) {
2074                 arizona_calc_fll(fll, &cfg, fll->ref_freq, false);
2075
2076                 arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src,
2077                                   false);
2078                 if (fll->sync_src >= 0) {
2079                         arizona_calc_fll(fll, &cfg, fll->sync_freq, true);
2080
2081                         arizona_apply_fll(arizona, fll->base + 0x10, &cfg,
2082                                           fll->sync_src, true);
2083                         use_sync = true;
2084                 }
2085         } else if (fll->sync_src >= 0) {
2086                 arizona_calc_fll(fll, &cfg, fll->sync_freq, false);
2087
2088                 arizona_apply_fll(arizona, fll->base, &cfg,
2089                                   fll->sync_src, false);
2090
2091                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
2092                                          ARIZONA_FLL1_SYNC_ENA, 0);
2093         } else {
2094                 arizona_fll_err(fll, "No clocks provided\n");
2095                 return -EINVAL;
2096         }
2097
2098         /*
2099          * Increase the bandwidth if we're not using a low frequency
2100          * sync source.
2101          */
2102         if (use_sync && fll->sync_freq > 100000)
2103                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
2104                                          ARIZONA_FLL1_SYNC_BW, 0);
2105         else
2106                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
2107                                          ARIZONA_FLL1_SYNC_BW,
2108                                          ARIZONA_FLL1_SYNC_BW);
2109
2110         if (!already_enabled)
2111                 pm_runtime_get(arizona->dev);
2112
2113         /* Clear any pending completions */
2114         try_wait_for_completion(&fll->ok);
2115
2116         regmap_update_bits_async(arizona->regmap, fll->base + 1,
2117                                  ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
2118         if (use_sync)
2119                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
2120                                          ARIZONA_FLL1_SYNC_ENA,
2121                                          ARIZONA_FLL1_SYNC_ENA);
2122
2123         if (already_enabled)
2124                 regmap_update_bits_async(arizona->regmap, fll->base + 1,
2125                                          ARIZONA_FLL1_FREERUN, 0);
2126
2127         time_left = wait_for_completion_timeout(&fll->ok,
2128                                           msecs_to_jiffies(250));
2129         if (time_left == 0)
2130                 arizona_fll_warn(fll, "Timed out waiting for lock\n");
2131
2132         return 0;
2133 }
2134
2135 static void arizona_disable_fll(struct arizona_fll *fll)
2136 {
2137         struct arizona *arizona = fll->arizona;
2138         bool change;
2139
2140         regmap_update_bits_async(arizona->regmap, fll->base + 1,
2141                                  ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
2142         regmap_update_bits_check(arizona->regmap, fll->base + 1,
2143                                  ARIZONA_FLL1_ENA, 0, &change);
2144         regmap_update_bits(arizona->regmap, fll->base + 0x11,
2145                            ARIZONA_FLL1_SYNC_ENA, 0);
2146         regmap_update_bits_async(arizona->regmap, fll->base + 1,
2147                                  ARIZONA_FLL1_FREERUN, 0);
2148
2149         if (change)
2150                 pm_runtime_put_autosuspend(arizona->dev);
2151 }
2152
2153 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
2154                            unsigned int Fref, unsigned int Fout)
2155 {
2156         int ret = 0;
2157
2158         if (fll->ref_src == source && fll->ref_freq == Fref)
2159                 return 0;
2160
2161         if (fll->fout && Fref > 0) {
2162                 ret = arizona_validate_fll(fll, Fref, fll->fout);
2163                 if (ret != 0)
2164                         return ret;
2165         }
2166
2167         fll->ref_src = source;
2168         fll->ref_freq = Fref;
2169
2170         if (fll->fout && Fref > 0) {
2171                 ret = arizona_enable_fll(fll);
2172         }
2173
2174         return ret;
2175 }
2176 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
2177
2178 int arizona_set_fll(struct arizona_fll *fll, int source,
2179                     unsigned int Fref, unsigned int Fout)
2180 {
2181         int ret = 0;
2182
2183         if (fll->sync_src == source &&
2184             fll->sync_freq == Fref && fll->fout == Fout)
2185                 return 0;
2186
2187         if (Fout) {
2188                 if (fll->ref_src >= 0) {
2189                         ret = arizona_validate_fll(fll, fll->ref_freq, Fout);
2190                         if (ret != 0)
2191                                 return ret;
2192                 }
2193
2194                 ret = arizona_validate_fll(fll, Fref, Fout);
2195                 if (ret != 0)
2196                         return ret;
2197         }
2198
2199         fll->sync_src = source;
2200         fll->sync_freq = Fref;
2201         fll->fout = Fout;
2202
2203         if (Fout)
2204                 ret = arizona_enable_fll(fll);
2205         else
2206                 arizona_disable_fll(fll);
2207
2208         return ret;
2209 }
2210 EXPORT_SYMBOL_GPL(arizona_set_fll);
2211
2212 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
2213                      int ok_irq, struct arizona_fll *fll)
2214 {
2215         int ret;
2216         unsigned int val;
2217
2218         init_completion(&fll->ok);
2219
2220         fll->id = id;
2221         fll->base = base;
2222         fll->arizona = arizona;
2223         fll->sync_src = ARIZONA_FLL_SRC_NONE;
2224
2225         /* Configure default refclk to 32kHz if we have one */
2226         regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
2227         switch (val & ARIZONA_CLK_32K_SRC_MASK) {
2228         case ARIZONA_CLK_SRC_MCLK1:
2229         case ARIZONA_CLK_SRC_MCLK2:
2230                 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
2231                 break;
2232         default:
2233                 fll->ref_src = ARIZONA_FLL_SRC_NONE;
2234         }
2235         fll->ref_freq = 32768;
2236
2237         snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
2238         snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
2239                  "FLL%d clock OK", id);
2240
2241         ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
2242                                   arizona_fll_clock_ok, fll);
2243         if (ret != 0) {
2244                 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
2245                         id, ret);
2246         }
2247
2248         regmap_update_bits(arizona->regmap, fll->base + 1,
2249                            ARIZONA_FLL1_FREERUN, 0);
2250
2251         return 0;
2252 }
2253 EXPORT_SYMBOL_GPL(arizona_init_fll);
2254
2255 /**
2256  * arizona_set_output_mode - Set the mode of the specified output
2257  *
2258  * @codec: Device to configure
2259  * @output: Output number
2260  * @diff: True to set the output to differential mode
2261  *
2262  * Some systems use external analogue switches to connect more
2263  * analogue devices to the CODEC than are supported by the device.  In
2264  * some systems this requires changing the switched output from single
2265  * ended to differential mode dynamically at runtime, an operation
2266  * supported using this function.
2267  *
2268  * Most systems have a single static configuration and should use
2269  * platform data instead.
2270  */
2271 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
2272 {
2273         unsigned int reg, val;
2274
2275         if (output < 1 || output > 6)
2276                 return -EINVAL;
2277
2278         reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
2279
2280         if (diff)
2281                 val = ARIZONA_OUT1_MONO;
2282         else
2283                 val = 0;
2284
2285         return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
2286 }
2287 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
2288
2289 static const struct soc_enum arizona_adsp2_rate_enum[] = {
2290         SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
2291                               ARIZONA_DSP1_RATE_SHIFT, 0xf,
2292                               ARIZONA_RATE_ENUM_SIZE,
2293                               arizona_rate_text, arizona_rate_val),
2294         SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
2295                               ARIZONA_DSP1_RATE_SHIFT, 0xf,
2296                               ARIZONA_RATE_ENUM_SIZE,
2297                               arizona_rate_text, arizona_rate_val),
2298         SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
2299                               ARIZONA_DSP1_RATE_SHIFT, 0xf,
2300                               ARIZONA_RATE_ENUM_SIZE,
2301                               arizona_rate_text, arizona_rate_val),
2302         SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
2303                               ARIZONA_DSP1_RATE_SHIFT, 0xf,
2304                               ARIZONA_RATE_ENUM_SIZE,
2305                               arizona_rate_text, arizona_rate_val),
2306 };
2307
2308 const struct snd_kcontrol_new arizona_adsp2_rate_controls[] = {
2309         SOC_ENUM("DSP1 Rate", arizona_adsp2_rate_enum[0]),
2310         SOC_ENUM("DSP2 Rate", arizona_adsp2_rate_enum[1]),
2311         SOC_ENUM("DSP3 Rate", arizona_adsp2_rate_enum[2]),
2312         SOC_ENUM("DSP4 Rate", arizona_adsp2_rate_enum[3]),
2313 };
2314 EXPORT_SYMBOL_GPL(arizona_adsp2_rate_controls);
2315
2316 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
2317 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2318 MODULE_LICENSE("GPL");