sound/soc/codecs/arizona.c

   1 /*
   2  * arizona.c - Wolfson Arizona class device shared support
   3  *
   4  * Copyright 2012 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/gcd.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <sound/pcm.h>
  18 #include <sound/pcm_params.h>
  19 #include <sound/tlv.h>
  20
  21 #include <linux/mfd/arizona/core.h>
  22 #include <linux/mfd/arizona/registers.h>
  23
  24 #include "arizona.h"
  25
  26 #define ARIZONA_AIF_BCLK_CTRL                   0x00
  27 #define ARIZONA_AIF_TX_PIN_CTRL                 0x01
  28 #define ARIZONA_AIF_RX_PIN_CTRL                 0x02
  29 #define ARIZONA_AIF_RATE_CTRL                   0x03
  30 #define ARIZONA_AIF_FORMAT                      0x04
  31 #define ARIZONA_AIF_TX_BCLK_RATE                0x05
  32 #define ARIZONA_AIF_RX_BCLK_RATE                0x06
  33 #define ARIZONA_AIF_FRAME_CTRL_1                0x07
  34 #define ARIZONA_AIF_FRAME_CTRL_2                0x08
  35 #define ARIZONA_AIF_FRAME_CTRL_3                0x09
  36 #define ARIZONA_AIF_FRAME_CTRL_4                0x0A
  37 #define ARIZONA_AIF_FRAME_CTRL_5                0x0B
  38 #define ARIZONA_AIF_FRAME_CTRL_6                0x0C
  39 #define ARIZONA_AIF_FRAME_CTRL_7                0x0D
  40 #define ARIZONA_AIF_FRAME_CTRL_8                0x0E
  41 #define ARIZONA_AIF_FRAME_CTRL_9                0x0F
  42 #define ARIZONA_AIF_FRAME_CTRL_10               0x10
  43 #define ARIZONA_AIF_FRAME_CTRL_11               0x11
  44 #define ARIZONA_AIF_FRAME_CTRL_12               0x12
  45 #define ARIZONA_AIF_FRAME_CTRL_13               0x13
  46 #define ARIZONA_AIF_FRAME_CTRL_14               0x14
  47 #define ARIZONA_AIF_FRAME_CTRL_15               0x15
  48 #define ARIZONA_AIF_FRAME_CTRL_16               0x16
  49 #define ARIZONA_AIF_FRAME_CTRL_17               0x17
  50 #define ARIZONA_AIF_FRAME_CTRL_18               0x18
  51 #define ARIZONA_AIF_TX_ENABLES                  0x19
  52 #define ARIZONA_AIF_RX_ENABLES                  0x1A
  53 #define ARIZONA_AIF_FORCE_WRITE                 0x1B
  54
  55 #define ARIZONA_FLL_VCO_CORNER 141900000
  56 #define ARIZONA_FLL_MAX_FREF   13500000
  57 #define ARIZONA_FLL_MIN_FVCO   90000000
  58 #define ARIZONA_FLL_MAX_FRATIO 16
  59 #define ARIZONA_FLL_MAX_REFDIV 8
  60 #define ARIZONA_FLL_MIN_OUTDIV 2
  61 #define ARIZONA_FLL_MAX_OUTDIV 7
  62
  63 #define ARIZONA_FMT_DSP_MODE_A          0
  64 #define ARIZONA_FMT_DSP_MODE_B          1
  65 #define ARIZONA_FMT_I2S_MODE            2
  66 #define ARIZONA_FMT_LEFT_JUSTIFIED_MODE 3
  67
  68 #define arizona_fll_err(_fll, fmt, ...) \
  69         dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  70 #define arizona_fll_warn(_fll, fmt, ...) \
  71         dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  72 #define arizona_fll_dbg(_fll, fmt, ...) \
  73         dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  74
  75 #define arizona_aif_err(_dai, fmt, ...) \
  76         dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  77 #define arizona_aif_warn(_dai, fmt, ...) \
  78         dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  79 #define arizona_aif_dbg(_dai, fmt, ...) \
  80         dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  81
  82 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
  83                           struct snd_kcontrol *kcontrol,
  84                           int event)
  85 {
  86         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  87         struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
  88         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
  89         bool manual_ena = false;
  90         int val;
  91
  92         switch (arizona->type) {
  93         case WM5102:
  94                 switch (arizona->rev) {
  95                 case 0:
  96                         break;
  97                 default:
  98                         manual_ena = true;
  99                         break;
 100                 }
 101         default:
 102                 break;
 103         }
 104
 105         switch (event) {
 106         case SND_SOC_DAPM_PRE_PMU:
 107                 if (!priv->spk_ena && manual_ena) {
 108                         regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
 109                         priv->spk_ena_pending = true;
 110                 }
 111                 break;
 112         case SND_SOC_DAPM_POST_PMU:
 113                 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
 114                 if (val & ARIZONA_SPK_OVERHEAT_STS) {
 115                         dev_crit(arizona->dev,
 116                                  "Speaker not enabled due to temperature\n");
 117                         return -EBUSY;
 118                 }
 119
 120                 regmap_update_bits_async(arizona->regmap,
 121                                          ARIZONA_OUTPUT_ENABLES_1,
 122                                          1 << w->shift, 1 << w->shift);
 123
 124                 if (priv->spk_ena_pending) {
 125                         msleep(75);
 126                         regmap_write_async(arizona->regmap, 0x4f5, 0xda);
 127                         priv->spk_ena_pending = false;
 128                         priv->spk_ena++;
 129                 }
 130                 break;
 131         case SND_SOC_DAPM_PRE_PMD:
 132                 if (manual_ena) {
 133                         priv->spk_ena--;
 134                         if (!priv->spk_ena)
 135                                 regmap_write_async(arizona->regmap,
 136                                                    0x4f5, 0x25a);
 137                 }
 138
 139                 regmap_update_bits_async(arizona->regmap,
 140                                          ARIZONA_OUTPUT_ENABLES_1,
 141                                          1 << w->shift, 0);
 142                 break;
 143         case SND_SOC_DAPM_POST_PMD:
 144                 if (manual_ena) {
 145                         if (!priv->spk_ena)
 146                                 regmap_write_async(arizona->regmap,
 147                                                    0x4f5, 0x0da);
 148                 }
 149                 break;
 150         default:
 151                 break;
 152         }
 153
 154         return 0;
 155 }
 156
 157 static irqreturn_t arizona_thermal_warn(int irq, void *data)
 158 {
 159         struct arizona *arizona = data;
 160         unsigned int val;
 161         int ret;
 162
 163         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
 164                           &val);
 165         if (ret != 0) {
 166                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
 167                         ret);
 168         } else if (val & ARIZONA_SPK_OVERHEAT_WARN_STS) {
 169                 dev_crit(arizona->dev, "Thermal warning\n");
 170         }
 171
 172         return IRQ_HANDLED;
 173 }
 174
 175 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
 176 {
 177         struct arizona *arizona = data;
 178         unsigned int val;
 179         int ret;
 180
 181         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
 182                           &val);
 183         if (ret != 0) {
 184                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
 185                         ret);
 186         } else if (val & ARIZONA_SPK_OVERHEAT_STS) {
 187                 dev_crit(arizona->dev, "Thermal shutdown\n");
 188                 ret = regmap_update_bits(arizona->regmap,
 189                                          ARIZONA_OUTPUT_ENABLES_1,
 190                                          ARIZONA_OUT4L_ENA |
 191                                          ARIZONA_OUT4R_ENA, 0);
 192                 if (ret != 0)
 193                         dev_crit(arizona->dev,
 194                                  "Failed to disable speaker outputs: %d\n",
 195                                  ret);
 196         }
 197
 198         return IRQ_HANDLED;
 199 }
 200
 201 static const struct snd_soc_dapm_widget arizona_spkl =
 202         SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
 203                            ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
 204                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
 205
 206 static const struct snd_soc_dapm_widget arizona_spkr =
 207         SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
 208                            ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
 209                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
 210
 211 int arizona_init_spk(struct snd_soc_codec *codec)
 212 {
 213         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 214         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 215         struct arizona *arizona = priv->arizona;
 216         int ret;
 217
 218         ret = snd_soc_dapm_new_controls(dapm, &arizona_spkl, 1);
 219         if (ret != 0)
 220                 return ret;
 221
 222         switch (arizona->type) {
 223         case WM8997:
 224                 break;
 225         default:
 226                 ret = snd_soc_dapm_new_controls(dapm, &arizona_spkr, 1);
 227                 if (ret != 0)
 228                         return ret;
 229                 break;
 230         }
 231
 232         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN,
 233                                   "Thermal warning", arizona_thermal_warn,
 234                                   arizona);
 235         if (ret != 0)
 236                 dev_err(arizona->dev,
 237                         "Failed to get thermal warning IRQ: %d\n",
 238                         ret);
 239
 240         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT,
 241                                   "Thermal shutdown", arizona_thermal_shutdown,
 242                                   arizona);
 243         if (ret != 0)
 244                 dev_err(arizona->dev,
 245                         "Failed to get thermal shutdown IRQ: %d\n",
 246                         ret);
 247
 248         return 0;
 249 }
 250 EXPORT_SYMBOL_GPL(arizona_init_spk);
 251
 252 static const struct snd_soc_dapm_route arizona_mono_routes[] = {
 253         { "OUT1R", NULL, "OUT1L" },
 254         { "OUT2R", NULL, "OUT2L" },
 255         { "OUT3R", NULL, "OUT3L" },
 256         { "OUT4R", NULL, "OUT4L" },
 257         { "OUT5R", NULL, "OUT5L" },
 258         { "OUT6R", NULL, "OUT6L" },
 259 };
 260
 261 int arizona_init_mono(struct snd_soc_codec *codec)
 262 {
 263         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 264         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 265         struct arizona *arizona = priv->arizona;
 266         int i;
 267
 268         for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) {
 269                 if (arizona->pdata.out_mono[i])
 270                         snd_soc_dapm_add_routes(dapm,
 271                                                 &arizona_mono_routes[i], 1);
 272         }
 273
 274         return 0;
 275 }
 276 EXPORT_SYMBOL_GPL(arizona_init_mono);
 277
 278 int arizona_init_gpio(struct snd_soc_codec *codec)
 279 {
 280         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 281         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 282         struct arizona *arizona = priv->arizona;
 283         int i;
 284
 285         switch (arizona->type) {
 286         case WM5110:
 287         case WM8280:
 288                 snd_soc_dapm_disable_pin(dapm, "DRC2 Signal Activity");
 289                 break;
 290         default:
 291                 break;
 292         }
 293
 294         snd_soc_dapm_disable_pin(dapm, "DRC1 Signal Activity");
 295
 296         for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
 297                 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
 298                 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
 299                         snd_soc_dapm_enable_pin(dapm, "DRC1 Signal Activity");
 300                         break;
 301                 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
 302                         snd_soc_dapm_enable_pin(dapm, "DRC2 Signal Activity");
 303                         break;
 304                 default:
 305                         break;
 306                 }
 307         }
 308
 309         return 0;
 310 }
 311 EXPORT_SYMBOL_GPL(arizona_init_gpio);
 312
 313 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
 314         "None",
 315         "Tone Generator 1",
 316         "Tone Generator 2",
 317         "Haptics",
 318         "AEC",
 319         "Mic Mute Mixer",
 320         "Noise Generator",
 321         "IN1L",
 322         "IN1R",
 323         "IN2L",
 324         "IN2R",
 325         "IN3L",
 326         "IN3R",
 327         "IN4L",
 328         "IN4R",
 329         "AIF1RX1",
 330         "AIF1RX2",
 331         "AIF1RX3",
 332         "AIF1RX4",
 333         "AIF1RX5",
 334         "AIF1RX6",
 335         "AIF1RX7",
 336         "AIF1RX8",
 337         "AIF2RX1",
 338         "AIF2RX2",
 339         "AIF2RX3",
 340         "AIF2RX4",
 341         "AIF2RX5",
 342         "AIF2RX6",
 343         "AIF3RX1",
 344         "AIF3RX2",
 345         "SLIMRX1",
 346         "SLIMRX2",
 347         "SLIMRX3",
 348         "SLIMRX4",
 349         "SLIMRX5",
 350         "SLIMRX6",
 351         "SLIMRX7",
 352         "SLIMRX8",
 353         "EQ1",
 354         "EQ2",
 355         "EQ3",
 356         "EQ4",
 357         "DRC1L",
 358         "DRC1R",
 359         "DRC2L",
 360         "DRC2R",
 361         "LHPF1",
 362         "LHPF2",
 363         "LHPF3",
 364         "LHPF4",
 365         "DSP1.1",
 366         "DSP1.2",
 367         "DSP1.3",
 368         "DSP1.4",
 369         "DSP1.5",
 370         "DSP1.6",
 371         "DSP2.1",
 372         "DSP2.2",
 373         "DSP2.3",
 374         "DSP2.4",
 375         "DSP2.5",
 376         "DSP2.6",
 377         "DSP3.1",
 378         "DSP3.2",
 379         "DSP3.3",
 380         "DSP3.4",
 381         "DSP3.5",
 382         "DSP3.6",
 383         "DSP4.1",
 384         "DSP4.2",
 385         "DSP4.3",
 386         "DSP4.4",
 387         "DSP4.5",
 388         "DSP4.6",
 389         "ASRC1L",
 390         "ASRC1R",
 391         "ASRC2L",
 392         "ASRC2R",
 393         "ISRC1INT1",
 394         "ISRC1INT2",
 395         "ISRC1INT3",
 396         "ISRC1INT4",
 397         "ISRC1DEC1",
 398         "ISRC1DEC2",
 399         "ISRC1DEC3",
 400         "ISRC1DEC4",
 401         "ISRC2INT1",
 402         "ISRC2INT2",
 403         "ISRC2INT3",
 404         "ISRC2INT4",
 405         "ISRC2DEC1",
 406         "ISRC2DEC2",
 407         "ISRC2DEC3",
 408         "ISRC2DEC4",
 409         "ISRC3INT1",
 410         "ISRC3INT2",
 411         "ISRC3INT3",
 412         "ISRC3INT4",
 413         "ISRC3DEC1",
 414         "ISRC3DEC2",
 415         "ISRC3DEC3",
 416         "ISRC3DEC4",
 417 };
 418 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
 419
 420 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
 421         0x00,  /* None */
 422         0x04,  /* Tone */
 423         0x05,
 424         0x06,  /* Haptics */
 425         0x08,  /* AEC */
 426         0x0c,  /* Noise mixer */
 427         0x0d,  /* Comfort noise */
 428         0x10,  /* IN1L */
 429         0x11,
 430         0x12,
 431         0x13,
 432         0x14,
 433         0x15,
 434         0x16,
 435         0x17,
 436         0x20,  /* AIF1RX1 */
 437         0x21,
 438         0x22,
 439         0x23,
 440         0x24,
 441         0x25,
 442         0x26,
 443         0x27,
 444         0x28,  /* AIF2RX1 */
 445         0x29,
 446         0x2a,
 447         0x2b,
 448         0x2c,
 449         0x2d,
 450         0x30,  /* AIF3RX1 */
 451         0x31,
 452         0x38,  /* SLIMRX1 */
 453         0x39,
 454         0x3a,
 455         0x3b,
 456         0x3c,
 457         0x3d,
 458         0x3e,
 459         0x3f,
 460         0x50,  /* EQ1 */
 461         0x51,
 462         0x52,
 463         0x53,
 464         0x58,  /* DRC1L */
 465         0x59,
 466         0x5a,
 467         0x5b,
 468         0x60,  /* LHPF1 */
 469         0x61,
 470         0x62,
 471         0x63,
 472         0x68,  /* DSP1.1 */
 473         0x69,
 474         0x6a,
 475         0x6b,
 476         0x6c,
 477         0x6d,
 478         0x70,  /* DSP2.1 */
 479         0x71,
 480         0x72,
 481         0x73,
 482         0x74,
 483         0x75,
 484         0x78,  /* DSP3.1 */
 485         0x79,
 486         0x7a,
 487         0x7b,
 488         0x7c,
 489         0x7d,
 490         0x80,  /* DSP4.1 */
 491         0x81,
 492         0x82,
 493         0x83,
 494         0x84,
 495         0x85,
 496         0x90,  /* ASRC1L */
 497         0x91,
 498         0x92,
 499         0x93,
 500         0xa0,  /* ISRC1INT1 */
 501         0xa1,
 502         0xa2,
 503         0xa3,
 504         0xa4,  /* ISRC1DEC1 */
 505         0xa5,
 506         0xa6,
 507         0xa7,
 508         0xa8,  /* ISRC2DEC1 */
 509         0xa9,
 510         0xaa,
 511         0xab,
 512         0xac,  /* ISRC2INT1 */
 513         0xad,
 514         0xae,
 515         0xaf,
 516         0xb0,  /* ISRC3DEC1 */
 517         0xb1,
 518         0xb2,
 519         0xb3,
 520         0xb4,  /* ISRC3INT1 */
 521         0xb5,
 522         0xb6,
 523         0xb7,
 524 };
 525 EXPORT_SYMBOL_GPL(arizona_mixer_values);
 526
 527 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
 528 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
 529
 530 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
 531         "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
 532 };
 533 EXPORT_SYMBOL_GPL(arizona_rate_text);
 534
 535 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
 536         0, 1, 2, 8,
 537 };
 538 EXPORT_SYMBOL_GPL(arizona_rate_val);
 539
 540
 541 const struct soc_enum arizona_isrc_fsh[] = {
 542         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1,
 543                               ARIZONA_ISRC1_FSH_SHIFT, 0xf,
 544                               ARIZONA_RATE_ENUM_SIZE,
 545                               arizona_rate_text, arizona_rate_val),
 546         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1,
 547                               ARIZONA_ISRC2_FSH_SHIFT, 0xf,
 548                               ARIZONA_RATE_ENUM_SIZE,
 549                               arizona_rate_text, arizona_rate_val),
 550         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1,
 551                               ARIZONA_ISRC3_FSH_SHIFT, 0xf,
 552                               ARIZONA_RATE_ENUM_SIZE,
 553                               arizona_rate_text, arizona_rate_val),
 554 };
 555 EXPORT_SYMBOL_GPL(arizona_isrc_fsh);
 556
 557 const struct soc_enum arizona_isrc_fsl[] = {
 558         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
 559                               ARIZONA_ISRC1_FSL_SHIFT, 0xf,
 560                               ARIZONA_RATE_ENUM_SIZE,
 561                               arizona_rate_text, arizona_rate_val),
 562         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
 563                               ARIZONA_ISRC2_FSL_SHIFT, 0xf,
 564                               ARIZONA_RATE_ENUM_SIZE,
 565                               arizona_rate_text, arizona_rate_val),
 566         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
 567                               ARIZONA_ISRC3_FSL_SHIFT, 0xf,
 568                               ARIZONA_RATE_ENUM_SIZE,
 569                               arizona_rate_text, arizona_rate_val),
 570 };
 571 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
 572
 573 const struct soc_enum arizona_asrc_rate1 =
 574         SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1,
 575                               ARIZONA_ASRC_RATE1_SHIFT, 0xf,
 576                               ARIZONA_RATE_ENUM_SIZE - 1,
 577                               arizona_rate_text, arizona_rate_val);
 578 EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
 579
 580 static const char *arizona_vol_ramp_text[] = {
 581         "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
 582         "15ms/6dB", "30ms/6dB",
 583 };
 584
 585 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp,
 586                      ARIZONA_INPUT_VOLUME_RAMP,
 587                      ARIZONA_IN_VD_RAMP_SHIFT,
 588                      arizona_vol_ramp_text);
 589 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
 590
 591 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp,
 592                      ARIZONA_INPUT_VOLUME_RAMP,
 593                      ARIZONA_IN_VI_RAMP_SHIFT,
 594                      arizona_vol_ramp_text);
 595 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
 596
 597 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp,
 598                      ARIZONA_OUTPUT_VOLUME_RAMP,
 599                      ARIZONA_OUT_VD_RAMP_SHIFT,
 600                      arizona_vol_ramp_text);
 601 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
 602
 603 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
 604                      ARIZONA_OUTPUT_VOLUME_RAMP,
 605                      ARIZONA_OUT_VI_RAMP_SHIFT,
 606                      arizona_vol_ramp_text);
 607 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
 608
 609 static const char *arizona_lhpf_mode_text[] = {
 610         "Low-pass", "High-pass"
 611 };
 612
 613 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode,
 614                      ARIZONA_HPLPF1_1,
 615                      ARIZONA_LHPF1_MODE_SHIFT,
 616                      arizona_lhpf_mode_text);
 617 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
 618
 619 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode,
 620                      ARIZONA_HPLPF2_1,
 621                      ARIZONA_LHPF2_MODE_SHIFT,
 622                      arizona_lhpf_mode_text);
 623 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
 624
 625 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode,
 626                      ARIZONA_HPLPF3_1,
 627                      ARIZONA_LHPF3_MODE_SHIFT,
 628                      arizona_lhpf_mode_text);
 629 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
 630
 631 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
 632                      ARIZONA_HPLPF4_1,
 633                      ARIZONA_LHPF4_MODE_SHIFT,
 634                      arizona_lhpf_mode_text);
 635 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
 636
 637 static const char *arizona_ng_hold_text[] = {
 638         "30ms", "120ms", "250ms", "500ms",
 639 };
 640
 641 SOC_ENUM_SINGLE_DECL(arizona_ng_hold,
 642                      ARIZONA_NOISE_GATE_CONTROL,
 643                      ARIZONA_NGATE_HOLD_SHIFT,
 644                      arizona_ng_hold_text);
 645 EXPORT_SYMBOL_GPL(arizona_ng_hold);
 646
 647 static const char * const arizona_in_hpf_cut_text[] = {
 648         "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
 649 };
 650
 651 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum,
 652                      ARIZONA_HPF_CONTROL,
 653                      ARIZONA_IN_HPF_CUT_SHIFT,
 654                      arizona_in_hpf_cut_text);
 655 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum);
 656
 657 static const char * const arizona_in_dmic_osr_text[] = {
 658         "1.536MHz", "3.072MHz", "6.144MHz", "768kHz",
 659 };
 660
 661 const struct soc_enum arizona_in_dmic_osr[] = {
 662         SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
 663                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 664                         arizona_in_dmic_osr_text),
 665         SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
 666                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 667                         arizona_in_dmic_osr_text),
 668         SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
 669                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 670                         arizona_in_dmic_osr_text),
 671         SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
 672                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 673                         arizona_in_dmic_osr_text),
 674 };
 675 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
 676
 677 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
 678 {
 679         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 680         unsigned int val;
 681         int i;
 682
 683         if (ena)
 684                 val = ARIZONA_IN_VU;
 685         else
 686                 val = 0;
 687
 688         for (i = 0; i < priv->num_inputs; i++)
 689                 snd_soc_update_bits(codec,
 690                                     ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
 691                                     ARIZONA_IN_VU, val);
 692 }
 693
 694 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
 695                   int event)
 696 {
 697         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 698         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 699         unsigned int reg;
 700
 701         if (w->shift % 2)
 702                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
 703         else
 704                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
 705
 706         switch (event) {
 707         case SND_SOC_DAPM_PRE_PMU:
 708                 priv->in_pending++;
 709                 break;
 710         case SND_SOC_DAPM_POST_PMU:
 711                 snd_soc_update_bits(codec, reg, ARIZONA_IN1L_MUTE, 0);
 712
 713                 /* If this is the last input pending then allow VU */
 714                 priv->in_pending--;
 715                 if (priv->in_pending == 0) {
 716                         msleep(1);
 717                         arizona_in_set_vu(codec, 1);
 718                 }
 719                 break;
 720         case SND_SOC_DAPM_PRE_PMD:
 721                 snd_soc_update_bits(codec, reg,
 722                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
 723                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
 724                 break;
 725         case SND_SOC_DAPM_POST_PMD:
 726                 /* Disable volume updates if no inputs are enabled */
 727                 reg = snd_soc_read(codec, ARIZONA_INPUT_ENABLES);
 728                 if (reg == 0)
 729                         arizona_in_set_vu(codec, 0);
 730                 break;
 731         default:
 732                 break;
 733         }
 734
 735         return 0;
 736 }
 737 EXPORT_SYMBOL_GPL(arizona_in_ev);
 738
 739 int arizona_out_ev(struct snd_soc_dapm_widget *w,
 740                    struct snd_kcontrol *kcontrol,
 741                    int event)
 742 {
 743         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 744         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 745
 746         switch (event) {
 747         case SND_SOC_DAPM_PRE_PMU:
 748                 switch (w->shift) {
 749                 case ARIZONA_OUT1L_ENA_SHIFT:
 750                 case ARIZONA_OUT1R_ENA_SHIFT:
 751                 case ARIZONA_OUT2L_ENA_SHIFT:
 752                 case ARIZONA_OUT2R_ENA_SHIFT:
 753                 case ARIZONA_OUT3L_ENA_SHIFT:
 754                 case ARIZONA_OUT3R_ENA_SHIFT:
 755                         priv->out_up_pending++;
 756                         priv->out_up_delay += 17;
 757                         break;
 758                 default:
 759                         break;
 760                 }
 761                 break;
 762         case SND_SOC_DAPM_POST_PMU:
 763                 switch (w->shift) {
 764                 case ARIZONA_OUT1L_ENA_SHIFT:
 765                 case ARIZONA_OUT1R_ENA_SHIFT:
 766                 case ARIZONA_OUT2L_ENA_SHIFT:
 767                 case ARIZONA_OUT2R_ENA_SHIFT:
 768                 case ARIZONA_OUT3L_ENA_SHIFT:
 769                 case ARIZONA_OUT3R_ENA_SHIFT:
 770                         priv->out_up_pending--;
 771                         if (!priv->out_up_pending) {
 772                                 msleep(priv->out_up_delay);
 773                                 priv->out_up_delay = 0;
 774                         }
 775                         break;
 776
 777                 default:
 778                         break;
 779                 }
 780                 break;
 781         case SND_SOC_DAPM_PRE_PMD:
 782                 switch (w->shift) {
 783                 case ARIZONA_OUT1L_ENA_SHIFT:
 784                 case ARIZONA_OUT1R_ENA_SHIFT:
 785                 case ARIZONA_OUT2L_ENA_SHIFT:
 786                 case ARIZONA_OUT2R_ENA_SHIFT:
 787                 case ARIZONA_OUT3L_ENA_SHIFT:
 788                 case ARIZONA_OUT3R_ENA_SHIFT:
 789                         priv->out_down_pending++;
 790                         priv->out_down_delay++;
 791                         break;
 792                 default:
 793                         break;
 794                 }
 795                 break;
 796         case SND_SOC_DAPM_POST_PMD:
 797                 switch (w->shift) {
 798                 case ARIZONA_OUT1L_ENA_SHIFT:
 799                 case ARIZONA_OUT1R_ENA_SHIFT:
 800                 case ARIZONA_OUT2L_ENA_SHIFT:
 801                 case ARIZONA_OUT2R_ENA_SHIFT:
 802                 case ARIZONA_OUT3L_ENA_SHIFT:
 803                 case ARIZONA_OUT3R_ENA_SHIFT:
 804                         priv->out_down_pending--;
 805                         if (!priv->out_down_pending) {
 806                                 msleep(priv->out_down_delay);
 807                                 priv->out_down_delay = 0;
 808                         }
 809                         break;
 810                 default:
 811                         break;
 812                 }
 813                 break;
 814         default:
 815                 break;
 816         }
 817
 818         return 0;
 819 }
 820 EXPORT_SYMBOL_GPL(arizona_out_ev);
 821
 822 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
 823                    struct snd_kcontrol *kcontrol,
 824                    int event)
 825 {
 826         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 827         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 828         struct arizona *arizona = priv->arizona;
 829         unsigned int mask = 1 << w->shift;
 830         unsigned int val;
 831
 832         switch (event) {
 833         case SND_SOC_DAPM_POST_PMU:
 834                 val = mask;
 835                 break;
 836         case SND_SOC_DAPM_PRE_PMD:
 837                 val = 0;
 838                 break;
 839         case SND_SOC_DAPM_PRE_PMU:
 840         case SND_SOC_DAPM_POST_PMD:
 841                 return arizona_out_ev(w, kcontrol, event);
 842         default:
 843                 return -EINVAL;
 844         }
 845
 846         /* Store the desired state for the HP outputs */
 847         priv->arizona->hp_ena &= ~mask;
 848         priv->arizona->hp_ena |= val;
 849
 850         /* Force off if HPDET clamp is active */
 851         if (priv->arizona->hpdet_clamp)
 852                 val = 0;
 853
 854         regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
 855                                  mask, val);
 856
 857         return arizona_out_ev(w, kcontrol, event);
 858 }
 859 EXPORT_SYMBOL_GPL(arizona_hp_ev);
 860
 861 static int arizona_dvfs_enable(struct snd_soc_codec *codec)
 862 {
 863         const struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 864         struct arizona *arizona = priv->arizona;
 865         int ret;
 866
 867         ret = regulator_set_voltage(arizona->dcvdd, 1800000, 1800000);
 868         if (ret) {
 869                 dev_err(codec->dev, "Failed to boost DCVDD: %d\n", ret);
 870                 return ret;
 871         }
 872
 873         ret = regmap_update_bits(arizona->regmap,
 874                                  ARIZONA_DYNAMIC_FREQUENCY_SCALING_1,
 875                                  ARIZONA_SUBSYS_MAX_FREQ,
 876                                  ARIZONA_SUBSYS_MAX_FREQ);
 877         if (ret) {
 878                 dev_err(codec->dev, "Failed to enable subsys max: %d\n", ret);
 879                 regulator_set_voltage(arizona->dcvdd, 1200000, 1800000);
 880                 return ret;
 881         }
 882
 883         return 0;
 884 }
 885
 886 static int arizona_dvfs_disable(struct snd_soc_codec *codec)
 887 {
 888         const struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 889         struct arizona *arizona = priv->arizona;
 890         int ret;
 891
 892         ret = regmap_update_bits(arizona->regmap,
 893                                  ARIZONA_DYNAMIC_FREQUENCY_SCALING_1,
 894                                  ARIZONA_SUBSYS_MAX_FREQ, 0);
 895         if (ret) {
 896                 dev_err(codec->dev, "Failed to disable subsys max: %d\n", ret);
 897                 return ret;
 898         }
 899
 900         ret = regulator_set_voltage(arizona->dcvdd, 1200000, 1800000);
 901         if (ret) {
 902                 dev_err(codec->dev, "Failed to unboost DCVDD: %d\n", ret);
 903                 return ret;
 904         }
 905
 906         return 0;
 907 }
 908
 909 int arizona_dvfs_up(struct snd_soc_codec *codec, unsigned int flags)
 910 {
 911         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 912         int ret = 0;
 913
 914         mutex_lock(&priv->dvfs_lock);
 915
 916         if (!priv->dvfs_cached && !priv->dvfs_reqs) {
 917                 ret = arizona_dvfs_enable(codec);
 918                 if (ret)
 919                         goto err;
 920         }
 921
 922         priv->dvfs_reqs |= flags;
 923 err:
 924         mutex_unlock(&priv->dvfs_lock);
 925         return ret;
 926 }
 927 EXPORT_SYMBOL_GPL(arizona_dvfs_up);
 928
 929 int arizona_dvfs_down(struct snd_soc_codec *codec, unsigned int flags)
 930 {
 931         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 932         unsigned int old_reqs;
 933         int ret = 0;
 934
 935         mutex_lock(&priv->dvfs_lock);
 936
 937         old_reqs = priv->dvfs_reqs;
 938         priv->dvfs_reqs &= ~flags;
 939
 940         if (!priv->dvfs_cached && old_reqs && !priv->dvfs_reqs)
 941                 ret = arizona_dvfs_disable(codec);
 942
 943         mutex_unlock(&priv->dvfs_lock);
 944         return ret;
 945 }
 946 EXPORT_SYMBOL_GPL(arizona_dvfs_down);
 947
 948 int arizona_dvfs_sysclk_ev(struct snd_soc_dapm_widget *w,
 949                            struct snd_kcontrol *kcontrol, int event)
 950 {
 951         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 952         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 953         int ret = 0;
 954
 955         mutex_lock(&priv->dvfs_lock);
 956
 957         switch (event) {
 958         case SND_SOC_DAPM_POST_PMU:
 959                 if (priv->dvfs_reqs)
 960                         ret = arizona_dvfs_enable(codec);
 961
 962                 priv->dvfs_cached = false;
 963                 break;
 964         case SND_SOC_DAPM_PRE_PMD:
 965                 /* We must ensure DVFS is disabled before the codec goes into
 966                  * suspend so that we are never in an illegal state of DVFS
 967                  * enabled without enough DCVDD
 968                  */
 969                 priv->dvfs_cached = true;
 970
 971                 if (priv->dvfs_reqs)
 972                         ret = arizona_dvfs_disable(codec);
 973                 break;
 974         default:
 975                 break;
 976         }
 977
 978         mutex_unlock(&priv->dvfs_lock);
 979         return ret;
 980 }
 981 EXPORT_SYMBOL_GPL(arizona_dvfs_sysclk_ev);
 982
 983 void arizona_init_dvfs(struct arizona_priv *priv)
 984 {
 985         mutex_init(&priv->dvfs_lock);
 986 }
 987 EXPORT_SYMBOL_GPL(arizona_init_dvfs);
 988
 989 static unsigned int arizona_sysclk_48k_rates[] = {
 990         6144000,
 991         12288000,
 992         24576000,
 993         49152000,
 994         73728000,
 995         98304000,
 996         147456000,
 997 };
 998
 999 static unsigned int arizona_sysclk_44k1_rates[] = {
1000         5644800,
1001         11289600,
1002         22579200,
1003         45158400,
1004         67737600,
1005         90316800,
1006         135475200,
1007 };
1008
1009 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
1010                              unsigned int freq)
1011 {
1012         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1013         unsigned int reg;
1014         unsigned int *rates;
1015         int ref, div, refclk;
1016
1017         switch (clk) {
1018         case ARIZONA_CLK_OPCLK:
1019                 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
1020                 refclk = priv->sysclk;
1021                 break;
1022         case ARIZONA_CLK_ASYNC_OPCLK:
1023                 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
1024                 refclk = priv->asyncclk;
1025                 break;
1026         default:
1027                 return -EINVAL;
1028         }
1029
1030         if (refclk % 8000)
1031                 rates = arizona_sysclk_44k1_rates;
1032         else
1033                 rates = arizona_sysclk_48k_rates;
1034
1035         for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
1036                      rates[ref] <= refclk; ref++) {
1037                 div = 1;
1038                 while (rates[ref] / div >= freq && div < 32) {
1039                         if (rates[ref] / div == freq) {
1040                                 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
1041                                         freq);
1042                                 snd_soc_update_bits(codec, reg,
1043                                                     ARIZONA_OPCLK_DIV_MASK |
1044                                                     ARIZONA_OPCLK_SEL_MASK,
1045                                                     (div <<
1046                                                      ARIZONA_OPCLK_DIV_SHIFT) |
1047                                                     ref);
1048                                 return 0;
1049                         }
1050                         div++;
1051                 }
1052         }
1053
1054         dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
1055         return -EINVAL;
1056 }
1057
1058 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1059                        int source, unsigned int freq, int dir)
1060 {
1061         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1062         struct arizona *arizona = priv->arizona;
1063         char *name;
1064         unsigned int reg;
1065         unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
1066         unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
1067         unsigned int *clk;
1068
1069         switch (clk_id) {
1070         case ARIZONA_CLK_SYSCLK:
1071                 name = "SYSCLK";
1072                 reg = ARIZONA_SYSTEM_CLOCK_1;
1073                 clk = &priv->sysclk;
1074                 mask |= ARIZONA_SYSCLK_FRAC;
1075                 break;
1076         case ARIZONA_CLK_ASYNCCLK:
1077                 name = "ASYNCCLK";
1078                 reg = ARIZONA_ASYNC_CLOCK_1;
1079                 clk = &priv->asyncclk;
1080                 break;
1081         case ARIZONA_CLK_OPCLK:
1082         case ARIZONA_CLK_ASYNC_OPCLK:
1083                 return arizona_set_opclk(codec, clk_id, freq);
1084         default:
1085                 return -EINVAL;
1086         }
1087
1088         switch (freq) {
1089         case  5644800:
1090         case  6144000:
1091                 break;
1092         case 11289600:
1093         case 12288000:
1094                 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1095                 break;
1096         case 22579200:
1097         case 24576000:
1098                 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1099                 break;
1100         case 45158400:
1101         case 49152000:
1102                 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1103                 break;
1104         case 67737600:
1105         case 73728000:
1106                 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1107                 break;
1108         case 90316800:
1109         case 98304000:
1110                 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1111                 break;
1112         case 135475200:
1113         case 147456000:
1114                 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1115                 break;
1116         case 0:
1117                 dev_dbg(arizona->dev, "%s cleared\n", name);
1118                 *clk = freq;
1119                 return 0;
1120         default:
1121                 return -EINVAL;
1122         }
1123
1124         *clk = freq;
1125
1126         if (freq % 6144000)
1127                 val |= ARIZONA_SYSCLK_FRAC;
1128
1129         dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
1130
1131         return regmap_update_bits(arizona->regmap, reg, mask, val);
1132 }
1133 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
1134
1135 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1136 {
1137         struct snd_soc_codec *codec = dai->codec;
1138         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1139         struct arizona *arizona = priv->arizona;
1140         int lrclk, bclk, mode, base;
1141
1142         base = dai->driver->base;
1143
1144         lrclk = 0;
1145         bclk = 0;
1146
1147         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1148         case SND_SOC_DAIFMT_DSP_A:
1149                 mode = ARIZONA_FMT_DSP_MODE_A;
1150                 break;
1151         case SND_SOC_DAIFMT_DSP_B:
1152                 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK)
1153                                 != SND_SOC_DAIFMT_CBM_CFM) {
1154                         arizona_aif_err(dai, "DSP_B not valid in slave mode\n");
1155                         return -EINVAL;
1156                 }
1157                 mode = ARIZONA_FMT_DSP_MODE_B;
1158                 break;
1159         case SND_SOC_DAIFMT_I2S:
1160                 mode = ARIZONA_FMT_I2S_MODE;
1161                 break;
1162         case SND_SOC_DAIFMT_LEFT_J:
1163                 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK)
1164                                 != SND_SOC_DAIFMT_CBM_CFM) {
1165                         arizona_aif_err(dai, "LEFT_J not valid in slave mode\n");
1166                         return -EINVAL;
1167                 }
1168                 mode = ARIZONA_FMT_LEFT_JUSTIFIED_MODE;
1169                 break;
1170         default:
1171                 arizona_aif_err(dai, "Unsupported DAI format %d\n",
1172                                 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1173                 return -EINVAL;
1174         }
1175
1176         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1177         case SND_SOC_DAIFMT_CBS_CFS:
1178                 break;
1179         case SND_SOC_DAIFMT_CBS_CFM:
1180                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
1181                 break;
1182         case SND_SOC_DAIFMT_CBM_CFS:
1183                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
1184                 break;
1185         case SND_SOC_DAIFMT_CBM_CFM:
1186                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
1187                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
1188                 break;
1189         default:
1190                 arizona_aif_err(dai, "Unsupported master mode %d\n",
1191                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1192                 return -EINVAL;
1193         }
1194
1195         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1196         case SND_SOC_DAIFMT_NB_NF:
1197                 break;
1198         case SND_SOC_DAIFMT_IB_IF:
1199                 bclk |= ARIZONA_AIF1_BCLK_INV;
1200                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
1201                 break;
1202         case SND_SOC_DAIFMT_IB_NF:
1203                 bclk |= ARIZONA_AIF1_BCLK_INV;
1204                 break;
1205         case SND_SOC_DAIFMT_NB_IF:
1206                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
1207                 break;
1208         default:
1209                 return -EINVAL;
1210         }
1211
1212         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
1213                                  ARIZONA_AIF1_BCLK_INV |
1214                                  ARIZONA_AIF1_BCLK_MSTR,
1215                                  bclk);
1216         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
1217                                  ARIZONA_AIF1TX_LRCLK_INV |
1218                                  ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
1219         regmap_update_bits_async(arizona->regmap,
1220                                  base + ARIZONA_AIF_RX_PIN_CTRL,
1221                                  ARIZONA_AIF1RX_LRCLK_INV |
1222                                  ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
1223         regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
1224                            ARIZONA_AIF1_FMT_MASK, mode);
1225
1226         return 0;
1227 }
1228
1229 static const int arizona_48k_bclk_rates[] = {
1230         -1,
1231         48000,
1232         64000,
1233         96000,
1234         128000,
1235         192000,
1236         256000,
1237         384000,
1238         512000,
1239         768000,
1240         1024000,
1241         1536000,
1242         2048000,
1243         3072000,
1244         4096000,
1245         6144000,
1246         8192000,
1247         12288000,
1248         24576000,
1249 };
1250
1251 static const unsigned int arizona_48k_rates[] = {
1252         12000,
1253         24000,
1254         48000,
1255         96000,
1256         192000,
1257         384000,
1258         768000,
1259         4000,
1260         8000,
1261         16000,
1262         32000,
1263         64000,
1264         128000,
1265         256000,
1266         512000,
1267 };
1268
1269 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
1270         .count  = ARRAY_SIZE(arizona_48k_rates),
1271         .list   = arizona_48k_rates,
1272 };
1273
1274 static const int arizona_44k1_bclk_rates[] = {
1275         -1,
1276         44100,
1277         58800,
1278         88200,
1279         117600,
1280         177640,
1281         235200,
1282         352800,
1283         470400,
1284         705600,
1285         940800,
1286         1411200,
1287         1881600,
1288         2822400,
1289         3763200,
1290         5644800,
1291         7526400,
1292         11289600,
1293         22579200,
1294 };
1295
1296 static const unsigned int arizona_44k1_rates[] = {
1297         11025,
1298         22050,
1299         44100,
1300         88200,
1301         176400,
1302         352800,
1303         705600,
1304 };
1305
1306 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
1307         .count  = ARRAY_SIZE(arizona_44k1_rates),
1308         .list   = arizona_44k1_rates,
1309 };
1310
1311 static int arizona_sr_vals[] = {
1312         0,
1313         12000,
1314         24000,
1315         48000,
1316         96000,
1317         192000,
1318         384000,
1319         768000,
1320         0,
1321         11025,
1322         22050,
1323         44100,
1324         88200,
1325         176400,
1326         352800,
1327         705600,
1328         4000,
1329         8000,
1330         16000,
1331         32000,
1332         64000,
1333         128000,
1334         256000,
1335         512000,
1336 };
1337
1338 static int arizona_startup(struct snd_pcm_substream *substream,
1339                            struct snd_soc_dai *dai)
1340 {
1341         struct snd_soc_codec *codec = dai->codec;
1342         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1343         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1344         const struct snd_pcm_hw_constraint_list *constraint;
1345         unsigned int base_rate;
1346
1347         switch (dai_priv->clk) {
1348         case ARIZONA_CLK_SYSCLK:
1349                 base_rate = priv->sysclk;
1350                 break;
1351         case ARIZONA_CLK_ASYNCCLK:
1352                 base_rate = priv->asyncclk;
1353                 break;
1354         default:
1355                 return 0;
1356         }
1357
1358         if (base_rate == 0)
1359                 return 0;
1360
1361         if (base_rate % 8000)
1362                 constraint = &arizona_44k1_constraint;
1363         else
1364                 constraint = &arizona_48k_constraint;
1365
1366         return snd_pcm_hw_constraint_list(substream->runtime, 0,
1367                                           SNDRV_PCM_HW_PARAM_RATE,
1368                                           constraint);
1369 }
1370
1371 static void arizona_wm5102_set_dac_comp(struct snd_soc_codec *codec,
1372                                         unsigned int rate)
1373 {
1374         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1375         struct arizona *arizona = priv->arizona;
1376         struct reg_sequence dac_comp[] = {
1377                 { 0x80, 0x3 },
1378                 { ARIZONA_DAC_COMP_1, 0 },
1379                 { ARIZONA_DAC_COMP_2, 0 },
1380                 { 0x80, 0x0 },
1381         };
1382
1383         mutex_lock(&arizona->dac_comp_lock);
1384
1385         dac_comp[1].def = arizona->dac_comp_coeff;
1386         if (rate >= 176400)
1387                 dac_comp[2].def = arizona->dac_comp_enabled;
1388
1389         mutex_unlock(&arizona->dac_comp_lock);
1390
1391         regmap_multi_reg_write(arizona->regmap,
1392                                dac_comp,
1393                                ARRAY_SIZE(dac_comp));
1394 }
1395
1396 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1397                                   struct snd_pcm_hw_params *params,
1398                                   struct snd_soc_dai *dai)
1399 {
1400         struct snd_soc_codec *codec = dai->codec;
1401         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1402         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1403         int base = dai->driver->base;
1404         int i, sr_val, ret;
1405
1406         /*
1407          * We will need to be more flexible than this in future,
1408          * currently we use a single sample rate for SYSCLK.
1409          */
1410         for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1411                 if (arizona_sr_vals[i] == params_rate(params))
1412                         break;
1413         if (i == ARRAY_SIZE(arizona_sr_vals)) {
1414                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1415                                 params_rate(params));
1416                 return -EINVAL;
1417         }
1418         sr_val = i;
1419
1420         switch (priv->arizona->type) {
1421         case WM5102:
1422         case WM8997:
1423                 if (arizona_sr_vals[sr_val] >= 88200)
1424                         ret = arizona_dvfs_up(codec, ARIZONA_DVFS_SR1_RQ);
1425                 else
1426                         ret = arizona_dvfs_down(codec, ARIZONA_DVFS_SR1_RQ);
1427
1428                 if (ret) {
1429                         arizona_aif_err(dai, "Failed to change DVFS %d\n", ret);
1430                         return ret;
1431                 }
1432                 break;
1433         default:
1434                 break;
1435         }
1436
1437         switch (dai_priv->clk) {
1438         case ARIZONA_CLK_SYSCLK:
1439                 switch (priv->arizona->type) {
1440                 case WM5102:
1441                         arizona_wm5102_set_dac_comp(codec,
1442                                                     params_rate(params));
1443                         break;
1444                 default:
1445                         break;
1446                 }
1447
1448                 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1449                                     ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1450                 if (base)
1451                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1452                                             ARIZONA_AIF1_RATE_MASK, 0);
1453                 break;
1454         case ARIZONA_CLK_ASYNCCLK:
1455                 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1456                                     ARIZONA_ASYNC_SAMPLE_RATE_1_MASK, sr_val);
1457                 if (base)
1458                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1459                                             ARIZONA_AIF1_RATE_MASK,
1460                                             8 << ARIZONA_AIF1_RATE_SHIFT);
1461                 break;
1462         default:
1463                 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1464                 return -EINVAL;
1465         }
1466
1467         return 0;
1468 }
1469
1470 static bool arizona_aif_cfg_changed(struct snd_soc_codec *codec,
1471                                     int base, int bclk, int lrclk, int frame)
1472 {
1473         int val;
1474
1475         val = snd_soc_read(codec, base + ARIZONA_AIF_BCLK_CTRL);
1476         if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK))
1477                 return true;
1478
1479         val = snd_soc_read(codec, base + ARIZONA_AIF_TX_BCLK_RATE);
1480         if (lrclk != (val & ARIZONA_AIF1TX_BCPF_MASK))
1481                 return true;
1482
1483         val = snd_soc_read(codec, base + ARIZONA_AIF_FRAME_CTRL_1);
1484         if (frame != (val & (ARIZONA_AIF1TX_WL_MASK |
1485                              ARIZONA_AIF1TX_SLOT_LEN_MASK)))
1486                 return true;
1487
1488         return false;
1489 }
1490
1491 static int arizona_hw_params(struct snd_pcm_substream *substream,
1492                              struct snd_pcm_hw_params *params,
1493                              struct snd_soc_dai *dai)
1494 {
1495         struct snd_soc_codec *codec = dai->codec;
1496         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1497         struct arizona *arizona = priv->arizona;
1498         int base = dai->driver->base;
1499         const int *rates;
1500         int i, ret, val;
1501         int channels = params_channels(params);
1502         int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1503         int tdm_width = arizona->tdm_width[dai->id - 1];
1504         int tdm_slots = arizona->tdm_slots[dai->id - 1];
1505         int bclk, lrclk, wl, frame, bclk_target;
1506         bool reconfig;
1507         unsigned int aif_tx_state, aif_rx_state;
1508
1509         if (params_rate(params) % 8000)
1510                 rates = &arizona_44k1_bclk_rates[0];
1511         else
1512                 rates = &arizona_48k_bclk_rates[0];
1513
1514         wl = params_width(params);
1515
1516         if (tdm_slots) {
1517                 arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n",
1518                                 tdm_slots, tdm_width);
1519                 bclk_target = tdm_slots * tdm_width * params_rate(params);
1520                 channels = tdm_slots;
1521         } else {
1522                 bclk_target = snd_soc_params_to_bclk(params);
1523                 tdm_width = wl;
1524         }
1525
1526         if (chan_limit && chan_limit < channels) {
1527                 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1528                 bclk_target /= channels;
1529                 bclk_target *= chan_limit;
1530         }
1531
1532         /* Force multiple of 2 channels for I2S mode */
1533         val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1534         val &= ARIZONA_AIF1_FMT_MASK;
1535         if ((channels & 1) && (val == ARIZONA_FMT_I2S_MODE)) {
1536                 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1537                 bclk_target /= channels;
1538                 bclk_target *= channels + 1;
1539         }
1540
1541         for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1542                 if (rates[i] >= bclk_target &&
1543                     rates[i] % params_rate(params) == 0) {
1544                         bclk = i;
1545                         break;
1546                 }
1547         }
1548         if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1549                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1550                                 params_rate(params));
1551                 return -EINVAL;
1552         }
1553
1554         lrclk = rates[bclk] / params_rate(params);
1555
1556         arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1557                         rates[bclk], rates[bclk] / lrclk);
1558
1559         frame = wl << ARIZONA_AIF1TX_WL_SHIFT | tdm_width;
1560
1561         reconfig = arizona_aif_cfg_changed(codec, base, bclk, lrclk, frame);
1562
1563         if (reconfig) {
1564                 /* Save AIF TX/RX state */
1565                 aif_tx_state = snd_soc_read(codec,
1566                                             base + ARIZONA_AIF_TX_ENABLES);
1567                 aif_rx_state = snd_soc_read(codec,
1568                                             base + ARIZONA_AIF_RX_ENABLES);
1569                 /* Disable AIF TX/RX before reconfiguring it */
1570                 regmap_update_bits_async(arizona->regmap,
1571                                     base + ARIZONA_AIF_TX_ENABLES, 0xff, 0x0);
1572                 regmap_update_bits(arizona->regmap,
1573                                     base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0);
1574         }
1575
1576         ret = arizona_hw_params_rate(substream, params, dai);
1577         if (ret != 0)
1578                 goto restore_aif;
1579
1580         if (reconfig) {
1581                 regmap_update_bits_async(arizona->regmap,
1582                                          base + ARIZONA_AIF_BCLK_CTRL,
1583                                          ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1584                 regmap_update_bits_async(arizona->regmap,
1585                                          base + ARIZONA_AIF_TX_BCLK_RATE,
1586                                          ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1587                 regmap_update_bits_async(arizona->regmap,
1588                                          base + ARIZONA_AIF_RX_BCLK_RATE,
1589                                          ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1590                 regmap_update_bits_async(arizona->regmap,
1591                                          base + ARIZONA_AIF_FRAME_CTRL_1,
1592                                          ARIZONA_AIF1TX_WL_MASK |
1593                                          ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1594                 regmap_update_bits(arizona->regmap,
1595                                    base + ARIZONA_AIF_FRAME_CTRL_2,
1596                                    ARIZONA_AIF1RX_WL_MASK |
1597                                    ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1598         }
1599
1600 restore_aif:
1601         if (reconfig) {
1602                 /* Restore AIF TX/RX state */
1603                 regmap_update_bits_async(arizona->regmap,
1604                                          base + ARIZONA_AIF_TX_ENABLES,
1605                                          0xff, aif_tx_state);
1606                 regmap_update_bits(arizona->regmap,
1607                                    base + ARIZONA_AIF_RX_ENABLES,
1608                                    0xff, aif_rx_state);
1609         }
1610         return ret;
1611 }
1612
1613 static const char *arizona_dai_clk_str(int clk_id)
1614 {
1615         switch (clk_id) {
1616         case ARIZONA_CLK_SYSCLK:
1617                 return "SYSCLK";
1618         case ARIZONA_CLK_ASYNCCLK:
1619                 return "ASYNCCLK";
1620         default:
1621                 return "Unknown clock";
1622         }
1623 }
1624
1625 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1626                                   int clk_id, unsigned int freq, int dir)
1627 {
1628         struct snd_soc_codec *codec = dai->codec;
1629         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1630         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1631         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1632         struct snd_soc_dapm_route routes[2];
1633
1634         switch (clk_id) {
1635         case ARIZONA_CLK_SYSCLK:
1636         case ARIZONA_CLK_ASYNCCLK:
1637                 break;
1638         default:
1639                 return -EINVAL;
1640         }
1641
1642         if (clk_id == dai_priv->clk)
1643                 return 0;
1644
1645         if (dai->active) {
1646                 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1647                         dai->id);
1648                 return -EBUSY;
1649         }
1650
1651         dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1652                 arizona_dai_clk_str(clk_id));
1653
1654         memset(&routes, 0, sizeof(routes));
1655         routes[0].sink = dai->driver->capture.stream_name;
1656         routes[1].sink = dai->driver->playback.stream_name;
1657
1658         routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1659         routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1660         snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
1661
1662         routes[0].source = arizona_dai_clk_str(clk_id);
1663         routes[1].source = arizona_dai_clk_str(clk_id);
1664         snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1665
1666         dai_priv->clk = clk_id;
1667
1668         return snd_soc_dapm_sync(dapm);
1669 }
1670
1671 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1672 {
1673         struct snd_soc_codec *codec = dai->codec;
1674         int base = dai->driver->base;
1675         unsigned int reg;
1676
1677         if (tristate)
1678                 reg = ARIZONA_AIF1_TRI;
1679         else
1680                 reg = 0;
1681
1682         return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1683                                    ARIZONA_AIF1_TRI, reg);
1684 }
1685
1686 static void arizona_set_channels_to_mask(struct snd_soc_dai *dai,
1687                                          unsigned int base,
1688                                          int channels, unsigned int mask)
1689 {
1690         struct snd_soc_codec *codec = dai->codec;
1691         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1692         struct arizona *arizona = priv->arizona;
1693         int slot, i;
1694
1695         for (i = 0; i < channels; ++i) {
1696                 slot = ffs(mask) - 1;
1697                 if (slot < 0)
1698                         return;
1699
1700                 regmap_write(arizona->regmap, base + i, slot);
1701
1702                 mask &= ~(1 << slot);
1703         }
1704
1705         if (mask)
1706                 arizona_aif_warn(dai, "Too many channels in TDM mask\n");
1707 }
1708
1709 static int arizona_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1710                                 unsigned int rx_mask, int slots, int slot_width)
1711 {
1712         struct snd_soc_codec *codec = dai->codec;
1713         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1714         struct arizona *arizona = priv->arizona;
1715         int base = dai->driver->base;
1716         int rx_max_chan = dai->driver->playback.channels_max;
1717         int tx_max_chan = dai->driver->capture.channels_max;
1718
1719         /* Only support TDM for the physical AIFs */
1720         if (dai->id > ARIZONA_MAX_AIF)
1721                 return -ENOTSUPP;
1722
1723         if (slots == 0) {
1724                 tx_mask = (1 << tx_max_chan) - 1;
1725                 rx_mask = (1 << rx_max_chan) - 1;
1726         }
1727
1728         arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3,
1729                                      tx_max_chan, tx_mask);
1730         arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11,
1731                                      rx_max_chan, rx_mask);
1732
1733         arizona->tdm_width[dai->id - 1] = slot_width;
1734         arizona->tdm_slots[dai->id - 1] = slots;
1735
1736         return 0;
1737 }
1738
1739 const struct snd_soc_dai_ops arizona_dai_ops = {
1740         .startup = arizona_startup,
1741         .set_fmt = arizona_set_fmt,
1742         .set_tdm_slot = arizona_set_tdm_slot,
1743         .hw_params = arizona_hw_params,
1744         .set_sysclk = arizona_dai_set_sysclk,
1745         .set_tristate = arizona_set_tristate,
1746 };
1747 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1748
1749 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1750         .startup = arizona_startup,
1751         .hw_params = arizona_hw_params_rate,
1752         .set_sysclk = arizona_dai_set_sysclk,
1753 };
1754 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1755
1756 int arizona_init_dai(struct arizona_priv *priv, int id)
1757 {
1758         struct arizona_dai_priv *dai_priv = &priv->dai[id];
1759
1760         dai_priv->clk = ARIZONA_CLK_SYSCLK;
1761
1762         return 0;
1763 }
1764 EXPORT_SYMBOL_GPL(arizona_init_dai);
1765
1766 static struct {
1767         unsigned int min;
1768         unsigned int max;
1769         u16 fratio;
1770         int ratio;
1771 } fll_fratios[] = {
1772         {       0,    64000, 4, 16 },
1773         {   64000,   128000, 3,  8 },
1774         {  128000,   256000, 2,  4 },
1775         {  256000,  1000000, 1,  2 },
1776         { 1000000, 13500000, 0,  1 },
1777 };
1778
1779 static struct {
1780         unsigned int min;
1781         unsigned int max;
1782         u16 gain;
1783 } fll_gains[] = {
1784         {       0,   256000, 0 },
1785         {  256000,  1000000, 2 },
1786         { 1000000, 13500000, 4 },
1787 };
1788
1789 struct arizona_fll_cfg {
1790         int n;
1791         int theta;
1792         int lambda;
1793         int refdiv;
1794         int outdiv;
1795         int fratio;
1796         int gain;
1797 };
1798
1799 static int arizona_validate_fll(struct arizona_fll *fll,
1800                                 unsigned int Fref,
1801                                 unsigned int Fout)
1802 {
1803         unsigned int Fvco_min;
1804
1805         if (fll->fout && Fout != fll->fout) {
1806                 arizona_fll_err(fll,
1807                                 "Can't change output on active FLL\n");
1808                 return -EINVAL;
1809         }
1810
1811         if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
1812                 arizona_fll_err(fll,
1813                                 "Can't scale %dMHz in to <=13.5MHz\n",
1814                                 Fref);
1815                 return -EINVAL;
1816         }
1817
1818         Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult;
1819         if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) {
1820                 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1821                                 Fout);
1822                 return -EINVAL;
1823         }
1824
1825         return 0;
1826 }
1827
1828 static int arizona_find_fratio(unsigned int Fref, int *fratio)
1829 {
1830         int i;
1831
1832         /* Find an appropriate FLL_FRATIO */
1833         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1834                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1835                         if (fratio)
1836                                 *fratio = fll_fratios[i].fratio;
1837                         return fll_fratios[i].ratio;
1838                 }
1839         }
1840
1841         return -EINVAL;
1842 }
1843
1844 static int arizona_calc_fratio(struct arizona_fll *fll,
1845                                struct arizona_fll_cfg *cfg,
1846                                unsigned int target,
1847                                unsigned int Fref, bool sync)
1848 {
1849         int init_ratio, ratio;
1850         int refdiv, div;
1851
1852         /* Fref must be <=13.5MHz, find initial refdiv */
1853         div = 1;
1854         cfg->refdiv = 0;
1855         while (Fref > ARIZONA_FLL_MAX_FREF) {
1856                 div *= 2;
1857                 Fref /= 2;
1858                 cfg->refdiv++;
1859
1860                 if (div > ARIZONA_FLL_MAX_REFDIV)
1861                         return -EINVAL;
1862         }
1863
1864         /* Find an appropriate FLL_FRATIO */
1865         init_ratio = arizona_find_fratio(Fref, &cfg->fratio);
1866         if (init_ratio < 0) {
1867                 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1868                                 Fref);
1869                 return init_ratio;
1870         }
1871
1872         switch (fll->arizona->type) {
1873         case WM5110:
1874         case WM8280:
1875                 if (fll->arizona->rev < 3 || sync)
1876                         return init_ratio;
1877                 break;
1878         default:
1879                 return init_ratio;
1880         }
1881
1882         cfg->fratio = init_ratio - 1;
1883
1884         /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1885         refdiv = cfg->refdiv;
1886
1887         while (div <= ARIZONA_FLL_MAX_REFDIV) {
1888                 for (ratio = init_ratio; ratio <= ARIZONA_FLL_MAX_FRATIO;
1889                      ratio++) {
1890                         if ((ARIZONA_FLL_VCO_CORNER / 2) /
1891                             (fll->vco_mult * ratio) < Fref)
1892                                 break;
1893
1894                         if (target % (ratio * Fref)) {
1895                                 cfg->refdiv = refdiv;
1896                                 cfg->fratio = ratio - 1;
1897                                 return ratio;
1898                         }
1899                 }
1900
1901                 for (ratio = init_ratio - 1; ratio > 0; ratio--) {
1902                         if (target % (ratio * Fref)) {
1903                                 cfg->refdiv = refdiv;
1904                                 cfg->fratio = ratio - 1;
1905                                 return ratio;
1906                         }
1907                 }
1908
1909                 div *= 2;
1910                 Fref /= 2;
1911                 refdiv++;
1912                 init_ratio = arizona_find_fratio(Fref, NULL);
1913         }
1914
1915         arizona_fll_warn(fll, "Falling back to integer mode operation\n");
1916         return cfg->fratio + 1;
1917 }
1918
1919 static int arizona_calc_fll(struct arizona_fll *fll,
1920                             struct arizona_fll_cfg *cfg,
1921                             unsigned int Fref, bool sync)
1922 {
1923         unsigned int target, div, gcd_fll;
1924         int i, ratio;
1925
1926         arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout);
1927
1928         /* Fvco should be over the targt; don't check the upper bound */
1929         div = ARIZONA_FLL_MIN_OUTDIV;
1930         while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) {
1931                 div++;
1932                 if (div > ARIZONA_FLL_MAX_OUTDIV)
1933                         return -EINVAL;
1934         }
1935         target = fll->fout * div / fll->vco_mult;
1936         cfg->outdiv = div;
1937
1938         arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1939
1940         /* Find an appropriate FLL_FRATIO and refdiv */
1941         ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync);
1942         if (ratio < 0)
1943                 return ratio;
1944
1945         /* Apply the division for our remaining calculations */
1946         Fref = Fref / (1 << cfg->refdiv);
1947
1948         cfg->n = target / (ratio * Fref);
1949
1950         if (target % (ratio * Fref)) {
1951                 gcd_fll = gcd(target, ratio * Fref);
1952                 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1953
1954                 cfg->theta = (target - (cfg->n * ratio * Fref))
1955                         / gcd_fll;
1956                 cfg->lambda = (ratio * Fref) / gcd_fll;
1957         } else {
1958                 cfg->theta = 0;
1959                 cfg->lambda = 0;
1960         }
1961
1962         /* Round down to 16bit range with cost of accuracy lost.
1963          * Denominator must be bigger than numerator so we only
1964          * take care of it.
1965          */
1966         while (cfg->lambda >= (1 << 16)) {
1967                 cfg->theta >>= 1;
1968                 cfg->lambda >>= 1;
1969         }
1970
1971         for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1972                 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1973                         cfg->gain = fll_gains[i].gain;
1974                         break;
1975                 }
1976         }
1977         if (i == ARRAY_SIZE(fll_gains)) {
1978                 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1979                                 Fref);
1980                 return -EINVAL;
1981         }
1982
1983         arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1984                         cfg->n, cfg->theta, cfg->lambda);
1985         arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1986                         cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1987         arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1988
1989         return 0;
1990
1991 }
1992
1993 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1994                               struct arizona_fll_cfg *cfg, int source,
1995                               bool sync)
1996 {
1997         regmap_update_bits_async(arizona->regmap, base + 3,
1998                                  ARIZONA_FLL1_THETA_MASK, cfg->theta);
1999         regmap_update_bits_async(arizona->regmap, base + 4,
2000                                  ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
2001         regmap_update_bits_async(arizona->regmap, base + 5,
2002                                  ARIZONA_FLL1_FRATIO_MASK,
2003                                  cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
2004         regmap_update_bits_async(arizona->regmap, base + 6,
2005                                  ARIZONA_FLL1_CLK_REF_DIV_MASK |
2006                                  ARIZONA_FLL1_CLK_REF_SRC_MASK,
2007                                  cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
2008                                  source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
2009
2010         if (sync) {
2011                 regmap_update_bits(arizona->regmap, base + 0x7,
2012                                    ARIZONA_FLL1_GAIN_MASK,
2013                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
2014         } else {
2015                 regmap_update_bits(arizona->regmap, base + 0x5,
2016                                    ARIZONA_FLL1_OUTDIV_MASK,
2017                                    cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
2018                 regmap_update_bits(arizona->regmap, base + 0x9,
2019                                    ARIZONA_FLL1_GAIN_MASK,
2020                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
2021         }
2022
2023         regmap_update_bits_async(arizona->regmap, base + 2,
2024                                  ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
2025                                  ARIZONA_FLL1_CTRL_UPD | cfg->n);
2026 }
2027
2028 static int arizona_is_enabled_fll(struct arizona_fll *fll)
2029 {
2030         struct arizona *arizona = fll->arizona;
2031         unsigned int reg;
2032         int ret;
2033
2034         ret = regmap_read(arizona->regmap, fll->base + 1, &reg);
2035         if (ret != 0) {
2036                 arizona_fll_err(fll, "Failed to read current state: %d\n",
2037                                 ret);
2038                 return ret;
2039         }
2040
2041         return reg & ARIZONA_FLL1_ENA;
2042 }
2043
2044 static int arizona_enable_fll(struct arizona_fll *fll)
2045 {
2046         struct arizona *arizona = fll->arizona;
2047         bool use_sync = false;
2048         int already_enabled = arizona_is_enabled_fll(fll);
2049         struct arizona_fll_cfg cfg;
2050         int i;
2051         unsigned int val;
2052
2053         if (already_enabled < 0)
2054                 return already_enabled;
2055
2056         if (already_enabled) {
2057                 /* Facilitate smooth refclk across the transition */
2058                 regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9,
2059                                          ARIZONA_FLL1_GAIN_MASK, 0);
2060                 regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,
2061                                          ARIZONA_FLL1_FREERUN,
2062                                          ARIZONA_FLL1_FREERUN);
2063         }
2064
2065         /*
2066          * If we have both REFCLK and SYNCCLK then enable both,
2067          * otherwise apply the SYNCCLK settings to REFCLK.
2068          */
2069         if (fll->ref_src >= 0 && fll->ref_freq &&
2070             fll->ref_src != fll->sync_src) {
2071                 arizona_calc_fll(fll, &cfg, fll->ref_freq, false);
2072
2073                 arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src,
2074                                   false);
2075                 if (fll->sync_src >= 0) {
2076                         arizona_calc_fll(fll, &cfg, fll->sync_freq, true);
2077
2078                         arizona_apply_fll(arizona, fll->base + 0x10, &cfg,
2079                                           fll->sync_src, true);
2080                         use_sync = true;
2081                 }
2082         } else if (fll->sync_src >= 0) {
2083                 arizona_calc_fll(fll, &cfg, fll->sync_freq, false);
2084
2085                 arizona_apply_fll(arizona, fll->base, &cfg,
2086                                   fll->sync_src, false);
2087
2088                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
2089                                          ARIZONA_FLL1_SYNC_ENA, 0);
2090         } else {
2091                 arizona_fll_err(fll, "No clocks provided\n");
2092                 return -EINVAL;
2093         }
2094
2095         /*
2096          * Increase the bandwidth if we're not using a low frequency
2097          * sync source.
2098          */
2099         if (use_sync && fll->sync_freq > 100000)
2100                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
2101                                          ARIZONA_FLL1_SYNC_BW, 0);
2102         else
2103                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
2104                                          ARIZONA_FLL1_SYNC_BW,
2105                                          ARIZONA_FLL1_SYNC_BW);
2106
2107         if (!already_enabled)
2108                 pm_runtime_get(arizona->dev);
2109
2110         regmap_update_bits_async(arizona->regmap, fll->base + 1,
2111                                  ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
2112         if (use_sync)
2113                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
2114                                          ARIZONA_FLL1_SYNC_ENA,
2115                                          ARIZONA_FLL1_SYNC_ENA);
2116
2117         if (already_enabled)
2118                 regmap_update_bits_async(arizona->regmap, fll->base + 1,
2119                                          ARIZONA_FLL1_FREERUN, 0);
2120
2121         arizona_fll_dbg(fll, "Waiting for FLL lock...\n");
2122         val = 0;
2123         for (i = 0; i < 15; i++) {
2124                 if (i < 5)
2125                         usleep_range(200, 400);
2126                 else
2127                         msleep(20);
2128
2129                 regmap_read(arizona->regmap,
2130                             ARIZONA_INTERRUPT_RAW_STATUS_5,
2131                             &val);
2132                 if (val & (ARIZONA_FLL1_CLOCK_OK_STS << (fll->id - 1)))
2133                         break;
2134         }
2135         if (i == 15)
2136                 arizona_fll_warn(fll, "Timed out waiting for lock\n");
2137         else
2138                 arizona_fll_dbg(fll, "FLL locked (%d polls)\n", i);
2139
2140         return 0;
2141 }
2142
2143 static void arizona_disable_fll(struct arizona_fll *fll)
2144 {
2145         struct arizona *arizona = fll->arizona;
2146         bool change;
2147
2148         regmap_update_bits_async(arizona->regmap, fll->base + 1,
2149                                  ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
2150         regmap_update_bits_check(arizona->regmap, fll->base + 1,
2151                                  ARIZONA_FLL1_ENA, 0, &change);
2152         regmap_update_bits(arizona->regmap, fll->base + 0x11,
2153                            ARIZONA_FLL1_SYNC_ENA, 0);
2154         regmap_update_bits_async(arizona->regmap, fll->base + 1,
2155                                  ARIZONA_FLL1_FREERUN, 0);
2156
2157         if (change)
2158                 pm_runtime_put_autosuspend(arizona->dev);
2159 }
2160
2161 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
2162                            unsigned int Fref, unsigned int Fout)
2163 {
2164         int ret = 0;
2165
2166         if (fll->ref_src == source && fll->ref_freq == Fref)
2167                 return 0;
2168
2169         if (fll->fout && Fref > 0) {
2170                 ret = arizona_validate_fll(fll, Fref, fll->fout);
2171                 if (ret != 0)
2172                         return ret;
2173         }
2174
2175         fll->ref_src = source;
2176         fll->ref_freq = Fref;
2177
2178         if (fll->fout && Fref > 0) {
2179                 ret = arizona_enable_fll(fll);
2180         }
2181
2182         return ret;
2183 }
2184 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
2185
2186 int arizona_set_fll(struct arizona_fll *fll, int source,
2187                     unsigned int Fref, unsigned int Fout)
2188 {
2189         int ret = 0;
2190
2191         if (fll->sync_src == source &&
2192             fll->sync_freq == Fref && fll->fout == Fout)
2193                 return 0;
2194
2195         if (Fout) {
2196                 if (fll->ref_src >= 0) {
2197                         ret = arizona_validate_fll(fll, fll->ref_freq, Fout);
2198                         if (ret != 0)
2199                                 return ret;
2200                 }
2201
2202                 ret = arizona_validate_fll(fll, Fref, Fout);
2203                 if (ret != 0)
2204                         return ret;
2205         }
2206
2207         fll->sync_src = source;
2208         fll->sync_freq = Fref;
2209         fll->fout = Fout;
2210
2211         if (Fout)
2212                 ret = arizona_enable_fll(fll);
2213         else
2214                 arizona_disable_fll(fll);
2215
2216         return ret;
2217 }
2218 EXPORT_SYMBOL_GPL(arizona_set_fll);
2219
2220 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
2221                      int ok_irq, struct arizona_fll *fll)
2222 {
2223         unsigned int val;
2224
2225         fll->id = id;
2226         fll->base = base;
2227         fll->arizona = arizona;
2228         fll->sync_src = ARIZONA_FLL_SRC_NONE;
2229
2230         /* Configure default refclk to 32kHz if we have one */
2231         regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
2232         switch (val & ARIZONA_CLK_32K_SRC_MASK) {
2233         case ARIZONA_CLK_SRC_MCLK1:
2234         case ARIZONA_CLK_SRC_MCLK2:
2235                 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
2236                 break;
2237         default:
2238                 fll->ref_src = ARIZONA_FLL_SRC_NONE;
2239         }
2240         fll->ref_freq = 32768;
2241
2242         snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
2243         snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
2244                  "FLL%d clock OK", id);
2245
2246         regmap_update_bits(arizona->regmap, fll->base + 1,
2247                            ARIZONA_FLL1_FREERUN, 0);
2248
2249         return 0;
2250 }
2251 EXPORT_SYMBOL_GPL(arizona_init_fll);
2252
2253 /**
2254  * arizona_set_output_mode - Set the mode of the specified output
2255  *
2256  * @codec: Device to configure
2257  * @output: Output number
2258  * @diff: True to set the output to differential mode
2259  *
2260  * Some systems use external analogue switches to connect more
2261  * analogue devices to the CODEC than are supported by the device.  In
2262  * some systems this requires changing the switched output from single
2263  * ended to differential mode dynamically at runtime, an operation
2264  * supported using this function.
2265  *
2266  * Most systems have a single static configuration and should use
2267  * platform data instead.
2268  */
2269 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
2270 {
2271         unsigned int reg, val;
2272
2273         if (output < 1 || output > 6)
2274                 return -EINVAL;
2275
2276         reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
2277
2278         if (diff)
2279                 val = ARIZONA_OUT1_MONO;
2280         else
2281                 val = 0;
2282
2283         return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
2284 }
2285 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
2286
2287 static const struct soc_enum arizona_adsp2_rate_enum[] = {
2288         SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
2289                               ARIZONA_DSP1_RATE_SHIFT, 0xf,
2290                               ARIZONA_RATE_ENUM_SIZE,
2291                               arizona_rate_text, arizona_rate_val),
2292         SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
2293                               ARIZONA_DSP1_RATE_SHIFT, 0xf,
2294                               ARIZONA_RATE_ENUM_SIZE,
2295                               arizona_rate_text, arizona_rate_val),
2296         SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
2297                               ARIZONA_DSP1_RATE_SHIFT, 0xf,
2298                               ARIZONA_RATE_ENUM_SIZE,
2299                               arizona_rate_text, arizona_rate_val),
2300         SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
2301                               ARIZONA_DSP1_RATE_SHIFT, 0xf,
2302                               ARIZONA_RATE_ENUM_SIZE,
2303                               arizona_rate_text, arizona_rate_val),
2304 };
2305
2306 const struct snd_kcontrol_new arizona_adsp2_rate_controls[] = {
2307         SOC_ENUM("DSP1 Rate", arizona_adsp2_rate_enum[0]),
2308         SOC_ENUM("DSP2 Rate", arizona_adsp2_rate_enum[1]),
2309         SOC_ENUM("DSP3 Rate", arizona_adsp2_rate_enum[2]),
2310         SOC_ENUM("DSP4 Rate", arizona_adsp2_rate_enum[3]),
2311 };
2312 EXPORT_SYMBOL_GPL(arizona_adsp2_rate_controls);
2313
2314 static bool arizona_eq_filter_unstable(bool mode, __be16 _a, __be16 _b)
2315 {
2316         s16 a = be16_to_cpu(_a);
2317         s16 b = be16_to_cpu(_b);
2318
2319         if (!mode) {
2320                 return abs(a) >= 4096;
2321         } else {
2322                 if (abs(b) >= 4096)
2323                         return true;
2324
2325                 return (abs((a << 16) / (4096 - b)) >= 4096 << 4);
2326         }
2327 }
2328
2329 int arizona_eq_coeff_put(struct snd_kcontrol *kcontrol,
2330                          struct snd_ctl_elem_value *ucontrol)
2331 {
2332         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2333         struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
2334         struct soc_bytes *params = (void *)kcontrol->private_value;
2335         unsigned int val;
2336         __be16 *data;
2337         int len;
2338         int ret;
2339
2340         len = params->num_regs * regmap_get_val_bytes(arizona->regmap);
2341
2342         data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA);
2343         if (!data)
2344                 return -ENOMEM;
2345
2346         data[0] &= cpu_to_be16(ARIZONA_EQ1_B1_MODE);
2347
2348         if (arizona_eq_filter_unstable(!!data[0], data[1], data[2]) ||
2349             arizona_eq_filter_unstable(true, data[4], data[5]) ||
2350             arizona_eq_filter_unstable(true, data[8], data[9]) ||
2351             arizona_eq_filter_unstable(true, data[12], data[13]) ||
2352             arizona_eq_filter_unstable(false, data[16], data[17])) {
2353                 dev_err(arizona->dev, "Rejecting unstable EQ coefficients\n");
2354                 ret = -EINVAL;
2355                 goto out;
2356         }
2357
2358         ret = regmap_read(arizona->regmap, params->base, &val);
2359         if (ret != 0)
2360                 goto out;
2361
2362         val &= ~ARIZONA_EQ1_B1_MODE;
2363         data[0] |= cpu_to_be16(val);
2364
2365         ret = regmap_raw_write(arizona->regmap, params->base, data, len);
2366
2367 out:
2368         kfree(data);
2369         return ret;
2370 }
2371 EXPORT_SYMBOL_GPL(arizona_eq_coeff_put);
2372
2373 int arizona_lhpf_coeff_put(struct snd_kcontrol *kcontrol,
2374                            struct snd_ctl_elem_value *ucontrol)
2375 {
2376         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2377         struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
2378         __be16 *data = (__be16 *)ucontrol->value.bytes.data;
2379         s16 val = be16_to_cpu(*data);
2380
2381         if (abs(val) >= 4096) {
2382                 dev_err(arizona->dev, "Rejecting unstable LHPF coefficients\n");
2383                 return -EINVAL;
2384         }
2385
2386         return snd_soc_bytes_put(kcontrol, ucontrol);
2387 }
2388 EXPORT_SYMBOL_GPL(arizona_lhpf_coeff_put);
2389
2390 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
2391 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2392 MODULE_LICENSE("GPL");