2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk-provider.h>
25 #define BRRx_MASK(x) (0x3FF & x)
27 static struct rsnd_mod_ops adg_ops = {
32 struct clk *clk[CLKMAX];
33 struct clk *clkout[CLKOUTMAX];
34 struct clk_onecell_data onecell;
37 int rbga_rate_for_441khz; /* RBGA */
38 int rbgb_rate_for_48khz; /* RBGB */
41 #define for_each_rsnd_clk(pos, adg, i) \
44 ((pos) = adg->clk[i]); \
46 #define for_each_rsnd_clkout(pos, adg, i) \
49 ((pos) = adg->clkout[i]); \
51 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
53 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
60 for (i = 3; i >= 0; i--) {
62 if (0 == (div % ratio))
63 return (u32)((i << 8) | ((div / ratio) - 1));
69 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
71 struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
72 int id = rsnd_mod_id(mod);
75 if (rsnd_ssi_is_pin_sharing(io)) {
90 return (0x6 + ws) << 8;
93 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
94 struct rsnd_dai_stream *io)
96 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
97 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
98 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
99 int id = rsnd_mod_id(mod);
100 int shift = (id % 2) ? 16 : 0;
103 val = rsnd_adg_ssi_ws_timing_gen2(io);
106 mask = 0xffff << shift;
108 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
113 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod,
114 struct rsnd_dai_stream *io,
117 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
118 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
119 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
120 int is_play = rsnd_io_is_play(io);
121 int id = rsnd_mod_id(src_mod);
122 int shift = (id % 2) ? 16 : 0;
126 rsnd_mod_confirm_src(src_mod);
128 ws = rsnd_adg_ssi_ws_timing_gen2(io);
130 in = (is_play) ? timsel : ws;
131 out = (is_play) ? ws : timsel;
135 mask = 0xffff << shift;
139 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
140 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
143 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
144 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
147 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
148 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
151 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
152 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
155 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
156 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
163 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *src_mod,
164 struct rsnd_dai_stream *io,
165 unsigned int src_rate,
166 unsigned int dst_rate)
168 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
169 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
170 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
171 struct device *dev = rsnd_priv_to_dev(priv);
172 int idx, sel, div, step, ret;
174 unsigned int min, diff;
175 unsigned int sel_rate [] = {
176 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
177 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
178 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
179 adg->rbga_rate_for_441khz, /* 0011: RBGA */
180 adg->rbgb_rate_for_48khz, /* 0100: RBGB */
183 rsnd_mod_confirm_src(src_mod);
188 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
195 for (div = 2; div <= 98304; div += step) {
196 diff = abs(src_rate - sel_rate[sel] / div);
198 val = (sel << 8) | idx;
200 en = 1 << (sel + 1); /* fixme */
204 * step of 0_0000 / 0_0001 / 0_1101
207 if ((idx > 2) && (idx % 2))
218 dev_err(dev, "no Input clock\n");
222 ret = rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
224 dev_err(dev, "timsel error\n");
228 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
230 dev_dbg(dev, "convert rate %d <-> %d\n", src_rate, dst_rate);
235 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *src_mod,
236 struct rsnd_dai_stream *io)
238 u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
240 rsnd_mod_confirm_src(src_mod);
242 return rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
245 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
246 struct rsnd_mod *mod,
247 unsigned int src_rate,
248 unsigned int dst_rate)
250 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
251 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
252 struct device *dev = rsnd_priv_to_dev(priv);
253 int idx, sel, div, shift;
255 int id = rsnd_mod_id(mod);
256 unsigned int sel_rate [] = {
257 clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */
258 clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */
259 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */
260 0, /* 011: MLBCLK (not used) */
261 adg->rbga_rate_for_441khz, /* 100: RBGA */
262 adg->rbgb_rate_for_48khz, /* 101: RBGB */
265 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
266 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
267 for (div = 128, idx = 0;
270 if (src_rate == sel_rate[sel] / div) {
271 val = (idx << 4) | sel;
276 dev_err(dev, "can't find convert src clk\n");
280 shift = (id % 4) * 8;
281 mask = 0xFF << shift;
284 dev_dbg(dev, "adg convert src clk = %02x\n", val);
288 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL3, mask, val);
291 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL4, mask, val);
294 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL5, mask, val);
299 * Gen1 doesn't need dst_rate settings,
300 * since it uses SSI WS pin.
301 * see also rsnd_src_set_route_if_gen1()
307 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
309 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
310 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
311 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
312 int id = rsnd_mod_id(ssi_mod);
313 int shift = (id % 4) * 8;
314 u32 mask = 0xFF << shift;
316 rsnd_mod_confirm_ssi(ssi_mod);
321 * SSI 8 is not connected to ADG.
322 * it works with SSI 7
329 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
332 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
335 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
340 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
343 * "mod" = "ssi" here.
344 * we can get "ssi id" from mod
346 rsnd_adg_set_ssi_clk(mod, 0);
351 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
353 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
354 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
355 struct device *dev = rsnd_priv_to_dev(priv);
366 dev_dbg(dev, "request clock = %d\n", rate);
369 * find suitable clock from
370 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
373 for_each_rsnd_clk(clk, adg, i) {
374 if (rate == clk_get_rate(clk)) {
381 * find divided clock from BRGA/BRGB
383 if (rate == adg->rbga_rate_for_441khz) {
388 if (rate == adg->rbgb_rate_for_48khz) {
398 * This "mod" = "ssi" here.
399 * we can get "ssi id" from mod
401 rsnd_adg_set_ssi_clk(mod, data);
403 dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
404 rsnd_mod_name(mod), rsnd_mod_id(mod),
410 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
411 struct rsnd_adg *adg)
413 struct device *dev = rsnd_priv_to_dev(priv);
415 static const char * const clk_name[] = {
423 for (i = 0; i < CLKMAX; i++) {
424 clk = devm_clk_get(dev, clk_name[i]);
425 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
428 for_each_rsnd_clk(clk, adg, i)
429 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
432 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
433 struct rsnd_adg *adg)
436 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
437 struct device *dev = rsnd_priv_to_dev(priv);
438 struct device_node *np = dev->of_node;
439 u32 ckr, rbgx, rbga, rbgb;
440 u32 rate, req_rate, div;
442 unsigned long req_48kHz_rate, req_441kHz_rate;
444 const char *parent_clk_name = NULL;
445 static const char * const clkout_name[] = {
446 [CLKOUT] = "audio_clkout",
447 [CLKOUT1] = "audio_clkout1",
448 [CLKOUT2] = "audio_clkout2",
449 [CLKOUT3] = "audio_clkout3",
458 of_property_read_u32(np, "#clock-cells", &count);
461 * ADG supports BRRA/BRRB output only
462 * this means all clkout0/1/2/3 will be same rate
464 of_property_read_u32(np, "clock-frequency", &req_rate);
467 if (0 == (req_rate % 44100))
468 req_441kHz_rate = req_rate;
469 if (0 == (req_rate % 48000))
470 req_48kHz_rate = req_rate;
473 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
474 * have 44.1kHz or 48kHz base clocks for now.
476 * SSI itself can divide parent clock by 1/1 - 1/16
478 * rsnd_adg_ssi_clk_try_start()
479 * rsnd_ssi_master_clk_start()
482 rbga = 2; /* default 1/6 */
483 rbgb = 2; /* default 1/6 */
484 adg->rbga_rate_for_441khz = 0;
485 adg->rbgb_rate_for_48khz = 0;
486 for_each_rsnd_clk(clk, adg, i) {
487 rate = clk_get_rate(clk);
489 if (0 == rate) /* not used */
493 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
496 div = rate / req_441kHz_rate;
497 rbgx = rsnd_adg_calculate_rbgx(div);
498 if (BRRx_MASK(rbgx) == rbgx) {
500 adg->rbga_rate_for_441khz = rate / div;
501 ckr |= brg_table[i] << 20;
503 parent_clk_name = __clk_get_name(clk);
508 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
511 div = rate / req_48kHz_rate;
512 rbgx = rsnd_adg_calculate_rbgx(div);
513 if (BRRx_MASK(rbgx) == rbgx) {
515 adg->rbgb_rate_for_48khz = rate / div;
516 ckr |= brg_table[i] << 16;
517 if (req_48kHz_rate) {
518 parent_clk_name = __clk_get_name(clk);
526 * ADG supports BRRA/BRRB output only.
527 * this means all clkout0/1/2/3 will be * same rate
534 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
537 0 : CLK_IS_ROOT, req_rate);
539 adg->clkout[CLKOUT] = clk;
540 of_clk_add_provider(np, of_clk_src_simple_get, clk);
547 for (i = 0; i < CLKOUTMAX; i++) {
548 clk = clk_register_fixed_rate(dev, clkout_name[i],
554 adg->onecell.clks = adg->clkout;
555 adg->onecell.clk_num = CLKOUTMAX;
557 adg->clkout[i] = clk;
559 of_clk_add_provider(np, of_clk_src_onecell_get,
565 rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr);
566 rsnd_mod_write(adg_mod, BRRA, rbga);
567 rsnd_mod_write(adg_mod, BRRB, rbgb);
569 for_each_rsnd_clkout(clk, adg, i)
570 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
571 dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
575 int rsnd_adg_probe(struct platform_device *pdev,
576 const struct rsnd_of_data *of_data,
577 struct rsnd_priv *priv)
579 struct rsnd_adg *adg;
580 struct device *dev = rsnd_priv_to_dev(priv);
582 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
584 dev_err(dev, "ADG allocate failed\n");
589 * ADG is special module.
590 * Use ADG mod without rsnd_mod_init() to make debug easy
591 * for rsnd_write/rsnd_read
593 adg->mod.ops = &adg_ops;
594 adg->mod.priv = priv;
596 rsnd_adg_get_clkin(priv, adg);
597 rsnd_adg_get_clkout(priv, adg);