virt/kvm/arm/vgic.c

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17  */
  18
  19 #include <linux/cpu.h>
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_host.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/uaccess.h>
  28
  29 #include <linux/irqchip/arm-gic.h>
  30
  31 #include <asm/kvm_emulate.h>
  32 #include <asm/kvm_arm.h>
  33 #include <asm/kvm_mmu.h>
  34
  35 /*
  36  * How the whole thing works (courtesy of Christoffer Dall):
  37  *
  38  * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
  39  *   something is pending on the CPU interface.
  40  * - Interrupts that are pending on the distributor are stored on the
  41  *   vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
  42  *   ioctls and guest mmio ops, and other in-kernel peripherals such as the
  43  *   arch. timers).
  44  * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
  45  *   recalculated
  46  * - To calculate the oracle, we need info for each cpu from
  47  *   compute_pending_for_cpu, which considers:
  48  *   - PPI: dist->irq_pending & dist->irq_enable
  49  *   - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
  50  *   - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
  51  *     registers, stored on each vcpu. We only keep one bit of
  52  *     information per interrupt, making sure that only one vcpu can
  53  *     accept the interrupt.
  54  * - If any of the above state changes, we must recalculate the oracle.
  55  * - The same is true when injecting an interrupt, except that we only
  56  *   consider a single interrupt at a time. The irq_spi_cpu array
  57  *   contains the target CPU for each SPI.
  58  *
  59  * The handling of level interrupts adds some extra complexity. We
  60  * need to track when the interrupt has been EOIed, so we can sample
  61  * the 'line' again. This is achieved as such:
  62  *
  63  * - When a level interrupt is moved onto a vcpu, the corresponding
  64  *   bit in irq_queued is set. As long as this bit is set, the line
  65  *   will be ignored for further interrupts. The interrupt is injected
  66  *   into the vcpu with the GICH_LR_EOI bit set (generate a
  67  *   maintenance interrupt on EOI).
  68  * - When the interrupt is EOIed, the maintenance interrupt fires,
  69  *   and clears the corresponding bit in irq_queued. This allows the
  70  *   interrupt line to be sampled again.
  71  * - Note that level-triggered interrupts can also be set to pending from
  72  *   writes to GICD_ISPENDRn and lowering the external input line does not
  73  *   cause the interrupt to become inactive in such a situation.
  74  *   Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
  75  *   inactive as long as the external input line is held high.
  76  */
  77
  78 #define VGIC_ADDR_UNDEF         (-1)
  79 #define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
  80
  81 #define PRODUCT_ID_KVM          0x4b    /* ASCII code K */
  82 #define IMPLEMENTER_ARM         0x43b
  83 #define GICC_ARCH_VERSION_V2    0x2
  84
  85 #define ACCESS_READ_VALUE       (1 << 0)
  86 #define ACCESS_READ_RAZ         (0 << 0)
  87 #define ACCESS_READ_MASK(x)     ((x) & (1 << 0))
  88 #define ACCESS_WRITE_IGNORED    (0 << 1)
  89 #define ACCESS_WRITE_SETBIT     (1 << 1)
  90 #define ACCESS_WRITE_CLEARBIT   (2 << 1)
  91 #define ACCESS_WRITE_VALUE      (3 << 1)
  92 #define ACCESS_WRITE_MASK(x)    ((x) & (3 << 1))
  93
  94 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
  95 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
  96 static void vgic_update_state(struct kvm *kvm);
  97 static void vgic_kick_vcpus(struct kvm *kvm);
  98 static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi);
  99 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
 100 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
 101 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
 102 static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 103 static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 104
 105 static const struct vgic_ops *vgic_ops;
 106 static const struct vgic_params *vgic;
 107
 108 /*
 109  * struct vgic_bitmap contains a bitmap made of unsigned longs, but
 110  * extracts u32s out of them.
 111  *
 112  * This does not work on 64-bit BE systems, because the bitmap access
 113  * will store two consecutive 32-bit words with the higher-addressed
 114  * register's bits at the lower index and the lower-addressed register's
 115  * bits at the higher index.
 116  *
 117  * Therefore, swizzle the register index when accessing the 32-bit word
 118  * registers to access the right register's value.
 119  */
 120 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
 121 #define REG_OFFSET_SWIZZLE      1
 122 #else
 123 #define REG_OFFSET_SWIZZLE      0
 124 #endif
 125
 126 static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs)
 127 {
 128         int nr_longs;
 129
 130         nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS);
 131
 132         b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL);
 133         if (!b->private)
 134                 return -ENOMEM;
 135
 136         b->shared = b->private + nr_cpus;
 137
 138         return 0;
 139 }
 140
 141 static void vgic_free_bitmap(struct vgic_bitmap *b)
 142 {
 143         kfree(b->private);
 144         b->private = NULL;
 145         b->shared = NULL;
 146 }
 147
 148 /*
 149  * Call this function to convert a u64 value to an unsigned long * bitmask
 150  * in a way that works on both 32-bit and 64-bit LE and BE platforms.
 151  *
 152  * Warning: Calling this function may modify *val.
 153  */
 154 static unsigned long *u64_to_bitmask(u64 *val)
 155 {
 156 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
 157         *val = (*val >> 32) | (*val << 32);
 158 #endif
 159         return (unsigned long *)val;
 160 }
 161
 162 static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
 163                                 int cpuid, u32 offset)
 164 {
 165         offset >>= 2;
 166         if (!offset)
 167                 return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE;
 168         else
 169                 return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE);
 170 }
 171
 172 static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
 173                                    int cpuid, int irq)
 174 {
 175         if (irq < VGIC_NR_PRIVATE_IRQS)
 176                 return test_bit(irq, x->private + cpuid);
 177
 178         return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared);
 179 }
 180
 181 static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
 182                                     int irq, int val)
 183 {
 184         unsigned long *reg;
 185
 186         if (irq < VGIC_NR_PRIVATE_IRQS) {
 187                 reg = x->private + cpuid;
 188         } else {
 189                 reg = x->shared;
 190                 irq -= VGIC_NR_PRIVATE_IRQS;
 191         }
 192
 193         if (val)
 194                 set_bit(irq, reg);
 195         else
 196                 clear_bit(irq, reg);
 197 }
 198
 199 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
 200 {
 201         return x->private + cpuid;
 202 }
 203
 204 static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
 205 {
 206         return x->shared;
 207 }
 208
 209 static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs)
 210 {
 211         int size;
 212
 213         size  = nr_cpus * VGIC_NR_PRIVATE_IRQS;
 214         size += nr_irqs - VGIC_NR_PRIVATE_IRQS;
 215
 216         x->private = kzalloc(size, GFP_KERNEL);
 217         if (!x->private)
 218                 return -ENOMEM;
 219
 220         x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32);
 221         return 0;
 222 }
 223
 224 static void vgic_free_bytemap(struct vgic_bytemap *b)
 225 {
 226         kfree(b->private);
 227         b->private = NULL;
 228         b->shared = NULL;
 229 }
 230
 231 static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
 232 {
 233         u32 *reg;
 234
 235         if (offset < VGIC_NR_PRIVATE_IRQS) {
 236                 reg = x->private;
 237                 offset += cpuid * VGIC_NR_PRIVATE_IRQS;
 238         } else {
 239                 reg = x->shared;
 240                 offset -= VGIC_NR_PRIVATE_IRQS;
 241         }
 242
 243         return reg + (offset / sizeof(u32));
 244 }
 245
 246 #define VGIC_CFG_LEVEL  0
 247 #define VGIC_CFG_EDGE   1
 248
 249 static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
 250 {
 251         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 252         int irq_val;
 253
 254         irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
 255         return irq_val == VGIC_CFG_EDGE;
 256 }
 257
 258 static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
 259 {
 260         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 261
 262         return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
 263 }
 264
 265 static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq)
 266 {
 267         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 268
 269         return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq);
 270 }
 271
 272 static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq)
 273 {
 274         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 275
 276         vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1);
 277 }
 278
 279 static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq)
 280 {
 281         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 282
 283         vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0);
 284 }
 285
 286 static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq)
 287 {
 288         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 289
 290         return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq);
 291 }
 292
 293 static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq)
 294 {
 295         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 296
 297         vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1);
 298 }
 299
 300 static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq)
 301 {
 302         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 303
 304         vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0);
 305 }
 306
 307 static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq)
 308 {
 309         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 310
 311         return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq);
 312 }
 313
 314 static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq)
 315 {
 316         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 317
 318         vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0);
 319 }
 320
 321 static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
 322 {
 323         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 324
 325         return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq);
 326 }
 327
 328 static void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq)
 329 {
 330         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 331
 332         vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1);
 333 }
 334
 335 static void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq)
 336 {
 337         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 338
 339         vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0);
 340 }
 341
 342 static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
 343 {
 344         if (irq < VGIC_NR_PRIVATE_IRQS)
 345                 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
 346         else
 347                 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
 348                         vcpu->arch.vgic_cpu.pending_shared);
 349 }
 350
 351 static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
 352 {
 353         if (irq < VGIC_NR_PRIVATE_IRQS)
 354                 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
 355         else
 356                 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
 357                           vcpu->arch.vgic_cpu.pending_shared);
 358 }
 359
 360 static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq)
 361 {
 362         return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq);
 363 }
 364
 365 static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
 366 {
 367         return le32_to_cpu(*((u32 *)mmio->data)) & mask;
 368 }
 369
 370 static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
 371 {
 372         *((u32 *)mmio->data) = cpu_to_le32(value) & mask;
 373 }
 374
 375 /**
 376  * vgic_reg_access - access vgic register
 377  * @mmio:   pointer to the data describing the mmio access
 378  * @reg:    pointer to the virtual backing of vgic distributor data
 379  * @offset: least significant 2 bits used for word offset
 380  * @mode:   ACCESS_ mode (see defines above)
 381  *
 382  * Helper to make vgic register access easier using one of the access
 383  * modes defined for vgic register access
 384  * (read,raz,write-ignored,setbit,clearbit,write)
 385  */
 386 static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
 387                             phys_addr_t offset, int mode)
 388 {
 389         int word_offset = (offset & 3) * 8;
 390         u32 mask = (1UL << (mmio->len * 8)) - 1;
 391         u32 regval;
 392
 393         /*
 394          * Any alignment fault should have been delivered to the guest
 395          * directly (ARM ARM B3.12.7 "Prioritization of aborts").
 396          */
 397
 398         if (reg) {
 399                 regval = *reg;
 400         } else {
 401                 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
 402                 regval = 0;
 403         }
 404
 405         if (mmio->is_write) {
 406                 u32 data = mmio_data_read(mmio, mask) << word_offset;
 407                 switch (ACCESS_WRITE_MASK(mode)) {
 408                 case ACCESS_WRITE_IGNORED:
 409                         return;
 410
 411                 case ACCESS_WRITE_SETBIT:
 412                         regval |= data;
 413                         break;
 414
 415                 case ACCESS_WRITE_CLEARBIT:
 416                         regval &= ~data;
 417                         break;
 418
 419                 case ACCESS_WRITE_VALUE:
 420                         regval = (regval & ~(mask << word_offset)) | data;
 421                         break;
 422                 }
 423                 *reg = regval;
 424         } else {
 425                 switch (ACCESS_READ_MASK(mode)) {
 426                 case ACCESS_READ_RAZ:
 427                         regval = 0;
 428                         /* fall through */
 429
 430                 case ACCESS_READ_VALUE:
 431                         mmio_data_write(mmio, mask, regval >> word_offset);
 432                 }
 433         }
 434 }
 435
 436 static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
 437                              struct kvm_exit_mmio *mmio, phys_addr_t offset)
 438 {
 439         u32 reg;
 440         u32 word_offset = offset & 3;
 441
 442         switch (offset & ~3) {
 443         case 0:                 /* GICD_CTLR */
 444                 reg = vcpu->kvm->arch.vgic.enabled;
 445                 vgic_reg_access(mmio, &reg, word_offset,
 446                                 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
 447                 if (mmio->is_write) {
 448                         vcpu->kvm->arch.vgic.enabled = reg & 1;
 449                         vgic_update_state(vcpu->kvm);
 450                         return true;
 451                 }
 452                 break;
 453
 454         case 4:                 /* GICD_TYPER */
 455                 reg  = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
 456                 reg |= (vcpu->kvm->arch.vgic.nr_irqs >> 5) - 1;
 457                 vgic_reg_access(mmio, &reg, word_offset,
 458                                 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
 459                 break;
 460
 461         case 8:                 /* GICD_IIDR */
 462                 reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 463                 vgic_reg_access(mmio, &reg, word_offset,
 464                                 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
 465                 break;
 466         }
 467
 468         return false;
 469 }
 470
 471 static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
 472                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
 473 {
 474         vgic_reg_access(mmio, NULL, offset,
 475                         ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
 476         return false;
 477 }
 478
 479 static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
 480                                        struct kvm_exit_mmio *mmio,
 481                                        phys_addr_t offset)
 482 {
 483         u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
 484                                        vcpu->vcpu_id, offset);
 485         vgic_reg_access(mmio, reg, offset,
 486                         ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
 487         if (mmio->is_write) {
 488                 vgic_update_state(vcpu->kvm);
 489                 return true;
 490         }
 491
 492         return false;
 493 }
 494
 495 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
 496                                          struct kvm_exit_mmio *mmio,
 497                                          phys_addr_t offset)
 498 {
 499         u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
 500                                        vcpu->vcpu_id, offset);
 501         vgic_reg_access(mmio, reg, offset,
 502                         ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
 503         if (mmio->is_write) {
 504                 if (offset < 4) /* Force SGI enabled */
 505                         *reg |= 0xffff;
 506                 vgic_retire_disabled_irqs(vcpu);
 507                 vgic_update_state(vcpu->kvm);
 508                 return true;
 509         }
 510
 511         return false;
 512 }
 513
 514 static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
 515                                         struct kvm_exit_mmio *mmio,
 516                                         phys_addr_t offset)
 517 {
 518         u32 *reg, orig;
 519         u32 level_mask;
 520         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 521
 522         reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu->vcpu_id, offset);
 523         level_mask = (~(*reg));
 524
 525         /* Mark both level and edge triggered irqs as pending */
 526         reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset);
 527         orig = *reg;
 528         vgic_reg_access(mmio, reg, offset,
 529                         ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
 530
 531         if (mmio->is_write) {
 532                 /* Set the soft-pending flag only for level-triggered irqs */
 533                 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
 534                                           vcpu->vcpu_id, offset);
 535                 vgic_reg_access(mmio, reg, offset,
 536                                 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
 537                 *reg &= level_mask;
 538
 539                 /* Ignore writes to SGIs */
 540                 if (offset < 2) {
 541                         *reg &= ~0xffff;
 542                         *reg |= orig & 0xffff;
 543                 }
 544
 545                 vgic_update_state(vcpu->kvm);
 546                 return true;
 547         }
 548
 549         return false;
 550 }
 551
 552 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
 553                                           struct kvm_exit_mmio *mmio,
 554                                           phys_addr_t offset)
 555 {
 556         u32 *level_active;
 557         u32 *reg, orig;
 558         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 559
 560         reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset);
 561         orig = *reg;
 562         vgic_reg_access(mmio, reg, offset,
 563                         ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
 564         if (mmio->is_write) {
 565                 /* Re-set level triggered level-active interrupts */
 566                 level_active = vgic_bitmap_get_reg(&dist->irq_level,
 567                                           vcpu->vcpu_id, offset);
 568                 reg = vgic_bitmap_get_reg(&dist->irq_pending,
 569                                           vcpu->vcpu_id, offset);
 570                 *reg |= *level_active;
 571
 572                 /* Ignore writes to SGIs */
 573                 if (offset < 2) {
 574                         *reg &= ~0xffff;
 575                         *reg |= orig & 0xffff;
 576                 }
 577
 578                 /* Clear soft-pending flags */
 579                 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
 580                                           vcpu->vcpu_id, offset);
 581                 vgic_reg_access(mmio, reg, offset,
 582                                 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
 583
 584                 vgic_update_state(vcpu->kvm);
 585                 return true;
 586         }
 587
 588         return false;
 589 }
 590
 591 static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
 592                                      struct kvm_exit_mmio *mmio,
 593                                      phys_addr_t offset)
 594 {
 595         u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
 596                                         vcpu->vcpu_id, offset);
 597         vgic_reg_access(mmio, reg, offset,
 598                         ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
 599         return false;
 600 }
 601
 602 #define GICD_ITARGETSR_SIZE     32
 603 #define GICD_CPUTARGETS_BITS    8
 604 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
 605 static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
 606 {
 607         struct vgic_dist *dist = &kvm->arch.vgic;
 608         int i;
 609         u32 val = 0;
 610
 611         irq -= VGIC_NR_PRIVATE_IRQS;
 612
 613         for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
 614                 val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8);
 615
 616         return val;
 617 }
 618
 619 static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
 620 {
 621         struct vgic_dist *dist = &kvm->arch.vgic;
 622         struct kvm_vcpu *vcpu;
 623         int i, c;
 624         unsigned long *bmap;
 625         u32 target;
 626
 627         irq -= VGIC_NR_PRIVATE_IRQS;
 628
 629         /*
 630          * Pick the LSB in each byte. This ensures we target exactly
 631          * one vcpu per IRQ. If the byte is null, assume we target
 632          * CPU0.
 633          */
 634         for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
 635                 int shift = i * GICD_CPUTARGETS_BITS;
 636                 target = ffs((val >> shift) & 0xffU);
 637                 target = target ? (target - 1) : 0;
 638                 dist->irq_spi_cpu[irq + i] = target;
 639                 kvm_for_each_vcpu(c, vcpu, kvm) {
 640                         bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
 641                         if (c == target)
 642                                 set_bit(irq + i, bmap);
 643                         else
 644                                 clear_bit(irq + i, bmap);
 645                 }
 646         }
 647 }
 648
 649 static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
 650                                    struct kvm_exit_mmio *mmio,
 651                                    phys_addr_t offset)
 652 {
 653         u32 reg;
 654
 655         /* We treat the banked interrupts targets as read-only */
 656         if (offset < 32) {
 657                 u32 roreg = 1 << vcpu->vcpu_id;
 658                 roreg |= roreg << 8;
 659                 roreg |= roreg << 16;
 660
 661                 vgic_reg_access(mmio, &roreg, offset,
 662                                 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
 663                 return false;
 664         }
 665
 666         reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
 667         vgic_reg_access(mmio, &reg, offset,
 668                         ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
 669         if (mmio->is_write) {
 670                 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
 671                 vgic_update_state(vcpu->kvm);
 672                 return true;
 673         }
 674
 675         return false;
 676 }
 677
 678 static u32 vgic_cfg_expand(u16 val)
 679 {
 680         u32 res = 0;
 681         int i;
 682
 683         /*
 684          * Turn a 16bit value like abcd...mnop into a 32bit word
 685          * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
 686          */
 687         for (i = 0; i < 16; i++)
 688                 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
 689
 690         return res;
 691 }
 692
 693 static u16 vgic_cfg_compress(u32 val)
 694 {
 695         u16 res = 0;
 696         int i;
 697
 698         /*
 699          * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
 700          * abcd...mnop which is what we really care about.
 701          */
 702         for (i = 0; i < 16; i++)
 703                 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
 704
 705         return res;
 706 }
 707
 708 /*
 709  * The distributor uses 2 bits per IRQ for the CFG register, but the
 710  * LSB is always 0. As such, we only keep the upper bit, and use the
 711  * two above functions to compress/expand the bits
 712  */
 713 static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
 714                                 struct kvm_exit_mmio *mmio, phys_addr_t offset)
 715 {
 716         u32 val;
 717         u32 *reg;
 718
 719         reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
 720                                   vcpu->vcpu_id, offset >> 1);
 721
 722         if (offset & 4)
 723                 val = *reg >> 16;
 724         else
 725                 val = *reg & 0xffff;
 726
 727         val = vgic_cfg_expand(val);
 728         vgic_reg_access(mmio, &val, offset,
 729                         ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
 730         if (mmio->is_write) {
 731                 if (offset < 8) {
 732                         *reg = ~0U; /* Force PPIs/SGIs to 1 */
 733                         return false;
 734                 }
 735
 736                 val = vgic_cfg_compress(val);
 737                 if (offset & 4) {
 738                         *reg &= 0xffff;
 739                         *reg |= val << 16;
 740                 } else {
 741                         *reg &= 0xffff << 16;
 742                         *reg |= val;
 743                 }
 744         }
 745
 746         return false;
 747 }
 748
 749 static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
 750                                 struct kvm_exit_mmio *mmio, phys_addr_t offset)
 751 {
 752         u32 reg;
 753         vgic_reg_access(mmio, &reg, offset,
 754                         ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
 755         if (mmio->is_write) {
 756                 vgic_dispatch_sgi(vcpu, reg);
 757                 vgic_update_state(vcpu->kvm);
 758                 return true;
 759         }
 760
 761         return false;
 762 }
 763
 764 /**
 765  * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
 766  * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
 767  *
 768  * Move any pending IRQs that have already been assigned to LRs back to the
 769  * emulated distributor state so that the complete emulated state can be read
 770  * from the main emulation structures without investigating the LRs.
 771  *
 772  * Note that IRQs in the active state in the LRs get their pending state moved
 773  * to the distributor but the active state stays in the LRs, because we don't
 774  * track the active state on the distributor side.
 775  */
 776 static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
 777 {
 778         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 779         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 780         int vcpu_id = vcpu->vcpu_id;
 781         int i;
 782
 783         for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
 784                 struct vgic_lr lr = vgic_get_lr(vcpu, i);
 785
 786                 /*
 787                  * There are three options for the state bits:
 788                  *
 789                  * 01: pending
 790                  * 10: active
 791                  * 11: pending and active
 792                  *
 793                  * If the LR holds only an active interrupt (not pending) then
 794                  * just leave it alone.
 795                  */
 796                 if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE)
 797                         continue;
 798
 799                 /*
 800                  * Reestablish the pending state on the distributor and the
 801                  * CPU interface.  It may have already been pending, but that
 802                  * is fine, then we are only setting a few bits that were
 803                  * already set.
 804                  */
 805                 vgic_dist_irq_set_pending(vcpu, lr.irq);
 806                 if (lr.irq < VGIC_NR_SGIS)
 807                         *vgic_get_sgi_sources(dist, vcpu_id, lr.irq) |= 1 << lr.source;
 808                 lr.state &= ~LR_STATE_PENDING;
 809                 vgic_set_lr(vcpu, i, lr);
 810
 811                 /*
 812                  * If there's no state left on the LR (it could still be
 813                  * active), then the LR does not hold any useful info and can
 814                  * be marked as free for other use.
 815                  */
 816                 if (!(lr.state & LR_STATE_MASK)) {
 817                         vgic_retire_lr(i, lr.irq, vcpu);
 818                         vgic_irq_clear_queued(vcpu, lr.irq);
 819                 }
 820
 821                 /* Finally update the VGIC state. */
 822                 vgic_update_state(vcpu->kvm);
 823         }
 824 }
 825
 826 /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
 827 static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
 828                                         struct kvm_exit_mmio *mmio,
 829                                         phys_addr_t offset)
 830 {
 831         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 832         int sgi;
 833         int min_sgi = (offset & ~0x3);
 834         int max_sgi = min_sgi + 3;
 835         int vcpu_id = vcpu->vcpu_id;
 836         u32 reg = 0;
 837
 838         /* Copy source SGIs from distributor side */
 839         for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
 840                 int shift = 8 * (sgi - min_sgi);
 841                 reg |= ((u32)*vgic_get_sgi_sources(dist, vcpu_id, sgi)) << shift;
 842         }
 843
 844         mmio_data_write(mmio, ~0, reg);
 845         return false;
 846 }
 847
 848 static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
 849                                          struct kvm_exit_mmio *mmio,
 850                                          phys_addr_t offset, bool set)
 851 {
 852         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 853         int sgi;
 854         int min_sgi = (offset & ~0x3);
 855         int max_sgi = min_sgi + 3;
 856         int vcpu_id = vcpu->vcpu_id;
 857         u32 reg;
 858         bool updated = false;
 859
 860         reg = mmio_data_read(mmio, ~0);
 861
 862         /* Clear pending SGIs on the distributor */
 863         for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
 864                 u8 mask = reg >> (8 * (sgi - min_sgi));
 865                 u8 *src = vgic_get_sgi_sources(dist, vcpu_id, sgi);
 866                 if (set) {
 867                         if ((*src & mask) != mask)
 868                                 updated = true;
 869                         *src |= mask;
 870                 } else {
 871                         if (*src & mask)
 872                                 updated = true;
 873                         *src &= ~mask;
 874                 }
 875         }
 876
 877         if (updated)
 878                 vgic_update_state(vcpu->kvm);
 879
 880         return updated;
 881 }
 882
 883 static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
 884                                 struct kvm_exit_mmio *mmio,
 885                                 phys_addr_t offset)
 886 {
 887         if (!mmio->is_write)
 888                 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
 889         else
 890                 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true);
 891 }
 892
 893 static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
 894                                   struct kvm_exit_mmio *mmio,
 895                                   phys_addr_t offset)
 896 {
 897         if (!mmio->is_write)
 898                 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
 899         else
 900                 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false);
 901 }
 902
 903 /*
 904  * I would have liked to use the kvm_bus_io_*() API instead, but it
 905  * cannot cope with banked registers (only the VM pointer is passed
 906  * around, and we need the vcpu). One of these days, someone please
 907  * fix it!
 908  */
 909 struct mmio_range {
 910         phys_addr_t base;
 911         unsigned long len;
 912         int bits_per_irq;
 913         bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
 914                             phys_addr_t offset);
 915 };
 916
 917 static const struct mmio_range vgic_dist_ranges[] = {
 918         {
 919                 .base           = GIC_DIST_CTRL,
 920                 .len            = 12,
 921                 .bits_per_irq   = 0,
 922                 .handle_mmio    = handle_mmio_misc,
 923         },
 924         {
 925                 .base           = GIC_DIST_IGROUP,
 926                 .len            = VGIC_MAX_IRQS / 8,
 927                 .bits_per_irq   = 1,
 928                 .handle_mmio    = handle_mmio_raz_wi,
 929         },
 930         {
 931                 .base           = GIC_DIST_ENABLE_SET,
 932                 .len            = VGIC_MAX_IRQS / 8,
 933                 .bits_per_irq   = 1,
 934                 .handle_mmio    = handle_mmio_set_enable_reg,
 935         },
 936         {
 937                 .base           = GIC_DIST_ENABLE_CLEAR,
 938                 .len            = VGIC_MAX_IRQS / 8,
 939                 .bits_per_irq   = 1,
 940                 .handle_mmio    = handle_mmio_clear_enable_reg,
 941         },
 942         {
 943                 .base           = GIC_DIST_PENDING_SET,
 944                 .len            = VGIC_MAX_IRQS / 8,
 945                 .bits_per_irq   = 1,
 946                 .handle_mmio    = handle_mmio_set_pending_reg,
 947         },
 948         {
 949                 .base           = GIC_DIST_PENDING_CLEAR,
 950                 .len            = VGIC_MAX_IRQS / 8,
 951                 .bits_per_irq   = 1,
 952                 .handle_mmio    = handle_mmio_clear_pending_reg,
 953         },
 954         {
 955                 .base           = GIC_DIST_ACTIVE_SET,
 956                 .len            = VGIC_MAX_IRQS / 8,
 957                 .bits_per_irq   = 1,
 958                 .handle_mmio    = handle_mmio_raz_wi,
 959         },
 960         {
 961                 .base           = GIC_DIST_ACTIVE_CLEAR,
 962                 .len            = VGIC_MAX_IRQS / 8,
 963                 .bits_per_irq   = 1,
 964                 .handle_mmio    = handle_mmio_raz_wi,
 965         },
 966         {
 967                 .base           = GIC_DIST_PRI,
 968                 .len            = VGIC_MAX_IRQS,
 969                 .bits_per_irq   = 8,
 970                 .handle_mmio    = handle_mmio_priority_reg,
 971         },
 972         {
 973                 .base           = GIC_DIST_TARGET,
 974                 .len            = VGIC_MAX_IRQS,
 975                 .bits_per_irq   = 8,
 976                 .handle_mmio    = handle_mmio_target_reg,
 977         },
 978         {
 979                 .base           = GIC_DIST_CONFIG,
 980                 .len            = VGIC_MAX_IRQS / 4,
 981                 .bits_per_irq   = 2,
 982                 .handle_mmio    = handle_mmio_cfg_reg,
 983         },
 984         {
 985                 .base           = GIC_DIST_SOFTINT,
 986                 .len            = 4,
 987                 .handle_mmio    = handle_mmio_sgi_reg,
 988         },
 989         {
 990                 .base           = GIC_DIST_SGI_PENDING_CLEAR,
 991                 .len            = VGIC_NR_SGIS,
 992                 .handle_mmio    = handle_mmio_sgi_clear,
 993         },
 994         {
 995                 .base           = GIC_DIST_SGI_PENDING_SET,
 996                 .len            = VGIC_NR_SGIS,
 997                 .handle_mmio    = handle_mmio_sgi_set,
 998         },
 999         {}
1000 };
1001
1002 static const
1003 struct mmio_range *find_matching_range(const struct mmio_range *ranges,
1004                                        struct kvm_exit_mmio *mmio,
1005                                        phys_addr_t offset)
1006 {
1007         const struct mmio_range *r = ranges;
1008
1009         while (r->len) {
1010                 if (offset >= r->base &&
1011                     (offset + mmio->len) <= (r->base + r->len))
1012                         return r;
1013                 r++;
1014         }
1015
1016         return NULL;
1017 }
1018
1019 static bool vgic_validate_access(const struct vgic_dist *dist,
1020                                  const struct mmio_range *range,
1021                                  unsigned long offset)
1022 {
1023         int irq;
1024
1025         if (!range->bits_per_irq)
1026                 return true;    /* Not an irq-based access */
1027
1028         irq = offset * 8 / range->bits_per_irq;
1029         if (irq >= dist->nr_irqs)
1030                 return false;
1031
1032         return true;
1033 }
1034
1035 /**
1036  * vgic_handle_mmio - handle an in-kernel MMIO access
1037  * @vcpu:       pointer to the vcpu performing the access
1038  * @run:        pointer to the kvm_run structure
1039  * @mmio:       pointer to the data describing the access
1040  *
1041  * returns true if the MMIO access has been performed in kernel space,
1042  * and false if it needs to be emulated in user space.
1043  */
1044 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
1045                       struct kvm_exit_mmio *mmio)
1046 {
1047         const struct mmio_range *range;
1048         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1049         unsigned long base = dist->vgic_dist_base;
1050         bool updated_state;
1051         unsigned long offset;
1052
1053         if (!irqchip_in_kernel(vcpu->kvm) ||
1054             mmio->phys_addr < base ||
1055             (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
1056                 return false;
1057
1058         /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
1059         if (mmio->len > 4) {
1060                 kvm_inject_dabt(vcpu, mmio->phys_addr);
1061                 return true;
1062         }
1063
1064         offset = mmio->phys_addr - base;
1065         range = find_matching_range(vgic_dist_ranges, mmio, offset);
1066         if (unlikely(!range || !range->handle_mmio)) {
1067                 pr_warn("Unhandled access %d %08llx %d\n",
1068                         mmio->is_write, mmio->phys_addr, mmio->len);
1069                 return false;
1070         }
1071
1072         spin_lock(&vcpu->kvm->arch.vgic.lock);
1073         offset = mmio->phys_addr - range->base - base;
1074         if (vgic_validate_access(dist, range, offset)) {
1075                 updated_state = range->handle_mmio(vcpu, mmio, offset);
1076         } else {
1077                 vgic_reg_access(mmio, NULL, offset,
1078                                 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
1079                 updated_state = false;
1080         }
1081         spin_unlock(&vcpu->kvm->arch.vgic.lock);
1082         kvm_prepare_mmio(run, mmio);
1083         kvm_handle_mmio_return(vcpu, run);
1084
1085         if (updated_state)
1086                 vgic_kick_vcpus(vcpu->kvm);
1087
1088         return true;
1089 }
1090
1091 static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi)
1092 {
1093         return dist->irq_sgi_sources + vcpu_id * VGIC_NR_SGIS + sgi;
1094 }
1095
1096 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
1097 {
1098         struct kvm *kvm = vcpu->kvm;
1099         struct vgic_dist *dist = &kvm->arch.vgic;
1100         int nrcpus = atomic_read(&kvm->online_vcpus);
1101         u8 target_cpus;
1102         int sgi, mode, c, vcpu_id;
1103
1104         vcpu_id = vcpu->vcpu_id;
1105
1106         sgi = reg & 0xf;
1107         target_cpus = (reg >> 16) & 0xff;
1108         mode = (reg >> 24) & 3;
1109
1110         switch (mode) {
1111         case 0:
1112                 if (!target_cpus)
1113                         return;
1114                 break;
1115
1116         case 1:
1117                 target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
1118                 break;
1119
1120         case 2:
1121                 target_cpus = 1 << vcpu_id;
1122                 break;
1123         }
1124
1125         kvm_for_each_vcpu(c, vcpu, kvm) {
1126                 if (target_cpus & 1) {
1127                         /* Flag the SGI as pending */
1128                         vgic_dist_irq_set_pending(vcpu, sgi);
1129                         *vgic_get_sgi_sources(dist, c, sgi) |= 1 << vcpu_id;
1130                         kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
1131                 }
1132
1133                 target_cpus >>= 1;
1134         }
1135 }
1136
1137 static int vgic_nr_shared_irqs(struct vgic_dist *dist)
1138 {
1139         return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS;
1140 }
1141
1142 static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
1143 {
1144         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1145         unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
1146         unsigned long pending_private, pending_shared;
1147         int nr_shared = vgic_nr_shared_irqs(dist);
1148         int vcpu_id;
1149
1150         vcpu_id = vcpu->vcpu_id;
1151         pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
1152         pend_shared = vcpu->arch.vgic_cpu.pending_shared;
1153
1154         pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id);
1155         enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
1156         bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
1157
1158         pending = vgic_bitmap_get_shared_map(&dist->irq_pending);
1159         enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
1160         bitmap_and(pend_shared, pending, enabled, nr_shared);
1161         bitmap_and(pend_shared, pend_shared,
1162                    vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
1163                    nr_shared);
1164
1165         pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
1166         pending_shared = find_first_bit(pend_shared, nr_shared);
1167         return (pending_private < VGIC_NR_PRIVATE_IRQS ||
1168                 pending_shared < vgic_nr_shared_irqs(dist));
1169 }
1170
1171 /*
1172  * Update the interrupt state and determine which CPUs have pending
1173  * interrupts. Must be called with distributor lock held.
1174  */
1175 static void vgic_update_state(struct kvm *kvm)
1176 {
1177         struct vgic_dist *dist = &kvm->arch.vgic;
1178         struct kvm_vcpu *vcpu;
1179         int c;
1180
1181         if (!dist->enabled) {
1182                 set_bit(0, dist->irq_pending_on_cpu);
1183                 return;
1184         }
1185
1186         kvm_for_each_vcpu(c, vcpu, kvm) {
1187                 if (compute_pending_for_cpu(vcpu)) {
1188                         pr_debug("CPU%d has pending interrupts\n", c);
1189                         set_bit(c, dist->irq_pending_on_cpu);
1190                 }
1191         }
1192 }
1193
1194 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr)
1195 {
1196         return vgic_ops->get_lr(vcpu, lr);
1197 }
1198
1199 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr,
1200                                struct vgic_lr vlr)
1201 {
1202         vgic_ops->set_lr(vcpu, lr, vlr);
1203 }
1204
1205 static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1206                                struct vgic_lr vlr)
1207 {
1208         vgic_ops->sync_lr_elrsr(vcpu, lr, vlr);
1209 }
1210
1211 static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu)
1212 {
1213         return vgic_ops->get_elrsr(vcpu);
1214 }
1215
1216 static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu)
1217 {
1218         return vgic_ops->get_eisr(vcpu);
1219 }
1220
1221 static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu)
1222 {
1223         return vgic_ops->get_interrupt_status(vcpu);
1224 }
1225
1226 static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu)
1227 {
1228         vgic_ops->enable_underflow(vcpu);
1229 }
1230
1231 static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu)
1232 {
1233         vgic_ops->disable_underflow(vcpu);
1234 }
1235
1236 static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1237 {
1238         vgic_ops->get_vmcr(vcpu, vmcr);
1239 }
1240
1241 static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1242 {
1243         vgic_ops->set_vmcr(vcpu, vmcr);
1244 }
1245
1246 static inline void vgic_enable(struct kvm_vcpu *vcpu)
1247 {
1248         vgic_ops->enable(vcpu);
1249 }
1250
1251 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu)
1252 {
1253         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1254         struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr);
1255
1256         vlr.state = 0;
1257         vgic_set_lr(vcpu, lr_nr, vlr);
1258         clear_bit(lr_nr, vgic_cpu->lr_used);
1259         vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1260 }
1261
1262 /*
1263  * An interrupt may have been disabled after being made pending on the
1264  * CPU interface (the classic case is a timer running while we're
1265  * rebooting the guest - the interrupt would kick as soon as the CPU
1266  * interface gets enabled, with deadly consequences).
1267  *
1268  * The solution is to examine already active LRs, and check the
1269  * interrupt is still enabled. If not, just retire it.
1270  */
1271 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1272 {
1273         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1274         int lr;
1275
1276         for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) {
1277                 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1278
1279                 if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
1280                         vgic_retire_lr(lr, vlr.irq, vcpu);
1281                         if (vgic_irq_is_queued(vcpu, vlr.irq))
1282                                 vgic_irq_clear_queued(vcpu, vlr.irq);
1283                 }
1284         }
1285 }
1286
1287 /*
1288  * Queue an interrupt to a CPU virtual interface. Return true on success,
1289  * or false if it wasn't possible to queue it.
1290  */
1291 static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1292 {
1293         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1294         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1295         struct vgic_lr vlr;
1296         int lr;
1297
1298         /* Sanitize the input... */
1299         BUG_ON(sgi_source_id & ~7);
1300         BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1301         BUG_ON(irq >= dist->nr_irqs);
1302
1303         kvm_debug("Queue IRQ%d\n", irq);
1304
1305         lr = vgic_cpu->vgic_irq_lr_map[irq];
1306
1307         /* Do we have an active interrupt for the same CPUID? */
1308         if (lr != LR_EMPTY) {
1309                 vlr = vgic_get_lr(vcpu, lr);
1310                 if (vlr.source == sgi_source_id) {
1311                         kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq);
1312                         BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1313                         vlr.state |= LR_STATE_PENDING;
1314                         vgic_set_lr(vcpu, lr, vlr);
1315                         return true;
1316                 }
1317         }
1318
1319         /* Try to use another LR for this interrupt */
1320         lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
1321                                vgic->nr_lr);
1322         if (lr >= vgic->nr_lr)
1323                 return false;
1324
1325         kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
1326         vgic_cpu->vgic_irq_lr_map[irq] = lr;
1327         set_bit(lr, vgic_cpu->lr_used);
1328
1329         vlr.irq = irq;
1330         vlr.source = sgi_source_id;
1331         vlr.state = LR_STATE_PENDING;
1332         if (!vgic_irq_is_edge(vcpu, irq))
1333                 vlr.state |= LR_EOI_INT;
1334
1335         vgic_set_lr(vcpu, lr, vlr);
1336
1337         return true;
1338 }
1339
1340 static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
1341 {
1342         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1343         unsigned long sources;
1344         int vcpu_id = vcpu->vcpu_id;
1345         int c;
1346
1347         sources = *vgic_get_sgi_sources(dist, vcpu_id, irq);
1348
1349         for_each_set_bit(c, &sources, dist->nr_cpus) {
1350                 if (vgic_queue_irq(vcpu, c, irq))
1351                         clear_bit(c, &sources);
1352         }
1353
1354         *vgic_get_sgi_sources(dist, vcpu_id, irq) = sources;
1355
1356         /*
1357          * If the sources bitmap has been cleared it means that we
1358          * could queue all the SGIs onto link registers (see the
1359          * clear_bit above), and therefore we are done with them in
1360          * our emulated gic and can get rid of them.
1361          */
1362         if (!sources) {
1363                 vgic_dist_irq_clear_pending(vcpu, irq);
1364                 vgic_cpu_irq_clear(vcpu, irq);
1365                 return true;
1366         }
1367
1368         return false;
1369 }
1370
1371 static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1372 {
1373         if (!vgic_can_sample_irq(vcpu, irq))
1374                 return true; /* level interrupt, already queued */
1375
1376         if (vgic_queue_irq(vcpu, 0, irq)) {
1377                 if (vgic_irq_is_edge(vcpu, irq)) {
1378                         vgic_dist_irq_clear_pending(vcpu, irq);
1379                         vgic_cpu_irq_clear(vcpu, irq);
1380                 } else {
1381                         vgic_irq_set_queued(vcpu, irq);
1382                 }
1383
1384                 return true;
1385         }
1386
1387         return false;
1388 }
1389
1390 /*
1391  * Fill the list registers with pending interrupts before running the
1392  * guest.
1393  */
1394 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1395 {
1396         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1397         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1398         int i, vcpu_id;
1399         int overflow = 0;
1400
1401         vcpu_id = vcpu->vcpu_id;
1402
1403         /*
1404          * We may not have any pending interrupt, or the interrupts
1405          * may have been serviced from another vcpu. In all cases,
1406          * move along.
1407          */
1408         if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
1409                 pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
1410                 goto epilog;
1411         }
1412
1413         /* SGIs */
1414         for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
1415                 if (!vgic_queue_sgi(vcpu, i))
1416                         overflow = 1;
1417         }
1418
1419         /* PPIs */
1420         for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
1421                 if (!vgic_queue_hwirq(vcpu, i))
1422                         overflow = 1;
1423         }
1424
1425         /* SPIs */
1426         for_each_set_bit(i, vgic_cpu->pending_shared, vgic_nr_shared_irqs(dist)) {
1427                 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1428                         overflow = 1;
1429         }
1430
1431 epilog:
1432         if (overflow) {
1433                 vgic_enable_underflow(vcpu);
1434         } else {
1435                 vgic_disable_underflow(vcpu);
1436                 /*
1437                  * We're about to run this VCPU, and we've consumed
1438                  * everything the distributor had in store for
1439                  * us. Claim we don't have anything pending. We'll
1440                  * adjust that if needed while exiting.
1441                  */
1442                 clear_bit(vcpu_id, dist->irq_pending_on_cpu);
1443         }
1444 }
1445
1446 static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1447 {
1448         u32 status = vgic_get_interrupt_status(vcpu);
1449         bool level_pending = false;
1450
1451         kvm_debug("STATUS = %08x\n", status);
1452
1453         if (status & INT_STATUS_EOI) {
1454                 /*
1455                  * Some level interrupts have been EOIed. Clear their
1456                  * active bit.
1457                  */
1458                 u64 eisr = vgic_get_eisr(vcpu);
1459                 unsigned long *eisr_ptr = u64_to_bitmask(&eisr);
1460                 int lr;
1461
1462                 for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) {
1463                         struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1464                         WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq));
1465
1466                         vgic_irq_clear_queued(vcpu, vlr.irq);
1467                         WARN_ON(vlr.state & LR_STATE_MASK);
1468                         vlr.state = 0;
1469                         vgic_set_lr(vcpu, lr, vlr);
1470
1471                         /*
1472                          * If the IRQ was EOIed it was also ACKed and we we
1473                          * therefore assume we can clear the soft pending
1474                          * state (should it had been set) for this interrupt.
1475                          *
1476                          * Note: if the IRQ soft pending state was set after
1477                          * the IRQ was acked, it actually shouldn't be
1478                          * cleared, but we have no way of knowing that unless
1479                          * we start trapping ACKs when the soft-pending state
1480                          * is set.
1481                          */
1482                         vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq);
1483
1484                         /* Any additional pending interrupt? */
1485                         if (vgic_dist_irq_get_level(vcpu, vlr.irq)) {
1486                                 vgic_cpu_irq_set(vcpu, vlr.irq);
1487                                 level_pending = true;
1488                         } else {
1489                                 vgic_dist_irq_clear_pending(vcpu, vlr.irq);
1490                                 vgic_cpu_irq_clear(vcpu, vlr.irq);
1491                         }
1492
1493                         /*
1494                          * Despite being EOIed, the LR may not have
1495                          * been marked as empty.
1496                          */
1497                         vgic_sync_lr_elrsr(vcpu, lr, vlr);
1498                 }
1499         }
1500
1501         if (status & INT_STATUS_UNDERFLOW)
1502                 vgic_disable_underflow(vcpu);
1503
1504         return level_pending;
1505 }
1506
1507 /*
1508  * Sync back the VGIC state after a guest run. The distributor lock is
1509  * needed so we don't get preempted in the middle of the state processing.
1510  */
1511 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1512 {
1513         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1514         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1515         u64 elrsr;
1516         unsigned long *elrsr_ptr;
1517         int lr, pending;
1518         bool level_pending;
1519
1520         level_pending = vgic_process_maintenance(vcpu);
1521         elrsr = vgic_get_elrsr(vcpu);
1522         elrsr_ptr = u64_to_bitmask(&elrsr);
1523
1524         /* Clear mappings for empty LRs */
1525         for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) {
1526                 struct vgic_lr vlr;
1527
1528                 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1529                         continue;
1530
1531                 vlr = vgic_get_lr(vcpu, lr);
1532
1533                 BUG_ON(vlr.irq >= dist->nr_irqs);
1534                 vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
1535         }
1536
1537         /* Check if we still have something up our sleeve... */
1538         pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr);
1539         if (level_pending || pending < vgic->nr_lr)
1540                 set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
1541 }
1542
1543 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1544 {
1545         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1546
1547         if (!irqchip_in_kernel(vcpu->kvm))
1548                 return;
1549
1550         spin_lock(&dist->lock);
1551         __kvm_vgic_flush_hwstate(vcpu);
1552         spin_unlock(&dist->lock);
1553 }
1554
1555 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1556 {
1557         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1558
1559         if (!irqchip_in_kernel(vcpu->kvm))
1560                 return;
1561
1562         spin_lock(&dist->lock);
1563         __kvm_vgic_sync_hwstate(vcpu);
1564         spin_unlock(&dist->lock);
1565 }
1566
1567 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1568 {
1569         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1570
1571         if (!irqchip_in_kernel(vcpu->kvm))
1572                 return 0;
1573
1574         return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
1575 }
1576
1577 static void vgic_kick_vcpus(struct kvm *kvm)
1578 {
1579         struct kvm_vcpu *vcpu;
1580         int c;
1581
1582         /*
1583          * We've injected an interrupt, time to find out who deserves
1584          * a good kick...
1585          */
1586         kvm_for_each_vcpu(c, vcpu, kvm) {
1587                 if (kvm_vgic_vcpu_pending_irq(vcpu))
1588                         kvm_vcpu_kick(vcpu);
1589         }
1590 }
1591
1592 static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1593 {
1594         int edge_triggered = vgic_irq_is_edge(vcpu, irq);
1595
1596         /*
1597          * Only inject an interrupt if:
1598          * - edge triggered and we have a rising edge
1599          * - level triggered and we change level
1600          */
1601         if (edge_triggered) {
1602                 int state = vgic_dist_irq_is_pending(vcpu, irq);
1603                 return level > state;
1604         } else {
1605                 int state = vgic_dist_irq_get_level(vcpu, irq);
1606                 return level != state;
1607         }
1608 }
1609
1610 static bool vgic_update_irq_pending(struct kvm *kvm, int cpuid,
1611                                   unsigned int irq_num, bool level)
1612 {
1613         struct vgic_dist *dist = &kvm->arch.vgic;
1614         struct kvm_vcpu *vcpu;
1615         int edge_triggered, level_triggered;
1616         int enabled;
1617         bool ret = true;
1618
1619         spin_lock(&dist->lock);
1620
1621         vcpu = kvm_get_vcpu(kvm, cpuid);
1622         edge_triggered = vgic_irq_is_edge(vcpu, irq_num);
1623         level_triggered = !edge_triggered;
1624
1625         if (!vgic_validate_injection(vcpu, irq_num, level)) {
1626                 ret = false;
1627                 goto out;
1628         }
1629
1630         if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1631                 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1632                 vcpu = kvm_get_vcpu(kvm, cpuid);
1633         }
1634
1635         kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1636
1637         if (level) {
1638                 if (level_triggered)
1639                         vgic_dist_irq_set_level(vcpu, irq_num);
1640                 vgic_dist_irq_set_pending(vcpu, irq_num);
1641         } else {
1642                 if (level_triggered) {
1643                         vgic_dist_irq_clear_level(vcpu, irq_num);
1644                         if (!vgic_dist_irq_soft_pend(vcpu, irq_num))
1645                                 vgic_dist_irq_clear_pending(vcpu, irq_num);
1646                 } else {
1647                         vgic_dist_irq_clear_pending(vcpu, irq_num);
1648                 }
1649         }
1650
1651         enabled = vgic_irq_is_enabled(vcpu, irq_num);
1652
1653         if (!enabled) {
1654                 ret = false;
1655                 goto out;
1656         }
1657
1658         if (!vgic_can_sample_irq(vcpu, irq_num)) {
1659                 /*
1660                  * Level interrupt in progress, will be picked up
1661                  * when EOId.
1662                  */
1663                 ret = false;
1664                 goto out;
1665         }
1666
1667         if (level) {
1668                 vgic_cpu_irq_set(vcpu, irq_num);
1669                 set_bit(cpuid, dist->irq_pending_on_cpu);
1670         }
1671
1672 out:
1673         spin_unlock(&dist->lock);
1674
1675         return ret;
1676 }
1677
1678 /**
1679  * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1680  * @kvm:     The VM structure pointer
1681  * @cpuid:   The CPU for PPIs
1682  * @irq_num: The IRQ number that is assigned to the device
1683  * @level:   Edge-triggered:  true:  to trigger the interrupt
1684  *                            false: to ignore the call
1685  *           Level-sensitive  true:  activates an interrupt
1686  *                            false: deactivates an interrupt
1687  *
1688  * The GIC is not concerned with devices being active-LOW or active-HIGH for
1689  * level-sensitive interrupts.  You can think of the level parameter as 1
1690  * being HIGH and 0 being LOW and all devices being active-HIGH.
1691  */
1692 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1693                         bool level)
1694 {
1695         if (likely(vgic_initialized(kvm)) &&
1696             vgic_update_irq_pending(kvm, cpuid, irq_num, level))
1697                 vgic_kick_vcpus(kvm);
1698
1699         return 0;
1700 }
1701
1702 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1703 {
1704         /*
1705          * We cannot rely on the vgic maintenance interrupt to be
1706          * delivered synchronously. This means we can only use it to
1707          * exit the VM, and we perform the handling of EOIed
1708          * interrupts on the exit path (see vgic_process_maintenance).
1709          */
1710         return IRQ_HANDLED;
1711 }
1712
1713 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
1714 {
1715         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1716
1717         kfree(vgic_cpu->pending_shared);
1718         kfree(vgic_cpu->vgic_irq_lr_map);
1719         vgic_cpu->pending_shared = NULL;
1720         vgic_cpu->vgic_irq_lr_map = NULL;
1721 }
1722
1723 static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs)
1724 {
1725         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1726
1727         int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8;
1728         vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL);
1729         vgic_cpu->vgic_irq_lr_map = kzalloc(nr_irqs, GFP_KERNEL);
1730
1731         if (!vgic_cpu->pending_shared || !vgic_cpu->vgic_irq_lr_map) {
1732                 kvm_vgic_vcpu_destroy(vcpu);
1733                 return -ENOMEM;
1734         }
1735
1736         return 0;
1737 }
1738
1739 /**
1740  * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1741  * @vcpu: pointer to the vcpu struct
1742  *
1743  * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1744  * this vcpu and enable the VGIC for this VCPU
1745  */
1746 static void kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
1747 {
1748         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1749         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1750         int i;
1751
1752         for (i = 0; i < dist->nr_irqs; i++) {
1753                 if (i < VGIC_NR_PPIS)
1754                         vgic_bitmap_set_irq_val(&dist->irq_enabled,
1755                                                 vcpu->vcpu_id, i, 1);
1756                 if (i < VGIC_NR_PRIVATE_IRQS)
1757                         vgic_bitmap_set_irq_val(&dist->irq_cfg,
1758                                                 vcpu->vcpu_id, i, VGIC_CFG_EDGE);
1759
1760                 vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
1761         }
1762
1763         /*
1764          * Store the number of LRs per vcpu, so we don't have to go
1765          * all the way to the distributor structure to find out. Only
1766          * assembly code should use this one.
1767          */
1768         vgic_cpu->nr_lr = vgic->nr_lr;
1769
1770         vgic_enable(vcpu);
1771 }
1772
1773 void kvm_vgic_destroy(struct kvm *kvm)
1774 {
1775         struct vgic_dist *dist = &kvm->arch.vgic;
1776         struct kvm_vcpu *vcpu;
1777         int i;
1778
1779         kvm_for_each_vcpu(i, vcpu, kvm)
1780                 kvm_vgic_vcpu_destroy(vcpu);
1781
1782         vgic_free_bitmap(&dist->irq_enabled);
1783         vgic_free_bitmap(&dist->irq_level);
1784         vgic_free_bitmap(&dist->irq_pending);
1785         vgic_free_bitmap(&dist->irq_soft_pend);
1786         vgic_free_bitmap(&dist->irq_queued);
1787         vgic_free_bitmap(&dist->irq_cfg);
1788         vgic_free_bytemap(&dist->irq_priority);
1789         if (dist->irq_spi_target) {
1790                 for (i = 0; i < dist->nr_cpus; i++)
1791                         vgic_free_bitmap(&dist->irq_spi_target[i]);
1792         }
1793         kfree(dist->irq_sgi_sources);
1794         kfree(dist->irq_spi_cpu);
1795         kfree(dist->irq_spi_target);
1796         kfree(dist->irq_pending_on_cpu);
1797         dist->irq_sgi_sources = NULL;
1798         dist->irq_spi_cpu = NULL;
1799         dist->irq_spi_target = NULL;
1800         dist->irq_pending_on_cpu = NULL;
1801 }
1802
1803 /*
1804  * Allocate and initialize the various data structures. Must be called
1805  * with kvm->lock held!
1806  */
1807 static int vgic_init_maps(struct kvm *kvm)
1808 {
1809         struct vgic_dist *dist = &kvm->arch.vgic;
1810         struct kvm_vcpu *vcpu;
1811         int nr_cpus, nr_irqs;
1812         int ret, i;
1813
1814         if (dist->nr_cpus)      /* Already allocated */
1815                 return 0;
1816
1817         nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus);
1818         if (!nr_cpus)           /* No vcpus? Can't be good... */
1819                 return -EINVAL;
1820
1821         /*
1822          * If nobody configured the number of interrupts, use the
1823          * legacy one.
1824          */
1825         if (!dist->nr_irqs)
1826                 dist->nr_irqs = VGIC_NR_IRQS_LEGACY;
1827
1828         nr_irqs = dist->nr_irqs;
1829
1830         ret  = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs);
1831         ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs);
1832         ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs);
1833         ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs);
1834         ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs);
1835         ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs);
1836         ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs);
1837
1838         if (ret)
1839                 goto out;
1840
1841         dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL);
1842         dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL);
1843         dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus,
1844                                        GFP_KERNEL);
1845         dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long),
1846                                            GFP_KERNEL);
1847         if (!dist->irq_sgi_sources ||
1848             !dist->irq_spi_cpu ||
1849             !dist->irq_spi_target ||
1850             !dist->irq_pending_on_cpu) {
1851                 ret = -ENOMEM;
1852                 goto out;
1853         }
1854
1855         for (i = 0; i < nr_cpus; i++)
1856                 ret |= vgic_init_bitmap(&dist->irq_spi_target[i],
1857                                         nr_cpus, nr_irqs);
1858
1859         if (ret)
1860                 goto out;
1861
1862         kvm_for_each_vcpu(i, vcpu, kvm) {
1863                 ret = vgic_vcpu_init_maps(vcpu, nr_irqs);
1864                 if (ret) {
1865                         kvm_err("VGIC: Failed to allocate vcpu memory\n");
1866                         break;
1867                 }
1868         }
1869
1870         for (i = VGIC_NR_PRIVATE_IRQS; i < dist->nr_irqs; i += 4)
1871                 vgic_set_target_reg(kvm, 0, i);
1872
1873 out:
1874         if (ret)
1875                 kvm_vgic_destroy(kvm);
1876
1877         return ret;
1878 }
1879
1880 /**
1881  * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1882  * @kvm: pointer to the kvm struct
1883  *
1884  * Map the virtual CPU interface into the VM before running any VCPUs.  We
1885  * can't do this at creation time, because user space must first set the
1886  * virtual CPU interface address in the guest physical address space.  Also
1887  * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1888  */
1889 int kvm_vgic_init(struct kvm *kvm)
1890 {
1891         struct kvm_vcpu *vcpu;
1892         int ret = 0, i;
1893
1894         if (!irqchip_in_kernel(kvm))
1895                 return 0;
1896
1897         mutex_lock(&kvm->lock);
1898
1899         if (vgic_initialized(kvm))
1900                 goto out;
1901
1902         if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
1903             IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
1904                 kvm_err("Need to set vgic cpu and dist addresses first\n");
1905                 ret = -ENXIO;
1906                 goto out;
1907         }
1908
1909         ret = vgic_init_maps(kvm);
1910         if (ret) {
1911                 kvm_err("Unable to allocate maps\n");
1912                 goto out;
1913         }
1914
1915         ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
1916                                     vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE,
1917                                     true);
1918         if (ret) {
1919                 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1920                 goto out;
1921         }
1922
1923         kvm_for_each_vcpu(i, vcpu, kvm)
1924                 kvm_vgic_vcpu_init(vcpu);
1925
1926         kvm->arch.vgic.ready = true;
1927 out:
1928         if (ret)
1929                 kvm_vgic_destroy(kvm);
1930         mutex_unlock(&kvm->lock);
1931         return ret;
1932 }
1933
1934 int kvm_vgic_create(struct kvm *kvm)
1935 {
1936         int i, vcpu_lock_idx = -1, ret;
1937         struct kvm_vcpu *vcpu;
1938
1939         mutex_lock(&kvm->lock);
1940
1941         if (kvm->arch.vgic.vctrl_base) {
1942                 ret = -EEXIST;
1943                 goto out;
1944         }
1945
1946         /*
1947          * Any time a vcpu is run, vcpu_load is called which tries to grab the
1948          * vcpu->mutex.  By grabbing the vcpu->mutex of all VCPUs we ensure
1949          * that no other VCPUs are run while we create the vgic.
1950          */
1951         ret = -EBUSY;
1952         kvm_for_each_vcpu(i, vcpu, kvm) {
1953                 if (!mutex_trylock(&vcpu->mutex))
1954                         goto out_unlock;
1955                 vcpu_lock_idx = i;
1956         }
1957
1958         kvm_for_each_vcpu(i, vcpu, kvm) {
1959                 if (vcpu->arch.has_run_once)
1960                         goto out_unlock;
1961         }
1962         ret = 0;
1963
1964         spin_lock_init(&kvm->arch.vgic.lock);
1965         kvm->arch.vgic.in_kernel = true;
1966         kvm->arch.vgic.vctrl_base = vgic->vctrl_base;
1967         kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1968         kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1969
1970 out_unlock:
1971         for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
1972                 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
1973                 mutex_unlock(&vcpu->mutex);
1974         }
1975
1976 out:
1977         mutex_unlock(&kvm->lock);
1978         return ret;
1979 }
1980
1981 static int vgic_ioaddr_overlap(struct kvm *kvm)
1982 {
1983         phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1984         phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1985
1986         if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1987                 return 0;
1988         if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1989             (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1990                 return -EBUSY;
1991         return 0;
1992 }
1993
1994 static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1995                               phys_addr_t addr, phys_addr_t size)
1996 {
1997         int ret;
1998
1999         if (addr & ~KVM_PHYS_MASK)
2000                 return -E2BIG;
2001
2002         if (addr & (SZ_4K - 1))
2003                 return -EINVAL;
2004
2005         if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
2006                 return -EEXIST;
2007         if (addr + size < addr)
2008                 return -EINVAL;
2009
2010         *ioaddr = addr;
2011         ret = vgic_ioaddr_overlap(kvm);
2012         if (ret)
2013                 *ioaddr = VGIC_ADDR_UNDEF;
2014
2015         return ret;
2016 }
2017
2018 /**
2019  * kvm_vgic_addr - set or get vgic VM base addresses
2020  * @kvm:   pointer to the vm struct
2021  * @type:  the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
2022  * @addr:  pointer to address value
2023  * @write: if true set the address in the VM address space, if false read the
2024  *          address
2025  *
2026  * Set or get the vgic base addresses for the distributor and the virtual CPU
2027  * interface in the VM physical address space.  These addresses are properties
2028  * of the emulated core/SoC and therefore user space initially knows this
2029  * information.
2030  */
2031 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
2032 {
2033         int r = 0;
2034         struct vgic_dist *vgic = &kvm->arch.vgic;
2035
2036         mutex_lock(&kvm->lock);
2037         switch (type) {
2038         case KVM_VGIC_V2_ADDR_TYPE_DIST:
2039                 if (write) {
2040                         r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
2041                                                *addr, KVM_VGIC_V2_DIST_SIZE);
2042                 } else {
2043                         *addr = vgic->vgic_dist_base;
2044                 }
2045                 break;
2046         case KVM_VGIC_V2_ADDR_TYPE_CPU:
2047                 if (write) {
2048                         r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
2049                                                *addr, KVM_VGIC_V2_CPU_SIZE);
2050                 } else {
2051                         *addr = vgic->vgic_cpu_base;
2052                 }
2053                 break;
2054         default:
2055                 r = -ENODEV;
2056         }
2057
2058         mutex_unlock(&kvm->lock);
2059         return r;
2060 }
2061
2062 static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu,
2063                                  struct kvm_exit_mmio *mmio, phys_addr_t offset)
2064 {
2065         bool updated = false;
2066         struct vgic_vmcr vmcr;
2067         u32 *vmcr_field;
2068         u32 reg;
2069
2070         vgic_get_vmcr(vcpu, &vmcr);
2071
2072         switch (offset & ~0x3) {
2073         case GIC_CPU_CTRL:
2074                 vmcr_field = &vmcr.ctlr;
2075                 break;
2076         case GIC_CPU_PRIMASK:
2077                 vmcr_field = &vmcr.pmr;
2078                 break;
2079         case GIC_CPU_BINPOINT:
2080                 vmcr_field = &vmcr.bpr;
2081                 break;
2082         case GIC_CPU_ALIAS_BINPOINT:
2083                 vmcr_field = &vmcr.abpr;
2084                 break;
2085         default:
2086                 BUG();
2087         }
2088
2089         if (!mmio->is_write) {
2090                 reg = *vmcr_field;
2091                 mmio_data_write(mmio, ~0, reg);
2092         } else {
2093                 reg = mmio_data_read(mmio, ~0);
2094                 if (reg != *vmcr_field) {
2095                         *vmcr_field = reg;
2096                         vgic_set_vmcr(vcpu, &vmcr);
2097                         updated = true;
2098                 }
2099         }
2100         return updated;
2101 }
2102
2103 static bool handle_mmio_abpr(struct kvm_vcpu *vcpu,
2104                              struct kvm_exit_mmio *mmio, phys_addr_t offset)
2105 {
2106         return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT);
2107 }
2108
2109 static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu,
2110                                   struct kvm_exit_mmio *mmio,
2111                                   phys_addr_t offset)
2112 {
2113         u32 reg;
2114
2115         if (mmio->is_write)
2116                 return false;
2117
2118         /* GICC_IIDR */
2119         reg = (PRODUCT_ID_KVM << 20) |
2120               (GICC_ARCH_VERSION_V2 << 16) |
2121               (IMPLEMENTER_ARM << 0);
2122         mmio_data_write(mmio, ~0, reg);
2123         return false;
2124 }
2125
2126 /*
2127  * CPU Interface Register accesses - these are not accessed by the VM, but by
2128  * user space for saving and restoring VGIC state.
2129  */
2130 static const struct mmio_range vgic_cpu_ranges[] = {
2131         {
2132                 .base           = GIC_CPU_CTRL,
2133                 .len            = 12,
2134                 .handle_mmio    = handle_cpu_mmio_misc,
2135         },
2136         {
2137                 .base           = GIC_CPU_ALIAS_BINPOINT,
2138                 .len            = 4,
2139                 .handle_mmio    = handle_mmio_abpr,
2140         },
2141         {
2142                 .base           = GIC_CPU_ACTIVEPRIO,
2143                 .len            = 16,
2144                 .handle_mmio    = handle_mmio_raz_wi,
2145         },
2146         {
2147                 .base           = GIC_CPU_IDENT,
2148                 .len            = 4,
2149                 .handle_mmio    = handle_cpu_mmio_ident,
2150         },
2151 };
2152
2153 static int vgic_attr_regs_access(struct kvm_device *dev,
2154                                  struct kvm_device_attr *attr,
2155                                  u32 *reg, bool is_write)
2156 {
2157         const struct mmio_range *r = NULL, *ranges;
2158         phys_addr_t offset;
2159         int ret, cpuid, c;
2160         struct kvm_vcpu *vcpu, *tmp_vcpu;
2161         struct vgic_dist *vgic;
2162         struct kvm_exit_mmio mmio;
2163
2164         offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2165         cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
2166                 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
2167
2168         mutex_lock(&dev->kvm->lock);
2169
2170         ret = vgic_init_maps(dev->kvm);
2171         if (ret)
2172                 goto out;
2173
2174         if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) {
2175                 ret = -EINVAL;
2176                 goto out;
2177         }
2178
2179         vcpu = kvm_get_vcpu(dev->kvm, cpuid);
2180         vgic = &dev->kvm->arch.vgic;
2181
2182         mmio.len = 4;
2183         mmio.is_write = is_write;
2184         if (is_write)
2185                 mmio_data_write(&mmio, ~0, *reg);
2186         switch (attr->group) {
2187         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2188                 mmio.phys_addr = vgic->vgic_dist_base + offset;
2189                 ranges = vgic_dist_ranges;
2190                 break;
2191         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2192                 mmio.phys_addr = vgic->vgic_cpu_base + offset;
2193                 ranges = vgic_cpu_ranges;
2194                 break;
2195         default:
2196                 BUG();
2197         }
2198         r = find_matching_range(ranges, &mmio, offset);
2199
2200         if (unlikely(!r || !r->handle_mmio)) {
2201                 ret = -ENXIO;
2202                 goto out;
2203         }
2204
2205
2206         spin_lock(&vgic->lock);
2207
2208         /*
2209          * Ensure that no other VCPU is running by checking the vcpu->cpu
2210          * field.  If no other VPCUs are running we can safely access the VGIC
2211          * state, because even if another VPU is run after this point, that
2212          * VCPU will not touch the vgic state, because it will block on
2213          * getting the vgic->lock in kvm_vgic_sync_hwstate().
2214          */
2215         kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) {
2216                 if (unlikely(tmp_vcpu->cpu != -1)) {
2217                         ret = -EBUSY;
2218                         goto out_vgic_unlock;
2219                 }
2220         }
2221
2222         /*
2223          * Move all pending IRQs from the LRs on all VCPUs so the pending
2224          * state can be properly represented in the register state accessible
2225          * through this API.
2226          */
2227         kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm)
2228                 vgic_unqueue_irqs(tmp_vcpu);
2229
2230         offset -= r->base;
2231         r->handle_mmio(vcpu, &mmio, offset);
2232
2233         if (!is_write)
2234                 *reg = mmio_data_read(&mmio, ~0);
2235
2236         ret = 0;
2237 out_vgic_unlock:
2238         spin_unlock(&vgic->lock);
2239 out:
2240         mutex_unlock(&dev->kvm->lock);
2241         return ret;
2242 }
2243
2244 static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2245 {
2246         int r;
2247
2248         switch (attr->group) {
2249         case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2250                 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2251                 u64 addr;
2252                 unsigned long type = (unsigned long)attr->attr;
2253
2254                 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2255                         return -EFAULT;
2256
2257                 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
2258                 return (r == -ENODEV) ? -ENXIO : r;
2259         }
2260
2261         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2262         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2263                 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2264                 u32 reg;
2265
2266                 if (get_user(reg, uaddr))
2267                         return -EFAULT;
2268
2269                 return vgic_attr_regs_access(dev, attr, &reg, true);
2270         }
2271         case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
2272                 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2273                 u32 val;
2274                 int ret = 0;
2275
2276                 if (get_user(val, uaddr))
2277                         return -EFAULT;
2278
2279                 /*
2280                  * We require:
2281                  * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
2282                  * - at most 1024 interrupts
2283                  * - a multiple of 32 interrupts
2284                  */
2285                 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
2286                     val > VGIC_MAX_IRQS ||
2287                     (val & 31))
2288                         return -EINVAL;
2289
2290                 mutex_lock(&dev->kvm->lock);
2291
2292                 if (vgic_initialized(dev->kvm) || dev->kvm->arch.vgic.nr_irqs)
2293                         ret = -EBUSY;
2294                 else
2295                         dev->kvm->arch.vgic.nr_irqs = val;
2296
2297                 mutex_unlock(&dev->kvm->lock);
2298
2299                 return ret;
2300         }
2301
2302         }
2303
2304         return -ENXIO;
2305 }
2306
2307 static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2308 {
2309         int r = -ENXIO;
2310
2311         switch (attr->group) {
2312         case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2313                 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2314                 u64 addr;
2315                 unsigned long type = (unsigned long)attr->attr;
2316
2317                 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
2318                 if (r)
2319                         return (r == -ENODEV) ? -ENXIO : r;
2320
2321                 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2322                         return -EFAULT;
2323                 break;
2324         }
2325
2326         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2327         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2328                 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2329                 u32 reg = 0;
2330
2331                 r = vgic_attr_regs_access(dev, attr, &reg, false);
2332                 if (r)
2333                         return r;
2334                 r = put_user(reg, uaddr);
2335                 break;
2336         }
2337         case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
2338                 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2339                 r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr);
2340                 break;
2341         }
2342
2343         }
2344
2345         return r;
2346 }
2347
2348 static int vgic_has_attr_regs(const struct mmio_range *ranges,
2349                               phys_addr_t offset)
2350 {
2351         struct kvm_exit_mmio dev_attr_mmio;
2352
2353         dev_attr_mmio.len = 4;
2354         if (find_matching_range(ranges, &dev_attr_mmio, offset))
2355                 return 0;
2356         else
2357                 return -ENXIO;
2358 }
2359
2360 static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2361 {
2362         phys_addr_t offset;
2363
2364         switch (attr->group) {
2365         case KVM_DEV_ARM_VGIC_GRP_ADDR:
2366                 switch (attr->attr) {
2367                 case KVM_VGIC_V2_ADDR_TYPE_DIST:
2368                 case KVM_VGIC_V2_ADDR_TYPE_CPU:
2369                         return 0;
2370                 }
2371                 break;
2372         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2373                 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2374                 return vgic_has_attr_regs(vgic_dist_ranges, offset);
2375         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2376                 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2377                 return vgic_has_attr_regs(vgic_cpu_ranges, offset);
2378         case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
2379                 return 0;
2380         }
2381         return -ENXIO;
2382 }
2383
2384 static void vgic_destroy(struct kvm_device *dev)
2385 {
2386         kfree(dev);
2387 }
2388
2389 static int vgic_create(struct kvm_device *dev, u32 type)
2390 {
2391         return kvm_vgic_create(dev->kvm);
2392 }
2393
2394 static struct kvm_device_ops kvm_arm_vgic_v2_ops = {
2395         .name = "kvm-arm-vgic",
2396         .create = vgic_create,
2397         .destroy = vgic_destroy,
2398         .set_attr = vgic_set_attr,
2399         .get_attr = vgic_get_attr,
2400         .has_attr = vgic_has_attr,
2401 };
2402
2403 static void vgic_init_maintenance_interrupt(void *info)
2404 {
2405         enable_percpu_irq(vgic->maint_irq, 0);
2406 }
2407
2408 static int vgic_cpu_notify(struct notifier_block *self,
2409                            unsigned long action, void *cpu)
2410 {
2411         switch (action) {
2412         case CPU_STARTING:
2413         case CPU_STARTING_FROZEN:
2414                 vgic_init_maintenance_interrupt(NULL);
2415                 break;
2416         case CPU_DYING:
2417         case CPU_DYING_FROZEN:
2418                 disable_percpu_irq(vgic->maint_irq);
2419                 break;
2420         }
2421
2422         return NOTIFY_OK;
2423 }
2424
2425 static struct notifier_block vgic_cpu_nb = {
2426         .notifier_call = vgic_cpu_notify,
2427 };
2428
2429 static const struct of_device_id vgic_ids[] = {
2430         { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
2431         { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
2432         {},
2433 };
2434
2435 int kvm_vgic_hyp_init(void)
2436 {
2437         const struct of_device_id *matched_id;
2438         const int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
2439                                 const struct vgic_params **);
2440         struct device_node *vgic_node;
2441         int ret;
2442
2443         vgic_node = of_find_matching_node_and_match(NULL,
2444                                                     vgic_ids, &matched_id);
2445         if (!vgic_node) {
2446                 kvm_err("error: no compatible GIC node found\n");
2447                 return -ENODEV;
2448         }
2449
2450         vgic_probe = matched_id->data;
2451         ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
2452         if (ret)
2453                 return ret;
2454
2455         ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
2456                                  "vgic", kvm_get_running_vcpus());
2457         if (ret) {
2458                 kvm_err("Cannot register interrupt %d\n", vgic->maint_irq);
2459                 return ret;
2460         }
2461
2462         ret = __register_cpu_notifier(&vgic_cpu_nb);
2463         if (ret) {
2464                 kvm_err("Cannot register vgic CPU notifier\n");
2465                 goto out_free_irq;
2466         }
2467
2468         /* Callback into for arch code for setup */
2469         vgic_arch_setup(vgic);
2470
2471         on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
2472
2473         return kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
2474                                        KVM_DEV_TYPE_ARM_VGIC_V2);
2475
2476 out_free_irq:
2477         free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus());
2478         return ret;
2479 }