ARC: add/fix some comments in code - no functional change

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index 1cd5e82f5dc2c6f74cb36d40632998fd26195426..846481f37eef08bd8911859009fddf390974b193 100644 (file)
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -72,12 +72,13 @@
        };
 
        /*
-        * This INTC is actually connected to DW APB GPIO
-        * which acts as a wire between MB INTC and CPU INTC.
-        * GPIO INTC is configured in platform init code
-        * and here we mimic direct connection from MB INTC to
-        * CPU INTC, thus we set "interrupts = <7>" instead of
-        * "interrupts = <12>"
+        * The DW APB ICTL intc on MB is connected to CPU intc via a
+        * DT "invisible" DW APB GPIO block, configured to simply pass thru
+        * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
+        *
+        * So here we mimic a direct connection betwen them, ignoring the
+        * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
+        * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
         *
         * This intc actually resides on MB, but we move it here to
         * avoid duplicating the MB dtsi file given that IRQ from

diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h
index 44fd531f4d7b93a9df7bff6dec976af5e571506c..af7a2db139c96887a758f711140175f88b85845d 100644 (file)
--- a/arch/arc/include/asm/cmpxchg.h
+++ b/arch/arc/include/asm/cmpxchg.h
@@ -110,18 +110,18 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
                                                 sizeof(*(ptr))))
 
 /*
- * On ARC700, EX insn is inherently atomic, so by default "vanilla" xchg() need
- * not require any locking. However there's a quirk.
- * ARC lacks native CMPXCHG, thus emulated (see above), using external locking -
- * incidently it "reuses" the same atomic_ops_lock used by atomic APIs.
- * Now, llist code uses cmpxchg() and xchg() on same data, so xchg() needs to
- * abide by same serializing rules, thus ends up using atomic_ops_lock as well.
+ * xchg() maps directly to ARC EX instruction which guarantees atomicity.
+ * However in !LLSC config, it also needs to be use @atomic_ops_lock spinlock
+ * due to a subtle reason:
+ *  - For !LLSC, cmpxchg() needs to use that lock (see above) and there is lot
+ *    of  kernel code which calls xchg()/cmpxchg() on same data (see llist.h)
+ *    Hence xchg() needs to follow same locking rules.
  *
- * This however is only relevant if SMP and/or ARC lacks LLSC
- *   if (UP or LLSC)
- *      xchg doesn't need serialization
- *   else <==> !(UP or LLSC) <==> (!UP and !LLSC) <==> (SMP and !LLSC)
- *      xchg needs serialization
+ * Technically the lock is also needed for UP (boils down to irq save/restore)
+ * but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to
+ * be disabled thus can't possibly be interrpted/preempted/clobbered by xchg()
+ * Other way around, xchg is one instruction anyways, so can't be interrupted
+ * as such
  */
 
 #if !defined(CONFIG_ARC_HAS_LLSC) && defined(CONFIG_SMP)

diff --git a/arch/arc/include/asm/perf_event.h b/arch/arc/include/asm/perf_event.h
index 2b8880e953a294f4dc4abf7fbe7ae04580dd82ce..e2eaf6fb0468de2f68fdb4178a991020a669a83f 100644 (file)
--- a/arch/arc/include/asm/perf_event.h
+++ b/arch/arc/include/asm/perf_event.h
@@ -95,7 +95,7 @@ static const char * const arc_pmu_ev_hw_map[] = {
 
        /* counts condition */
        [PERF_COUNT_HW_INSTRUCTIONS] = "iall",
-       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp",
+       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", /* Excludes ZOL jumps */
        [PERF_COUNT_ARC_BPOK]         = "bpok",   /* NP-NT, PT-T, PNT-NT */
        [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
 

diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c
index 1287388c258ace8ef57f1030a46acb65f0fbb87e..79ab199a9778f6489b2fb6e26e718fddf7d58da8 100644 (file)
--- a/arch/arc/kernel/perf_event.c
+++ b/arch/arc/kernel/perf_event.c
@@ -199,8 +199,8 @@ static void arc_pmu_start(struct perf_event *event, int flags)
        event->hw.state = 0;
 
        /* enable ARC pmu here */
-       write_aux_reg(ARC_REG_PCT_INDEX, idx);
-       write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);
+       write_aux_reg(ARC_REG_PCT_INDEX, idx);          /* counter # */
+       write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */
 }
 
 static void arc_pmu_stop(struct perf_event *event, int flags)

diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 44092456776f8e9cd929b36e5083fbc4074dac9b..91d5a0f1f3f79cdd454e99e7781b2e3741caae76 100644 (file)
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -65,7 +65,7 @@ asmlinkage void ret_from_fork(void);
  * ------------------
  * |     r25        |   <==== top of Stack (thread.ksp)
  * ~                ~
- * |    --to--      |   (CALLEE Regs of user mode)
+ * |    --to--      |   (CALLEE Regs of kernel mode)
  * |     r13        |
  * ------------------
  * |     fp         |

diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index e7769c3ab5f2b7793aff703ca5e926983b45ec29..ad9825d4026aefe0b51d0f85037a2858f1ccda83 100644 (file)
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -46,7 +46,7 @@ static void __init axs10x_enable_gpio_intc_wire(void)
         * -------------------   -------------------
         * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |
         * -------------------   -------------------
-        *        |                         |
+        *        | #12                     |
         *        |                 [ Debug UART on cpu card ]
         *        |
         * ------------------------