Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

* 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  perf, x86: Complain louder about BIOSen corrupting CPU/PMU state and continue
  perf, x86: P4 PMU - Read proper MSR register to catch unflagged overflows
  perf symbols: Look at .dynsym again if .symtab not found
  perf build-id: Add quirk to deal with perf.data file format breakage
  perf session: Pass evsel in event_ops->sample()
  perf: Better fit max unprivileged mlock pages for tools needs
  perf_events: Fix stale ->cgrp pointer in update_cgrp_time_from_cpuctx()
  perf top: Fix uninitialized 'counter' variable
  tracing: Fix set_ftrace_filter probe function display
  perf, x86: Fix Intel fixed counters base initialization

diff --combined arch/x86/kernel/cpu/perf_event.c
index 87eab4a27dfccc0ad75d17338d6a8be5c5a1a1e0,eb00677ee2aec8bfe1a0ba91c0eed682766d5862..eed3673a8656f5688d54f6b4d72fd9774c831fcb
--- 1/arch/x86/kernel/cpu/perf_event.c
--- 2/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@@ -500,12 -500,17 +500,17 @@@ static bool check_hw_exists(void
        return true;
  
  bios_fail:
-       printk(KERN_CONT "Broken BIOS detected, using software events only.\n");
+       /*
+        * We still allow the PMU driver to operate:
+        */
+       printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
        printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
-       return false;
+ 
+       return true;
  
  msr_fail:
        printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
+ 
        return false;
  }
  
@@@ -912,7 -917,7 +917,7 @@@ static inline void x86_assign_hw_event(
                hwc->event_base = 0;
        } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
                hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
-               hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0;
+               hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
        } else {
                hwc->config_base = x86_pmu_config_addr(hwc->idx);
                hwc->event_base  = x86_pmu_event_addr(hwc->idx);
@@@ -1109,7 -1114,7 +1114,7 @@@ static int x86_pmu_add(struct perf_even
  
        /*
         * If group events scheduling transaction was started,
 -       * skip the schedulability test here, it will be peformed
 +       * skip the schedulability test here, it will be performed
         * at commit time (->commit_txn) as a whole
         */
        if (cpuc->group_flag & PERF_EVENT_TXN)
@@@ -1790,7 -1795,7 +1795,7 @@@ perf_callchain_kernel(struct perf_callc
  
        perf_callchain_store(entry, regs->ip);
  
 -      dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
 +      dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
  }
  
  #ifdef CONFIG_COMPAT

diff --combined arch/x86/kernel/cpu/perf_event_p4.c
index 0811f5ebfba6643083b50d81c5710292db12b4b6,d3d7b59841e5bf913f008c4d55ad331ea927f8c4..c2520e178d32147fd9e2acd954d59e4217115add
--- 1/arch/x86/kernel/cpu/perf_event_p4.c
--- 2/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@@ -1,5 -1,5 +1,5 @@@
  /*
 - * Netburst Perfomance Events (P4, old Xeon)
 + * Netburst Performance Events (P4, old Xeon)
   *
   *  Copyright (C) 2010 Parallels, Inc., Cyrill Gorcunov <gorcunov@openvz.org>
   *  Copyright (C) 2010 Intel Corporation, Lin Ming <ming.m.lin@intel.com>
@@@ -679,7 -679,7 +679,7 @@@ static int p4_validate_raw_event(struc
         */
  
        /*
 -       * if an event is shared accross the logical threads
 +       * if an event is shared across the logical threads
         * the user needs special permissions to be able to use it
         */
        if (p4_ht_active() && p4_event_bind_map[v].shared) {
@@@ -777,6 -777,7 +777,7 @@@ static inline int p4_pmu_clear_cccr_ovf
         * the counter has reached zero value and continued counting before
         * real NMI signal was received:
         */
+       rdmsrl(hwc->event_base, v);
        if (!(v & ARCH_P4_UNFLAGGED_BIT))
                return 1;
  
@@@ -790,13 -791,13 +791,13 @@@ static void p4_pmu_disable_pebs(void
         *
         * It's still allowed that two threads setup same cache
         * events so we can't simply clear metrics until we knew
 -       * noone is depending on us, so we need kind of counter
 +       * no one is depending on us, so we need kind of counter
         * for "ReplayEvent" users.
         *
         * What is more complex -- RAW events, if user (for some
         * reason) will pass some cache event metric with improper
         * event opcode -- it's fine from hardware point of view
 -       * but completely nonsence from "meaning" of such action.
 +       * but completely nonsense from "meaning" of such action.
         *
         * So at moment let leave metrics turned on forever -- it's
         * ok for now but need to be revisited!