[PATCH] ARM: 2782/1: PXA27x MDREFR K0DB4 define

Patch from Todd Poynor

Add definition of K0DB4 SDCLK<0,3> divide-by-4 control/status bit in the
MDREFR register for Intel XScale PXA27x.

Signed-off-by: Todd Poynor <tpoynor@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 803dc92c90389ad3965597640ebab0dbf3e3f2fd..51f0fe0ac165bb4a6ee64f69faeaa2576994fce8 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1966,6 +1966,7 @@
 #define MECR_NOS       (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
 #define MECR_CIT       (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
 
+#define MDREFR_K0DB4   (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
 #define MDREFR_K2FREE  (1 << 25)       /* SDRAM Free-Running Control */
 #define MDREFR_K1FREE  (1 << 24)       /* SDRAM Free-Running Control */
 #define MDREFR_K0FREE  (1 << 23)       /* SDRAM Free-Running Control */