ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles

For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 635a16a64cb4693aa536a3bce865ec386b77e0db..3f95dc568b2350cdf14759189ca40c441138eeb9 100644 (file)
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -90,6 +90,8 @@
                        compatible = "arm,pl310-cache";
                        reg = <0xac0000 0x1000>;
                        cache-level = <2>;
+                       arm,data-latency = <2 2 2>;
+                       arm,tag-latency = <2 2 2>;
                };
 
                scu: snoop-control-unit@ad0000 {