arm: plat-orion: Add coherency attribute when setup mbus target

Recent SoC such as Armada 370/XP came with the possibility to deal
with the I/O coherency by hardware. In this case the transaction
attribute of the window must be flagged as "Shared transaction". Once
this flag is set, then the transactions will be forced to be sent
through the coherency block, in other case transaction is driven
directly to DRAM.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index a7b8060c293a47d2394515c4751e9ea5f0311d6e..febe3862873ca2238aaaccf3265991c97fe5384c 100644 (file)
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -42,6 +42,8 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 #define WIN_REMAP_LO_OFF       0x0008
 #define WIN_REMAP_HI_OFF       0x000c
 
+#define ATTR_HW_COHERENCY      (0x1 << 4)
+
 /*
  * Default implementation
  */
@@ -163,6 +165,8 @@ void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
                        w = &orion_mbus_dram_info.cs[cs++];
                        w->cs_index = i;
                        w->mbus_attr = 0xf & ~(1 << i);
+                       if (cfg->hw_io_coherency)
+                               w->mbus_attr |= ATTR_HW_COHERENCY;
                        w->base = base & 0xffff0000;
                        w->size = (size | 0x0000ffff) + 1;
                }

diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index ec63e4a627d07c3f007bdc897a4c5daa55c2860e..b76c06569fe5c122ada0a7f7ff5fda83937c8507 100644 (file)
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -17,6 +17,7 @@ struct orion_addr_map_cfg {
        const int num_wins;     /* Total number of windows */
        const int remappable_wins;
        void __iomem *bridge_virt_base;
+       int hw_io_coherency;
 
        /* If NULL, the default cpu_win_can_remap will be used, using
           the value in remappable_wins */