Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm...

- a fix from Eric for synchronization with etnaviv exported dma-bufs
- thermal throttle support for newer GPU cores
- updated module clock gating to work around GPU errata
- a fix to restore userspace buffer cache performance

* 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux:
  drm/etnaviv: restore ETNA_PREP_NOSYNC behaviour
  drm/etnaviv: implement cooling support for new GPU cores
  drm/etnaviv: update MLCG disables with info from newer Vivante driver
  drm/etnaviv: update common.xml.h
  drm/etnaviv: Expose our reservation object when exporting a dmabuf.

diff --git a/drivers/gpu/drm/etnaviv/common.xml.h b/drivers/gpu/drm/etnaviv/common.xml.h
index e881482b5971d16ee2539307f6bf41746fc4dbef..207f45c999c34e2840e9fe138d44169402cb9881 100644 (file)
--- a/drivers/gpu/drm/etnaviv/common.xml.h
+++ b/drivers/gpu/drm/etnaviv/common.xml.h
@@ -8,10 +8,38 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- state_hi.xml (  24309 bytes, from 2015-12-12 09:02:53)
-- common.xml   (  18379 bytes, from 2015-12-12 09:02:53)
+- state.xml     (  19930 bytes, from 2017-03-09 15:43:43)
+- common.xml    (  23473 bytes, from 2017-03-09 15:43:43)
+- state_hi.xml  (  26403 bytes, from 2017-03-09 15:43:43)
+- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
+- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
+- state_3d.xml  (  66957 bytes, from 2017-03-09 15:43:43)
+- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
 
-Copyright (C) 2015
+Copyright (C) 2012-2017 by the following authors:
+- Wladimir J. van der Laan <laanwj@gmail.com>
+- Christian Gmeiner <christian.gmeiner@gmail.com>
+- Lucas Stach <l.stach@pengutronix.de>
+- Russell King <rmk@arm.linux.org.uk>
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sub license,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
 */
 
 
@@ -162,129 +190,129 @@ Copyright (C) 2015
 #define chipMinorFeatures1_FC_FLUSH_STALL                      0x80000000
 #define chipMinorFeatures2_LINE_LOOP                           0x00000001
 #define chipMinorFeatures2_LOGIC_OP                            0x00000002
-#define chipMinorFeatures2_UNK2                                        0x00000004
+#define chipMinorFeatures2_SEAMLESS_CUBE_MAP                   0x00000004
 #define chipMinorFeatures2_SUPERTILED_TEXTURE                  0x00000008
-#define chipMinorFeatures2_UNK4                                        0x00000010
+#define chipMinorFeatures2_LINEAR_PE                           0x00000010
 #define chipMinorFeatures2_RECT_PRIMITIVE                      0x00000020
 #define chipMinorFeatures2_COMPOSITION                         0x00000040
 #define chipMinorFeatures2_CORRECT_AUTO_DISABLE_COUNT          0x00000080
-#define chipMinorFeatures2_UNK8                                        0x00000100
-#define chipMinorFeatures2_UNK9                                        0x00000200
-#define chipMinorFeatures2_UNK10                               0x00000400
+#define chipMinorFeatures2_PE_SWIZZLE                          0x00000100
+#define chipMinorFeatures2_END_EVENT                           0x00000200
+#define chipMinorFeatures2_S1S8                                        0x00000400
 #define chipMinorFeatures2_HALTI1                              0x00000800
-#define chipMinorFeatures2_UNK12                               0x00001000
-#define chipMinorFeatures2_UNK13                               0x00002000
-#define chipMinorFeatures2_UNK14                               0x00004000
+#define chipMinorFeatures2_RGB888                              0x00001000
+#define chipMinorFeatures2_TX__YUV_ASSEMBLER                   0x00002000
+#define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING           0x00004000
 #define chipMinorFeatures2_EXTRA_TEXTURE_STATE                 0x00008000
 #define chipMinorFeatures2_FULL_DIRECTFB                       0x00010000
 #define chipMinorFeatures2_2D_TILING                           0x00020000
 #define chipMinorFeatures2_THREAD_WALKER_IN_PS                 0x00040000
 #define chipMinorFeatures2_TILE_FILLER                         0x00080000
-#define chipMinorFeatures2_UNK20                               0x00100000
+#define chipMinorFeatures2_YUV_STANDARD                                0x00100000
 #define chipMinorFeatures2_2D_MULTI_SOURCE_BLIT                        0x00200000
-#define chipMinorFeatures2_UNK22                               0x00400000
-#define chipMinorFeatures2_UNK23                               0x00800000
-#define chipMinorFeatures2_UNK24                               0x01000000
+#define chipMinorFeatures2_YUV_CONVERSION                      0x00400000
+#define chipMinorFeatures2_FLUSH_FIXED_2D                      0x00800000
+#define chipMinorFeatures2_INTERLEAVER                         0x01000000
 #define chipMinorFeatures2_MIXED_STREAMS                       0x02000000
 #define chipMinorFeatures2_2D_420_L2CACHE                      0x04000000
-#define chipMinorFeatures2_UNK27                               0x08000000
+#define chipMinorFeatures2_BUG_FIXES7                          0x08000000
 #define chipMinorFeatures2_2D_NO_INDEX8_BRUSH                  0x10000000
 #define chipMinorFeatures2_TEXTURE_TILED_READ                  0x20000000
-#define chipMinorFeatures2_UNK30                               0x40000000
-#define chipMinorFeatures2_UNK31                               0x80000000
+#define chipMinorFeatures2_DECOMPRESS_Z16                      0x40000000
+#define chipMinorFeatures2_BUG_FIXES8                          0x80000000
 #define chipMinorFeatures3_ROTATION_STALL_FIX                  0x00000001
-#define chipMinorFeatures3_UNK1                                        0x00000002
+#define chipMinorFeatures3_OCL_ONLY                            0x00000002
 #define chipMinorFeatures3_2D_MULTI_SOURCE_BLT_EX              0x00000004
-#define chipMinorFeatures3_UNK3                                        0x00000008
-#define chipMinorFeatures3_UNK4                                        0x00000010
-#define chipMinorFeatures3_UNK5                                        0x00000020
-#define chipMinorFeatures3_UNK6                                        0x00000040
-#define chipMinorFeatures3_UNK7                                        0x00000080
+#define chipMinorFeatures3_INSTRUCTION_CACHE                   0x00000008
+#define chipMinorFeatures3_GEOMETRY_SHADER                     0x00000010
+#define chipMinorFeatures3_TEX_COMPRESSION_SUPERTILED          0x00000020
+#define chipMinorFeatures3_GENERICS                            0x00000040
+#define chipMinorFeatures3_BUG_FIXES9                          0x00000080
 #define chipMinorFeatures3_FAST_MSAA                           0x00000100
-#define chipMinorFeatures3_UNK9                                        0x00000200
+#define chipMinorFeatures3_WCLIP                               0x00000200
 #define chipMinorFeatures3_BUG_FIXES10                         0x00000400
-#define chipMinorFeatures3_UNK11                               0x00000800
+#define chipMinorFeatures3_UNIFIED_SAMPLERS                    0x00000800
 #define chipMinorFeatures3_BUG_FIXES11                         0x00001000
-#define chipMinorFeatures3_UNK13                               0x00002000
-#define chipMinorFeatures3_UNK14                               0x00004000
-#define chipMinorFeatures3_UNK15                               0x00008000
-#define chipMinorFeatures3_UNK16                               0x00010000
-#define chipMinorFeatures3_UNK17                               0x00020000
+#define chipMinorFeatures3_PERFORMANCE_COUNTERS                        0x00002000
+#define chipMinorFeatures3_HAS_FAST_TRANSCENDENTALS            0x00004000
+#define chipMinorFeatures3_BUG_FIXES12                         0x00008000
+#define chipMinorFeatures3_BUG_FIXES13                         0x00010000
+#define chipMinorFeatures3_DE_ENHANCEMENTS1                    0x00020000
 #define chipMinorFeatures3_ACE                                 0x00040000
-#define chipMinorFeatures3_UNK19                               0x00080000
-#define chipMinorFeatures3_UNK20                               0x00100000
-#define chipMinorFeatures3_UNK21                               0x00200000
+#define chipMinorFeatures3_TX_ENHANCEMENTS1                    0x00080000
+#define chipMinorFeatures3_SH_ENHANCEMENTS1                    0x00100000
+#define chipMinorFeatures3_SH_ENHANCEMENTS2                    0x00200000
 #define chipMinorFeatures3_UNK22                               0x00400000
-#define chipMinorFeatures3_UNK23                               0x00800000
+#define chipMinorFeatures3_2D_FC_SOURCE                                0x00800000
 #define chipMinorFeatures3_UNK24                               0x01000000
 #define chipMinorFeatures3_UNK25                               0x02000000
 #define chipMinorFeatures3_NEW_HZ                              0x04000000
 #define chipMinorFeatures3_UNK27                               0x08000000
 #define chipMinorFeatures3_UNK28                               0x10000000
-#define chipMinorFeatures3_UNK29                               0x20000000
+#define chipMinorFeatures3_SH_ENHANCEMENTS3                    0x20000000
 #define chipMinorFeatures3_UNK30                               0x40000000
 #define chipMinorFeatures3_UNK31                               0x80000000
 #define chipMinorFeatures4_UNK0                                        0x00000001
-#define chipMinorFeatures4_UNK1                                        0x00000002
-#define chipMinorFeatures4_UNK2                                        0x00000004
+#define chipMinorFeatures4_PE_ENHANCEMENTS2                    0x00000002
+#define chipMinorFeatures4_FRUSTUM_CLIP_FIX                    0x00000004
 #define chipMinorFeatures4_UNK3                                        0x00000008
 #define chipMinorFeatures4_UNK4                                        0x00000010
-#define chipMinorFeatures4_UNK5                                        0x00000020
-#define chipMinorFeatures4_UNK6                                        0x00000040
+#define chipMinorFeatures4_2D_GAMMA                            0x00000020
+#define chipMinorFeatures4_SINGLE_BUFFER                       0x00000040
 #define chipMinorFeatures4_UNK7                                        0x00000080
 #define chipMinorFeatures4_UNK8                                        0x00000100
 #define chipMinorFeatures4_UNK9                                        0x00000200
 #define chipMinorFeatures4_UNK10                               0x00000400
-#define chipMinorFeatures4_UNK11                               0x00000800
-#define chipMinorFeatures4_UNK12                               0x00001000
-#define chipMinorFeatures4_UNK13                               0x00002000
+#define chipMinorFeatures4_TX_LERP_PRECISION_FIX               0x00000800
+#define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION           0x00001000
+#define chipMinorFeatures4_TEXTURE_ASTC                                0x00002000
 #define chipMinorFeatures4_UNK14                               0x00004000
 #define chipMinorFeatures4_UNK15                               0x00008000
 #define chipMinorFeatures4_HALTI2                              0x00010000
 #define chipMinorFeatures4_UNK17                               0x00020000
 #define chipMinorFeatures4_SMALL_MSAA                          0x00040000
 #define chipMinorFeatures4_UNK19                               0x00080000
-#define chipMinorFeatures4_UNK20                               0x00100000
-#define chipMinorFeatures4_UNK21                               0x00200000
-#define chipMinorFeatures4_UNK22                               0x00400000
-#define chipMinorFeatures4_UNK23                               0x00800000
-#define chipMinorFeatures4_UNK24                               0x01000000
-#define chipMinorFeatures4_UNK25                               0x02000000
-#define chipMinorFeatures4_UNK26                               0x04000000
-#define chipMinorFeatures4_UNK27                               0x08000000
+#define chipMinorFeatures4_NEW_RA                              0x00100000
+#define chipMinorFeatures4_2D_OPF_YUV_OUTPUT                   0x00200000
+#define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2             0x00400000
+#define chipMinorFeatures4_NO_USER_CSC                         0x00800000
+#define chipMinorFeatures4_ZFIXES                              0x01000000
+#define chipMinorFeatures4_BUG_FIXES18                         0x02000000
+#define chipMinorFeatures4_2D_COMPRESSION                      0x04000000
+#define chipMinorFeatures4_PROBE                               0x08000000
 #define chipMinorFeatures4_UNK28                               0x10000000
-#define chipMinorFeatures4_UNK29                               0x20000000
+#define chipMinorFeatures4_2D_SUPER_TILE_VERSION               0x20000000
 #define chipMinorFeatures4_UNK30                               0x40000000
 #define chipMinorFeatures4_UNK31                               0x80000000
 #define chipMinorFeatures5_UNK0                                        0x00000001
 #define chipMinorFeatures5_UNK1                                        0x00000002
 #define chipMinorFeatures5_UNK2                                        0x00000004
 #define chipMinorFeatures5_UNK3                                        0x00000008
-#define chipMinorFeatures5_UNK4                                        0x00000010
+#define chipMinorFeatures5_EEZ                                 0x00000010
 #define chipMinorFeatures5_UNK5                                        0x00000020
 #define chipMinorFeatures5_UNK6                                        0x00000040
 #define chipMinorFeatures5_UNK7                                        0x00000080
 #define chipMinorFeatures5_UNK8                                        0x00000100
 #define chipMinorFeatures5_HALTI3                              0x00000200
 #define chipMinorFeatures5_UNK10                               0x00000400
-#define chipMinorFeatures5_UNK11                               0x00000800
+#define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP              0x00000800
 #define chipMinorFeatures5_UNK12                               0x00001000
-#define chipMinorFeatures5_UNK13                               0x00002000
-#define chipMinorFeatures5_UNK14                               0x00004000
+#define chipMinorFeatures5_SEPARATE_SRC_DST                    0x00002000
+#define chipMinorFeatures5_HALTI4                              0x00004000
 #define chipMinorFeatures5_UNK15                               0x00008000
-#define chipMinorFeatures5_UNK16                               0x00010000
-#define chipMinorFeatures5_UNK17                               0x00020000
+#define chipMinorFeatures5_ANDROID_ONLY                                0x00010000
+#define chipMinorFeatures5_HAS_PRODUCTID                       0x00020000
 #define chipMinorFeatures5_UNK18                               0x00040000
 #define chipMinorFeatures5_UNK19                               0x00080000
-#define chipMinorFeatures5_UNK20                               0x00100000
+#define chipMinorFeatures5_PE_DITHER_FIX2                      0x00100000
 #define chipMinorFeatures5_UNK21                               0x00200000
 #define chipMinorFeatures5_UNK22                               0x00400000
 #define chipMinorFeatures5_UNK23                               0x00800000
 #define chipMinorFeatures5_UNK24                               0x01000000
 #define chipMinorFeatures5_UNK25                               0x02000000
 #define chipMinorFeatures5_UNK26                               0x04000000
-#define chipMinorFeatures5_UNK27                               0x08000000
-#define chipMinorFeatures5_UNK28                               0x10000000
+#define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT      0x08000000
+#define chipMinorFeatures5_V2_MSAA_COMP_FIX                    0x10000000
 #define chipMinorFeatures5_UNK29                               0x20000000
 #define chipMinorFeatures5_UNK30                               0x40000000
 #define chipMinorFeatures5_UNK31                               0x80000000

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 5255278dde5603a6f13587b1276c0cbc8adc908d..91e17aeee1da5ffff6530451e866b8bc9b3f01b0 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -495,6 +495,7 @@ static struct drm_driver etnaviv_drm_driver = {
        .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
        .gem_prime_export   = drm_gem_prime_export,
        .gem_prime_import   = drm_gem_prime_import,
+       .gem_prime_res_obj  = etnaviv_gem_prime_res_obj,
        .gem_prime_pin      = etnaviv_gem_prime_pin,
        .gem_prime_unpin    = etnaviv_gem_prime_unpin,
        .gem_prime_get_sg_table = etnaviv_gem_prime_get_sg_table,

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index e41f38667c1c858a6f28d69d692e72160850c48a..058389f93b697a9136549c728e01ed62c6978af1 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
@@ -80,6 +80,7 @@ void *etnaviv_gem_prime_vmap(struct drm_gem_object *obj);
 void etnaviv_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
 int etnaviv_gem_prime_mmap(struct drm_gem_object *obj,
                           struct vm_area_struct *vma);
+struct reservation_object *etnaviv_gem_prime_res_obj(struct drm_gem_object *obj);
 struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev,
        struct dma_buf_attachment *attach, struct sg_table *sg);
 int etnaviv_gem_prime_pin(struct drm_gem_object *obj);

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
index d6fb724fc3ccc9ca8760c8590f7c963a9d134dc7..9a3bea738330208841b4e2a7a50aa73f8999c64d 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
@@ -411,16 +411,20 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op,
        struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);
        struct drm_device *dev = obj->dev;
        bool write = !!(op & ETNA_PREP_WRITE);
-       unsigned long remain =
-               op & ETNA_PREP_NOSYNC ? 0 : etnaviv_timeout_to_jiffies(timeout);
-       long lret;
-
-       lret = reservation_object_wait_timeout_rcu(etnaviv_obj->resv,
-                                                  write, true, remain);
-       if (lret < 0)
-               return lret;
-       else if (lret == 0)
-               return remain == 0 ? -EBUSY : -ETIMEDOUT;
+       int ret;
+
+       if (op & ETNA_PREP_NOSYNC) {
+               if (!reservation_object_test_signaled_rcu(etnaviv_obj->resv,
+                                                         write))
+                       return -EBUSY;
+       } else {
+               unsigned long remain = etnaviv_timeout_to_jiffies(timeout);
+
+               ret = reservation_object_wait_timeout_rcu(etnaviv_obj->resv,
+                                                         write, true, remain);
+               if (ret <= 0)
+                       return ret == 0 ? -ETIMEDOUT : ret;
+       }
 
        if (etnaviv_obj->flags & ETNA_BO_CACHED) {
                if (!etnaviv_obj->sgt) {

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
index 367bf952f61a18e2945e505f1c14c5539336fdd9..e5da4f2300ba13b3450627c1f2c2239e5fe3aeb4 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
@@ -150,3 +150,10 @@ fail:
 
        return ERR_PTR(ret);
 }
+
+struct reservation_object *etnaviv_gem_prime_res_obj(struct drm_gem_object *obj)
+{
+       struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);
+
+       return etnaviv_obj->resv;
+}

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 9a9c407178018a7521577cf04f12914facf73d4c..ada45fdd0eaeead886cd7cac4068ad5f97c53add 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -412,13 +412,19 @@ static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 
 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 {
-       unsigned int fscale = 1 << (6 - gpu->freq_scale);
-       u32 clock;
-
-       clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
-               VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
+       if (gpu->identity.minor_features2 &
+           chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
+               clk_set_rate(gpu->clk_core,
+                            gpu->base_rate_core >> gpu->freq_scale);
+               clk_set_rate(gpu->clk_shader,
+                            gpu->base_rate_shader >> gpu->freq_scale);
+       } else {
+               unsigned int fscale = 1 << (6 - gpu->freq_scale);
+               u32 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
+                           VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 
-       etnaviv_gpu_load_clock(gpu, clock);
+               etnaviv_gpu_load_clock(gpu, clock);
+       }
 }
 
 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
@@ -523,9 +529,10 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 
        pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 
-       /* Disable PA clock gating for GC400+ except for GC420 */
+       /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
        if (gpu->identity.model >= chipModel_GC400 &&
-           gpu->identity.model != chipModel_GC420)
+           gpu->identity.model != chipModel_GC420 &&
+           !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
                pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 
        /*
@@ -541,6 +548,11 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
        if (gpu->identity.revision < 0x5422)
                pmc |= BIT(15); /* Unknown bit */
 
+       /* Disable TX clock gating on affected core revisions. */
+       if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
+           etnaviv_is_model_rev(gpu, GC2000, 0x5108))
+               pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
+
        pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
        pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 
@@ -1736,11 +1748,13 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
        DBG("clk_core: %p", gpu->clk_core);
        if (IS_ERR(gpu->clk_core))
                gpu->clk_core = NULL;
+       gpu->base_rate_core = clk_get_rate(gpu->clk_core);
 
        gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
        DBG("clk_shader: %p", gpu->clk_shader);
        if (IS_ERR(gpu->clk_shader))
                gpu->clk_shader = NULL;
+       gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
 
        /* TODO: figure out max mapped size */
        dev_set_drvdata(dev, gpu);

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
index 9227a97404473baa373d2ce2934dcf2cf497a7b7..689cb8f3680c97bcd62836bfd90885f134862650 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
@@ -152,6 +152,8 @@ struct etnaviv_gpu {
        u32 hangcheck_dma_addr;
        struct work_struct recover_work;
        unsigned int freq_scale;
+       unsigned long base_rate_core;
+       unsigned long base_rate_shader;
 };
 
 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)