Merge tag 'v3.6-rc2' into drm-intel-next

Backmerge Linux 3.6-rc2 to resolve a few funny conflicts before we put
even more madness on top:

- drivers/gpu/drm/i915/i915_irq.c: Just a spurious WARN removed in
  -fixes, that has been changed in a variable-rename in -next, too.

- drivers/gpu/drm/i915/intel_ringbuffer.c: -next remove scratch_addr
  (since all their users have been extracted in another fucntion),
  -fixes added another user for a hw workaroudn.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --cc drivers/gpu/drm/i915/i915_drv.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_execbuffer.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_irq.c
index 0c37101934f81c5b40373c4be7c867b7b9ff4fcb,8a3828528b9ddfa9678e7bfbf015bd7acdfdc29d..a61b41a8c607878cb82d881d8645d12dba9805b6
--- 1/drivers/gpu/drm/i915/i915_irq.c
--- 2/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@@ -500,20 -488,19 +500,19 @@@ static void gen6_queue_rps_work(struct 
         * IIR bits should never already be set because IMR should
         * prevent an interrupt from being shown in IIR. The warning
         * displays a case where we've unsafely cleared
 -       * dev_priv->pm_iir. Although missing an interrupt of the same
 +       * dev_priv->rps.pm_iir. Although missing an interrupt of the same
         * type is not a problem, it displays a problem in the logic.
         *
 -       * The mask bit in IMR is cleared by rps_work.
 +       * The mask bit in IMR is cleared by dev_priv->rps.work.
         */
  
 -      spin_lock_irqsave(&dev_priv->rps_lock, flags);
 -      dev_priv->pm_iir |= pm_iir;
 -      I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 +      spin_lock_irqsave(&dev_priv->rps.lock, flags);
-       WARN(dev_priv->rps.pm_iir & pm_iir, "Missed a PM interrupt\n");
 +      dev_priv->rps.pm_iir |= pm_iir;
 +      I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
        POSTING_READ(GEN6_PMIMR);
 -      spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 +      spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
  
 -      queue_work(dev_priv->wq, &dev_priv->rps_work);
 +      queue_work(dev_priv->wq, &dev_priv->rps.work);
  }
  
  static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)

diff --cc drivers/gpu/drm/i915/i915_sysfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ringbuffer.c
index e278675cdff9a94e3fdfabf29196f6a0b0034fa9,e2a73b38abe96e7dc49674d39806c5ca3cab6e51..c828169c73ae8103c351f177000688cd4500b6f4
--- 1/drivers/gpu/drm/i915/intel_ringbuffer.c
--- 2/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@@ -214,8 -214,15 +214,10 @@@ gen6_render_ring_flush(struct intel_rin
                           u32 invalidate_domains, u32 flush_domains)
  {
        u32 flags = 0;
+       struct pipe_control *pc = ring->private;
+       u32 scratch_addr = pc->gtt_offset + 128;
        int ret;
  
 -      /* Force SNB workarounds for PIPE_CONTROL flushes */
 -      ret = intel_emit_post_sync_nonzero_flush(ring);
 -      if (ret)
 -              return ret;
 -
        /* Just flush everything.  Experiments have shown that reducing the
         * number of bits based on the write domains has little performance
         * impact.

diff --cc drivers/gpu/drm/i915/intel_sdvo.c
Simple merge