]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs
authorGregory CLEMENT <gregory.clement@free-electrons.com>
Mon, 27 Apr 2015 06:55:18 +0000 (08:55 +0200)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Fri, 1 May 2015 17:21:57 +0000 (19:21 +0200)
Whereas for Armada 370 and XP the main PLL frequency was 2GHz for the
Armada 375, 38x and 39x, the frequency is 1GHz. When writing support
for these last SoCs, there was no official value for the PLL. Now that
we have it, this patch fixes it in the device tree.

This value is currently only used by the NAND driver for the setting
the NAND timing. Fortunately it is not actually used: all the mainline
board with a NAND flash comes with a NAND device tree node using the
"marvell,nand-keep-config" property. With this property the timings
are not modified in the kernel driver and are kept from the
bootloader.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Marcin Wojtas <mw@semihalf.com>
arch/arm/boot/dts/armada-375.dtsi
arch/arm/boot/dts/armada-38x.dtsi
arch/arm/boot/dts/armada-39x.dtsi

index c675257f2377f8797565871e38e77ba50fe7678b..f076ff856d8b8223466f3ec8536caaa1974186ca 100644 (file)
@@ -69,7 +69,7 @@
                mainpll: mainpll {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
-                       clock-frequency = <2000000000>;
+                       clock-frequency = <1000000000>;
                };
                /* 25 MHz reference crystal */
                refclk: oscillator {
index ed2dd8ba4080df7a7f85db89068de44cd693446b..218a2acd36e509b0de8e22dc207e06253b1163fe 100644 (file)
                mainpll: mainpll {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
-                       clock-frequency = <2000000000>;
+                       clock-frequency = <1000000000>;
                };
 
                /* 25 MHz reference crystal */
index 0e85fc15cedad84c1ea5ebea6db033a2ace60703..ecd1318109bac8fb5d1e29c96f7c30779d217fda 100644 (file)
                mainpll: mainpll {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
-                       clock-frequency = <2000000000>;
+                       clock-frequency = <1000000000>;
                };
        };
 };