ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY

Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index f5dca1ff1d6e222876ea6a59165852a2f0781fb4..3ff6d7c3857c2fb0fd0bd85ec0105eccb4a590fe 100644 (file)
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
                reg = <0x021c>, <0x0220>;
        };
 
+       optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+               compatible = "ti,gate-clock";
+               clocks = <&sys_32k_ck>;
+               #clock-cells = <0>;
+               reg = <0x13b0>;
+               ti,bit-shift = <8>;
+       };
+
        optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
                compatible = "ti,divider-clock";
                clocks = <&apll_pcie_ck>;