dsa: mv88e6xxx: Set the RGMII delay based on phy interface

Some Marvell switches allow the RGMII Rx and Tx clock to be delayed
when the port is using RGMII. Have the adjust_link function look at
the phy interface type and enable this delay as requested.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c
index 1a8c45f3e68057d1b9c8f8044c618bc9b68f7425..90dee97ae7938264cabc958b54f2e6b53ac50668 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx.c
+++ b/drivers/net/dsa/mv88e6xxx.c
@@ -612,6 +612,16 @@ void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
        if (phydev->duplex == DUPLEX_FULL)
                reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 
+       if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
+           (port >= ps->num_ports - 2)) {
+               if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+                       reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
+               if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+                       reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
+               if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+                       reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
+                               PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
+       }
        _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
 
 out:

diff --git a/drivers/net/dsa/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx.h
index 79003c55fe62c96c09a224f86d0258e6e1c43d44..9b6f3d9d5ae1cfa9034f1a2fb381d631ecd0d017 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx.h
+++ b/drivers/net/dsa/mv88e6xxx.h
@@ -46,6 +46,8 @@
 #define PORT_STATUS_TX_PAUSED  BIT(5)
 #define PORT_STATUS_FLOW_CTRL  BIT(4)
 #define PORT_PCS_CTRL          0x01
+#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK        BIT(15)
+#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK        BIT(14)
 #define PORT_PCS_CTRL_FC               BIT(7)
 #define PORT_PCS_CTRL_FORCE_FC         BIT(6)
 #define PORT_PCS_CTRL_LINK_UP          BIT(5)