ARM: sunxi: add PLL4 support

This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
device trees. PLL4 is compatible with PLL1.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 319cc6b509da8e29ee657730497d87f1215745a8..a6c1caeae6a0226d8ff1943383e8ad726c5920c0 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -66,6 +66,13 @@
                        clocks = <&osc24M>;
                };
 
+               pll4: pll4@01c20018 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-pll1-clk";
+                       reg = <0x01c20018 0x4>;
+                       clocks = <&osc24M>;
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 52476742a1043e5e9703505d03b2eae5d2a5bc1a..c3f4eed3691bb6268f3be343247b8257fb0bbb20 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -63,6 +63,13 @@
                        clocks = <&osc24M>;
                };
 
+               pll4: pll4@01c20018 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-pll1-clk";
+                       reg = <0x01c20018 0x4>;
+                       clocks = <&osc24M>;
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index ce8ef2a45be098a35521db6d7fa41c472cd0b85a..8c4a9c3c069c79c61668d98150ce349050194545 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -67,6 +67,13 @@
                        clocks = <&osc24M>;
                };
 
+               pll4: pll4@01c20018 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-pll1-clk";
+                       reg = <0x01c20018 0x4>;
+                       clocks = <&osc24M>;
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e46cfedde74c220b698c829458dfa40cef916159..e4a5d37a12f8164b21871d6281100d73b1a6e153 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -62,6 +62,13 @@
                        clocks = <&osc24M>;
                };
 
+               pll4: pll4@01c20018 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-pll1-clk";
+                       reg = <0x01c20018 0x4>;
+                       clocks = <&osc24M>;
+               };
+
                /*
                 * This is a dummy clock, to be used as placeholder on
                 * other mux clocks when a specific parent clock is not