1 //==========================================================================
3 // devs_eth_arm_cerf.inl
5 // CERF ethernet I/O definitions.
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Purpose: CERF ethernet defintions
48 //####DESCRIPTIONEND####
49 //==========================================================================
51 #include <cyg/hal/hal_intr.h>
52 #include <cyg/hal/hal_if.h>
53 #include <cyg/hal/cerf.h>
56 # include <pkgconf/redboot.h>
57 # ifdef CYGSEM_REDBOOT_FLASH_CONFIG
59 # include <flash_config.h>
64 # define CS8900A_step 2
69 #ifdef CYGPKG_DEVS_ETH_ARM_CERF_ETH0
71 #ifndef CYGSEM_DEVS_ETH_ARM_CERF_ETH0_SET_ESA
72 # if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
73 RedBoot_config_option("Set " CYGDAT_DEVS_ETH_ARM_CERF_ETH0_NAME " network hardware address [MAC]",
78 RedBoot_config_option(CYGDAT_DEVS_ETH_ARM_CERF_ETH0_NAME " network hardware address [MAC]",
83 # endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
85 # ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
86 // Note that this section *is* active in an application, outside RedBoot,
87 // where the above section is not included.
89 # include <cyg/hal/hal_if.h>
92 # define CONFIG_ESA (6)
95 # define CONFIG_BOOL (1)
99 _cerf_provide_eth0_esa(struct cs8900a_priv_data* cpd)
103 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
104 "eth0_esa", &set_esa, CONFIG_BOOL);
106 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
107 "eth0_esa_data", cpd->esa, CONFIG_ESA);
109 return ok && set_esa;
112 # endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
113 #endif // ! CYGSEM_DEVS_ETH_ARM_CERF_ETH0_SET_ESA
115 // ------------------------------------------------------------------------
116 // EEPROM access functions
118 #define PP_ECR 0x0040
119 #define PP_EE_READ_CMD 0x0200
120 #define PP_EE_WRITE_CMD 0x0100
121 #define PP_EE_DATA 0x0042
122 #define PP_EE_ADDR_W0 0x001C
123 #define PP_EE_ADDR_W1 0x001D
124 #define PP_EE_ADDR_W2 0x001E
126 static __inline__ cyg_uint16
127 read_eeprom(cyg_addrword_t base, cyg_uint16 offset)
129 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
132 put_reg(base, PP_ECR, (offset | PP_EE_READ_CMD));
134 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
137 return get_reg(base, PP_EE_DATA);
140 static __inline__ void
141 copy_eeprom(cyg_addrword_t base)
145 for (i = 0; i < 6; i += 2)
147 esa_word = read_eeprom(base, PP_EE_ADDR_W0 + (i/2));
148 put_reg(base, PP_IA+(i/2), esa_word);
152 static __inline__ void
153 post_reset(cyg_addrword_t base)
155 // Toggle A0 connected to the SBHE line on the Crystal chip.
156 *(char*)(0x20000000) = 1;
157 *(char*)(0x20000001) = 2;
158 *(char*)(0x20000000) = 3;
159 *(char*)(0x20000001) = 0;
162 #undef CYGHWR_CL_CS8900A_PLF_POST_RESET
163 #define CYGHWR_CL_CS8900A_PLF_POST_RESET(base) post_reset(base)
165 #undef CYGHWR_CL_CS8900A_PLF_RESET
166 #define CYGHWR_CL_CS8900A_PLF_RESET(base) copy_eeprom(base)
168 static cs8900a_priv_data_t cs8900a_eth0_priv_data = {
169 base : (cyg_addrword_t) 0xf0000300,
170 interrupt:SA1110_IRQ_GPIO_ETH,
171 #ifdef CYGSEM_DEVS_ETH_ARM_CERF_ETH0_SET_ESA
172 esa : CYGDAT_DEVS_ETH_ARM_CERF_ETH0_ESA,
173 hardwired_esa : true,
175 hardwired_esa : false,
176 # ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
177 provide_esa : &_cerf_provide_eth0_esa,
186 ETH_DRV_SC(cs8900a_sc,
187 &cs8900a_eth0_priv_data, // Driver specific data
188 CYGDAT_DEVS_ETH_ARM_CERF_ETH0_NAME,
195 cs8900a_deliver, // "pseudoDSR" called from fast net thread
196 cs8900a_poll, // poll function, encapsulates ISR and DSR
199 NETDEVTAB_ENTRY(cs8900a_netdev,
200 "cs8900a_" CYGDAT_DEVS_ETH_ARM_CERF_ETH0_NAME,
204 #endif // CYGPKG_DEVS_ETH_ARM_CERF_ETH0
206 #endif // __WANT_DEVS
208 // EOF devs_eth_arm_cerf.inl